1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 clocks { 14 sleep_clk: sleep_clk { 15 compatible = "fixed-clock"; 16 clock-frequency = <32000>; 17 #clock-cells = <0>; 18 }; 19 20 xo: xo { 21 compatible = "fixed-clock"; 22 clock-frequency = <19200000>; 23 #clock-cells = <0>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <0x1>; 29 #size-cells = <0x0>; 30 31 CPU0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0x0>; 35 next-level-cache = <&L2_0>; 36 enable-method = "psci"; 37 }; 38 39 CPU1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 next-level-cache = <&L2_0>; 45 }; 46 47 CPU2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 next-level-cache = <&L2_0>; 53 }; 54 55 CPU3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <0x2>; 66 }; 67 }; 68 69 pmu { 70 compatible = "arm,cortex-a53-pmu"; 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72 }; 73 74 psci { 75 compatible = "arm,psci-1.0"; 76 method = "smc"; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq8074", "qcom,scm"; 82 }; 83 }; 84 85 soc: soc { 86 #address-cells = <0x1>; 87 #size-cells = <0x1>; 88 ranges = <0 0 0 0xffffffff>; 89 compatible = "simple-bus"; 90 91 ssphy_1: phy@58000 { 92 compatible = "qcom,ipq8074-qmp-usb3-phy"; 93 reg = <0x00058000 0x1c4>; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 ranges; 97 98 clocks = <&gcc GCC_USB1_AUX_CLK>, 99 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 100 <&xo>; 101 clock-names = "aux", "cfg_ahb", "ref"; 102 103 resets = <&gcc GCC_USB1_PHY_BCR>, 104 <&gcc GCC_USB3PHY_1_PHY_BCR>; 105 reset-names = "phy","common"; 106 status = "disabled"; 107 108 usb1_ssphy: phy@58200 { 109 reg = <0x00058200 0x130>, /* Tx */ 110 <0x00058400 0x200>, /* Rx */ 111 <0x00058800 0x1f8>, /* PCS */ 112 <0x00058600 0x044>; /* PCS misc*/ 113 #phy-cells = <0>; 114 #clock-cells = <1>; 115 clocks = <&gcc GCC_USB1_PIPE_CLK>; 116 clock-names = "pipe0"; 117 clock-output-names = "gcc_usb1_pipe_clk_src"; 118 }; 119 }; 120 121 qusb_phy_1: phy@59000 { 122 compatible = "qcom,ipq8074-qusb2-phy"; 123 reg = <0x00059000 0x180>; 124 #phy-cells = <0>; 125 126 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 127 <&xo>; 128 clock-names = "cfg_ahb", "ref"; 129 130 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 131 status = "disabled"; 132 }; 133 134 ssphy_0: phy@78000 { 135 compatible = "qcom,ipq8074-qmp-usb3-phy"; 136 reg = <0x00078000 0x1c4>; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges; 140 141 clocks = <&gcc GCC_USB0_AUX_CLK>, 142 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 143 <&xo>; 144 clock-names = "aux", "cfg_ahb", "ref"; 145 146 resets = <&gcc GCC_USB0_PHY_BCR>, 147 <&gcc GCC_USB3PHY_0_PHY_BCR>; 148 reset-names = "phy","common"; 149 status = "disabled"; 150 151 usb0_ssphy: phy@78200 { 152 reg = <0x00078200 0x130>, /* Tx */ 153 <0x00078400 0x200>, /* Rx */ 154 <0x00078800 0x1f8>, /* PCS */ 155 <0x00078600 0x044>; /* PCS misc*/ 156 #phy-cells = <0>; 157 #clock-cells = <1>; 158 clocks = <&gcc GCC_USB0_PIPE_CLK>; 159 clock-names = "pipe0"; 160 clock-output-names = "gcc_usb0_pipe_clk_src"; 161 }; 162 }; 163 164 qusb_phy_0: phy@79000 { 165 compatible = "qcom,ipq8074-qusb2-phy"; 166 reg = <0x00079000 0x180>; 167 #phy-cells = <0>; 168 169 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 170 <&xo>; 171 clock-names = "cfg_ahb", "ref"; 172 173 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 174 status = "disabled"; 175 }; 176 177 pcie_qmp0: phy@86000 { 178 compatible = "qcom,ipq8074-qmp-pcie-phy"; 179 reg = <0x00086000 0x1000>; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 184 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 185 <&gcc GCC_PCIE0_AHB_CLK>; 186 clock-names = "aux", "cfg_ahb"; 187 resets = <&gcc GCC_PCIE0_PHY_BCR>, 188 <&gcc GCC_PCIE0PHY_PHY_BCR>; 189 reset-names = "phy", 190 "common"; 191 status = "disabled"; 192 193 pcie_phy0: phy@86200 { 194 reg = <0x86200 0x16c>, 195 <0x86400 0x200>, 196 <0x86800 0x4f4>; 197 #phy-cells = <0>; 198 #clock-cells = <0>; 199 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 200 clock-names = "pipe0"; 201 clock-output-names = "pcie_0_pipe_clk"; 202 }; 203 }; 204 205 pcie_qmp1: phy@8e000 { 206 compatible = "qcom,ipq8074-qmp-pcie-phy"; 207 reg = <0x0008e000 0x1000>; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 213 <&gcc GCC_PCIE1_AHB_CLK>; 214 clock-names = "aux", "cfg_ahb"; 215 resets = <&gcc GCC_PCIE1_PHY_BCR>, 216 <&gcc GCC_PCIE1PHY_PHY_BCR>; 217 reset-names = "phy", 218 "common"; 219 status = "disabled"; 220 221 pcie_phy1: phy@8e200 { 222 reg = <0x8e200 0x16c>, 223 <0x8e400 0x200>, 224 <0x8e800 0x4f4>; 225 #phy-cells = <0>; 226 #clock-cells = <0>; 227 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 228 clock-names = "pipe0"; 229 clock-output-names = "pcie_1_pipe_clk"; 230 }; 231 }; 232 233 mdio: mdio@90000 { 234 compatible = "qcom,ipq4019-mdio"; 235 reg = <0x00090000 0x64>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 239 clocks = <&gcc GCC_MDIO_AHB_CLK>; 240 clock-names = "gcc_mdio_ahb_clk"; 241 242 status = "disabled"; 243 }; 244 245 prng: rng@e3000 { 246 compatible = "qcom,prng-ee"; 247 reg = <0x000e3000 0x1000>; 248 clocks = <&gcc GCC_PRNG_AHB_CLK>; 249 clock-names = "core"; 250 status = "disabled"; 251 }; 252 253 cryptobam: dma-controller@704000 { 254 compatible = "qcom,bam-v1.7.0"; 255 reg = <0x00704000 0x20000>; 256 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 258 clock-names = "bam_clk"; 259 #dma-cells = <1>; 260 qcom,ee = <1>; 261 qcom,controlled-remotely; 262 status = "disabled"; 263 }; 264 265 crypto: crypto@73a000 { 266 compatible = "qcom,crypto-v5.1"; 267 reg = <0x0073a000 0x6000>; 268 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 269 <&gcc GCC_CRYPTO_AXI_CLK>, 270 <&gcc GCC_CRYPTO_CLK>; 271 clock-names = "iface", "bus", "core"; 272 dmas = <&cryptobam 2>, <&cryptobam 3>; 273 dma-names = "rx", "tx"; 274 status = "disabled"; 275 }; 276 277 tlmm: pinctrl@1000000 { 278 compatible = "qcom,ipq8074-pinctrl"; 279 reg = <0x01000000 0x300000>; 280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 281 gpio-controller; 282 gpio-ranges = <&tlmm 0 0 70>; 283 #gpio-cells = <0x2>; 284 interrupt-controller; 285 #interrupt-cells = <0x2>; 286 287 serial_4_pins: serial4-pinmux { 288 pins = "gpio23", "gpio24"; 289 function = "blsp4_uart1"; 290 drive-strength = <8>; 291 bias-disable; 292 }; 293 294 i2c_0_pins: i2c-0-pinmux { 295 pins = "gpio42", "gpio43"; 296 function = "blsp1_i2c"; 297 drive-strength = <8>; 298 bias-disable; 299 }; 300 301 spi_0_pins: spi-0-pins { 302 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 303 function = "blsp0_spi"; 304 drive-strength = <8>; 305 bias-disable; 306 }; 307 308 hsuart_pins: hsuart-pins { 309 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 310 function = "blsp2_uart"; 311 drive-strength = <8>; 312 bias-disable; 313 }; 314 315 qpic_pins: qpic-pins { 316 pins = "gpio1", "gpio3", "gpio4", 317 "gpio5", "gpio6", "gpio7", 318 "gpio8", "gpio10", "gpio11", 319 "gpio12", "gpio13", "gpio14", 320 "gpio15", "gpio16", "gpio17"; 321 function = "qpic"; 322 drive-strength = <8>; 323 bias-disable; 324 }; 325 }; 326 327 gcc: gcc@1800000 { 328 compatible = "qcom,gcc-ipq8074"; 329 reg = <0x01800000 0x80000>; 330 #clock-cells = <0x1>; 331 #reset-cells = <0x1>; 332 }; 333 334 spmi_bus: spmi@200f000 { 335 compatible = "qcom,spmi-pmic-arb"; 336 reg = <0x0200f000 0x001000>, 337 <0x02400000 0x800000>, 338 <0x02c00000 0x800000>, 339 <0x03800000 0x200000>, 340 <0x0200a000 0x000700>; 341 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 342 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-names = "periph_irq"; 344 qcom,ee = <0>; 345 qcom,channel = <0>; 346 #address-cells = <2>; 347 #size-cells = <0>; 348 interrupt-controller; 349 #interrupt-cells = <4>; 350 cell-index = <0>; 351 }; 352 353 sdhc_1: sdhci@7824900 { 354 compatible = "qcom,sdhci-msm-v4"; 355 reg = <0x7824900 0x500>, <0x7824000 0x800>; 356 reg-names = "hc_mem", "core_mem"; 357 358 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "hc_irq", "pwr_irq"; 361 362 clocks = <&xo>, 363 <&gcc GCC_SDCC1_AHB_CLK>, 364 <&gcc GCC_SDCC1_APPS_CLK>; 365 clock-names = "xo", "iface", "core"; 366 max-frequency = <384000000>; 367 mmc-ddr-1_8v; 368 mmc-hs200-1_8v; 369 mmc-hs400-1_8v; 370 bus-width = <8>; 371 372 status = "disabled"; 373 }; 374 375 blsp_dma: dma-controller@7884000 { 376 compatible = "qcom,bam-v1.7.0"; 377 reg = <0x07884000 0x2b000>; 378 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 380 clock-names = "bam_clk"; 381 #dma-cells = <1>; 382 qcom,ee = <0>; 383 }; 384 385 blsp1_uart1: serial@78af000 { 386 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 387 reg = <0x078af000 0x200>; 388 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 390 <&gcc GCC_BLSP1_AHB_CLK>; 391 clock-names = "core", "iface"; 392 status = "disabled"; 393 }; 394 395 blsp1_uart3: serial@78b1000 { 396 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 397 reg = <0x078b1000 0x200>; 398 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 400 <&gcc GCC_BLSP1_AHB_CLK>; 401 clock-names = "core", "iface"; 402 dmas = <&blsp_dma 4>, 403 <&blsp_dma 5>; 404 dma-names = "tx", "rx"; 405 pinctrl-0 = <&hsuart_pins>; 406 pinctrl-names = "default"; 407 status = "disabled"; 408 }; 409 410 blsp1_uart5: serial@78b3000 { 411 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 412 reg = <0x078b3000 0x200>; 413 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 415 <&gcc GCC_BLSP1_AHB_CLK>; 416 clock-names = "core", "iface"; 417 pinctrl-0 = <&serial_4_pins>; 418 pinctrl-names = "default"; 419 status = "disabled"; 420 }; 421 422 blsp1_spi1: spi@78b5000 { 423 compatible = "qcom,spi-qup-v2.2.1"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 reg = <0x078b5000 0x600>; 427 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 428 spi-max-frequency = <50000000>; 429 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 430 <&gcc GCC_BLSP1_AHB_CLK>; 431 clock-names = "core", "iface"; 432 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 433 dma-names = "tx", "rx"; 434 pinctrl-0 = <&spi_0_pins>; 435 pinctrl-names = "default"; 436 status = "disabled"; 437 }; 438 439 blsp1_i2c2: i2c@78b6000 { 440 compatible = "qcom,i2c-qup-v2.2.1"; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 reg = <0x078b6000 0x600>; 444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 446 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 447 clock-names = "iface", "core"; 448 clock-frequency = <400000>; 449 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 450 dma-names = "rx", "tx"; 451 pinctrl-0 = <&i2c_0_pins>; 452 pinctrl-names = "default"; 453 status = "disabled"; 454 }; 455 456 blsp1_i2c3: i2c@78b7000 { 457 compatible = "qcom,i2c-qup-v2.2.1"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 reg = <0x078b7000 0x600>; 461 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 463 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 464 clock-names = "iface", "core"; 465 clock-frequency = <100000>; 466 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 467 dma-names = "rx", "tx"; 468 status = "disabled"; 469 }; 470 471 blsp1_i2c5: i2c@78b9000 { 472 compatible = "qcom,i2c-qup-v2.2.1"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 reg = <0x78b9000 0x600>; 476 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 478 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 479 clock-names = "iface", "core"; 480 clock-frequency = <400000>; 481 dmas = <&blsp_dma 21>, <&blsp_dma 20>; 482 dma-names = "rx", "tx"; 483 status = "disabled"; 484 }; 485 486 blsp1_i2c6: i2c@78ba000 { 487 compatible = "qcom,i2c-qup-v2.2.1"; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 reg = <0x078ba000 0x600>; 491 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 493 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 494 clock-names = "iface", "core"; 495 clock-frequency = <100000>; 496 dmas = <&blsp_dma 23>, <&blsp_dma 22>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 qpic_bam: dma-controller@7984000 { 502 compatible = "qcom,bam-v1.7.0"; 503 reg = <0x07984000 0x1a000>; 504 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&gcc GCC_QPIC_AHB_CLK>; 506 clock-names = "bam_clk"; 507 #dma-cells = <1>; 508 qcom,ee = <0>; 509 status = "disabled"; 510 }; 511 512 qpic_nand: nand@79b0000 { 513 compatible = "qcom,ipq8074-nand"; 514 reg = <0x079b0000 0x10000>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&gcc GCC_QPIC_CLK>, 518 <&gcc GCC_QPIC_AHB_CLK>; 519 clock-names = "core", "aon"; 520 521 dmas = <&qpic_bam 0>, 522 <&qpic_bam 1>, 523 <&qpic_bam 2>; 524 dma-names = "tx", "rx", "cmd"; 525 pinctrl-0 = <&qpic_pins>; 526 pinctrl-names = "default"; 527 status = "disabled"; 528 }; 529 530 usb_0: usb@8af8800 { 531 compatible = "qcom,dwc3"; 532 reg = <0x08af8800 0x400>; 533 #address-cells = <1>; 534 #size-cells = <1>; 535 ranges; 536 537 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 538 <&gcc GCC_USB0_MASTER_CLK>, 539 <&gcc GCC_USB0_SLEEP_CLK>, 540 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 541 clock-names = "sys_noc_axi", 542 "master", 543 "sleep", 544 "mock_utmi"; 545 546 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 547 <&gcc GCC_USB0_MASTER_CLK>, 548 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 549 assigned-clock-rates = <133330000>, 550 <133330000>, 551 <19200000>; 552 553 resets = <&gcc GCC_USB0_BCR>; 554 status = "disabled"; 555 556 dwc_0: dwc3@8a00000 { 557 compatible = "snps,dwc3"; 558 reg = <0x8a00000 0xcd00>; 559 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 560 phys = <&qusb_phy_0>, <&usb0_ssphy>; 561 phy-names = "usb2-phy", "usb3-phy"; 562 snps,is-utmi-l1-suspend; 563 snps,hird-threshold = /bits/ 8 <0x0>; 564 snps,dis_u2_susphy_quirk; 565 snps,dis_u3_susphy_quirk; 566 dr_mode = "host"; 567 }; 568 }; 569 570 usb_1: usb@8cf8800 { 571 compatible = "qcom,dwc3"; 572 reg = <0x08cf8800 0x400>; 573 #address-cells = <1>; 574 #size-cells = <1>; 575 ranges; 576 577 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 578 <&gcc GCC_USB1_MASTER_CLK>, 579 <&gcc GCC_USB1_SLEEP_CLK>, 580 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 581 clock-names = "sys_noc_axi", 582 "master", 583 "sleep", 584 "mock_utmi"; 585 586 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 587 <&gcc GCC_USB1_MASTER_CLK>, 588 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 589 assigned-clock-rates = <133330000>, 590 <133330000>, 591 <19200000>; 592 593 resets = <&gcc GCC_USB1_BCR>; 594 status = "disabled"; 595 596 dwc_1: dwc3@8c00000 { 597 compatible = "snps,dwc3"; 598 reg = <0x8c00000 0xcd00>; 599 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 600 phys = <&qusb_phy_1>, <&usb1_ssphy>; 601 phy-names = "usb2-phy", "usb3-phy"; 602 snps,is-utmi-l1-suspend; 603 snps,hird-threshold = /bits/ 8 <0x0>; 604 snps,dis_u2_susphy_quirk; 605 snps,dis_u3_susphy_quirk; 606 dr_mode = "host"; 607 }; 608 }; 609 610 intc: interrupt-controller@b000000 { 611 compatible = "qcom,msm-qgic2"; 612 interrupt-controller; 613 #interrupt-cells = <0x3>; 614 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 615 }; 616 617 timer { 618 compatible = "arm,armv8-timer"; 619 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 620 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 621 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 622 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 623 }; 624 625 watchdog: watchdog@b017000 { 626 compatible = "qcom,kpss-wdt"; 627 reg = <0xb017000 0x1000>; 628 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 629 clocks = <&sleep_clk>; 630 timeout-sec = <30>; 631 }; 632 633 timer@b120000 { 634 #address-cells = <1>; 635 #size-cells = <1>; 636 ranges; 637 compatible = "arm,armv7-timer-mem"; 638 reg = <0x0b120000 0x1000>; 639 clock-frequency = <19200000>; 640 641 frame@b120000 { 642 frame-number = <0>; 643 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 645 reg = <0x0b121000 0x1000>, 646 <0x0b122000 0x1000>; 647 }; 648 649 frame@b123000 { 650 frame-number = <1>; 651 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 652 reg = <0x0b123000 0x1000>; 653 status = "disabled"; 654 }; 655 656 frame@b124000 { 657 frame-number = <2>; 658 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 659 reg = <0x0b124000 0x1000>; 660 status = "disabled"; 661 }; 662 663 frame@b125000 { 664 frame-number = <3>; 665 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 666 reg = <0x0b125000 0x1000>; 667 status = "disabled"; 668 }; 669 670 frame@b126000 { 671 frame-number = <4>; 672 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 673 reg = <0x0b126000 0x1000>; 674 status = "disabled"; 675 }; 676 677 frame@b127000 { 678 frame-number = <5>; 679 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 680 reg = <0x0b127000 0x1000>; 681 status = "disabled"; 682 }; 683 684 frame@b128000 { 685 frame-number = <6>; 686 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 687 reg = <0x0b128000 0x1000>; 688 status = "disabled"; 689 }; 690 }; 691 692 pcie1: pci@10000000 { 693 compatible = "qcom,pcie-ipq8074"; 694 reg = <0x10000000 0xf1d>, 695 <0x10000f20 0xa8>, 696 <0x00088000 0x2000>, 697 <0x10100000 0x1000>; 698 reg-names = "dbi", "elbi", "parf", "config"; 699 device_type = "pci"; 700 linux,pci-domain = <1>; 701 bus-range = <0x00 0xff>; 702 num-lanes = <1>; 703 #address-cells = <3>; 704 #size-cells = <2>; 705 706 phys = <&pcie_phy1>; 707 phy-names = "pciephy"; 708 709 ranges = <0x81000000 0 0x10200000 0x10200000 710 0 0x100000 /* downstream I/O */ 711 0x82000000 0 0x10300000 0x10300000 712 0 0xd00000>; /* non-prefetchable memory */ 713 714 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "msi"; 716 #interrupt-cells = <1>; 717 interrupt-map-mask = <0 0 0 0x7>; 718 interrupt-map = <0 0 0 1 &intc 0 142 719 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 720 <0 0 0 2 &intc 0 143 721 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 722 <0 0 0 3 &intc 0 144 723 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 724 <0 0 0 4 &intc 0 145 725 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 726 727 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 728 <&gcc GCC_PCIE1_AXI_M_CLK>, 729 <&gcc GCC_PCIE1_AXI_S_CLK>, 730 <&gcc GCC_PCIE1_AHB_CLK>, 731 <&gcc GCC_PCIE1_AUX_CLK>; 732 clock-names = "iface", 733 "axi_m", 734 "axi_s", 735 "ahb", 736 "aux"; 737 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 738 <&gcc GCC_PCIE1_SLEEP_ARES>, 739 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 740 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 741 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 742 <&gcc GCC_PCIE1_AHB_ARES>, 743 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 744 reset-names = "pipe", 745 "sleep", 746 "sticky", 747 "axi_m", 748 "axi_s", 749 "ahb", 750 "axi_m_sticky"; 751 status = "disabled"; 752 }; 753 754 pcie0: pci@20000000 { 755 compatible = "qcom,pcie-ipq8074"; 756 reg = <0x20000000 0xf1d>, 757 <0x20000f20 0xa8>, 758 <0x00080000 0x2000>, 759 <0x20100000 0x1000>; 760 reg-names = "dbi", "elbi", "parf", "config"; 761 device_type = "pci"; 762 linux,pci-domain = <0>; 763 bus-range = <0x00 0xff>; 764 num-lanes = <1>; 765 #address-cells = <3>; 766 #size-cells = <2>; 767 768 phys = <&pcie_phy0>; 769 phy-names = "pciephy"; 770 771 ranges = <0x81000000 0 0x20200000 0x20200000 772 0 0x100000 /* downstream I/O */ 773 0x82000000 0 0x20300000 0x20300000 774 0 0xd00000>; /* non-prefetchable memory */ 775 776 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "msi"; 778 #interrupt-cells = <1>; 779 interrupt-map-mask = <0 0 0 0x7>; 780 interrupt-map = <0 0 0 1 &intc 0 75 781 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 782 <0 0 0 2 &intc 0 78 783 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 784 <0 0 0 3 &intc 0 79 785 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 786 <0 0 0 4 &intc 0 83 787 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 788 789 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 790 <&gcc GCC_PCIE0_AXI_M_CLK>, 791 <&gcc GCC_PCIE0_AXI_S_CLK>, 792 <&gcc GCC_PCIE0_AHB_CLK>, 793 <&gcc GCC_PCIE0_AUX_CLK>; 794 795 clock-names = "iface", 796 "axi_m", 797 "axi_s", 798 "ahb", 799 "aux"; 800 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 801 <&gcc GCC_PCIE0_SLEEP_ARES>, 802 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 803 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 804 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 805 <&gcc GCC_PCIE0_AHB_ARES>, 806 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 807 reset-names = "pipe", 808 "sleep", 809 "sticky", 810 "axi_m", 811 "axi_s", 812 "ahb", 813 "axi_m_sticky"; 814 status = "disabled"; 815 }; 816 }; 817}; 818