1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 clocks { 14 sleep_clk: sleep_clk { 15 compatible = "fixed-clock"; 16 clock-frequency = <32000>; 17 #clock-cells = <0>; 18 }; 19 20 xo: xo { 21 compatible = "fixed-clock"; 22 clock-frequency = <19200000>; 23 #clock-cells = <0>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <0x1>; 29 #size-cells = <0x0>; 30 31 CPU0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0x0>; 35 next-level-cache = <&L2_0>; 36 enable-method = "psci"; 37 }; 38 39 CPU1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 next-level-cache = <&L2_0>; 45 }; 46 47 CPU2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 next-level-cache = <&L2_0>; 53 }; 54 55 CPU3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <0x2>; 66 }; 67 }; 68 69 pmu { 70 compatible = "arm,cortex-a53-pmu"; 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72 }; 73 74 psci { 75 compatible = "arm,psci-1.0"; 76 method = "smc"; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq8074", "qcom,scm"; 82 }; 83 }; 84 85 soc: soc { 86 #address-cells = <0x1>; 87 #size-cells = <0x1>; 88 ranges = <0 0 0 0xffffffff>; 89 compatible = "simple-bus"; 90 91 ssphy_1: phy@58000 { 92 compatible = "qcom,ipq8074-qmp-usb3-phy"; 93 reg = <0x00058000 0x1c4>; 94 #clock-cells = <1>; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 clocks = <&gcc GCC_USB1_AUX_CLK>, 100 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 101 <&xo>; 102 clock-names = "aux", "cfg_ahb", "ref"; 103 104 resets = <&gcc GCC_USB1_PHY_BCR>, 105 <&gcc GCC_USB3PHY_1_PHY_BCR>; 106 reset-names = "phy","common"; 107 status = "disabled"; 108 109 usb1_ssphy: lane@58200 { 110 reg = <0x00058200 0x130>, /* Tx */ 111 <0x00058400 0x200>, /* Rx */ 112 <0x00058800 0x1f8>, /* PCS */ 113 <0x00058600 0x044>; /* PCS misc*/ 114 #phy-cells = <0>; 115 clocks = <&gcc GCC_USB1_PIPE_CLK>; 116 clock-names = "pipe0"; 117 clock-output-names = "gcc_usb1_pipe_clk_src"; 118 }; 119 }; 120 121 qusb_phy_1: phy@59000 { 122 compatible = "qcom,ipq8074-qusb2-phy"; 123 reg = <0x00059000 0x180>; 124 #phy-cells = <0>; 125 126 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 127 <&xo>; 128 clock-names = "cfg_ahb", "ref"; 129 130 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 131 status = "disabled"; 132 }; 133 134 ssphy_0: phy@78000 { 135 compatible = "qcom,ipq8074-qmp-usb3-phy"; 136 reg = <0x00078000 0x1c4>; 137 #clock-cells = <1>; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges; 141 142 clocks = <&gcc GCC_USB0_AUX_CLK>, 143 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 144 <&xo>; 145 clock-names = "aux", "cfg_ahb", "ref"; 146 147 resets = <&gcc GCC_USB0_PHY_BCR>, 148 <&gcc GCC_USB3PHY_0_PHY_BCR>; 149 reset-names = "phy","common"; 150 status = "disabled"; 151 152 usb0_ssphy: lane@78200 { 153 reg = <0x00078200 0x130>, /* Tx */ 154 <0x00078400 0x200>, /* Rx */ 155 <0x00078800 0x1f8>, /* PCS */ 156 <0x00078600 0x044>; /* PCS misc*/ 157 #phy-cells = <0>; 158 clocks = <&gcc GCC_USB0_PIPE_CLK>; 159 clock-names = "pipe0"; 160 clock-output-names = "gcc_usb0_pipe_clk_src"; 161 }; 162 }; 163 164 qusb_phy_0: phy@79000 { 165 compatible = "qcom,ipq8074-qusb2-phy"; 166 reg = <0x00079000 0x180>; 167 #phy-cells = <0>; 168 169 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 170 <&xo>; 171 clock-names = "cfg_ahb", "ref"; 172 173 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 174 status = "disabled"; 175 }; 176 177 pcie_phy0: phy@86000 { 178 compatible = "qcom,ipq8074-qmp-pcie-phy"; 179 reg = <0x00086000 0x1000>; 180 #phy-cells = <0>; 181 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 182 clock-names = "pipe_clk"; 183 clock-output-names = "pcie20_phy0_pipe_clk"; 184 185 resets = <&gcc GCC_PCIE0_PHY_BCR>, 186 <&gcc GCC_PCIE0PHY_PHY_BCR>; 187 reset-names = "phy", 188 "common"; 189 status = "disabled"; 190 }; 191 192 pcie_phy1: phy@8e000 { 193 compatible = "qcom,ipq8074-qmp-pcie-phy"; 194 reg = <0x0008e000 0x1000>; 195 #phy-cells = <0>; 196 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 197 clock-names = "pipe_clk"; 198 clock-output-names = "pcie20_phy1_pipe_clk"; 199 200 resets = <&gcc GCC_PCIE1_PHY_BCR>, 201 <&gcc GCC_PCIE1PHY_PHY_BCR>; 202 reset-names = "phy", 203 "common"; 204 status = "disabled"; 205 }; 206 207 prng: rng@e3000 { 208 compatible = "qcom,prng-ee"; 209 reg = <0x000e3000 0x1000>; 210 clocks = <&gcc GCC_PRNG_AHB_CLK>; 211 clock-names = "core"; 212 status = "disabled"; 213 }; 214 215 cryptobam: dma-controller@704000 { 216 compatible = "qcom,bam-v1.7.0"; 217 reg = <0x00704000 0x20000>; 218 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 220 clock-names = "bam_clk"; 221 #dma-cells = <1>; 222 qcom,ee = <1>; 223 qcom,controlled-remotely; 224 status = "disabled"; 225 }; 226 227 crypto: crypto@73a000 { 228 compatible = "qcom,crypto-v5.1"; 229 reg = <0x0073a000 0x6000>; 230 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 231 <&gcc GCC_CRYPTO_AXI_CLK>, 232 <&gcc GCC_CRYPTO_CLK>; 233 clock-names = "iface", "bus", "core"; 234 dmas = <&cryptobam 2>, <&cryptobam 3>; 235 dma-names = "rx", "tx"; 236 status = "disabled"; 237 }; 238 239 tlmm: pinctrl@1000000 { 240 compatible = "qcom,ipq8074-pinctrl"; 241 reg = <0x01000000 0x300000>; 242 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 243 gpio-controller; 244 gpio-ranges = <&tlmm 0 0 70>; 245 #gpio-cells = <0x2>; 246 interrupt-controller; 247 #interrupt-cells = <0x2>; 248 249 serial_4_pins: serial4-pinmux { 250 pins = "gpio23", "gpio24"; 251 function = "blsp4_uart1"; 252 drive-strength = <8>; 253 bias-disable; 254 }; 255 256 i2c_0_pins: i2c-0-pinmux { 257 pins = "gpio42", "gpio43"; 258 function = "blsp1_i2c"; 259 drive-strength = <8>; 260 bias-disable; 261 }; 262 263 spi_0_pins: spi-0-pins { 264 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 265 function = "blsp0_spi"; 266 drive-strength = <8>; 267 bias-disable; 268 }; 269 270 hsuart_pins: hsuart-pins { 271 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 272 function = "blsp2_uart"; 273 drive-strength = <8>; 274 bias-disable; 275 }; 276 277 qpic_pins: qpic-pins { 278 pins = "gpio1", "gpio3", "gpio4", 279 "gpio5", "gpio6", "gpio7", 280 "gpio8", "gpio10", "gpio11", 281 "gpio12", "gpio13", "gpio14", 282 "gpio15", "gpio16", "gpio17"; 283 function = "qpic"; 284 drive-strength = <8>; 285 bias-disable; 286 }; 287 }; 288 289 gcc: gcc@1800000 { 290 compatible = "qcom,gcc-ipq8074"; 291 reg = <0x01800000 0x80000>; 292 #clock-cells = <0x1>; 293 #reset-cells = <0x1>; 294 }; 295 296 spmi_bus: spmi@200f000 { 297 compatible = "qcom,spmi-pmic-arb"; 298 reg = <0x0200f000 0x001000>, 299 <0x02400000 0x800000>, 300 <0x02c00000 0x800000>, 301 <0x03800000 0x200000>, 302 <0x0200a000 0x000700>; 303 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 304 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "periph_irq"; 306 qcom,ee = <0>; 307 qcom,channel = <0>; 308 #address-cells = <2>; 309 #size-cells = <0>; 310 interrupt-controller; 311 #interrupt-cells = <4>; 312 cell-index = <0>; 313 }; 314 315 sdhc_1: sdhci@7824900 { 316 compatible = "qcom,sdhci-msm-v4"; 317 reg = <0x7824900 0x500>, <0x7824000 0x800>; 318 reg-names = "hc_mem", "core_mem"; 319 320 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 322 interrupt-names = "hc_irq", "pwr_irq"; 323 324 clocks = <&xo>, 325 <&gcc GCC_SDCC1_AHB_CLK>, 326 <&gcc GCC_SDCC1_APPS_CLK>; 327 clock-names = "xo", "iface", "core"; 328 max-frequency = <384000000>; 329 mmc-ddr-1_8v; 330 mmc-hs200-1_8v; 331 mmc-hs400-1_8v; 332 bus-width = <8>; 333 334 status = "disabled"; 335 }; 336 337 blsp_dma: dma-controller@7884000 { 338 compatible = "qcom,bam-v1.7.0"; 339 reg = <0x07884000 0x2b000>; 340 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 342 clock-names = "bam_clk"; 343 #dma-cells = <1>; 344 qcom,ee = <0>; 345 }; 346 347 blsp1_uart1: serial@78af000 { 348 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 349 reg = <0x078af000 0x200>; 350 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 352 <&gcc GCC_BLSP1_AHB_CLK>; 353 clock-names = "core", "iface"; 354 status = "disabled"; 355 }; 356 357 blsp1_uart3: serial@78b1000 { 358 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 359 reg = <0x078b1000 0x200>; 360 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 362 <&gcc GCC_BLSP1_AHB_CLK>; 363 clock-names = "core", "iface"; 364 dmas = <&blsp_dma 4>, 365 <&blsp_dma 5>; 366 dma-names = "tx", "rx"; 367 pinctrl-0 = <&hsuart_pins>; 368 pinctrl-names = "default"; 369 status = "disabled"; 370 }; 371 372 blsp1_uart5: serial@78b3000 { 373 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 374 reg = <0x078b3000 0x200>; 375 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 377 <&gcc GCC_BLSP1_AHB_CLK>; 378 clock-names = "core", "iface"; 379 pinctrl-0 = <&serial_4_pins>; 380 pinctrl-names = "default"; 381 status = "disabled"; 382 }; 383 384 blsp1_spi1: spi@78b5000 { 385 compatible = "qcom,spi-qup-v2.2.1"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <0x078b5000 0x600>; 389 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 390 spi-max-frequency = <50000000>; 391 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 392 <&gcc GCC_BLSP1_AHB_CLK>; 393 clock-names = "core", "iface"; 394 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 395 dma-names = "tx", "rx"; 396 pinctrl-0 = <&spi_0_pins>; 397 pinctrl-names = "default"; 398 status = "disabled"; 399 }; 400 401 blsp1_i2c2: i2c@78b6000 { 402 compatible = "qcom,i2c-qup-v2.2.1"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 reg = <0x078b6000 0x600>; 406 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 408 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 409 clock-names = "iface", "core"; 410 clock-frequency = <400000>; 411 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 412 dma-names = "rx", "tx"; 413 pinctrl-0 = <&i2c_0_pins>; 414 pinctrl-names = "default"; 415 status = "disabled"; 416 }; 417 418 blsp1_i2c3: i2c@78b7000 { 419 compatible = "qcom,i2c-qup-v2.2.1"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <0x078b7000 0x600>; 423 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 425 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 426 clock-names = "iface", "core"; 427 clock-frequency = <100000>; 428 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 429 dma-names = "rx", "tx"; 430 status = "disabled"; 431 }; 432 433 blsp1_i2c6: i2c@78ba000 { 434 compatible = "qcom,i2c-qup-v2.2.1"; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 reg = <0x078ba000 0x600>; 438 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 440 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 441 clock-names = "iface", "core"; 442 clock-frequency = <100000>; 443 dmas = <&blsp_dma 23>, <&blsp_dma 22>; 444 dma-names = "rx", "tx"; 445 status = "disabled"; 446 }; 447 448 qpic_bam: dma-controller@7984000 { 449 compatible = "qcom,bam-v1.7.0"; 450 reg = <0x07984000 0x1a000>; 451 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&gcc GCC_QPIC_AHB_CLK>; 453 clock-names = "bam_clk"; 454 #dma-cells = <1>; 455 qcom,ee = <0>; 456 status = "disabled"; 457 }; 458 459 qpic_nand: nand@79b0000 { 460 compatible = "qcom,ipq8074-nand"; 461 reg = <0x079b0000 0x10000>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 clocks = <&gcc GCC_QPIC_CLK>, 465 <&gcc GCC_QPIC_AHB_CLK>; 466 clock-names = "core", "aon"; 467 468 dmas = <&qpic_bam 0>, 469 <&qpic_bam 1>, 470 <&qpic_bam 2>; 471 dma-names = "tx", "rx", "cmd"; 472 pinctrl-0 = <&qpic_pins>; 473 pinctrl-names = "default"; 474 status = "disabled"; 475 }; 476 477 usb_0: usb@8af8800 { 478 compatible = "qcom,dwc3"; 479 reg = <0x08af8800 0x400>; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 ranges; 483 484 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 485 <&gcc GCC_USB0_MASTER_CLK>, 486 <&gcc GCC_USB0_SLEEP_CLK>, 487 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 488 clock-names = "sys_noc_axi", 489 "master", 490 "sleep", 491 "mock_utmi"; 492 493 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 494 <&gcc GCC_USB0_MASTER_CLK>, 495 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 496 assigned-clock-rates = <133330000>, 497 <133330000>, 498 <19200000>; 499 500 resets = <&gcc GCC_USB0_BCR>; 501 status = "disabled"; 502 503 dwc_0: dwc3@8a00000 { 504 compatible = "snps,dwc3"; 505 reg = <0x8a00000 0xcd00>; 506 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 507 phys = <&qusb_phy_0>, <&usb0_ssphy>; 508 phy-names = "usb2-phy", "usb3-phy"; 509 snps,is-utmi-l1-suspend; 510 snps,hird-threshold = /bits/ 8 <0x0>; 511 snps,dis_u2_susphy_quirk; 512 snps,dis_u3_susphy_quirk; 513 dr_mode = "host"; 514 }; 515 }; 516 517 usb_1: usb@8cf8800 { 518 compatible = "qcom,dwc3"; 519 reg = <0x08cf8800 0x400>; 520 #address-cells = <1>; 521 #size-cells = <1>; 522 ranges; 523 524 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 525 <&gcc GCC_USB1_MASTER_CLK>, 526 <&gcc GCC_USB1_SLEEP_CLK>, 527 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 528 clock-names = "sys_noc_axi", 529 "master", 530 "sleep", 531 "mock_utmi"; 532 533 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 534 <&gcc GCC_USB1_MASTER_CLK>, 535 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 536 assigned-clock-rates = <133330000>, 537 <133330000>, 538 <19200000>; 539 540 resets = <&gcc GCC_USB1_BCR>; 541 status = "disabled"; 542 543 dwc_1: dwc3@8c00000 { 544 compatible = "snps,dwc3"; 545 reg = <0x8c00000 0xcd00>; 546 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 547 phys = <&qusb_phy_1>, <&usb1_ssphy>; 548 phy-names = "usb2-phy", "usb3-phy"; 549 snps,is-utmi-l1-suspend; 550 snps,hird-threshold = /bits/ 8 <0x0>; 551 snps,dis_u2_susphy_quirk; 552 snps,dis_u3_susphy_quirk; 553 dr_mode = "host"; 554 }; 555 }; 556 557 intc: interrupt-controller@b000000 { 558 compatible = "qcom,msm-qgic2"; 559 interrupt-controller; 560 #interrupt-cells = <0x3>; 561 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 562 }; 563 564 timer { 565 compatible = "arm,armv8-timer"; 566 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 567 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 568 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 569 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 570 }; 571 572 watchdog: watchdog@b017000 { 573 compatible = "qcom,kpss-wdt"; 574 reg = <0xb017000 0x1000>; 575 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 576 clocks = <&sleep_clk>; 577 timeout-sec = <30>; 578 }; 579 580 timer@b120000 { 581 #address-cells = <1>; 582 #size-cells = <1>; 583 ranges; 584 compatible = "arm,armv7-timer-mem"; 585 reg = <0x0b120000 0x1000>; 586 clock-frequency = <19200000>; 587 588 frame@b120000 { 589 frame-number = <0>; 590 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 592 reg = <0x0b121000 0x1000>, 593 <0x0b122000 0x1000>; 594 }; 595 596 frame@b123000 { 597 frame-number = <1>; 598 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 599 reg = <0x0b123000 0x1000>; 600 status = "disabled"; 601 }; 602 603 frame@b124000 { 604 frame-number = <2>; 605 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 606 reg = <0x0b124000 0x1000>; 607 status = "disabled"; 608 }; 609 610 frame@b125000 { 611 frame-number = <3>; 612 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 613 reg = <0x0b125000 0x1000>; 614 status = "disabled"; 615 }; 616 617 frame@b126000 { 618 frame-number = <4>; 619 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 620 reg = <0x0b126000 0x1000>; 621 status = "disabled"; 622 }; 623 624 frame@b127000 { 625 frame-number = <5>; 626 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 627 reg = <0x0b127000 0x1000>; 628 status = "disabled"; 629 }; 630 631 frame@b128000 { 632 frame-number = <6>; 633 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 634 reg = <0x0b128000 0x1000>; 635 status = "disabled"; 636 }; 637 }; 638 639 pcie1: pci@10000000 { 640 compatible = "qcom,pcie-ipq8074"; 641 reg = <0x10000000 0xf1d>, 642 <0x10000f20 0xa8>, 643 <0x00088000 0x2000>, 644 <0x10100000 0x1000>; 645 reg-names = "dbi", "elbi", "parf", "config"; 646 device_type = "pci"; 647 linux,pci-domain = <1>; 648 bus-range = <0x00 0xff>; 649 num-lanes = <1>; 650 #address-cells = <3>; 651 #size-cells = <2>; 652 653 phys = <&pcie_phy1>; 654 phy-names = "pciephy"; 655 656 ranges = <0x81000000 0 0x10200000 0x10200000 657 0 0x100000 /* downstream I/O */ 658 0x82000000 0 0x10300000 0x10300000 659 0 0xd00000>; /* non-prefetchable memory */ 660 661 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "msi"; 663 #interrupt-cells = <1>; 664 interrupt-map-mask = <0 0 0 0x7>; 665 interrupt-map = <0 0 0 1 &intc 0 142 666 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 667 <0 0 0 2 &intc 0 143 668 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 669 <0 0 0 3 &intc 0 144 670 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 671 <0 0 0 4 &intc 0 145 672 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 673 674 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 675 <&gcc GCC_PCIE1_AXI_M_CLK>, 676 <&gcc GCC_PCIE1_AXI_S_CLK>, 677 <&gcc GCC_PCIE1_AHB_CLK>, 678 <&gcc GCC_PCIE1_AUX_CLK>; 679 clock-names = "iface", 680 "axi_m", 681 "axi_s", 682 "ahb", 683 "aux"; 684 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 685 <&gcc GCC_PCIE1_SLEEP_ARES>, 686 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 687 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 688 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 689 <&gcc GCC_PCIE1_AHB_ARES>, 690 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 691 reset-names = "pipe", 692 "sleep", 693 "sticky", 694 "axi_m", 695 "axi_s", 696 "ahb", 697 "axi_m_sticky"; 698 status = "disabled"; 699 }; 700 701 pcie0: pci@20000000 { 702 compatible = "qcom,pcie-ipq8074"; 703 reg = <0x20000000 0xf1d>, 704 <0x20000f20 0xa8>, 705 <0x00080000 0x2000>, 706 <0x20100000 0x1000>; 707 reg-names = "dbi", "elbi", "parf", "config"; 708 device_type = "pci"; 709 linux,pci-domain = <0>; 710 bus-range = <0x00 0xff>; 711 num-lanes = <1>; 712 #address-cells = <3>; 713 #size-cells = <2>; 714 715 phys = <&pcie_phy0>; 716 phy-names = "pciephy"; 717 718 ranges = <0x81000000 0 0x20200000 0x20200000 719 0 0x100000 /* downstream I/O */ 720 0x82000000 0 0x20300000 0x20300000 721 0 0xd00000>; /* non-prefetchable memory */ 722 723 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-names = "msi"; 725 #interrupt-cells = <1>; 726 interrupt-map-mask = <0 0 0 0x7>; 727 interrupt-map = <0 0 0 1 &intc 0 75 728 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 729 <0 0 0 2 &intc 0 78 730 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 731 <0 0 0 3 &intc 0 79 732 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 733 <0 0 0 4 &intc 0 83 734 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 735 736 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 737 <&gcc GCC_PCIE0_AXI_M_CLK>, 738 <&gcc GCC_PCIE0_AXI_S_CLK>, 739 <&gcc GCC_PCIE0_AHB_CLK>, 740 <&gcc GCC_PCIE0_AUX_CLK>; 741 742 clock-names = "iface", 743 "axi_m", 744 "axi_s", 745 "ahb", 746 "aux"; 747 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 748 <&gcc GCC_PCIE0_SLEEP_ARES>, 749 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 750 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 751 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 752 <&gcc GCC_PCIE0_AHB_ARES>, 753 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 754 reset-names = "pipe", 755 "sleep", 756 "sticky", 757 "axi_m", 758 "axi_s", 759 "ahb", 760 "axi_m_sticky"; 761 status = "disabled"; 762 }; 763 }; 764}; 765