1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 clocks { 14 sleep_clk: sleep_clk { 15 compatible = "fixed-clock"; 16 clock-frequency = <32000>; 17 #clock-cells = <0>; 18 }; 19 20 xo: xo { 21 compatible = "fixed-clock"; 22 clock-frequency = <19200000>; 23 #clock-cells = <0>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <0x1>; 29 #size-cells = <0x0>; 30 31 CPU0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0x0>; 35 next-level-cache = <&L2_0>; 36 enable-method = "psci"; 37 }; 38 39 CPU1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 next-level-cache = <&L2_0>; 45 }; 46 47 CPU2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 next-level-cache = <&L2_0>; 53 }; 54 55 CPU3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <0x2>; 66 }; 67 }; 68 69 pmu { 70 compatible = "arm,cortex-a53-pmu"; 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72 }; 73 74 psci { 75 compatible = "arm,psci-1.0"; 76 method = "smc"; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq8074", "qcom,scm"; 82 }; 83 }; 84 85 soc: soc { 86 #address-cells = <0x1>; 87 #size-cells = <0x1>; 88 ranges = <0 0 0 0xffffffff>; 89 compatible = "simple-bus"; 90 91 ssphy_1: phy@58000 { 92 compatible = "qcom,ipq8074-qmp-usb3-phy"; 93 reg = <0x00058000 0x1c4>; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 ranges; 97 98 clocks = <&gcc GCC_USB1_AUX_CLK>, 99 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 100 <&xo>; 101 clock-names = "aux", "cfg_ahb", "ref"; 102 103 resets = <&gcc GCC_USB1_PHY_BCR>, 104 <&gcc GCC_USB3PHY_1_PHY_BCR>; 105 reset-names = "phy","common"; 106 status = "disabled"; 107 108 usb1_ssphy: phy@58200 { 109 reg = <0x00058200 0x130>, /* Tx */ 110 <0x00058400 0x200>, /* Rx */ 111 <0x00058800 0x1f8>, /* PCS */ 112 <0x00058600 0x044>; /* PCS misc*/ 113 #phy-cells = <0>; 114 #clock-cells = <1>; 115 clocks = <&gcc GCC_USB1_PIPE_CLK>; 116 clock-names = "pipe0"; 117 clock-output-names = "gcc_usb1_pipe_clk_src"; 118 }; 119 }; 120 121 qusb_phy_1: phy@59000 { 122 compatible = "qcom,ipq8074-qusb2-phy"; 123 reg = <0x00059000 0x180>; 124 #phy-cells = <0>; 125 126 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 127 <&xo>; 128 clock-names = "cfg_ahb", "ref"; 129 130 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 131 status = "disabled"; 132 }; 133 134 ssphy_0: phy@78000 { 135 compatible = "qcom,ipq8074-qmp-usb3-phy"; 136 reg = <0x00078000 0x1c4>; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges; 140 141 clocks = <&gcc GCC_USB0_AUX_CLK>, 142 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 143 <&xo>; 144 clock-names = "aux", "cfg_ahb", "ref"; 145 146 resets = <&gcc GCC_USB0_PHY_BCR>, 147 <&gcc GCC_USB3PHY_0_PHY_BCR>; 148 reset-names = "phy","common"; 149 status = "disabled"; 150 151 usb0_ssphy: phy@78200 { 152 reg = <0x00078200 0x130>, /* Tx */ 153 <0x00078400 0x200>, /* Rx */ 154 <0x00078800 0x1f8>, /* PCS */ 155 <0x00078600 0x044>; /* PCS misc*/ 156 #phy-cells = <0>; 157 #clock-cells = <1>; 158 clocks = <&gcc GCC_USB0_PIPE_CLK>; 159 clock-names = "pipe0"; 160 clock-output-names = "gcc_usb0_pipe_clk_src"; 161 }; 162 }; 163 164 qusb_phy_0: phy@79000 { 165 compatible = "qcom,ipq8074-qusb2-phy"; 166 reg = <0x00079000 0x180>; 167 #phy-cells = <0>; 168 169 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 170 <&xo>; 171 clock-names = "cfg_ahb", "ref"; 172 173 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 174 status = "disabled"; 175 }; 176 177 pcie_qmp0: phy@86000 { 178 compatible = "qcom,ipq8074-qmp-pcie-phy"; 179 reg = <0x00086000 0x1000>; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 184 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 185 <&gcc GCC_PCIE0_AHB_CLK>; 186 clock-names = "aux", "cfg_ahb"; 187 resets = <&gcc GCC_PCIE0_PHY_BCR>, 188 <&gcc GCC_PCIE0PHY_PHY_BCR>; 189 reset-names = "phy", 190 "common"; 191 status = "disabled"; 192 193 pcie_phy0: phy@86200 { 194 reg = <0x86200 0x16c>, 195 <0x86400 0x200>, 196 <0x86800 0x4f4>; 197 #phy-cells = <0>; 198 #clock-cells = <0>; 199 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 200 clock-names = "pipe0"; 201 clock-output-names = "pcie_0_pipe_clk"; 202 }; 203 }; 204 205 pcie_qmp1: phy@8e000 { 206 compatible = "qcom,ipq8074-qmp-pcie-phy"; 207 reg = <0x0008e000 0x1000>; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 213 <&gcc GCC_PCIE1_AHB_CLK>; 214 clock-names = "aux", "cfg_ahb"; 215 resets = <&gcc GCC_PCIE1_PHY_BCR>, 216 <&gcc GCC_PCIE1PHY_PHY_BCR>; 217 reset-names = "phy", 218 "common"; 219 status = "disabled"; 220 221 pcie_phy1: phy@8e200 { 222 reg = <0x8e200 0x16c>, 223 <0x8e400 0x200>, 224 <0x8e800 0x4f4>; 225 #phy-cells = <0>; 226 #clock-cells = <0>; 227 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 228 clock-names = "pipe0"; 229 clock-output-names = "pcie_1_pipe_clk"; 230 }; 231 }; 232 233 prng: rng@e3000 { 234 compatible = "qcom,prng-ee"; 235 reg = <0x000e3000 0x1000>; 236 clocks = <&gcc GCC_PRNG_AHB_CLK>; 237 clock-names = "core"; 238 status = "disabled"; 239 }; 240 241 cryptobam: dma-controller@704000 { 242 compatible = "qcom,bam-v1.7.0"; 243 reg = <0x00704000 0x20000>; 244 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 246 clock-names = "bam_clk"; 247 #dma-cells = <1>; 248 qcom,ee = <1>; 249 qcom,controlled-remotely; 250 status = "disabled"; 251 }; 252 253 crypto: crypto@73a000 { 254 compatible = "qcom,crypto-v5.1"; 255 reg = <0x0073a000 0x6000>; 256 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 257 <&gcc GCC_CRYPTO_AXI_CLK>, 258 <&gcc GCC_CRYPTO_CLK>; 259 clock-names = "iface", "bus", "core"; 260 dmas = <&cryptobam 2>, <&cryptobam 3>; 261 dma-names = "rx", "tx"; 262 status = "disabled"; 263 }; 264 265 tlmm: pinctrl@1000000 { 266 compatible = "qcom,ipq8074-pinctrl"; 267 reg = <0x01000000 0x300000>; 268 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 269 gpio-controller; 270 gpio-ranges = <&tlmm 0 0 70>; 271 #gpio-cells = <0x2>; 272 interrupt-controller; 273 #interrupt-cells = <0x2>; 274 275 serial_4_pins: serial4-pinmux { 276 pins = "gpio23", "gpio24"; 277 function = "blsp4_uart1"; 278 drive-strength = <8>; 279 bias-disable; 280 }; 281 282 i2c_0_pins: i2c-0-pinmux { 283 pins = "gpio42", "gpio43"; 284 function = "blsp1_i2c"; 285 drive-strength = <8>; 286 bias-disable; 287 }; 288 289 spi_0_pins: spi-0-pins { 290 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 291 function = "blsp0_spi"; 292 drive-strength = <8>; 293 bias-disable; 294 }; 295 296 hsuart_pins: hsuart-pins { 297 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 298 function = "blsp2_uart"; 299 drive-strength = <8>; 300 bias-disable; 301 }; 302 303 qpic_pins: qpic-pins { 304 pins = "gpio1", "gpio3", "gpio4", 305 "gpio5", "gpio6", "gpio7", 306 "gpio8", "gpio10", "gpio11", 307 "gpio12", "gpio13", "gpio14", 308 "gpio15", "gpio16", "gpio17"; 309 function = "qpic"; 310 drive-strength = <8>; 311 bias-disable; 312 }; 313 }; 314 315 gcc: gcc@1800000 { 316 compatible = "qcom,gcc-ipq8074"; 317 reg = <0x01800000 0x80000>; 318 #clock-cells = <0x1>; 319 #reset-cells = <0x1>; 320 }; 321 322 spmi_bus: spmi@200f000 { 323 compatible = "qcom,spmi-pmic-arb"; 324 reg = <0x0200f000 0x001000>, 325 <0x02400000 0x800000>, 326 <0x02c00000 0x800000>, 327 <0x03800000 0x200000>, 328 <0x0200a000 0x000700>; 329 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 330 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 331 interrupt-names = "periph_irq"; 332 qcom,ee = <0>; 333 qcom,channel = <0>; 334 #address-cells = <2>; 335 #size-cells = <0>; 336 interrupt-controller; 337 #interrupt-cells = <4>; 338 cell-index = <0>; 339 }; 340 341 sdhc_1: sdhci@7824900 { 342 compatible = "qcom,sdhci-msm-v4"; 343 reg = <0x7824900 0x500>, <0x7824000 0x800>; 344 reg-names = "hc_mem", "core_mem"; 345 346 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "hc_irq", "pwr_irq"; 349 350 clocks = <&xo>, 351 <&gcc GCC_SDCC1_AHB_CLK>, 352 <&gcc GCC_SDCC1_APPS_CLK>; 353 clock-names = "xo", "iface", "core"; 354 max-frequency = <384000000>; 355 mmc-ddr-1_8v; 356 mmc-hs200-1_8v; 357 mmc-hs400-1_8v; 358 bus-width = <8>; 359 360 status = "disabled"; 361 }; 362 363 blsp_dma: dma-controller@7884000 { 364 compatible = "qcom,bam-v1.7.0"; 365 reg = <0x07884000 0x2b000>; 366 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 368 clock-names = "bam_clk"; 369 #dma-cells = <1>; 370 qcom,ee = <0>; 371 }; 372 373 blsp1_uart1: serial@78af000 { 374 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 375 reg = <0x078af000 0x200>; 376 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 378 <&gcc GCC_BLSP1_AHB_CLK>; 379 clock-names = "core", "iface"; 380 status = "disabled"; 381 }; 382 383 blsp1_uart3: serial@78b1000 { 384 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 385 reg = <0x078b1000 0x200>; 386 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 388 <&gcc GCC_BLSP1_AHB_CLK>; 389 clock-names = "core", "iface"; 390 dmas = <&blsp_dma 4>, 391 <&blsp_dma 5>; 392 dma-names = "tx", "rx"; 393 pinctrl-0 = <&hsuart_pins>; 394 pinctrl-names = "default"; 395 status = "disabled"; 396 }; 397 398 blsp1_uart5: serial@78b3000 { 399 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 400 reg = <0x078b3000 0x200>; 401 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 403 <&gcc GCC_BLSP1_AHB_CLK>; 404 clock-names = "core", "iface"; 405 pinctrl-0 = <&serial_4_pins>; 406 pinctrl-names = "default"; 407 status = "disabled"; 408 }; 409 410 blsp1_spi1: spi@78b5000 { 411 compatible = "qcom,spi-qup-v2.2.1"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <0x078b5000 0x600>; 415 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 416 spi-max-frequency = <50000000>; 417 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 418 <&gcc GCC_BLSP1_AHB_CLK>; 419 clock-names = "core", "iface"; 420 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 421 dma-names = "tx", "rx"; 422 pinctrl-0 = <&spi_0_pins>; 423 pinctrl-names = "default"; 424 status = "disabled"; 425 }; 426 427 blsp1_i2c2: i2c@78b6000 { 428 compatible = "qcom,i2c-qup-v2.2.1"; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 reg = <0x078b6000 0x600>; 432 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 434 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 435 clock-names = "iface", "core"; 436 clock-frequency = <400000>; 437 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 438 dma-names = "rx", "tx"; 439 pinctrl-0 = <&i2c_0_pins>; 440 pinctrl-names = "default"; 441 status = "disabled"; 442 }; 443 444 blsp1_i2c3: i2c@78b7000 { 445 compatible = "qcom,i2c-qup-v2.2.1"; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 reg = <0x078b7000 0x600>; 449 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 451 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 452 clock-names = "iface", "core"; 453 clock-frequency = <100000>; 454 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 455 dma-names = "rx", "tx"; 456 status = "disabled"; 457 }; 458 459 blsp1_i2c5: i2c@78b9000 { 460 compatible = "qcom,i2c-qup-v2.2.1"; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 reg = <0x78b9000 0x600>; 464 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 466 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 467 clock-names = "iface", "core"; 468 clock-frequency = <400000>; 469 dmas = <&blsp_dma 21>, <&blsp_dma 20>; 470 dma-names = "rx", "tx"; 471 status = "disabled"; 472 }; 473 474 blsp1_i2c6: i2c@78ba000 { 475 compatible = "qcom,i2c-qup-v2.2.1"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <0x078ba000 0x600>; 479 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 481 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 482 clock-names = "iface", "core"; 483 clock-frequency = <100000>; 484 dmas = <&blsp_dma 23>, <&blsp_dma 22>; 485 dma-names = "rx", "tx"; 486 status = "disabled"; 487 }; 488 489 qpic_bam: dma-controller@7984000 { 490 compatible = "qcom,bam-v1.7.0"; 491 reg = <0x07984000 0x1a000>; 492 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&gcc GCC_QPIC_AHB_CLK>; 494 clock-names = "bam_clk"; 495 #dma-cells = <1>; 496 qcom,ee = <0>; 497 status = "disabled"; 498 }; 499 500 qpic_nand: nand@79b0000 { 501 compatible = "qcom,ipq8074-nand"; 502 reg = <0x079b0000 0x10000>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clocks = <&gcc GCC_QPIC_CLK>, 506 <&gcc GCC_QPIC_AHB_CLK>; 507 clock-names = "core", "aon"; 508 509 dmas = <&qpic_bam 0>, 510 <&qpic_bam 1>, 511 <&qpic_bam 2>; 512 dma-names = "tx", "rx", "cmd"; 513 pinctrl-0 = <&qpic_pins>; 514 pinctrl-names = "default"; 515 status = "disabled"; 516 }; 517 518 usb_0: usb@8af8800 { 519 compatible = "qcom,dwc3"; 520 reg = <0x08af8800 0x400>; 521 #address-cells = <1>; 522 #size-cells = <1>; 523 ranges; 524 525 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 526 <&gcc GCC_USB0_MASTER_CLK>, 527 <&gcc GCC_USB0_SLEEP_CLK>, 528 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 529 clock-names = "sys_noc_axi", 530 "master", 531 "sleep", 532 "mock_utmi"; 533 534 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 535 <&gcc GCC_USB0_MASTER_CLK>, 536 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 537 assigned-clock-rates = <133330000>, 538 <133330000>, 539 <19200000>; 540 541 resets = <&gcc GCC_USB0_BCR>; 542 status = "disabled"; 543 544 dwc_0: dwc3@8a00000 { 545 compatible = "snps,dwc3"; 546 reg = <0x8a00000 0xcd00>; 547 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 548 phys = <&qusb_phy_0>, <&usb0_ssphy>; 549 phy-names = "usb2-phy", "usb3-phy"; 550 snps,is-utmi-l1-suspend; 551 snps,hird-threshold = /bits/ 8 <0x0>; 552 snps,dis_u2_susphy_quirk; 553 snps,dis_u3_susphy_quirk; 554 dr_mode = "host"; 555 }; 556 }; 557 558 usb_1: usb@8cf8800 { 559 compatible = "qcom,dwc3"; 560 reg = <0x08cf8800 0x400>; 561 #address-cells = <1>; 562 #size-cells = <1>; 563 ranges; 564 565 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 566 <&gcc GCC_USB1_MASTER_CLK>, 567 <&gcc GCC_USB1_SLEEP_CLK>, 568 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 569 clock-names = "sys_noc_axi", 570 "master", 571 "sleep", 572 "mock_utmi"; 573 574 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 575 <&gcc GCC_USB1_MASTER_CLK>, 576 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 577 assigned-clock-rates = <133330000>, 578 <133330000>, 579 <19200000>; 580 581 resets = <&gcc GCC_USB1_BCR>; 582 status = "disabled"; 583 584 dwc_1: dwc3@8c00000 { 585 compatible = "snps,dwc3"; 586 reg = <0x8c00000 0xcd00>; 587 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 588 phys = <&qusb_phy_1>, <&usb1_ssphy>; 589 phy-names = "usb2-phy", "usb3-phy"; 590 snps,is-utmi-l1-suspend; 591 snps,hird-threshold = /bits/ 8 <0x0>; 592 snps,dis_u2_susphy_quirk; 593 snps,dis_u3_susphy_quirk; 594 dr_mode = "host"; 595 }; 596 }; 597 598 intc: interrupt-controller@b000000 { 599 compatible = "qcom,msm-qgic2"; 600 interrupt-controller; 601 #interrupt-cells = <0x3>; 602 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 603 }; 604 605 timer { 606 compatible = "arm,armv8-timer"; 607 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 608 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 609 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 610 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 611 }; 612 613 watchdog: watchdog@b017000 { 614 compatible = "qcom,kpss-wdt"; 615 reg = <0xb017000 0x1000>; 616 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 617 clocks = <&sleep_clk>; 618 timeout-sec = <30>; 619 }; 620 621 timer@b120000 { 622 #address-cells = <1>; 623 #size-cells = <1>; 624 ranges; 625 compatible = "arm,armv7-timer-mem"; 626 reg = <0x0b120000 0x1000>; 627 clock-frequency = <19200000>; 628 629 frame@b120000 { 630 frame-number = <0>; 631 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 633 reg = <0x0b121000 0x1000>, 634 <0x0b122000 0x1000>; 635 }; 636 637 frame@b123000 { 638 frame-number = <1>; 639 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 640 reg = <0x0b123000 0x1000>; 641 status = "disabled"; 642 }; 643 644 frame@b124000 { 645 frame-number = <2>; 646 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 647 reg = <0x0b124000 0x1000>; 648 status = "disabled"; 649 }; 650 651 frame@b125000 { 652 frame-number = <3>; 653 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 654 reg = <0x0b125000 0x1000>; 655 status = "disabled"; 656 }; 657 658 frame@b126000 { 659 frame-number = <4>; 660 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 661 reg = <0x0b126000 0x1000>; 662 status = "disabled"; 663 }; 664 665 frame@b127000 { 666 frame-number = <5>; 667 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 668 reg = <0x0b127000 0x1000>; 669 status = "disabled"; 670 }; 671 672 frame@b128000 { 673 frame-number = <6>; 674 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 675 reg = <0x0b128000 0x1000>; 676 status = "disabled"; 677 }; 678 }; 679 680 pcie1: pci@10000000 { 681 compatible = "qcom,pcie-ipq8074"; 682 reg = <0x10000000 0xf1d>, 683 <0x10000f20 0xa8>, 684 <0x00088000 0x2000>, 685 <0x10100000 0x1000>; 686 reg-names = "dbi", "elbi", "parf", "config"; 687 device_type = "pci"; 688 linux,pci-domain = <1>; 689 bus-range = <0x00 0xff>; 690 num-lanes = <1>; 691 #address-cells = <3>; 692 #size-cells = <2>; 693 694 phys = <&pcie_phy1>; 695 phy-names = "pciephy"; 696 697 ranges = <0x81000000 0 0x10200000 0x10200000 698 0 0x100000 /* downstream I/O */ 699 0x82000000 0 0x10300000 0x10300000 700 0 0xd00000>; /* non-prefetchable memory */ 701 702 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "msi"; 704 #interrupt-cells = <1>; 705 interrupt-map-mask = <0 0 0 0x7>; 706 interrupt-map = <0 0 0 1 &intc 0 142 707 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 708 <0 0 0 2 &intc 0 143 709 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 710 <0 0 0 3 &intc 0 144 711 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 712 <0 0 0 4 &intc 0 145 713 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 714 715 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 716 <&gcc GCC_PCIE1_AXI_M_CLK>, 717 <&gcc GCC_PCIE1_AXI_S_CLK>, 718 <&gcc GCC_PCIE1_AHB_CLK>, 719 <&gcc GCC_PCIE1_AUX_CLK>; 720 clock-names = "iface", 721 "axi_m", 722 "axi_s", 723 "ahb", 724 "aux"; 725 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 726 <&gcc GCC_PCIE1_SLEEP_ARES>, 727 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 728 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 729 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 730 <&gcc GCC_PCIE1_AHB_ARES>, 731 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 732 reset-names = "pipe", 733 "sleep", 734 "sticky", 735 "axi_m", 736 "axi_s", 737 "ahb", 738 "axi_m_sticky"; 739 status = "disabled"; 740 }; 741 742 pcie0: pci@20000000 { 743 compatible = "qcom,pcie-ipq8074"; 744 reg = <0x20000000 0xf1d>, 745 <0x20000f20 0xa8>, 746 <0x00080000 0x2000>, 747 <0x20100000 0x1000>; 748 reg-names = "dbi", "elbi", "parf", "config"; 749 device_type = "pci"; 750 linux,pci-domain = <0>; 751 bus-range = <0x00 0xff>; 752 num-lanes = <1>; 753 #address-cells = <3>; 754 #size-cells = <2>; 755 756 phys = <&pcie_phy0>; 757 phy-names = "pciephy"; 758 759 ranges = <0x81000000 0 0x20200000 0x20200000 760 0 0x100000 /* downstream I/O */ 761 0x82000000 0 0x20300000 0x20300000 762 0 0xd00000>; /* non-prefetchable memory */ 763 764 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "msi"; 766 #interrupt-cells = <1>; 767 interrupt-map-mask = <0 0 0 0x7>; 768 interrupt-map = <0 0 0 1 &intc 0 75 769 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 770 <0 0 0 2 &intc 0 78 771 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 772 <0 0 0 3 &intc 0 79 773 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 774 <0 0 0 4 &intc 0 83 775 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 776 777 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 778 <&gcc GCC_PCIE0_AXI_M_CLK>, 779 <&gcc GCC_PCIE0_AXI_S_CLK>, 780 <&gcc GCC_PCIE0_AHB_CLK>, 781 <&gcc GCC_PCIE0_AUX_CLK>; 782 783 clock-names = "iface", 784 "axi_m", 785 "axi_s", 786 "ahb", 787 "aux"; 788 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 789 <&gcc GCC_PCIE0_SLEEP_ARES>, 790 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 791 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 792 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 793 <&gcc GCC_PCIE0_AHB_ARES>, 794 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 795 reset-names = "pipe", 796 "sleep", 797 "sticky", 798 "axi_m", 799 "axi_s", 800 "ahb", 801 "axi_m_sticky"; 802 status = "disabled"; 803 }; 804 }; 805}; 806