197fb5e8dSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 241dac73eSVaradarajan Narayanan/* 341dac73eSVaradarajan Narayanan * Copyright (c) 2017, The Linux Foundation. All rights reserved. 441dac73eSVaradarajan Narayanan */ 541dac73eSVaradarajan Narayanan 641dac73eSVaradarajan Narayanan#include <dt-bindings/interrupt-controller/arm-gic.h> 741dac73eSVaradarajan Narayanan#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 841dac73eSVaradarajan Narayanan 941dac73eSVaradarajan Narayanan/ { 1041dac73eSVaradarajan Narayanan model = "Qualcomm Technologies, Inc. IPQ8074"; 1141dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074"; 1241dac73eSVaradarajan Narayanan 13e8a7fdc5SSivaprakash Murugesan clocks { 14e8a7fdc5SSivaprakash Murugesan sleep_clk: sleep_clk { 15e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 16e8a7fdc5SSivaprakash Murugesan clock-frequency = <32000>; 17e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 18e8a7fdc5SSivaprakash Murugesan }; 19e8a7fdc5SSivaprakash Murugesan 20e8a7fdc5SSivaprakash Murugesan xo: xo { 21e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 22e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 23e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 24e8a7fdc5SSivaprakash Murugesan }; 25e8a7fdc5SSivaprakash Murugesan }; 26e8a7fdc5SSivaprakash Murugesan 27e8a7fdc5SSivaprakash Murugesan cpus { 28e8a7fdc5SSivaprakash Murugesan #address-cells = <0x1>; 29e8a7fdc5SSivaprakash Murugesan #size-cells = <0x0>; 30e8a7fdc5SSivaprakash Murugesan 31e8a7fdc5SSivaprakash Murugesan CPU0: cpu@0 { 32e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 33e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 34e8a7fdc5SSivaprakash Murugesan reg = <0x0>; 35e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 36e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 37e8a7fdc5SSivaprakash Murugesan }; 38e8a7fdc5SSivaprakash Murugesan 39e8a7fdc5SSivaprakash Murugesan CPU1: cpu@1 { 40e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 41e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 42e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 43e8a7fdc5SSivaprakash Murugesan reg = <0x1>; 44e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 45e8a7fdc5SSivaprakash Murugesan }; 46e8a7fdc5SSivaprakash Murugesan 47e8a7fdc5SSivaprakash Murugesan CPU2: cpu@2 { 48e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 49e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 50e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 51e8a7fdc5SSivaprakash Murugesan reg = <0x2>; 52e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 53e8a7fdc5SSivaprakash Murugesan }; 54e8a7fdc5SSivaprakash Murugesan 55e8a7fdc5SSivaprakash Murugesan CPU3: cpu@3 { 56e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 57e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 58e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 59e8a7fdc5SSivaprakash Murugesan reg = <0x3>; 60e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 61e8a7fdc5SSivaprakash Murugesan }; 62e8a7fdc5SSivaprakash Murugesan 63e8a7fdc5SSivaprakash Murugesan L2_0: l2-cache { 64e8a7fdc5SSivaprakash Murugesan compatible = "cache"; 65e8a7fdc5SSivaprakash Murugesan cache-level = <0x2>; 66e8a7fdc5SSivaprakash Murugesan }; 67e8a7fdc5SSivaprakash Murugesan }; 68e8a7fdc5SSivaprakash Murugesan 69e8a7fdc5SSivaprakash Murugesan pmu { 70292b1874SKathiravan T compatible = "arm,cortex-a53-pmu"; 71e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72e8a7fdc5SSivaprakash Murugesan }; 73e8a7fdc5SSivaprakash Murugesan 74e8a7fdc5SSivaprakash Murugesan psci { 75e8a7fdc5SSivaprakash Murugesan compatible = "arm,psci-1.0"; 76e8a7fdc5SSivaprakash Murugesan method = "smc"; 77e8a7fdc5SSivaprakash Murugesan }; 78e8a7fdc5SSivaprakash Murugesan 7941dac73eSVaradarajan Narayanan soc: soc { 8041dac73eSVaradarajan Narayanan #address-cells = <0x1>; 8141dac73eSVaradarajan Narayanan #size-cells = <0x1>; 8241dac73eSVaradarajan Narayanan ranges = <0 0 0 0xffffffff>; 8341dac73eSVaradarajan Narayanan compatible = "simple-bus"; 8441dac73eSVaradarajan Narayanan 855e09bc51SSivaprakash Murugesan ssphy_1: phy@58000 { 865e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 875e09bc51SSivaprakash Murugesan reg = <0x00058000 0x1c4>; 885e09bc51SSivaprakash Murugesan #clock-cells = <1>; 895e09bc51SSivaprakash Murugesan #address-cells = <1>; 905e09bc51SSivaprakash Murugesan #size-cells = <1>; 915e09bc51SSivaprakash Murugesan ranges; 925e09bc51SSivaprakash Murugesan 935e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_AUX_CLK>, 945e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 955e09bc51SSivaprakash Murugesan <&xo>; 965e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 975e09bc51SSivaprakash Murugesan 985e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_PHY_BCR>, 995e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_1_PHY_BCR>; 1005e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1015e09bc51SSivaprakash Murugesan status = "disabled"; 1025e09bc51SSivaprakash Murugesan 1035e09bc51SSivaprakash Murugesan usb1_ssphy: lane@58200 { 1045e09bc51SSivaprakash Murugesan reg = <0x00058200 0x130>, /* Tx */ 1055e09bc51SSivaprakash Murugesan <0x00058400 0x200>, /* Rx */ 1065e09bc51SSivaprakash Murugesan <0x00058800 0x1f8>, /* PCS */ 1075e09bc51SSivaprakash Murugesan <0x00058600 0x044>; /* PCS misc*/ 1085e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1095e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PIPE_CLK>; 1105e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1115e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb1_pipe_clk_src"; 1125e09bc51SSivaprakash Murugesan }; 1135e09bc51SSivaprakash Murugesan }; 1145e09bc51SSivaprakash Murugesan 1155e09bc51SSivaprakash Murugesan qusb_phy_1: phy@59000 { 1165e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1175e09bc51SSivaprakash Murugesan reg = <0x00059000 0x180>; 1185e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1195e09bc51SSivaprakash Murugesan 1205e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1215e09bc51SSivaprakash Murugesan <&xo>; 1225e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1235e09bc51SSivaprakash Murugesan 1245e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 1255e09bc51SSivaprakash Murugesan status = "disabled"; 1265e09bc51SSivaprakash Murugesan }; 1275e09bc51SSivaprakash Murugesan 1285e09bc51SSivaprakash Murugesan ssphy_0: phy@78000 { 1295e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1305e09bc51SSivaprakash Murugesan reg = <0x00078000 0x1c4>; 1315e09bc51SSivaprakash Murugesan #clock-cells = <1>; 1325e09bc51SSivaprakash Murugesan #address-cells = <1>; 1335e09bc51SSivaprakash Murugesan #size-cells = <1>; 1345e09bc51SSivaprakash Murugesan ranges; 1355e09bc51SSivaprakash Murugesan 1365e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_AUX_CLK>, 1375e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1385e09bc51SSivaprakash Murugesan <&xo>; 1395e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1405e09bc51SSivaprakash Murugesan 1415e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_PHY_BCR>, 1425e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_0_PHY_BCR>; 1435e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1445e09bc51SSivaprakash Murugesan status = "disabled"; 1455e09bc51SSivaprakash Murugesan 1465e09bc51SSivaprakash Murugesan usb0_ssphy: lane@78200 { 1475e09bc51SSivaprakash Murugesan reg = <0x00078200 0x130>, /* Tx */ 1485e09bc51SSivaprakash Murugesan <0x00078400 0x200>, /* Rx */ 1495e09bc51SSivaprakash Murugesan <0x00078800 0x1f8>, /* PCS */ 1505e09bc51SSivaprakash Murugesan <0x00078600 0x044>; /* PCS misc*/ 1515e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1525e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PIPE_CLK>; 1535e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1545e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb0_pipe_clk_src"; 1555e09bc51SSivaprakash Murugesan }; 1565e09bc51SSivaprakash Murugesan }; 1575e09bc51SSivaprakash Murugesan 1585e09bc51SSivaprakash Murugesan qusb_phy_0: phy@79000 { 1595e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1605e09bc51SSivaprakash Murugesan reg = <0x00079000 0x180>; 1615e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1625e09bc51SSivaprakash Murugesan 1635e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1645e09bc51SSivaprakash Murugesan <&xo>; 1655e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1665e09bc51SSivaprakash Murugesan 1675e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 16858b2785dSRobert Marko status = "disabled"; 1695e09bc51SSivaprakash Murugesan }; 1705e09bc51SSivaprakash Murugesan 171e8a7fdc5SSivaprakash Murugesan pcie_phy0: phy@86000 { 172e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 173e8a7fdc5SSivaprakash Murugesan reg = <0x00086000 0x1000>; 174e8a7fdc5SSivaprakash Murugesan #phy-cells = <0>; 175e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 176e8a7fdc5SSivaprakash Murugesan clock-names = "pipe_clk"; 177e8a7fdc5SSivaprakash Murugesan clock-output-names = "pcie20_phy0_pipe_clk"; 178e8a7fdc5SSivaprakash Murugesan 179e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PHY_BCR>, 180e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0PHY_PHY_BCR>; 181e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 182e8a7fdc5SSivaprakash Murugesan "common"; 183e8a7fdc5SSivaprakash Murugesan status = "disabled"; 184e8a7fdc5SSivaprakash Murugesan }; 185e8a7fdc5SSivaprakash Murugesan 186e8a7fdc5SSivaprakash Murugesan pcie_phy1: phy@8e000 { 187e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 188e8a7fdc5SSivaprakash Murugesan reg = <0x0008e000 0x1000>; 189e8a7fdc5SSivaprakash Murugesan #phy-cells = <0>; 190e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 191e8a7fdc5SSivaprakash Murugesan clock-names = "pipe_clk"; 192e8a7fdc5SSivaprakash Murugesan clock-output-names = "pcie20_phy1_pipe_clk"; 193e8a7fdc5SSivaprakash Murugesan 194e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE1_PHY_BCR>, 195e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE1PHY_PHY_BCR>; 196e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 197e8a7fdc5SSivaprakash Murugesan "common"; 198e8a7fdc5SSivaprakash Murugesan status = "disabled"; 199e8a7fdc5SSivaprakash Murugesan }; 200e8a7fdc5SSivaprakash Murugesan 20133057e16SSricharan R tlmm: pinctrl@1000000 { 20241dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074-pinctrl"; 203e8a7fdc5SSivaprakash Murugesan reg = <0x01000000 0x300000>; 20441dac73eSVaradarajan Narayanan interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 20541dac73eSVaradarajan Narayanan gpio-controller; 206297177a4SChristian Lamparter gpio-ranges = <&tlmm 0 0 70>; 20741dac73eSVaradarajan Narayanan #gpio-cells = <0x2>; 20841dac73eSVaradarajan Narayanan interrupt-controller; 20941dac73eSVaradarajan Narayanan #interrupt-cells = <0x2>; 21022592a22SSricharan R 21122592a22SSricharan R serial_4_pins: serial4-pinmux { 21222592a22SSricharan R pins = "gpio23", "gpio24"; 21322592a22SSricharan R function = "blsp4_uart1"; 21422592a22SSricharan R drive-strength = <8>; 21522592a22SSricharan R bias-disable; 21622592a22SSricharan R }; 21722592a22SSricharan R 21822592a22SSricharan R i2c_0_pins: i2c-0-pinmux { 21922592a22SSricharan R pins = "gpio42", "gpio43"; 22022592a22SSricharan R function = "blsp1_i2c"; 22122592a22SSricharan R drive-strength = <8>; 22222592a22SSricharan R bias-disable; 22322592a22SSricharan R }; 22422592a22SSricharan R 22522592a22SSricharan R spi_0_pins: spi-0-pins { 22622592a22SSricharan R pins = "gpio38", "gpio39", "gpio40", "gpio41"; 22722592a22SSricharan R function = "blsp0_spi"; 22822592a22SSricharan R drive-strength = <8>; 22922592a22SSricharan R bias-disable; 23022592a22SSricharan R }; 23122592a22SSricharan R 23222592a22SSricharan R hsuart_pins: hsuart-pins { 23322592a22SSricharan R pins = "gpio46", "gpio47", "gpio48", "gpio49"; 23422592a22SSricharan R function = "blsp2_uart"; 23522592a22SSricharan R drive-strength = <8>; 23622592a22SSricharan R bias-disable; 23722592a22SSricharan R }; 23822592a22SSricharan R 23922592a22SSricharan R qpic_pins: qpic-pins { 24022592a22SSricharan R pins = "gpio1", "gpio3", "gpio4", 24122592a22SSricharan R "gpio5", "gpio6", "gpio7", 24222592a22SSricharan R "gpio8", "gpio10", "gpio11", 24322592a22SSricharan R "gpio12", "gpio13", "gpio14", 24422592a22SSricharan R "gpio15", "gpio16", "gpio17"; 24522592a22SSricharan R function = "qpic"; 24622592a22SSricharan R drive-strength = <8>; 24722592a22SSricharan R bias-disable; 24822592a22SSricharan R }; 24941dac73eSVaradarajan Narayanan }; 25041dac73eSVaradarajan Narayanan 25141dac73eSVaradarajan Narayanan gcc: gcc@1800000 { 25241dac73eSVaradarajan Narayanan compatible = "qcom,gcc-ipq8074"; 253e8a7fdc5SSivaprakash Murugesan reg = <0x01800000 0x80000>; 25441dac73eSVaradarajan Narayanan #clock-cells = <0x1>; 25541dac73eSVaradarajan Narayanan #reset-cells = <0x1>; 25641dac73eSVaradarajan Narayanan }; 25741dac73eSVaradarajan Narayanan 258cbc142c8SSivaprakash Murugesan sdhc_1: sdhci@7824900 { 259cbc142c8SSivaprakash Murugesan compatible = "qcom,sdhci-msm-v4"; 260cbc142c8SSivaprakash Murugesan reg = <0x7824900 0x500>, <0x7824000 0x800>; 261cbc142c8SSivaprakash Murugesan reg-names = "hc_mem", "core_mem"; 262cbc142c8SSivaprakash Murugesan 263cbc142c8SSivaprakash Murugesan interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 264cbc142c8SSivaprakash Murugesan <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 265cbc142c8SSivaprakash Murugesan interrupt-names = "hc_irq", "pwr_irq"; 266cbc142c8SSivaprakash Murugesan 267cbc142c8SSivaprakash Murugesan clocks = <&xo>, 268cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_AHB_CLK>, 269cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_APPS_CLK>; 270cbc142c8SSivaprakash Murugesan clock-names = "xo", "iface", "core"; 271cbc142c8SSivaprakash Murugesan max-frequency = <384000000>; 272cbc142c8SSivaprakash Murugesan mmc-ddr-1_8v; 273cbc142c8SSivaprakash Murugesan mmc-hs200-1_8v; 274cbc142c8SSivaprakash Murugesan mmc-hs400-1_8v; 275cbc142c8SSivaprakash Murugesan bus-width = <8>; 276cbc142c8SSivaprakash Murugesan 277cbc142c8SSivaprakash Murugesan status = "disabled"; 278cbc142c8SSivaprakash Murugesan }; 279cbc142c8SSivaprakash Murugesan 280b7fbf46cSVinod Koul blsp_dma: dma-controller@7884000 { 28122592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 282e8a7fdc5SSivaprakash Murugesan reg = <0x07884000 0x2b000>; 28322592a22SSricharan R interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 28422592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>; 28522592a22SSricharan R clock-names = "bam_clk"; 28622592a22SSricharan R #dma-cells = <1>; 28722592a22SSricharan R qcom,ee = <0>; 28822592a22SSricharan R }; 28922592a22SSricharan R 29022592a22SSricharan R blsp1_uart1: serial@78af000 { 29122592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 292e8a7fdc5SSivaprakash Murugesan reg = <0x078af000 0x200>; 29322592a22SSricharan R interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 29422592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 29522592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 29622592a22SSricharan R clock-names = "core", "iface"; 29722592a22SSricharan R status = "disabled"; 29822592a22SSricharan R }; 29922592a22SSricharan R 30022592a22SSricharan R blsp1_uart3: serial@78b1000 { 30122592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 302e8a7fdc5SSivaprakash Murugesan reg = <0x078b1000 0x200>; 30322592a22SSricharan R interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 30422592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 30522592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 30622592a22SSricharan R clock-names = "core", "iface"; 30722592a22SSricharan R dmas = <&blsp_dma 4>, 30822592a22SSricharan R <&blsp_dma 5>; 30922592a22SSricharan R dma-names = "tx", "rx"; 31022592a22SSricharan R pinctrl-0 = <&hsuart_pins>; 31122592a22SSricharan R pinctrl-names = "default"; 31222592a22SSricharan R status = "disabled"; 31322592a22SSricharan R }; 31422592a22SSricharan R 315e8a7fdc5SSivaprakash Murugesan blsp1_uart5: serial@78b3000 { 316e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 317e8a7fdc5SSivaprakash Murugesan reg = <0x078b3000 0x200>; 318e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 319e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 320e8a7fdc5SSivaprakash Murugesan <&gcc GCC_BLSP1_AHB_CLK>; 321e8a7fdc5SSivaprakash Murugesan clock-names = "core", "iface"; 322e8a7fdc5SSivaprakash Murugesan pinctrl-0 = <&serial_4_pins>; 323e8a7fdc5SSivaprakash Murugesan pinctrl-names = "default"; 324e8a7fdc5SSivaprakash Murugesan status = "disabled"; 325e8a7fdc5SSivaprakash Murugesan }; 326e8a7fdc5SSivaprakash Murugesan 32722592a22SSricharan R blsp1_spi1: spi@78b5000 { 32822592a22SSricharan R compatible = "qcom,spi-qup-v2.2.1"; 32922592a22SSricharan R #address-cells = <1>; 33022592a22SSricharan R #size-cells = <0>; 331e8a7fdc5SSivaprakash Murugesan reg = <0x078b5000 0x600>; 33222592a22SSricharan R interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 33322592a22SSricharan R spi-max-frequency = <50000000>; 33422592a22SSricharan R clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 33522592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 33622592a22SSricharan R clock-names = "core", "iface"; 33722592a22SSricharan R dmas = <&blsp_dma 12>, <&blsp_dma 13>; 33822592a22SSricharan R dma-names = "tx", "rx"; 33922592a22SSricharan R pinctrl-0 = <&spi_0_pins>; 34022592a22SSricharan R pinctrl-names = "default"; 34122592a22SSricharan R status = "disabled"; 34222592a22SSricharan R }; 34322592a22SSricharan R 34422592a22SSricharan R blsp1_i2c2: i2c@78b6000 { 34522592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 34622592a22SSricharan R #address-cells = <1>; 34722592a22SSricharan R #size-cells = <0>; 348e8a7fdc5SSivaprakash Murugesan reg = <0x078b6000 0x600>; 34922592a22SSricharan R interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 35022592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 35122592a22SSricharan R <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 35222592a22SSricharan R clock-names = "iface", "core"; 35322592a22SSricharan R clock-frequency = <400000>; 35422592a22SSricharan R dmas = <&blsp_dma 15>, <&blsp_dma 14>; 35522592a22SSricharan R dma-names = "rx", "tx"; 35622592a22SSricharan R pinctrl-0 = <&i2c_0_pins>; 35722592a22SSricharan R pinctrl-names = "default"; 35822592a22SSricharan R status = "disabled"; 35922592a22SSricharan R }; 36022592a22SSricharan R 36122592a22SSricharan R blsp1_i2c3: i2c@78b7000 { 36222592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 36322592a22SSricharan R #address-cells = <1>; 36422592a22SSricharan R #size-cells = <0>; 365e8a7fdc5SSivaprakash Murugesan reg = <0x078b7000 0x600>; 36622592a22SSricharan R interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 36722592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 36822592a22SSricharan R <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 36922592a22SSricharan R clock-names = "iface", "core"; 37022592a22SSricharan R clock-frequency = <100000>; 37122592a22SSricharan R dmas = <&blsp_dma 17>, <&blsp_dma 16>; 37222592a22SSricharan R dma-names = "rx", "tx"; 37322592a22SSricharan R status = "disabled"; 37422592a22SSricharan R }; 37522592a22SSricharan R 376b7fbf46cSVinod Koul qpic_bam: dma-controller@7984000 { 37722592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 378e8a7fdc5SSivaprakash Murugesan reg = <0x07984000 0x1a000>; 37922592a22SSricharan R interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 38022592a22SSricharan R clocks = <&gcc GCC_QPIC_AHB_CLK>; 38122592a22SSricharan R clock-names = "bam_clk"; 38222592a22SSricharan R #dma-cells = <1>; 38322592a22SSricharan R qcom,ee = <0>; 38422592a22SSricharan R status = "disabled"; 38522592a22SSricharan R }; 38622592a22SSricharan R 38722592a22SSricharan R qpic_nand: nand@79b0000 { 38822592a22SSricharan R compatible = "qcom,ipq8074-nand"; 389e8a7fdc5SSivaprakash Murugesan reg = <0x079b0000 0x10000>; 39022592a22SSricharan R #address-cells = <1>; 39122592a22SSricharan R #size-cells = <0>; 39222592a22SSricharan R clocks = <&gcc GCC_QPIC_CLK>, 39322592a22SSricharan R <&gcc GCC_QPIC_AHB_CLK>; 39422592a22SSricharan R clock-names = "core", "aon"; 39522592a22SSricharan R 39622592a22SSricharan R dmas = <&qpic_bam 0>, 39722592a22SSricharan R <&qpic_bam 1>, 39822592a22SSricharan R <&qpic_bam 2>; 39922592a22SSricharan R dma-names = "tx", "rx", "cmd"; 40022592a22SSricharan R pinctrl-0 = <&qpic_pins>; 40122592a22SSricharan R pinctrl-names = "default"; 40241dac73eSVaradarajan Narayanan status = "disabled"; 40341dac73eSVaradarajan Narayanan }; 40433057e16SSricharan R 4055e09bc51SSivaprakash Murugesan usb_0: usb@8af8800 { 4065e09bc51SSivaprakash Murugesan compatible = "qcom,dwc3"; 4075e09bc51SSivaprakash Murugesan reg = <0x08af8800 0x400>; 4085e09bc51SSivaprakash Murugesan #address-cells = <1>; 4095e09bc51SSivaprakash Murugesan #size-cells = <1>; 4105e09bc51SSivaprakash Murugesan ranges; 4115e09bc51SSivaprakash Murugesan 4125e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 4135e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 4145e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_SLEEP_CLK>, 4155e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 4165e09bc51SSivaprakash Murugesan clock-names = "sys_noc_axi", 4175e09bc51SSivaprakash Murugesan "master", 4185e09bc51SSivaprakash Murugesan "sleep", 4195e09bc51SSivaprakash Murugesan "mock_utmi"; 4205e09bc51SSivaprakash Murugesan 4215e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 4225e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 4235e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 4245e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 4255e09bc51SSivaprakash Murugesan <133330000>, 4265e09bc51SSivaprakash Murugesan <19200000>; 4275e09bc51SSivaprakash Murugesan 4285e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_BCR>; 4295e09bc51SSivaprakash Murugesan status = "disabled"; 4305e09bc51SSivaprakash Murugesan 431*eb9b7bfdSSerge Semin dwc_0: usb@8a00000 { 4325e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 4335e09bc51SSivaprakash Murugesan reg = <0x8a00000 0xcd00>; 4345e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4355e09bc51SSivaprakash Murugesan phys = <&qusb_phy_0>, <&usb0_ssphy>; 4365e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 4375e09bc51SSivaprakash Murugesan tx-fifo-resize; 4385e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 4395e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 4405e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 4415e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 4425e09bc51SSivaprakash Murugesan dr_mode = "host"; 4435e09bc51SSivaprakash Murugesan }; 4445e09bc51SSivaprakash Murugesan }; 4455e09bc51SSivaprakash Murugesan 4465e09bc51SSivaprakash Murugesan usb_1: usb@8cf8800 { 4475e09bc51SSivaprakash Murugesan compatible = "qcom,dwc3"; 4485e09bc51SSivaprakash Murugesan reg = <0x08cf8800 0x400>; 4495e09bc51SSivaprakash Murugesan #address-cells = <1>; 4505e09bc51SSivaprakash Murugesan #size-cells = <1>; 4515e09bc51SSivaprakash Murugesan ranges; 4525e09bc51SSivaprakash Murugesan 4535e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 4545e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 4555e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_SLEEP_CLK>, 4565e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 4575e09bc51SSivaprakash Murugesan clock-names = "sys_noc_axi", 4585e09bc51SSivaprakash Murugesan "master", 4595e09bc51SSivaprakash Murugesan "sleep", 4605e09bc51SSivaprakash Murugesan "mock_utmi"; 4615e09bc51SSivaprakash Murugesan 4625e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 4635e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 4645e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 4655e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 4665e09bc51SSivaprakash Murugesan <133330000>, 4675e09bc51SSivaprakash Murugesan <19200000>; 4685e09bc51SSivaprakash Murugesan 4695e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_BCR>; 4705e09bc51SSivaprakash Murugesan status = "disabled"; 4715e09bc51SSivaprakash Murugesan 472*eb9b7bfdSSerge Semin dwc_1: usb@8c00000 { 4735e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 4745e09bc51SSivaprakash Murugesan reg = <0x8c00000 0xcd00>; 4755e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 4765e09bc51SSivaprakash Murugesan phys = <&qusb_phy_1>, <&usb1_ssphy>; 4775e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 4785e09bc51SSivaprakash Murugesan tx-fifo-resize; 4795e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 4805e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 4815e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 4825e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 4835e09bc51SSivaprakash Murugesan dr_mode = "host"; 4845e09bc51SSivaprakash Murugesan }; 4855e09bc51SSivaprakash Murugesan }; 4865e09bc51SSivaprakash Murugesan 487e8a7fdc5SSivaprakash Murugesan intc: interrupt-controller@b000000 { 488e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-qgic2"; 489e8a7fdc5SSivaprakash Murugesan interrupt-controller; 490e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <0x3>; 491e8a7fdc5SSivaprakash Murugesan reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 492e8a7fdc5SSivaprakash Murugesan }; 49333057e16SSricharan R 494e8a7fdc5SSivaprakash Murugesan timer { 495e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv8-timer"; 496e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 497e8a7fdc5SSivaprakash Murugesan <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 498e8a7fdc5SSivaprakash Murugesan <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 499e8a7fdc5SSivaprakash Murugesan <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 500e8a7fdc5SSivaprakash Murugesan }; 501e8a7fdc5SSivaprakash Murugesan 502949766e0SKathiravan T watchdog: watchdog@b017000 { 503949766e0SKathiravan T compatible = "qcom,kpss-wdt"; 504949766e0SKathiravan T reg = <0xb017000 0x1000>; 505949766e0SKathiravan T interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 506949766e0SKathiravan T clocks = <&sleep_clk>; 507949766e0SKathiravan T timeout-sec = <30>; 508949766e0SKathiravan T }; 509949766e0SKathiravan T 510e8a7fdc5SSivaprakash Murugesan timer@b120000 { 511e8a7fdc5SSivaprakash Murugesan #address-cells = <1>; 512e8a7fdc5SSivaprakash Murugesan #size-cells = <1>; 513e8a7fdc5SSivaprakash Murugesan ranges; 514e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv7-timer-mem"; 515e8a7fdc5SSivaprakash Murugesan reg = <0x0b120000 0x1000>; 516e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 517e8a7fdc5SSivaprakash Murugesan 518e8a7fdc5SSivaprakash Murugesan frame@b120000 { 519e8a7fdc5SSivaprakash Murugesan frame-number = <0>; 520e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 521e8a7fdc5SSivaprakash Murugesan <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 522e8a7fdc5SSivaprakash Murugesan reg = <0x0b121000 0x1000>, 523e8a7fdc5SSivaprakash Murugesan <0x0b122000 0x1000>; 524e8a7fdc5SSivaprakash Murugesan }; 525e8a7fdc5SSivaprakash Murugesan 526e8a7fdc5SSivaprakash Murugesan frame@b123000 { 527e8a7fdc5SSivaprakash Murugesan frame-number = <1>; 528e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 529e8a7fdc5SSivaprakash Murugesan reg = <0x0b123000 0x1000>; 53033057e16SSricharan R status = "disabled"; 53133057e16SSricharan R }; 53233057e16SSricharan R 533e8a7fdc5SSivaprakash Murugesan frame@b124000 { 534e8a7fdc5SSivaprakash Murugesan frame-number = <2>; 535e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 536e8a7fdc5SSivaprakash Murugesan reg = <0x0b124000 0x1000>; 53733057e16SSricharan R status = "disabled"; 53833057e16SSricharan R }; 53933057e16SSricharan R 540e8a7fdc5SSivaprakash Murugesan frame@b125000 { 541e8a7fdc5SSivaprakash Murugesan frame-number = <3>; 542e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 543e8a7fdc5SSivaprakash Murugesan reg = <0x0b125000 0x1000>; 54433057e16SSricharan R status = "disabled"; 54533057e16SSricharan R }; 54633057e16SSricharan R 547e8a7fdc5SSivaprakash Murugesan frame@b126000 { 548e8a7fdc5SSivaprakash Murugesan frame-number = <4>; 549e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 550e8a7fdc5SSivaprakash Murugesan reg = <0x0b126000 0x1000>; 551e8a7fdc5SSivaprakash Murugesan status = "disabled"; 552e8a7fdc5SSivaprakash Murugesan }; 553e8a7fdc5SSivaprakash Murugesan 554e8a7fdc5SSivaprakash Murugesan frame@b127000 { 555e8a7fdc5SSivaprakash Murugesan frame-number = <5>; 556e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 557e8a7fdc5SSivaprakash Murugesan reg = <0x0b127000 0x1000>; 558e8a7fdc5SSivaprakash Murugesan status = "disabled"; 559e8a7fdc5SSivaprakash Murugesan }; 560e8a7fdc5SSivaprakash Murugesan 561e8a7fdc5SSivaprakash Murugesan frame@b128000 { 562e8a7fdc5SSivaprakash Murugesan frame-number = <6>; 563e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 564e8a7fdc5SSivaprakash Murugesan reg = <0x0b128000 0x1000>; 565e8a7fdc5SSivaprakash Murugesan status = "disabled"; 566e8a7fdc5SSivaprakash Murugesan }; 567e8a7fdc5SSivaprakash Murugesan }; 568e8a7fdc5SSivaprakash Murugesan 56933057e16SSricharan R pcie1: pci@10000000 { 57033057e16SSricharan R compatible = "qcom,pcie-ipq8074"; 57133057e16SSricharan R reg = <0x10000000 0xf1d 57233057e16SSricharan R 0x10000f20 0xa8 573e8a7fdc5SSivaprakash Murugesan 0x00088000 0x2000 57433057e16SSricharan R 0x10100000 0x1000>; 57533057e16SSricharan R reg-names = "dbi", "elbi", "parf", "config"; 57633057e16SSricharan R device_type = "pci"; 57733057e16SSricharan R linux,pci-domain = <1>; 57833057e16SSricharan R bus-range = <0x00 0xff>; 57933057e16SSricharan R num-lanes = <1>; 58033057e16SSricharan R #address-cells = <3>; 58133057e16SSricharan R #size-cells = <2>; 58233057e16SSricharan R 58333057e16SSricharan R phys = <&pcie_phy1>; 58433057e16SSricharan R phy-names = "pciephy"; 58533057e16SSricharan R 58633057e16SSricharan R ranges = <0x81000000 0 0x10200000 0x10200000 58733057e16SSricharan R 0 0x100000 /* downstream I/O */ 58833057e16SSricharan R 0x82000000 0 0x10300000 0x10300000 58933057e16SSricharan R 0 0xd00000>; /* non-prefetchable memory */ 59033057e16SSricharan R 59133057e16SSricharan R interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 59233057e16SSricharan R interrupt-names = "msi"; 59333057e16SSricharan R #interrupt-cells = <1>; 59433057e16SSricharan R interrupt-map-mask = <0 0 0 0x7>; 59533057e16SSricharan R interrupt-map = <0 0 0 1 &intc 0 142 59633057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 59733057e16SSricharan R <0 0 0 2 &intc 0 143 59833057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 59933057e16SSricharan R <0 0 0 3 &intc 0 144 60033057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 60133057e16SSricharan R <0 0 0 4 &intc 0 145 60233057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 60333057e16SSricharan R 60433057e16SSricharan R clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 60533057e16SSricharan R <&gcc GCC_PCIE1_AXI_M_CLK>, 60633057e16SSricharan R <&gcc GCC_PCIE1_AXI_S_CLK>, 60733057e16SSricharan R <&gcc GCC_PCIE1_AHB_CLK>, 60833057e16SSricharan R <&gcc GCC_PCIE1_AUX_CLK>; 60933057e16SSricharan R clock-names = "iface", 61033057e16SSricharan R "axi_m", 61133057e16SSricharan R "axi_s", 61233057e16SSricharan R "ahb", 61333057e16SSricharan R "aux"; 61433057e16SSricharan R resets = <&gcc GCC_PCIE1_PIPE_ARES>, 61533057e16SSricharan R <&gcc GCC_PCIE1_SLEEP_ARES>, 61633057e16SSricharan R <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 61733057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 61833057e16SSricharan R <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 61933057e16SSricharan R <&gcc GCC_PCIE1_AHB_ARES>, 62033057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 62133057e16SSricharan R reset-names = "pipe", 62233057e16SSricharan R "sleep", 62333057e16SSricharan R "sticky", 62433057e16SSricharan R "axi_m", 62533057e16SSricharan R "axi_s", 62633057e16SSricharan R "ahb", 62733057e16SSricharan R "axi_m_sticky"; 62833057e16SSricharan R status = "disabled"; 62933057e16SSricharan R }; 63041dac73eSVaradarajan Narayanan 631e8a7fdc5SSivaprakash Murugesan pcie0: pci@20000000 { 632e8a7fdc5SSivaprakash Murugesan compatible = "qcom,pcie-ipq8074"; 633e8a7fdc5SSivaprakash Murugesan reg = <0x20000000 0xf1d 634e8a7fdc5SSivaprakash Murugesan 0x20000f20 0xa8 635e8a7fdc5SSivaprakash Murugesan 0x00080000 0x2000 636e8a7fdc5SSivaprakash Murugesan 0x20100000 0x1000>; 637e8a7fdc5SSivaprakash Murugesan reg-names = "dbi", "elbi", "parf", "config"; 638e8a7fdc5SSivaprakash Murugesan device_type = "pci"; 639e8a7fdc5SSivaprakash Murugesan linux,pci-domain = <0>; 640e8a7fdc5SSivaprakash Murugesan bus-range = <0x00 0xff>; 641e8a7fdc5SSivaprakash Murugesan num-lanes = <1>; 642e8a7fdc5SSivaprakash Murugesan #address-cells = <3>; 643e8a7fdc5SSivaprakash Murugesan #size-cells = <2>; 64441dac73eSVaradarajan Narayanan 645e8a7fdc5SSivaprakash Murugesan phys = <&pcie_phy0>; 646e8a7fdc5SSivaprakash Murugesan phy-names = "pciephy"; 64741dac73eSVaradarajan Narayanan 648e8a7fdc5SSivaprakash Murugesan ranges = <0x81000000 0 0x20200000 0x20200000 649e8a7fdc5SSivaprakash Murugesan 0 0x100000 /* downstream I/O */ 650e8a7fdc5SSivaprakash Murugesan 0x82000000 0 0x20300000 0x20300000 651e8a7fdc5SSivaprakash Murugesan 0 0xd00000>; /* non-prefetchable memory */ 65241dac73eSVaradarajan Narayanan 653e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 654e8a7fdc5SSivaprakash Murugesan interrupt-names = "msi"; 655e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <1>; 656e8a7fdc5SSivaprakash Murugesan interrupt-map-mask = <0 0 0 0x7>; 657e8a7fdc5SSivaprakash Murugesan interrupt-map = <0 0 0 1 &intc 0 75 658e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 659e8a7fdc5SSivaprakash Murugesan <0 0 0 2 &intc 0 78 660e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 661e8a7fdc5SSivaprakash Murugesan <0 0 0 3 &intc 0 79 662e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 663e8a7fdc5SSivaprakash Murugesan <0 0 0 4 &intc 0 83 664e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 66541dac73eSVaradarajan Narayanan 666e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 667e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_M_CLK>, 668e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_S_CLK>, 669e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_CLK>, 670e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AUX_CLK>; 67141dac73eSVaradarajan Narayanan 672e8a7fdc5SSivaprakash Murugesan clock-names = "iface", 673e8a7fdc5SSivaprakash Murugesan "axi_m", 674e8a7fdc5SSivaprakash Murugesan "axi_s", 675e8a7fdc5SSivaprakash Murugesan "ahb", 676e8a7fdc5SSivaprakash Murugesan "aux"; 677e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PIPE_ARES>, 678e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_SLEEP_ARES>, 679e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 680e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 681e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 682e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_ARES>, 683e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 684e8a7fdc5SSivaprakash Murugesan reset-names = "pipe", 685e8a7fdc5SSivaprakash Murugesan "sleep", 686e8a7fdc5SSivaprakash Murugesan "sticky", 687e8a7fdc5SSivaprakash Murugesan "axi_m", 688e8a7fdc5SSivaprakash Murugesan "axi_s", 689e8a7fdc5SSivaprakash Murugesan "ahb", 690e8a7fdc5SSivaprakash Murugesan "axi_m_sticky"; 691e8a7fdc5SSivaprakash Murugesan status = "disabled"; 69241dac73eSVaradarajan Narayanan }; 69341dac73eSVaradarajan Narayanan }; 69441dac73eSVaradarajan Narayanan}; 695