197fb5e8dSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 241dac73eSVaradarajan Narayanan/* 341dac73eSVaradarajan Narayanan * Copyright (c) 2017, The Linux Foundation. All rights reserved. 441dac73eSVaradarajan Narayanan */ 541dac73eSVaradarajan Narayanan 641dac73eSVaradarajan Narayanan#include <dt-bindings/interrupt-controller/arm-gic.h> 741dac73eSVaradarajan Narayanan#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 841dac73eSVaradarajan Narayanan 941dac73eSVaradarajan Narayanan/ { 1041dac73eSVaradarajan Narayanan model = "Qualcomm Technologies, Inc. IPQ8074"; 1141dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074"; 1241dac73eSVaradarajan Narayanan 13e8a7fdc5SSivaprakash Murugesan clocks { 14e8a7fdc5SSivaprakash Murugesan sleep_clk: sleep_clk { 15e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 16e8a7fdc5SSivaprakash Murugesan clock-frequency = <32000>; 17e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 18e8a7fdc5SSivaprakash Murugesan }; 19e8a7fdc5SSivaprakash Murugesan 20e8a7fdc5SSivaprakash Murugesan xo: xo { 21e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 22e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 23e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 24e8a7fdc5SSivaprakash Murugesan }; 25e8a7fdc5SSivaprakash Murugesan }; 26e8a7fdc5SSivaprakash Murugesan 27e8a7fdc5SSivaprakash Murugesan cpus { 28e8a7fdc5SSivaprakash Murugesan #address-cells = <0x1>; 29e8a7fdc5SSivaprakash Murugesan #size-cells = <0x0>; 30e8a7fdc5SSivaprakash Murugesan 31e8a7fdc5SSivaprakash Murugesan CPU0: cpu@0 { 32e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 33e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 34e8a7fdc5SSivaprakash Murugesan reg = <0x0>; 35e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 36e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 37e8a7fdc5SSivaprakash Murugesan }; 38e8a7fdc5SSivaprakash Murugesan 39e8a7fdc5SSivaprakash Murugesan CPU1: cpu@1 { 40e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 41e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 42e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 43e8a7fdc5SSivaprakash Murugesan reg = <0x1>; 44e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 45e8a7fdc5SSivaprakash Murugesan }; 46e8a7fdc5SSivaprakash Murugesan 47e8a7fdc5SSivaprakash Murugesan CPU2: cpu@2 { 48e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 49e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 50e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 51e8a7fdc5SSivaprakash Murugesan reg = <0x2>; 52e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 53e8a7fdc5SSivaprakash Murugesan }; 54e8a7fdc5SSivaprakash Murugesan 55e8a7fdc5SSivaprakash Murugesan CPU3: cpu@3 { 56e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 57e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 58e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 59e8a7fdc5SSivaprakash Murugesan reg = <0x3>; 60e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 61e8a7fdc5SSivaprakash Murugesan }; 62e8a7fdc5SSivaprakash Murugesan 63e8a7fdc5SSivaprakash Murugesan L2_0: l2-cache { 64e8a7fdc5SSivaprakash Murugesan compatible = "cache"; 65e8a7fdc5SSivaprakash Murugesan cache-level = <0x2>; 66e8a7fdc5SSivaprakash Murugesan }; 67e8a7fdc5SSivaprakash Murugesan }; 68e8a7fdc5SSivaprakash Murugesan 69e8a7fdc5SSivaprakash Murugesan pmu { 70292b1874SKathiravan T compatible = "arm,cortex-a53-pmu"; 71e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72e8a7fdc5SSivaprakash Murugesan }; 73e8a7fdc5SSivaprakash Murugesan 74e8a7fdc5SSivaprakash Murugesan psci { 75e8a7fdc5SSivaprakash Murugesan compatible = "arm,psci-1.0"; 76e8a7fdc5SSivaprakash Murugesan method = "smc"; 77e8a7fdc5SSivaprakash Murugesan }; 78e8a7fdc5SSivaprakash Murugesan 796df9102fSGokul Sriram Palanisamy firmware { 806df9102fSGokul Sriram Palanisamy scm { 816df9102fSGokul Sriram Palanisamy compatible = "qcom,scm-ipq8074", "qcom,scm"; 826df9102fSGokul Sriram Palanisamy }; 836df9102fSGokul Sriram Palanisamy }; 846df9102fSGokul Sriram Palanisamy 8541dac73eSVaradarajan Narayanan soc: soc { 8641dac73eSVaradarajan Narayanan #address-cells = <0x1>; 8741dac73eSVaradarajan Narayanan #size-cells = <0x1>; 8841dac73eSVaradarajan Narayanan ranges = <0 0 0 0xffffffff>; 8941dac73eSVaradarajan Narayanan compatible = "simple-bus"; 9041dac73eSVaradarajan Narayanan 915e09bc51SSivaprakash Murugesan ssphy_1: phy@58000 { 925e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 935e09bc51SSivaprakash Murugesan reg = <0x00058000 0x1c4>; 945e09bc51SSivaprakash Murugesan #clock-cells = <1>; 955e09bc51SSivaprakash Murugesan #address-cells = <1>; 965e09bc51SSivaprakash Murugesan #size-cells = <1>; 975e09bc51SSivaprakash Murugesan ranges; 985e09bc51SSivaprakash Murugesan 995e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_AUX_CLK>, 1005e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1015e09bc51SSivaprakash Murugesan <&xo>; 1025e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1035e09bc51SSivaprakash Murugesan 1045e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_PHY_BCR>, 1055e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_1_PHY_BCR>; 1065e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1075e09bc51SSivaprakash Murugesan status = "disabled"; 1085e09bc51SSivaprakash Murugesan 1095e09bc51SSivaprakash Murugesan usb1_ssphy: lane@58200 { 1105e09bc51SSivaprakash Murugesan reg = <0x00058200 0x130>, /* Tx */ 1115e09bc51SSivaprakash Murugesan <0x00058400 0x200>, /* Rx */ 1125e09bc51SSivaprakash Murugesan <0x00058800 0x1f8>, /* PCS */ 1135e09bc51SSivaprakash Murugesan <0x00058600 0x044>; /* PCS misc*/ 1145e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1155e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PIPE_CLK>; 1165e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1175e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb1_pipe_clk_src"; 1185e09bc51SSivaprakash Murugesan }; 1195e09bc51SSivaprakash Murugesan }; 1205e09bc51SSivaprakash Murugesan 1215e09bc51SSivaprakash Murugesan qusb_phy_1: phy@59000 { 1225e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1235e09bc51SSivaprakash Murugesan reg = <0x00059000 0x180>; 1245e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1255e09bc51SSivaprakash Murugesan 1265e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1275e09bc51SSivaprakash Murugesan <&xo>; 1285e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1295e09bc51SSivaprakash Murugesan 1305e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 1315e09bc51SSivaprakash Murugesan status = "disabled"; 1325e09bc51SSivaprakash Murugesan }; 1335e09bc51SSivaprakash Murugesan 1345e09bc51SSivaprakash Murugesan ssphy_0: phy@78000 { 1355e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1365e09bc51SSivaprakash Murugesan reg = <0x00078000 0x1c4>; 1375e09bc51SSivaprakash Murugesan #clock-cells = <1>; 1385e09bc51SSivaprakash Murugesan #address-cells = <1>; 1395e09bc51SSivaprakash Murugesan #size-cells = <1>; 1405e09bc51SSivaprakash Murugesan ranges; 1415e09bc51SSivaprakash Murugesan 1425e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_AUX_CLK>, 1435e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1445e09bc51SSivaprakash Murugesan <&xo>; 1455e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1465e09bc51SSivaprakash Murugesan 1475e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_PHY_BCR>, 1485e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_0_PHY_BCR>; 1495e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1505e09bc51SSivaprakash Murugesan status = "disabled"; 1515e09bc51SSivaprakash Murugesan 1525e09bc51SSivaprakash Murugesan usb0_ssphy: lane@78200 { 1535e09bc51SSivaprakash Murugesan reg = <0x00078200 0x130>, /* Tx */ 1545e09bc51SSivaprakash Murugesan <0x00078400 0x200>, /* Rx */ 1555e09bc51SSivaprakash Murugesan <0x00078800 0x1f8>, /* PCS */ 1565e09bc51SSivaprakash Murugesan <0x00078600 0x044>; /* PCS misc*/ 1575e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1585e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PIPE_CLK>; 1595e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1605e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb0_pipe_clk_src"; 1615e09bc51SSivaprakash Murugesan }; 1625e09bc51SSivaprakash Murugesan }; 1635e09bc51SSivaprakash Murugesan 1645e09bc51SSivaprakash Murugesan qusb_phy_0: phy@79000 { 1655e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1665e09bc51SSivaprakash Murugesan reg = <0x00079000 0x180>; 1675e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1685e09bc51SSivaprakash Murugesan 1695e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1705e09bc51SSivaprakash Murugesan <&xo>; 1715e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1725e09bc51SSivaprakash Murugesan 1735e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 17458b2785dSRobert Marko status = "disabled"; 1755e09bc51SSivaprakash Murugesan }; 1765e09bc51SSivaprakash Murugesan 177e8a7fdc5SSivaprakash Murugesan pcie_phy0: phy@86000 { 178e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 179e8a7fdc5SSivaprakash Murugesan reg = <0x00086000 0x1000>; 180e8a7fdc5SSivaprakash Murugesan #phy-cells = <0>; 181e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 182e8a7fdc5SSivaprakash Murugesan clock-names = "pipe_clk"; 183e8a7fdc5SSivaprakash Murugesan clock-output-names = "pcie20_phy0_pipe_clk"; 184e8a7fdc5SSivaprakash Murugesan 185e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PHY_BCR>, 186e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0PHY_PHY_BCR>; 187e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 188e8a7fdc5SSivaprakash Murugesan "common"; 189e8a7fdc5SSivaprakash Murugesan status = "disabled"; 190e8a7fdc5SSivaprakash Murugesan }; 191e8a7fdc5SSivaprakash Murugesan 192e8a7fdc5SSivaprakash Murugesan pcie_phy1: phy@8e000 { 193e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 194e8a7fdc5SSivaprakash Murugesan reg = <0x0008e000 0x1000>; 195e8a7fdc5SSivaprakash Murugesan #phy-cells = <0>; 196e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 197e8a7fdc5SSivaprakash Murugesan clock-names = "pipe_clk"; 198e8a7fdc5SSivaprakash Murugesan clock-output-names = "pcie20_phy1_pipe_clk"; 199e8a7fdc5SSivaprakash Murugesan 200e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE1_PHY_BCR>, 201e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE1PHY_PHY_BCR>; 202e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 203e8a7fdc5SSivaprakash Murugesan "common"; 204e8a7fdc5SSivaprakash Murugesan status = "disabled"; 205e8a7fdc5SSivaprakash Murugesan }; 206e8a7fdc5SSivaprakash Murugesan 207f26f6a5eSRobert Marko prng: rng@e3000 { 208f26f6a5eSRobert Marko compatible = "qcom,prng-ee"; 209f26f6a5eSRobert Marko reg = <0x000e3000 0x1000>; 210f26f6a5eSRobert Marko clocks = <&gcc GCC_PRNG_AHB_CLK>; 211f26f6a5eSRobert Marko clock-names = "core"; 212f26f6a5eSRobert Marko status = "disabled"; 213f26f6a5eSRobert Marko }; 214f26f6a5eSRobert Marko 215bbef0142SShawn Guo cryptobam: dma-controller@704000 { 216f9e2df82SRobert Marko compatible = "qcom,bam-v1.7.0"; 217f9e2df82SRobert Marko reg = <0x00704000 0x20000>; 218f9e2df82SRobert Marko interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 219f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 220f9e2df82SRobert Marko clock-names = "bam_clk"; 221f9e2df82SRobert Marko #dma-cells = <1>; 222f9e2df82SRobert Marko qcom,ee = <1>; 2238c97f0acSShawn Guo qcom,controlled-remotely; 224f9e2df82SRobert Marko status = "disabled"; 225f9e2df82SRobert Marko }; 226f9e2df82SRobert Marko 227f9e2df82SRobert Marko crypto: crypto@73a000 { 228f9e2df82SRobert Marko compatible = "qcom,crypto-v5.1"; 229f9e2df82SRobert Marko reg = <0x0073a000 0x6000>; 230f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 231f9e2df82SRobert Marko <&gcc GCC_CRYPTO_AXI_CLK>, 232f9e2df82SRobert Marko <&gcc GCC_CRYPTO_CLK>; 233f9e2df82SRobert Marko clock-names = "iface", "bus", "core"; 234f9e2df82SRobert Marko dmas = <&cryptobam 2>, <&cryptobam 3>; 235f9e2df82SRobert Marko dma-names = "rx", "tx"; 236f9e2df82SRobert Marko status = "disabled"; 237f9e2df82SRobert Marko }; 238f9e2df82SRobert Marko 23933057e16SSricharan R tlmm: pinctrl@1000000 { 24041dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074-pinctrl"; 241e8a7fdc5SSivaprakash Murugesan reg = <0x01000000 0x300000>; 24241dac73eSVaradarajan Narayanan interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 24341dac73eSVaradarajan Narayanan gpio-controller; 244297177a4SChristian Lamparter gpio-ranges = <&tlmm 0 0 70>; 24541dac73eSVaradarajan Narayanan #gpio-cells = <0x2>; 24641dac73eSVaradarajan Narayanan interrupt-controller; 24741dac73eSVaradarajan Narayanan #interrupt-cells = <0x2>; 24822592a22SSricharan R 24922592a22SSricharan R serial_4_pins: serial4-pinmux { 25022592a22SSricharan R pins = "gpio23", "gpio24"; 25122592a22SSricharan R function = "blsp4_uart1"; 25222592a22SSricharan R drive-strength = <8>; 25322592a22SSricharan R bias-disable; 25422592a22SSricharan R }; 25522592a22SSricharan R 25622592a22SSricharan R i2c_0_pins: i2c-0-pinmux { 25722592a22SSricharan R pins = "gpio42", "gpio43"; 25822592a22SSricharan R function = "blsp1_i2c"; 25922592a22SSricharan R drive-strength = <8>; 26022592a22SSricharan R bias-disable; 26122592a22SSricharan R }; 26222592a22SSricharan R 26322592a22SSricharan R spi_0_pins: spi-0-pins { 26422592a22SSricharan R pins = "gpio38", "gpio39", "gpio40", "gpio41"; 26522592a22SSricharan R function = "blsp0_spi"; 26622592a22SSricharan R drive-strength = <8>; 26722592a22SSricharan R bias-disable; 26822592a22SSricharan R }; 26922592a22SSricharan R 27022592a22SSricharan R hsuart_pins: hsuart-pins { 27122592a22SSricharan R pins = "gpio46", "gpio47", "gpio48", "gpio49"; 27222592a22SSricharan R function = "blsp2_uart"; 27322592a22SSricharan R drive-strength = <8>; 27422592a22SSricharan R bias-disable; 27522592a22SSricharan R }; 27622592a22SSricharan R 27722592a22SSricharan R qpic_pins: qpic-pins { 27822592a22SSricharan R pins = "gpio1", "gpio3", "gpio4", 27922592a22SSricharan R "gpio5", "gpio6", "gpio7", 28022592a22SSricharan R "gpio8", "gpio10", "gpio11", 28122592a22SSricharan R "gpio12", "gpio13", "gpio14", 28222592a22SSricharan R "gpio15", "gpio16", "gpio17"; 28322592a22SSricharan R function = "qpic"; 28422592a22SSricharan R drive-strength = <8>; 28522592a22SSricharan R bias-disable; 28622592a22SSricharan R }; 28741dac73eSVaradarajan Narayanan }; 28841dac73eSVaradarajan Narayanan 28941dac73eSVaradarajan Narayanan gcc: gcc@1800000 { 29041dac73eSVaradarajan Narayanan compatible = "qcom,gcc-ipq8074"; 291e8a7fdc5SSivaprakash Murugesan reg = <0x01800000 0x80000>; 29241dac73eSVaradarajan Narayanan #clock-cells = <0x1>; 29341dac73eSVaradarajan Narayanan #reset-cells = <0x1>; 29441dac73eSVaradarajan Narayanan }; 29541dac73eSVaradarajan Narayanan 29663750607SRobert Marko spmi_bus: spmi@200f000 { 29763750607SRobert Marko compatible = "qcom,spmi-pmic-arb"; 29863750607SRobert Marko reg = <0x0200f000 0x001000>, 29963750607SRobert Marko <0x02400000 0x800000>, 30063750607SRobert Marko <0x02c00000 0x800000>, 30163750607SRobert Marko <0x03800000 0x200000>, 30263750607SRobert Marko <0x0200a000 0x000700>; 30363750607SRobert Marko reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 30463750607SRobert Marko interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 30563750607SRobert Marko interrupt-names = "periph_irq"; 30663750607SRobert Marko qcom,ee = <0>; 30763750607SRobert Marko qcom,channel = <0>; 30863750607SRobert Marko #address-cells = <2>; 30963750607SRobert Marko #size-cells = <0>; 31063750607SRobert Marko interrupt-controller; 31163750607SRobert Marko #interrupt-cells = <4>; 31263750607SRobert Marko cell-index = <0>; 31363750607SRobert Marko }; 31463750607SRobert Marko 315cbc142c8SSivaprakash Murugesan sdhc_1: sdhci@7824900 { 316cbc142c8SSivaprakash Murugesan compatible = "qcom,sdhci-msm-v4"; 317cbc142c8SSivaprakash Murugesan reg = <0x7824900 0x500>, <0x7824000 0x800>; 318cbc142c8SSivaprakash Murugesan reg-names = "hc_mem", "core_mem"; 319cbc142c8SSivaprakash Murugesan 320cbc142c8SSivaprakash Murugesan interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 321cbc142c8SSivaprakash Murugesan <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 322cbc142c8SSivaprakash Murugesan interrupt-names = "hc_irq", "pwr_irq"; 323cbc142c8SSivaprakash Murugesan 324cbc142c8SSivaprakash Murugesan clocks = <&xo>, 325cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_AHB_CLK>, 326cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_APPS_CLK>; 327cbc142c8SSivaprakash Murugesan clock-names = "xo", "iface", "core"; 328cbc142c8SSivaprakash Murugesan max-frequency = <384000000>; 329cbc142c8SSivaprakash Murugesan mmc-ddr-1_8v; 330cbc142c8SSivaprakash Murugesan mmc-hs200-1_8v; 331cbc142c8SSivaprakash Murugesan mmc-hs400-1_8v; 332cbc142c8SSivaprakash Murugesan bus-width = <8>; 333cbc142c8SSivaprakash Murugesan 334cbc142c8SSivaprakash Murugesan status = "disabled"; 335cbc142c8SSivaprakash Murugesan }; 336cbc142c8SSivaprakash Murugesan 337b7fbf46cSVinod Koul blsp_dma: dma-controller@7884000 { 33822592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 339e8a7fdc5SSivaprakash Murugesan reg = <0x07884000 0x2b000>; 34022592a22SSricharan R interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 34122592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>; 34222592a22SSricharan R clock-names = "bam_clk"; 34322592a22SSricharan R #dma-cells = <1>; 34422592a22SSricharan R qcom,ee = <0>; 34522592a22SSricharan R }; 34622592a22SSricharan R 34722592a22SSricharan R blsp1_uart1: serial@78af000 { 34822592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 349e8a7fdc5SSivaprakash Murugesan reg = <0x078af000 0x200>; 35022592a22SSricharan R interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 35122592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 35222592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 35322592a22SSricharan R clock-names = "core", "iface"; 35422592a22SSricharan R status = "disabled"; 35522592a22SSricharan R }; 35622592a22SSricharan R 35722592a22SSricharan R blsp1_uart3: serial@78b1000 { 35822592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 359e8a7fdc5SSivaprakash Murugesan reg = <0x078b1000 0x200>; 36022592a22SSricharan R interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 36122592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 36222592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 36322592a22SSricharan R clock-names = "core", "iface"; 36422592a22SSricharan R dmas = <&blsp_dma 4>, 36522592a22SSricharan R <&blsp_dma 5>; 36622592a22SSricharan R dma-names = "tx", "rx"; 36722592a22SSricharan R pinctrl-0 = <&hsuart_pins>; 36822592a22SSricharan R pinctrl-names = "default"; 36922592a22SSricharan R status = "disabled"; 37022592a22SSricharan R }; 37122592a22SSricharan R 372e8a7fdc5SSivaprakash Murugesan blsp1_uart5: serial@78b3000 { 373e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 374e8a7fdc5SSivaprakash Murugesan reg = <0x078b3000 0x200>; 375e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 376e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 377e8a7fdc5SSivaprakash Murugesan <&gcc GCC_BLSP1_AHB_CLK>; 378e8a7fdc5SSivaprakash Murugesan clock-names = "core", "iface"; 379e8a7fdc5SSivaprakash Murugesan pinctrl-0 = <&serial_4_pins>; 380e8a7fdc5SSivaprakash Murugesan pinctrl-names = "default"; 381e8a7fdc5SSivaprakash Murugesan status = "disabled"; 382e8a7fdc5SSivaprakash Murugesan }; 383e8a7fdc5SSivaprakash Murugesan 38422592a22SSricharan R blsp1_spi1: spi@78b5000 { 38522592a22SSricharan R compatible = "qcom,spi-qup-v2.2.1"; 38622592a22SSricharan R #address-cells = <1>; 38722592a22SSricharan R #size-cells = <0>; 388e8a7fdc5SSivaprakash Murugesan reg = <0x078b5000 0x600>; 38922592a22SSricharan R interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 39022592a22SSricharan R spi-max-frequency = <50000000>; 39122592a22SSricharan R clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 39222592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 39322592a22SSricharan R clock-names = "core", "iface"; 39422592a22SSricharan R dmas = <&blsp_dma 12>, <&blsp_dma 13>; 39522592a22SSricharan R dma-names = "tx", "rx"; 39622592a22SSricharan R pinctrl-0 = <&spi_0_pins>; 39722592a22SSricharan R pinctrl-names = "default"; 39822592a22SSricharan R status = "disabled"; 39922592a22SSricharan R }; 40022592a22SSricharan R 40122592a22SSricharan R blsp1_i2c2: i2c@78b6000 { 40222592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 40322592a22SSricharan R #address-cells = <1>; 40422592a22SSricharan R #size-cells = <0>; 405e8a7fdc5SSivaprakash Murugesan reg = <0x078b6000 0x600>; 40622592a22SSricharan R interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 40722592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 40822592a22SSricharan R <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 40922592a22SSricharan R clock-names = "iface", "core"; 41022592a22SSricharan R clock-frequency = <400000>; 41122592a22SSricharan R dmas = <&blsp_dma 15>, <&blsp_dma 14>; 41222592a22SSricharan R dma-names = "rx", "tx"; 41322592a22SSricharan R pinctrl-0 = <&i2c_0_pins>; 41422592a22SSricharan R pinctrl-names = "default"; 41522592a22SSricharan R status = "disabled"; 41622592a22SSricharan R }; 41722592a22SSricharan R 41822592a22SSricharan R blsp1_i2c3: i2c@78b7000 { 41922592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 42022592a22SSricharan R #address-cells = <1>; 42122592a22SSricharan R #size-cells = <0>; 422e8a7fdc5SSivaprakash Murugesan reg = <0x078b7000 0x600>; 42322592a22SSricharan R interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 42422592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 42522592a22SSricharan R <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 42622592a22SSricharan R clock-names = "iface", "core"; 42722592a22SSricharan R clock-frequency = <100000>; 42822592a22SSricharan R dmas = <&blsp_dma 17>, <&blsp_dma 16>; 42922592a22SSricharan R dma-names = "rx", "tx"; 43022592a22SSricharan R status = "disabled"; 43122592a22SSricharan R }; 43222592a22SSricharan R 433*9c0bd8e5SChukun Pan blsp1_i2c5: i2c@78b9000 { 434*9c0bd8e5SChukun Pan compatible = "qcom,i2c-qup-v2.2.1"; 435*9c0bd8e5SChukun Pan #address-cells = <1>; 436*9c0bd8e5SChukun Pan #size-cells = <0>; 437*9c0bd8e5SChukun Pan reg = <0x78b9000 0x600>; 438*9c0bd8e5SChukun Pan interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 439*9c0bd8e5SChukun Pan clocks = <&gcc GCC_BLSP1_AHB_CLK>, 440*9c0bd8e5SChukun Pan <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 441*9c0bd8e5SChukun Pan clock-names = "iface", "core"; 442*9c0bd8e5SChukun Pan clock-frequency = <400000>; 443*9c0bd8e5SChukun Pan dmas = <&blsp_dma 21>, <&blsp_dma 20>; 444*9c0bd8e5SChukun Pan dma-names = "rx", "tx"; 445*9c0bd8e5SChukun Pan status = "disabled"; 446*9c0bd8e5SChukun Pan }; 447*9c0bd8e5SChukun Pan 448abe66bb7SRobert Marko blsp1_i2c6: i2c@78ba000 { 449abe66bb7SRobert Marko compatible = "qcom,i2c-qup-v2.2.1"; 450abe66bb7SRobert Marko #address-cells = <1>; 451abe66bb7SRobert Marko #size-cells = <0>; 452abe66bb7SRobert Marko reg = <0x078ba000 0x600>; 453abe66bb7SRobert Marko interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 454abe66bb7SRobert Marko clocks = <&gcc GCC_BLSP1_AHB_CLK>, 455abe66bb7SRobert Marko <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 456abe66bb7SRobert Marko clock-names = "iface", "core"; 457abe66bb7SRobert Marko clock-frequency = <100000>; 458abe66bb7SRobert Marko dmas = <&blsp_dma 23>, <&blsp_dma 22>; 459abe66bb7SRobert Marko dma-names = "rx", "tx"; 460abe66bb7SRobert Marko status = "disabled"; 461abe66bb7SRobert Marko }; 462abe66bb7SRobert Marko 463b7fbf46cSVinod Koul qpic_bam: dma-controller@7984000 { 46422592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 465e8a7fdc5SSivaprakash Murugesan reg = <0x07984000 0x1a000>; 46622592a22SSricharan R interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 46722592a22SSricharan R clocks = <&gcc GCC_QPIC_AHB_CLK>; 46822592a22SSricharan R clock-names = "bam_clk"; 46922592a22SSricharan R #dma-cells = <1>; 47022592a22SSricharan R qcom,ee = <0>; 47122592a22SSricharan R status = "disabled"; 47222592a22SSricharan R }; 47322592a22SSricharan R 47422592a22SSricharan R qpic_nand: nand@79b0000 { 47522592a22SSricharan R compatible = "qcom,ipq8074-nand"; 476e8a7fdc5SSivaprakash Murugesan reg = <0x079b0000 0x10000>; 47722592a22SSricharan R #address-cells = <1>; 47822592a22SSricharan R #size-cells = <0>; 47922592a22SSricharan R clocks = <&gcc GCC_QPIC_CLK>, 48022592a22SSricharan R <&gcc GCC_QPIC_AHB_CLK>; 48122592a22SSricharan R clock-names = "core", "aon"; 48222592a22SSricharan R 48322592a22SSricharan R dmas = <&qpic_bam 0>, 48422592a22SSricharan R <&qpic_bam 1>, 48522592a22SSricharan R <&qpic_bam 2>; 48622592a22SSricharan R dma-names = "tx", "rx", "cmd"; 48722592a22SSricharan R pinctrl-0 = <&qpic_pins>; 48822592a22SSricharan R pinctrl-names = "default"; 48941dac73eSVaradarajan Narayanan status = "disabled"; 49041dac73eSVaradarajan Narayanan }; 49133057e16SSricharan R 4925e09bc51SSivaprakash Murugesan usb_0: usb@8af8800 { 4935e09bc51SSivaprakash Murugesan compatible = "qcom,dwc3"; 4945e09bc51SSivaprakash Murugesan reg = <0x08af8800 0x400>; 4955e09bc51SSivaprakash Murugesan #address-cells = <1>; 4965e09bc51SSivaprakash Murugesan #size-cells = <1>; 4975e09bc51SSivaprakash Murugesan ranges; 4985e09bc51SSivaprakash Murugesan 4995e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 5005e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 5015e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_SLEEP_CLK>, 5025e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 5035e09bc51SSivaprakash Murugesan clock-names = "sys_noc_axi", 5045e09bc51SSivaprakash Murugesan "master", 5055e09bc51SSivaprakash Murugesan "sleep", 5065e09bc51SSivaprakash Murugesan "mock_utmi"; 5075e09bc51SSivaprakash Murugesan 5085e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 5095e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 5105e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 5115e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 5125e09bc51SSivaprakash Murugesan <133330000>, 5135e09bc51SSivaprakash Murugesan <19200000>; 5145e09bc51SSivaprakash Murugesan 5155e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_BCR>; 5165e09bc51SSivaprakash Murugesan status = "disabled"; 5175e09bc51SSivaprakash Murugesan 5181f958f3dSGreg Kroah-Hartman dwc_0: dwc3@8a00000 { 5195e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 5205e09bc51SSivaprakash Murugesan reg = <0x8a00000 0xcd00>; 5215e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 5225e09bc51SSivaprakash Murugesan phys = <&qusb_phy_0>, <&usb0_ssphy>; 5235e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 5245e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 5255e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 5265e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 5275e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 5285e09bc51SSivaprakash Murugesan dr_mode = "host"; 5295e09bc51SSivaprakash Murugesan }; 5305e09bc51SSivaprakash Murugesan }; 5315e09bc51SSivaprakash Murugesan 5325e09bc51SSivaprakash Murugesan usb_1: usb@8cf8800 { 5335e09bc51SSivaprakash Murugesan compatible = "qcom,dwc3"; 5345e09bc51SSivaprakash Murugesan reg = <0x08cf8800 0x400>; 5355e09bc51SSivaprakash Murugesan #address-cells = <1>; 5365e09bc51SSivaprakash Murugesan #size-cells = <1>; 5375e09bc51SSivaprakash Murugesan ranges; 5385e09bc51SSivaprakash Murugesan 5395e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 5405e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 5415e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_SLEEP_CLK>, 5425e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 5435e09bc51SSivaprakash Murugesan clock-names = "sys_noc_axi", 5445e09bc51SSivaprakash Murugesan "master", 5455e09bc51SSivaprakash Murugesan "sleep", 5465e09bc51SSivaprakash Murugesan "mock_utmi"; 5475e09bc51SSivaprakash Murugesan 5485e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 5495e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 5505e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 5515e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 5525e09bc51SSivaprakash Murugesan <133330000>, 5535e09bc51SSivaprakash Murugesan <19200000>; 5545e09bc51SSivaprakash Murugesan 5555e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_BCR>; 5565e09bc51SSivaprakash Murugesan status = "disabled"; 5575e09bc51SSivaprakash Murugesan 5581f958f3dSGreg Kroah-Hartman dwc_1: dwc3@8c00000 { 5595e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 5605e09bc51SSivaprakash Murugesan reg = <0x8c00000 0xcd00>; 5615e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 5625e09bc51SSivaprakash Murugesan phys = <&qusb_phy_1>, <&usb1_ssphy>; 5635e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 5645e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 5655e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 5665e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 5675e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 5685e09bc51SSivaprakash Murugesan dr_mode = "host"; 5695e09bc51SSivaprakash Murugesan }; 5705e09bc51SSivaprakash Murugesan }; 5715e09bc51SSivaprakash Murugesan 572e8a7fdc5SSivaprakash Murugesan intc: interrupt-controller@b000000 { 573e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-qgic2"; 574e8a7fdc5SSivaprakash Murugesan interrupt-controller; 575e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <0x3>; 576e8a7fdc5SSivaprakash Murugesan reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 577e8a7fdc5SSivaprakash Murugesan }; 57833057e16SSricharan R 579e8a7fdc5SSivaprakash Murugesan timer { 580e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv8-timer"; 581e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 582e8a7fdc5SSivaprakash Murugesan <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 583e8a7fdc5SSivaprakash Murugesan <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 584e8a7fdc5SSivaprakash Murugesan <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 585e8a7fdc5SSivaprakash Murugesan }; 586e8a7fdc5SSivaprakash Murugesan 587949766e0SKathiravan T watchdog: watchdog@b017000 { 588949766e0SKathiravan T compatible = "qcom,kpss-wdt"; 589949766e0SKathiravan T reg = <0xb017000 0x1000>; 590949766e0SKathiravan T interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 591949766e0SKathiravan T clocks = <&sleep_clk>; 592949766e0SKathiravan T timeout-sec = <30>; 593949766e0SKathiravan T }; 594949766e0SKathiravan T 595e8a7fdc5SSivaprakash Murugesan timer@b120000 { 596e8a7fdc5SSivaprakash Murugesan #address-cells = <1>; 597e8a7fdc5SSivaprakash Murugesan #size-cells = <1>; 598e8a7fdc5SSivaprakash Murugesan ranges; 599e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv7-timer-mem"; 600e8a7fdc5SSivaprakash Murugesan reg = <0x0b120000 0x1000>; 601e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 602e8a7fdc5SSivaprakash Murugesan 603e8a7fdc5SSivaprakash Murugesan frame@b120000 { 604e8a7fdc5SSivaprakash Murugesan frame-number = <0>; 605e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 606e8a7fdc5SSivaprakash Murugesan <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 607e8a7fdc5SSivaprakash Murugesan reg = <0x0b121000 0x1000>, 608e8a7fdc5SSivaprakash Murugesan <0x0b122000 0x1000>; 609e8a7fdc5SSivaprakash Murugesan }; 610e8a7fdc5SSivaprakash Murugesan 611e8a7fdc5SSivaprakash Murugesan frame@b123000 { 612e8a7fdc5SSivaprakash Murugesan frame-number = <1>; 613e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 614e8a7fdc5SSivaprakash Murugesan reg = <0x0b123000 0x1000>; 61533057e16SSricharan R status = "disabled"; 61633057e16SSricharan R }; 61733057e16SSricharan R 618e8a7fdc5SSivaprakash Murugesan frame@b124000 { 619e8a7fdc5SSivaprakash Murugesan frame-number = <2>; 620e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 621e8a7fdc5SSivaprakash Murugesan reg = <0x0b124000 0x1000>; 62233057e16SSricharan R status = "disabled"; 62333057e16SSricharan R }; 62433057e16SSricharan R 625e8a7fdc5SSivaprakash Murugesan frame@b125000 { 626e8a7fdc5SSivaprakash Murugesan frame-number = <3>; 627e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 628e8a7fdc5SSivaprakash Murugesan reg = <0x0b125000 0x1000>; 62933057e16SSricharan R status = "disabled"; 63033057e16SSricharan R }; 63133057e16SSricharan R 632e8a7fdc5SSivaprakash Murugesan frame@b126000 { 633e8a7fdc5SSivaprakash Murugesan frame-number = <4>; 634e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 635e8a7fdc5SSivaprakash Murugesan reg = <0x0b126000 0x1000>; 636e8a7fdc5SSivaprakash Murugesan status = "disabled"; 637e8a7fdc5SSivaprakash Murugesan }; 638e8a7fdc5SSivaprakash Murugesan 639e8a7fdc5SSivaprakash Murugesan frame@b127000 { 640e8a7fdc5SSivaprakash Murugesan frame-number = <5>; 641e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 642e8a7fdc5SSivaprakash Murugesan reg = <0x0b127000 0x1000>; 643e8a7fdc5SSivaprakash Murugesan status = "disabled"; 644e8a7fdc5SSivaprakash Murugesan }; 645e8a7fdc5SSivaprakash Murugesan 646e8a7fdc5SSivaprakash Murugesan frame@b128000 { 647e8a7fdc5SSivaprakash Murugesan frame-number = <6>; 648e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 649e8a7fdc5SSivaprakash Murugesan reg = <0x0b128000 0x1000>; 650e8a7fdc5SSivaprakash Murugesan status = "disabled"; 651e8a7fdc5SSivaprakash Murugesan }; 652e8a7fdc5SSivaprakash Murugesan }; 653e8a7fdc5SSivaprakash Murugesan 65433057e16SSricharan R pcie1: pci@10000000 { 65533057e16SSricharan R compatible = "qcom,pcie-ipq8074"; 65652c9887fSVinod Koul reg = <0x10000000 0xf1d>, 65752c9887fSVinod Koul <0x10000f20 0xa8>, 65852c9887fSVinod Koul <0x00088000 0x2000>, 65952c9887fSVinod Koul <0x10100000 0x1000>; 66033057e16SSricharan R reg-names = "dbi", "elbi", "parf", "config"; 66133057e16SSricharan R device_type = "pci"; 66233057e16SSricharan R linux,pci-domain = <1>; 66333057e16SSricharan R bus-range = <0x00 0xff>; 66433057e16SSricharan R num-lanes = <1>; 66533057e16SSricharan R #address-cells = <3>; 66633057e16SSricharan R #size-cells = <2>; 66733057e16SSricharan R 66833057e16SSricharan R phys = <&pcie_phy1>; 66933057e16SSricharan R phy-names = "pciephy"; 67033057e16SSricharan R 67133057e16SSricharan R ranges = <0x81000000 0 0x10200000 0x10200000 67233057e16SSricharan R 0 0x100000 /* downstream I/O */ 67333057e16SSricharan R 0x82000000 0 0x10300000 0x10300000 67433057e16SSricharan R 0 0xd00000>; /* non-prefetchable memory */ 67533057e16SSricharan R 67633057e16SSricharan R interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 67733057e16SSricharan R interrupt-names = "msi"; 67833057e16SSricharan R #interrupt-cells = <1>; 67933057e16SSricharan R interrupt-map-mask = <0 0 0 0x7>; 68033057e16SSricharan R interrupt-map = <0 0 0 1 &intc 0 142 68133057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 68233057e16SSricharan R <0 0 0 2 &intc 0 143 68333057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 68433057e16SSricharan R <0 0 0 3 &intc 0 144 68533057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 68633057e16SSricharan R <0 0 0 4 &intc 0 145 68733057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 68833057e16SSricharan R 68933057e16SSricharan R clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 69033057e16SSricharan R <&gcc GCC_PCIE1_AXI_M_CLK>, 69133057e16SSricharan R <&gcc GCC_PCIE1_AXI_S_CLK>, 69233057e16SSricharan R <&gcc GCC_PCIE1_AHB_CLK>, 69333057e16SSricharan R <&gcc GCC_PCIE1_AUX_CLK>; 69433057e16SSricharan R clock-names = "iface", 69533057e16SSricharan R "axi_m", 69633057e16SSricharan R "axi_s", 69733057e16SSricharan R "ahb", 69833057e16SSricharan R "aux"; 69933057e16SSricharan R resets = <&gcc GCC_PCIE1_PIPE_ARES>, 70033057e16SSricharan R <&gcc GCC_PCIE1_SLEEP_ARES>, 70133057e16SSricharan R <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 70233057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 70333057e16SSricharan R <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 70433057e16SSricharan R <&gcc GCC_PCIE1_AHB_ARES>, 70533057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 70633057e16SSricharan R reset-names = "pipe", 70733057e16SSricharan R "sleep", 70833057e16SSricharan R "sticky", 70933057e16SSricharan R "axi_m", 71033057e16SSricharan R "axi_s", 71133057e16SSricharan R "ahb", 71233057e16SSricharan R "axi_m_sticky"; 71333057e16SSricharan R status = "disabled"; 71433057e16SSricharan R }; 71541dac73eSVaradarajan Narayanan 716e8a7fdc5SSivaprakash Murugesan pcie0: pci@20000000 { 717e8a7fdc5SSivaprakash Murugesan compatible = "qcom,pcie-ipq8074"; 71852c9887fSVinod Koul reg = <0x20000000 0xf1d>, 71952c9887fSVinod Koul <0x20000f20 0xa8>, 72052c9887fSVinod Koul <0x00080000 0x2000>, 72152c9887fSVinod Koul <0x20100000 0x1000>; 722e8a7fdc5SSivaprakash Murugesan reg-names = "dbi", "elbi", "parf", "config"; 723e8a7fdc5SSivaprakash Murugesan device_type = "pci"; 724e8a7fdc5SSivaprakash Murugesan linux,pci-domain = <0>; 725e8a7fdc5SSivaprakash Murugesan bus-range = <0x00 0xff>; 726e8a7fdc5SSivaprakash Murugesan num-lanes = <1>; 727e8a7fdc5SSivaprakash Murugesan #address-cells = <3>; 728e8a7fdc5SSivaprakash Murugesan #size-cells = <2>; 72941dac73eSVaradarajan Narayanan 730e8a7fdc5SSivaprakash Murugesan phys = <&pcie_phy0>; 731e8a7fdc5SSivaprakash Murugesan phy-names = "pciephy"; 73241dac73eSVaradarajan Narayanan 733e8a7fdc5SSivaprakash Murugesan ranges = <0x81000000 0 0x20200000 0x20200000 734e8a7fdc5SSivaprakash Murugesan 0 0x100000 /* downstream I/O */ 735e8a7fdc5SSivaprakash Murugesan 0x82000000 0 0x20300000 0x20300000 736e8a7fdc5SSivaprakash Murugesan 0 0xd00000>; /* non-prefetchable memory */ 73741dac73eSVaradarajan Narayanan 738e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 739e8a7fdc5SSivaprakash Murugesan interrupt-names = "msi"; 740e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <1>; 741e8a7fdc5SSivaprakash Murugesan interrupt-map-mask = <0 0 0 0x7>; 742e8a7fdc5SSivaprakash Murugesan interrupt-map = <0 0 0 1 &intc 0 75 743e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 744e8a7fdc5SSivaprakash Murugesan <0 0 0 2 &intc 0 78 745e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 746e8a7fdc5SSivaprakash Murugesan <0 0 0 3 &intc 0 79 747e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 748e8a7fdc5SSivaprakash Murugesan <0 0 0 4 &intc 0 83 749e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 75041dac73eSVaradarajan Narayanan 751e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 752e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_M_CLK>, 753e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_S_CLK>, 754e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_CLK>, 755e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AUX_CLK>; 75641dac73eSVaradarajan Narayanan 757e8a7fdc5SSivaprakash Murugesan clock-names = "iface", 758e8a7fdc5SSivaprakash Murugesan "axi_m", 759e8a7fdc5SSivaprakash Murugesan "axi_s", 760e8a7fdc5SSivaprakash Murugesan "ahb", 761e8a7fdc5SSivaprakash Murugesan "aux"; 762e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PIPE_ARES>, 763e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_SLEEP_ARES>, 764e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 765e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 766e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 767e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_ARES>, 768e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 769e8a7fdc5SSivaprakash Murugesan reset-names = "pipe", 770e8a7fdc5SSivaprakash Murugesan "sleep", 771e8a7fdc5SSivaprakash Murugesan "sticky", 772e8a7fdc5SSivaprakash Murugesan "axi_m", 773e8a7fdc5SSivaprakash Murugesan "axi_s", 774e8a7fdc5SSivaprakash Murugesan "ahb", 775e8a7fdc5SSivaprakash Murugesan "axi_m_sticky"; 776e8a7fdc5SSivaprakash Murugesan status = "disabled"; 77741dac73eSVaradarajan Narayanan }; 77841dac73eSVaradarajan Narayanan }; 77941dac73eSVaradarajan Narayanan}; 780