197fb5e8dSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 241dac73eSVaradarajan Narayanan/* 341dac73eSVaradarajan Narayanan * Copyright (c) 2017, The Linux Foundation. All rights reserved. 441dac73eSVaradarajan Narayanan */ 541dac73eSVaradarajan Narayanan 641dac73eSVaradarajan Narayanan#include <dt-bindings/interrupt-controller/arm-gic.h> 741dac73eSVaradarajan Narayanan#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 841dac73eSVaradarajan Narayanan 941dac73eSVaradarajan Narayanan/ { 1041dac73eSVaradarajan Narayanan model = "Qualcomm Technologies, Inc. IPQ8074"; 1141dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074"; 1241dac73eSVaradarajan Narayanan 13e8a7fdc5SSivaprakash Murugesan clocks { 14e8a7fdc5SSivaprakash Murugesan sleep_clk: sleep_clk { 15e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 16e8a7fdc5SSivaprakash Murugesan clock-frequency = <32000>; 17e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 18e8a7fdc5SSivaprakash Murugesan }; 19e8a7fdc5SSivaprakash Murugesan 20e8a7fdc5SSivaprakash Murugesan xo: xo { 21e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 22e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 23e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 24e8a7fdc5SSivaprakash Murugesan }; 25e8a7fdc5SSivaprakash Murugesan }; 26e8a7fdc5SSivaprakash Murugesan 27e8a7fdc5SSivaprakash Murugesan cpus { 28e8a7fdc5SSivaprakash Murugesan #address-cells = <0x1>; 29e8a7fdc5SSivaprakash Murugesan #size-cells = <0x0>; 30e8a7fdc5SSivaprakash Murugesan 31e8a7fdc5SSivaprakash Murugesan CPU0: cpu@0 { 32e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 33e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 34e8a7fdc5SSivaprakash Murugesan reg = <0x0>; 35e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 36e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 37e8a7fdc5SSivaprakash Murugesan }; 38e8a7fdc5SSivaprakash Murugesan 39e8a7fdc5SSivaprakash Murugesan CPU1: cpu@1 { 40e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 41e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 42e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 43e8a7fdc5SSivaprakash Murugesan reg = <0x1>; 44e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 45e8a7fdc5SSivaprakash Murugesan }; 46e8a7fdc5SSivaprakash Murugesan 47e8a7fdc5SSivaprakash Murugesan CPU2: cpu@2 { 48e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 49e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 50e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 51e8a7fdc5SSivaprakash Murugesan reg = <0x2>; 52e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 53e8a7fdc5SSivaprakash Murugesan }; 54e8a7fdc5SSivaprakash Murugesan 55e8a7fdc5SSivaprakash Murugesan CPU3: cpu@3 { 56e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 57e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 58e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 59e8a7fdc5SSivaprakash Murugesan reg = <0x3>; 60e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 61e8a7fdc5SSivaprakash Murugesan }; 62e8a7fdc5SSivaprakash Murugesan 63e8a7fdc5SSivaprakash Murugesan L2_0: l2-cache { 64e8a7fdc5SSivaprakash Murugesan compatible = "cache"; 65e8a7fdc5SSivaprakash Murugesan cache-level = <0x2>; 66e8a7fdc5SSivaprakash Murugesan }; 67e8a7fdc5SSivaprakash Murugesan }; 68e8a7fdc5SSivaprakash Murugesan 69e8a7fdc5SSivaprakash Murugesan pmu { 70292b1874SKathiravan T compatible = "arm,cortex-a53-pmu"; 71e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72e8a7fdc5SSivaprakash Murugesan }; 73e8a7fdc5SSivaprakash Murugesan 74e8a7fdc5SSivaprakash Murugesan psci { 75e8a7fdc5SSivaprakash Murugesan compatible = "arm,psci-1.0"; 76e8a7fdc5SSivaprakash Murugesan method = "smc"; 77e8a7fdc5SSivaprakash Murugesan }; 78e8a7fdc5SSivaprakash Murugesan 7942124b94SRobert Marko reserved-memory { 8042124b94SRobert Marko #address-cells = <2>; 8142124b94SRobert Marko #size-cells = <2>; 8242124b94SRobert Marko ranges; 8342124b94SRobert Marko 8442124b94SRobert Marko smem@4ab00000 { 8542124b94SRobert Marko compatible = "qcom,smem"; 8642124b94SRobert Marko reg = <0x0 0x4ab00000 0x0 0x00100000>; 8742124b94SRobert Marko no-map; 8842124b94SRobert Marko 8942124b94SRobert Marko hwlocks = <&tcsr_mutex 0>; 9042124b94SRobert Marko }; 91e4a4fdcfSKathiravan T 92e4a4fdcfSKathiravan T memory@4ac00000 { 93e4a4fdcfSKathiravan T no-map; 94e4a4fdcfSKathiravan T reg = <0x0 0x4ac00000 0x0 0x00400000>; 95e4a4fdcfSKathiravan T }; 9642124b94SRobert Marko }; 9742124b94SRobert Marko 986df9102fSGokul Sriram Palanisamy firmware { 996df9102fSGokul Sriram Palanisamy scm { 1006df9102fSGokul Sriram Palanisamy compatible = "qcom,scm-ipq8074", "qcom,scm"; 1016df9102fSGokul Sriram Palanisamy }; 1026df9102fSGokul Sriram Palanisamy }; 1036df9102fSGokul Sriram Palanisamy 10441dac73eSVaradarajan Narayanan soc: soc { 10541dac73eSVaradarajan Narayanan #address-cells = <0x1>; 10641dac73eSVaradarajan Narayanan #size-cells = <0x1>; 10741dac73eSVaradarajan Narayanan ranges = <0 0 0 0xffffffff>; 10841dac73eSVaradarajan Narayanan compatible = "simple-bus"; 10941dac73eSVaradarajan Narayanan 1105e09bc51SSivaprakash Murugesan ssphy_1: phy@58000 { 1115e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1125e09bc51SSivaprakash Murugesan reg = <0x00058000 0x1c4>; 1135e09bc51SSivaprakash Murugesan #address-cells = <1>; 1145e09bc51SSivaprakash Murugesan #size-cells = <1>; 1155e09bc51SSivaprakash Murugesan ranges; 1165e09bc51SSivaprakash Murugesan 1175e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_AUX_CLK>, 1185e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1195e09bc51SSivaprakash Murugesan <&xo>; 1205e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1215e09bc51SSivaprakash Murugesan 1225e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_PHY_BCR>, 1235e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_1_PHY_BCR>; 1245e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1255e09bc51SSivaprakash Murugesan status = "disabled"; 1265e09bc51SSivaprakash Murugesan 1271351512fSShawn Guo usb1_ssphy: phy@58200 { 1285e09bc51SSivaprakash Murugesan reg = <0x00058200 0x130>, /* Tx */ 1295e09bc51SSivaprakash Murugesan <0x00058400 0x200>, /* Rx */ 1305e09bc51SSivaprakash Murugesan <0x00058800 0x1f8>, /* PCS */ 1315e09bc51SSivaprakash Murugesan <0x00058600 0x044>; /* PCS misc*/ 1325e09bc51SSivaprakash Murugesan #phy-cells = <0>; 13382d61e19SShawn Guo #clock-cells = <1>; 1345e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PIPE_CLK>; 1355e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1365e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb1_pipe_clk_src"; 1375e09bc51SSivaprakash Murugesan }; 1385e09bc51SSivaprakash Murugesan }; 1395e09bc51SSivaprakash Murugesan 1405e09bc51SSivaprakash Murugesan qusb_phy_1: phy@59000 { 1415e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1425e09bc51SSivaprakash Murugesan reg = <0x00059000 0x180>; 1435e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1445e09bc51SSivaprakash Murugesan 1455e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1465e09bc51SSivaprakash Murugesan <&xo>; 1475e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1485e09bc51SSivaprakash Murugesan 1495e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 1505e09bc51SSivaprakash Murugesan status = "disabled"; 1515e09bc51SSivaprakash Murugesan }; 1525e09bc51SSivaprakash Murugesan 1535e09bc51SSivaprakash Murugesan ssphy_0: phy@78000 { 1545e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1555e09bc51SSivaprakash Murugesan reg = <0x00078000 0x1c4>; 1565e09bc51SSivaprakash Murugesan #address-cells = <1>; 1575e09bc51SSivaprakash Murugesan #size-cells = <1>; 1585e09bc51SSivaprakash Murugesan ranges; 1595e09bc51SSivaprakash Murugesan 1605e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_AUX_CLK>, 1615e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1625e09bc51SSivaprakash Murugesan <&xo>; 1635e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1645e09bc51SSivaprakash Murugesan 1655e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_PHY_BCR>, 1665e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_0_PHY_BCR>; 1675e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1685e09bc51SSivaprakash Murugesan status = "disabled"; 1695e09bc51SSivaprakash Murugesan 1701351512fSShawn Guo usb0_ssphy: phy@78200 { 1715e09bc51SSivaprakash Murugesan reg = <0x00078200 0x130>, /* Tx */ 1725e09bc51SSivaprakash Murugesan <0x00078400 0x200>, /* Rx */ 1735e09bc51SSivaprakash Murugesan <0x00078800 0x1f8>, /* PCS */ 1745e09bc51SSivaprakash Murugesan <0x00078600 0x044>; /* PCS misc*/ 1755e09bc51SSivaprakash Murugesan #phy-cells = <0>; 17682d61e19SShawn Guo #clock-cells = <1>; 1775e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PIPE_CLK>; 1785e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1795e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb0_pipe_clk_src"; 1805e09bc51SSivaprakash Murugesan }; 1815e09bc51SSivaprakash Murugesan }; 1825e09bc51SSivaprakash Murugesan 1835e09bc51SSivaprakash Murugesan qusb_phy_0: phy@79000 { 1845e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1855e09bc51SSivaprakash Murugesan reg = <0x00079000 0x180>; 1865e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1875e09bc51SSivaprakash Murugesan 1885e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1895e09bc51SSivaprakash Murugesan <&xo>; 1905e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1915e09bc51SSivaprakash Murugesan 1925e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 19358b2785dSRobert Marko status = "disabled"; 1945e09bc51SSivaprakash Murugesan }; 1955e09bc51SSivaprakash Murugesan 196942bcd33SShawn Guo pcie_qmp0: phy@86000 { 197e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 198e8a7fdc5SSivaprakash Murugesan reg = <0x00086000 0x1000>; 199942bcd33SShawn Guo #address-cells = <1>; 200942bcd33SShawn Guo #size-cells = <1>; 201942bcd33SShawn Guo ranges; 202e8a7fdc5SSivaprakash Murugesan 203942bcd33SShawn Guo clocks = <&gcc GCC_PCIE0_AUX_CLK>, 204942bcd33SShawn Guo <&gcc GCC_PCIE0_AHB_CLK>; 205942bcd33SShawn Guo clock-names = "aux", "cfg_ahb"; 206e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PHY_BCR>, 207e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0PHY_PHY_BCR>; 208e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 209e8a7fdc5SSivaprakash Murugesan "common"; 210e8a7fdc5SSivaprakash Murugesan status = "disabled"; 211942bcd33SShawn Guo 212942bcd33SShawn Guo pcie_phy0: phy@86200 { 213942bcd33SShawn Guo reg = <0x86200 0x16c>, 214942bcd33SShawn Guo <0x86400 0x200>, 215942bcd33SShawn Guo <0x86800 0x4f4>; 216942bcd33SShawn Guo #phy-cells = <0>; 217942bcd33SShawn Guo #clock-cells = <0>; 218942bcd33SShawn Guo clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 219942bcd33SShawn Guo clock-names = "pipe0"; 220942bcd33SShawn Guo clock-output-names = "pcie_0_pipe_clk"; 221942bcd33SShawn Guo }; 222e8a7fdc5SSivaprakash Murugesan }; 223e8a7fdc5SSivaprakash Murugesan 224942bcd33SShawn Guo pcie_qmp1: phy@8e000 { 225e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 226e8a7fdc5SSivaprakash Murugesan reg = <0x0008e000 0x1000>; 227942bcd33SShawn Guo #address-cells = <1>; 228942bcd33SShawn Guo #size-cells = <1>; 229942bcd33SShawn Guo ranges; 230e8a7fdc5SSivaprakash Murugesan 231942bcd33SShawn Guo clocks = <&gcc GCC_PCIE1_AUX_CLK>, 232942bcd33SShawn Guo <&gcc GCC_PCIE1_AHB_CLK>; 233942bcd33SShawn Guo clock-names = "aux", "cfg_ahb"; 234e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE1_PHY_BCR>, 235e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE1PHY_PHY_BCR>; 236e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 237e8a7fdc5SSivaprakash Murugesan "common"; 238e8a7fdc5SSivaprakash Murugesan status = "disabled"; 239942bcd33SShawn Guo 240942bcd33SShawn Guo pcie_phy1: phy@8e200 { 241942bcd33SShawn Guo reg = <0x8e200 0x16c>, 242942bcd33SShawn Guo <0x8e400 0x200>, 243942bcd33SShawn Guo <0x8e800 0x4f4>; 244942bcd33SShawn Guo #phy-cells = <0>; 245942bcd33SShawn Guo #clock-cells = <0>; 246942bcd33SShawn Guo clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 247942bcd33SShawn Guo clock-names = "pipe0"; 248942bcd33SShawn Guo clock-output-names = "pcie_1_pipe_clk"; 249942bcd33SShawn Guo }; 250e8a7fdc5SSivaprakash Murugesan }; 251e8a7fdc5SSivaprakash Murugesan 252d201f677SRobert Marko mdio: mdio@90000 { 253d201f677SRobert Marko compatible = "qcom,ipq4019-mdio"; 254d201f677SRobert Marko reg = <0x00090000 0x64>; 255d201f677SRobert Marko #address-cells = <1>; 256d201f677SRobert Marko #size-cells = <0>; 257d201f677SRobert Marko 258d201f677SRobert Marko clocks = <&gcc GCC_MDIO_AHB_CLK>; 259d201f677SRobert Marko clock-names = "gcc_mdio_ahb_clk"; 260d201f677SRobert Marko 261d201f677SRobert Marko status = "disabled"; 262d201f677SRobert Marko }; 263d201f677SRobert Marko 264f26f6a5eSRobert Marko prng: rng@e3000 { 265f26f6a5eSRobert Marko compatible = "qcom,prng-ee"; 266f26f6a5eSRobert Marko reg = <0x000e3000 0x1000>; 267f26f6a5eSRobert Marko clocks = <&gcc GCC_PRNG_AHB_CLK>; 268f26f6a5eSRobert Marko clock-names = "core"; 269f26f6a5eSRobert Marko status = "disabled"; 270f26f6a5eSRobert Marko }; 271f26f6a5eSRobert Marko 272bbef0142SShawn Guo cryptobam: dma-controller@704000 { 273f9e2df82SRobert Marko compatible = "qcom,bam-v1.7.0"; 274f9e2df82SRobert Marko reg = <0x00704000 0x20000>; 275f9e2df82SRobert Marko interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 276f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 277f9e2df82SRobert Marko clock-names = "bam_clk"; 278f9e2df82SRobert Marko #dma-cells = <1>; 279f9e2df82SRobert Marko qcom,ee = <1>; 2808c97f0acSShawn Guo qcom,controlled-remotely; 281f9e2df82SRobert Marko status = "disabled"; 282f9e2df82SRobert Marko }; 283f9e2df82SRobert Marko 284f9e2df82SRobert Marko crypto: crypto@73a000 { 285f9e2df82SRobert Marko compatible = "qcom,crypto-v5.1"; 286f9e2df82SRobert Marko reg = <0x0073a000 0x6000>; 287f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 288f9e2df82SRobert Marko <&gcc GCC_CRYPTO_AXI_CLK>, 289f9e2df82SRobert Marko <&gcc GCC_CRYPTO_CLK>; 290f9e2df82SRobert Marko clock-names = "iface", "bus", "core"; 291f9e2df82SRobert Marko dmas = <&cryptobam 2>, <&cryptobam 3>; 292f9e2df82SRobert Marko dma-names = "rx", "tx"; 293f9e2df82SRobert Marko status = "disabled"; 294f9e2df82SRobert Marko }; 295f9e2df82SRobert Marko 29633057e16SSricharan R tlmm: pinctrl@1000000 { 29741dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074-pinctrl"; 298e8a7fdc5SSivaprakash Murugesan reg = <0x01000000 0x300000>; 29941dac73eSVaradarajan Narayanan interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 30041dac73eSVaradarajan Narayanan gpio-controller; 301297177a4SChristian Lamparter gpio-ranges = <&tlmm 0 0 70>; 30241dac73eSVaradarajan Narayanan #gpio-cells = <0x2>; 30341dac73eSVaradarajan Narayanan interrupt-controller; 30441dac73eSVaradarajan Narayanan #interrupt-cells = <0x2>; 30522592a22SSricharan R 30622592a22SSricharan R serial_4_pins: serial4-pinmux { 30722592a22SSricharan R pins = "gpio23", "gpio24"; 30822592a22SSricharan R function = "blsp4_uart1"; 30922592a22SSricharan R drive-strength = <8>; 31022592a22SSricharan R bias-disable; 31122592a22SSricharan R }; 31222592a22SSricharan R 31322592a22SSricharan R i2c_0_pins: i2c-0-pinmux { 31422592a22SSricharan R pins = "gpio42", "gpio43"; 31522592a22SSricharan R function = "blsp1_i2c"; 31622592a22SSricharan R drive-strength = <8>; 31722592a22SSricharan R bias-disable; 31822592a22SSricharan R }; 31922592a22SSricharan R 32022592a22SSricharan R spi_0_pins: spi-0-pins { 32122592a22SSricharan R pins = "gpio38", "gpio39", "gpio40", "gpio41"; 32222592a22SSricharan R function = "blsp0_spi"; 32322592a22SSricharan R drive-strength = <8>; 32422592a22SSricharan R bias-disable; 32522592a22SSricharan R }; 32622592a22SSricharan R 32722592a22SSricharan R hsuart_pins: hsuart-pins { 32822592a22SSricharan R pins = "gpio46", "gpio47", "gpio48", "gpio49"; 32922592a22SSricharan R function = "blsp2_uart"; 33022592a22SSricharan R drive-strength = <8>; 33122592a22SSricharan R bias-disable; 33222592a22SSricharan R }; 33322592a22SSricharan R 33422592a22SSricharan R qpic_pins: qpic-pins { 33522592a22SSricharan R pins = "gpio1", "gpio3", "gpio4", 33622592a22SSricharan R "gpio5", "gpio6", "gpio7", 33722592a22SSricharan R "gpio8", "gpio10", "gpio11", 33822592a22SSricharan R "gpio12", "gpio13", "gpio14", 33922592a22SSricharan R "gpio15", "gpio16", "gpio17"; 34022592a22SSricharan R function = "qpic"; 34122592a22SSricharan R drive-strength = <8>; 34222592a22SSricharan R bias-disable; 34322592a22SSricharan R }; 34441dac73eSVaradarajan Narayanan }; 34541dac73eSVaradarajan Narayanan 34641dac73eSVaradarajan Narayanan gcc: gcc@1800000 { 34741dac73eSVaradarajan Narayanan compatible = "qcom,gcc-ipq8074"; 348e8a7fdc5SSivaprakash Murugesan reg = <0x01800000 0x80000>; 34941dac73eSVaradarajan Narayanan #clock-cells = <0x1>; 35041dac73eSVaradarajan Narayanan #reset-cells = <0x1>; 35141dac73eSVaradarajan Narayanan }; 35241dac73eSVaradarajan Narayanan 35342124b94SRobert Marko tcsr_mutex: hwlock@1905000 { 35442124b94SRobert Marko compatible = "qcom,tcsr-mutex"; 35542124b94SRobert Marko reg = <0x01905000 0x20000>; 35642124b94SRobert Marko #hwlock-cells = <1>; 35742124b94SRobert Marko }; 35842124b94SRobert Marko 35963750607SRobert Marko spmi_bus: spmi@200f000 { 36063750607SRobert Marko compatible = "qcom,spmi-pmic-arb"; 36163750607SRobert Marko reg = <0x0200f000 0x001000>, 36263750607SRobert Marko <0x02400000 0x800000>, 36363750607SRobert Marko <0x02c00000 0x800000>, 36463750607SRobert Marko <0x03800000 0x200000>, 36563750607SRobert Marko <0x0200a000 0x000700>; 36663750607SRobert Marko reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 36763750607SRobert Marko interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 36863750607SRobert Marko interrupt-names = "periph_irq"; 36963750607SRobert Marko qcom,ee = <0>; 37063750607SRobert Marko qcom,channel = <0>; 37163750607SRobert Marko #address-cells = <2>; 37263750607SRobert Marko #size-cells = <0>; 37363750607SRobert Marko interrupt-controller; 37463750607SRobert Marko #interrupt-cells = <4>; 37563750607SRobert Marko cell-index = <0>; 37663750607SRobert Marko }; 37763750607SRobert Marko 378cbc142c8SSivaprakash Murugesan sdhc_1: sdhci@7824900 { 379cbc142c8SSivaprakash Murugesan compatible = "qcom,sdhci-msm-v4"; 380cbc142c8SSivaprakash Murugesan reg = <0x7824900 0x500>, <0x7824000 0x800>; 381cbc142c8SSivaprakash Murugesan reg-names = "hc_mem", "core_mem"; 382cbc142c8SSivaprakash Murugesan 383cbc142c8SSivaprakash Murugesan interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 384cbc142c8SSivaprakash Murugesan <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 385cbc142c8SSivaprakash Murugesan interrupt-names = "hc_irq", "pwr_irq"; 386cbc142c8SSivaprakash Murugesan 387cbc142c8SSivaprakash Murugesan clocks = <&xo>, 388cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_AHB_CLK>, 389cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_APPS_CLK>; 390cbc142c8SSivaprakash Murugesan clock-names = "xo", "iface", "core"; 391cbc142c8SSivaprakash Murugesan max-frequency = <384000000>; 392cbc142c8SSivaprakash Murugesan mmc-ddr-1_8v; 393cbc142c8SSivaprakash Murugesan mmc-hs200-1_8v; 394cbc142c8SSivaprakash Murugesan mmc-hs400-1_8v; 395cbc142c8SSivaprakash Murugesan bus-width = <8>; 396cbc142c8SSivaprakash Murugesan 397cbc142c8SSivaprakash Murugesan status = "disabled"; 398cbc142c8SSivaprakash Murugesan }; 399cbc142c8SSivaprakash Murugesan 400b7fbf46cSVinod Koul blsp_dma: dma-controller@7884000 { 40122592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 402e8a7fdc5SSivaprakash Murugesan reg = <0x07884000 0x2b000>; 40322592a22SSricharan R interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 40422592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>; 40522592a22SSricharan R clock-names = "bam_clk"; 40622592a22SSricharan R #dma-cells = <1>; 40722592a22SSricharan R qcom,ee = <0>; 40822592a22SSricharan R }; 40922592a22SSricharan R 41022592a22SSricharan R blsp1_uart1: serial@78af000 { 41122592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 412e8a7fdc5SSivaprakash Murugesan reg = <0x078af000 0x200>; 41322592a22SSricharan R interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 41422592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 41522592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 41622592a22SSricharan R clock-names = "core", "iface"; 41722592a22SSricharan R status = "disabled"; 41822592a22SSricharan R }; 41922592a22SSricharan R 42022592a22SSricharan R blsp1_uart3: serial@78b1000 { 42122592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 422e8a7fdc5SSivaprakash Murugesan reg = <0x078b1000 0x200>; 42322592a22SSricharan R interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 42422592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 42522592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 42622592a22SSricharan R clock-names = "core", "iface"; 42722592a22SSricharan R dmas = <&blsp_dma 4>, 42822592a22SSricharan R <&blsp_dma 5>; 42922592a22SSricharan R dma-names = "tx", "rx"; 43022592a22SSricharan R pinctrl-0 = <&hsuart_pins>; 43122592a22SSricharan R pinctrl-names = "default"; 43222592a22SSricharan R status = "disabled"; 43322592a22SSricharan R }; 43422592a22SSricharan R 435e8a7fdc5SSivaprakash Murugesan blsp1_uart5: serial@78b3000 { 436e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 437e8a7fdc5SSivaprakash Murugesan reg = <0x078b3000 0x200>; 438e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 439e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 440e8a7fdc5SSivaprakash Murugesan <&gcc GCC_BLSP1_AHB_CLK>; 441e8a7fdc5SSivaprakash Murugesan clock-names = "core", "iface"; 442e8a7fdc5SSivaprakash Murugesan pinctrl-0 = <&serial_4_pins>; 443e8a7fdc5SSivaprakash Murugesan pinctrl-names = "default"; 444e8a7fdc5SSivaprakash Murugesan status = "disabled"; 445e8a7fdc5SSivaprakash Murugesan }; 446e8a7fdc5SSivaprakash Murugesan 44722592a22SSricharan R blsp1_spi1: spi@78b5000 { 44822592a22SSricharan R compatible = "qcom,spi-qup-v2.2.1"; 44922592a22SSricharan R #address-cells = <1>; 45022592a22SSricharan R #size-cells = <0>; 451e8a7fdc5SSivaprakash Murugesan reg = <0x078b5000 0x600>; 45222592a22SSricharan R interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 45322592a22SSricharan R spi-max-frequency = <50000000>; 45422592a22SSricharan R clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 45522592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 45622592a22SSricharan R clock-names = "core", "iface"; 45722592a22SSricharan R dmas = <&blsp_dma 12>, <&blsp_dma 13>; 45822592a22SSricharan R dma-names = "tx", "rx"; 45922592a22SSricharan R pinctrl-0 = <&spi_0_pins>; 46022592a22SSricharan R pinctrl-names = "default"; 46122592a22SSricharan R status = "disabled"; 46222592a22SSricharan R }; 46322592a22SSricharan R 46422592a22SSricharan R blsp1_i2c2: i2c@78b6000 { 46522592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 46622592a22SSricharan R #address-cells = <1>; 46722592a22SSricharan R #size-cells = <0>; 468e8a7fdc5SSivaprakash Murugesan reg = <0x078b6000 0x600>; 46922592a22SSricharan R interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 47022592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 47122592a22SSricharan R <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 47222592a22SSricharan R clock-names = "iface", "core"; 47322592a22SSricharan R clock-frequency = <400000>; 47422592a22SSricharan R dmas = <&blsp_dma 15>, <&blsp_dma 14>; 47522592a22SSricharan R dma-names = "rx", "tx"; 47622592a22SSricharan R pinctrl-0 = <&i2c_0_pins>; 47722592a22SSricharan R pinctrl-names = "default"; 47822592a22SSricharan R status = "disabled"; 47922592a22SSricharan R }; 48022592a22SSricharan R 48122592a22SSricharan R blsp1_i2c3: i2c@78b7000 { 48222592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 48322592a22SSricharan R #address-cells = <1>; 48422592a22SSricharan R #size-cells = <0>; 485e8a7fdc5SSivaprakash Murugesan reg = <0x078b7000 0x600>; 48622592a22SSricharan R interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 48722592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 48822592a22SSricharan R <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 48922592a22SSricharan R clock-names = "iface", "core"; 49022592a22SSricharan R clock-frequency = <100000>; 49122592a22SSricharan R dmas = <&blsp_dma 17>, <&blsp_dma 16>; 49222592a22SSricharan R dma-names = "rx", "tx"; 49322592a22SSricharan R status = "disabled"; 49422592a22SSricharan R }; 49522592a22SSricharan R 4969c0bd8e5SChukun Pan blsp1_i2c5: i2c@78b9000 { 4979c0bd8e5SChukun Pan compatible = "qcom,i2c-qup-v2.2.1"; 4989c0bd8e5SChukun Pan #address-cells = <1>; 4999c0bd8e5SChukun Pan #size-cells = <0>; 5009c0bd8e5SChukun Pan reg = <0x78b9000 0x600>; 5019c0bd8e5SChukun Pan interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 5029c0bd8e5SChukun Pan clocks = <&gcc GCC_BLSP1_AHB_CLK>, 5039c0bd8e5SChukun Pan <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 5049c0bd8e5SChukun Pan clock-names = "iface", "core"; 5059c0bd8e5SChukun Pan clock-frequency = <400000>; 5069c0bd8e5SChukun Pan dmas = <&blsp_dma 21>, <&blsp_dma 20>; 5079c0bd8e5SChukun Pan dma-names = "rx", "tx"; 5089c0bd8e5SChukun Pan status = "disabled"; 5099c0bd8e5SChukun Pan }; 5109c0bd8e5SChukun Pan 511abe66bb7SRobert Marko blsp1_i2c6: i2c@78ba000 { 512abe66bb7SRobert Marko compatible = "qcom,i2c-qup-v2.2.1"; 513abe66bb7SRobert Marko #address-cells = <1>; 514abe66bb7SRobert Marko #size-cells = <0>; 515abe66bb7SRobert Marko reg = <0x078ba000 0x600>; 516abe66bb7SRobert Marko interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 517abe66bb7SRobert Marko clocks = <&gcc GCC_BLSP1_AHB_CLK>, 518abe66bb7SRobert Marko <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 519abe66bb7SRobert Marko clock-names = "iface", "core"; 520abe66bb7SRobert Marko clock-frequency = <100000>; 521abe66bb7SRobert Marko dmas = <&blsp_dma 23>, <&blsp_dma 22>; 522abe66bb7SRobert Marko dma-names = "rx", "tx"; 523abe66bb7SRobert Marko status = "disabled"; 524abe66bb7SRobert Marko }; 525abe66bb7SRobert Marko 526b7fbf46cSVinod Koul qpic_bam: dma-controller@7984000 { 52722592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 528e8a7fdc5SSivaprakash Murugesan reg = <0x07984000 0x1a000>; 52922592a22SSricharan R interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 53022592a22SSricharan R clocks = <&gcc GCC_QPIC_AHB_CLK>; 53122592a22SSricharan R clock-names = "bam_clk"; 53222592a22SSricharan R #dma-cells = <1>; 53322592a22SSricharan R qcom,ee = <0>; 53422592a22SSricharan R status = "disabled"; 53522592a22SSricharan R }; 53622592a22SSricharan R 53722592a22SSricharan R qpic_nand: nand@79b0000 { 53822592a22SSricharan R compatible = "qcom,ipq8074-nand"; 539e8a7fdc5SSivaprakash Murugesan reg = <0x079b0000 0x10000>; 54022592a22SSricharan R #address-cells = <1>; 54122592a22SSricharan R #size-cells = <0>; 54222592a22SSricharan R clocks = <&gcc GCC_QPIC_CLK>, 54322592a22SSricharan R <&gcc GCC_QPIC_AHB_CLK>; 54422592a22SSricharan R clock-names = "core", "aon"; 54522592a22SSricharan R 54622592a22SSricharan R dmas = <&qpic_bam 0>, 54722592a22SSricharan R <&qpic_bam 1>, 54822592a22SSricharan R <&qpic_bam 2>; 54922592a22SSricharan R dma-names = "tx", "rx", "cmd"; 55022592a22SSricharan R pinctrl-0 = <&qpic_pins>; 55122592a22SSricharan R pinctrl-names = "default"; 55241dac73eSVaradarajan Narayanan status = "disabled"; 55341dac73eSVaradarajan Narayanan }; 55433057e16SSricharan R 5555e09bc51SSivaprakash Murugesan usb_0: usb@8af8800 { 5563a6b8bf1SKrzysztof Kozlowski compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 5575e09bc51SSivaprakash Murugesan reg = <0x08af8800 0x400>; 5585e09bc51SSivaprakash Murugesan #address-cells = <1>; 5595e09bc51SSivaprakash Murugesan #size-cells = <1>; 5605e09bc51SSivaprakash Murugesan ranges; 5615e09bc51SSivaprakash Murugesan 5625e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 5635e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 5645e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_SLEEP_CLK>, 5655e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 566*8d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 567*8d5fd4e4SKrzysztof Kozlowski "core", 5685e09bc51SSivaprakash Murugesan "sleep", 5695e09bc51SSivaprakash Murugesan "mock_utmi"; 5705e09bc51SSivaprakash Murugesan 5715e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 5725e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 5735e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 5745e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 5755e09bc51SSivaprakash Murugesan <133330000>, 5765e09bc51SSivaprakash Murugesan <19200000>; 5775e09bc51SSivaprakash Murugesan 5785e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_BCR>; 5795e09bc51SSivaprakash Murugesan status = "disabled"; 5805e09bc51SSivaprakash Murugesan 581b77a1c4dSKrzysztof Kozlowski dwc_0: usb@8a00000 { 5825e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 5835e09bc51SSivaprakash Murugesan reg = <0x8a00000 0xcd00>; 5845e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 5855e09bc51SSivaprakash Murugesan phys = <&qusb_phy_0>, <&usb0_ssphy>; 5865e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 5875e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 5885e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 5895e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 5905e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 5915e09bc51SSivaprakash Murugesan dr_mode = "host"; 5925e09bc51SSivaprakash Murugesan }; 5935e09bc51SSivaprakash Murugesan }; 5945e09bc51SSivaprakash Murugesan 5955e09bc51SSivaprakash Murugesan usb_1: usb@8cf8800 { 5963a6b8bf1SKrzysztof Kozlowski compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 5975e09bc51SSivaprakash Murugesan reg = <0x08cf8800 0x400>; 5985e09bc51SSivaprakash Murugesan #address-cells = <1>; 5995e09bc51SSivaprakash Murugesan #size-cells = <1>; 6005e09bc51SSivaprakash Murugesan ranges; 6015e09bc51SSivaprakash Murugesan 6025e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 6035e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 6045e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_SLEEP_CLK>, 6055e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 606*8d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 607*8d5fd4e4SKrzysztof Kozlowski "core", 6085e09bc51SSivaprakash Murugesan "sleep", 6095e09bc51SSivaprakash Murugesan "mock_utmi"; 6105e09bc51SSivaprakash Murugesan 6115e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 6125e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 6135e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 6145e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 6155e09bc51SSivaprakash Murugesan <133330000>, 6165e09bc51SSivaprakash Murugesan <19200000>; 6175e09bc51SSivaprakash Murugesan 6185e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_BCR>; 6195e09bc51SSivaprakash Murugesan status = "disabled"; 6205e09bc51SSivaprakash Murugesan 621b77a1c4dSKrzysztof Kozlowski dwc_1: usb@8c00000 { 6225e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 6235e09bc51SSivaprakash Murugesan reg = <0x8c00000 0xcd00>; 6245e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 6255e09bc51SSivaprakash Murugesan phys = <&qusb_phy_1>, <&usb1_ssphy>; 6265e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 6275e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 6285e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 6295e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 6305e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 6315e09bc51SSivaprakash Murugesan dr_mode = "host"; 6325e09bc51SSivaprakash Murugesan }; 6335e09bc51SSivaprakash Murugesan }; 6345e09bc51SSivaprakash Murugesan 635e8a7fdc5SSivaprakash Murugesan intc: interrupt-controller@b000000 { 636e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-qgic2"; 63759892de9SKathiravan T #address-cells = <1>; 63859892de9SKathiravan T #size-cells = <1>; 639e8a7fdc5SSivaprakash Murugesan interrupt-controller; 640e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <0x3>; 641e8a7fdc5SSivaprakash Murugesan reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 64259892de9SKathiravan T ranges = <0 0xb00a000 0xffd>; 64359892de9SKathiravan T 64459892de9SKathiravan T v2m@0 { 64559892de9SKathiravan T compatible = "arm,gic-v2m-frame"; 64659892de9SKathiravan T msi-controller; 64759892de9SKathiravan T reg = <0x0 0xffd>; 64859892de9SKathiravan T }; 649e8a7fdc5SSivaprakash Murugesan }; 65033057e16SSricharan R 651e8a7fdc5SSivaprakash Murugesan timer { 652e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv8-timer"; 653e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 654e8a7fdc5SSivaprakash Murugesan <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 655e8a7fdc5SSivaprakash Murugesan <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 656e8a7fdc5SSivaprakash Murugesan <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 657e8a7fdc5SSivaprakash Murugesan }; 658e8a7fdc5SSivaprakash Murugesan 659949766e0SKathiravan T watchdog: watchdog@b017000 { 660949766e0SKathiravan T compatible = "qcom,kpss-wdt"; 661949766e0SKathiravan T reg = <0xb017000 0x1000>; 662949766e0SKathiravan T interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 663949766e0SKathiravan T clocks = <&sleep_clk>; 664949766e0SKathiravan T timeout-sec = <30>; 665949766e0SKathiravan T }; 666949766e0SKathiravan T 667e8a7fdc5SSivaprakash Murugesan timer@b120000 { 668e8a7fdc5SSivaprakash Murugesan #address-cells = <1>; 669e8a7fdc5SSivaprakash Murugesan #size-cells = <1>; 670e8a7fdc5SSivaprakash Murugesan ranges; 671e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv7-timer-mem"; 672e8a7fdc5SSivaprakash Murugesan reg = <0x0b120000 0x1000>; 673e8a7fdc5SSivaprakash Murugesan 674e8a7fdc5SSivaprakash Murugesan frame@b120000 { 675e8a7fdc5SSivaprakash Murugesan frame-number = <0>; 676e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 677e8a7fdc5SSivaprakash Murugesan <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 678e8a7fdc5SSivaprakash Murugesan reg = <0x0b121000 0x1000>, 679e8a7fdc5SSivaprakash Murugesan <0x0b122000 0x1000>; 680e8a7fdc5SSivaprakash Murugesan }; 681e8a7fdc5SSivaprakash Murugesan 682e8a7fdc5SSivaprakash Murugesan frame@b123000 { 683e8a7fdc5SSivaprakash Murugesan frame-number = <1>; 684e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 685e8a7fdc5SSivaprakash Murugesan reg = <0x0b123000 0x1000>; 68633057e16SSricharan R status = "disabled"; 68733057e16SSricharan R }; 68833057e16SSricharan R 689e8a7fdc5SSivaprakash Murugesan frame@b124000 { 690e8a7fdc5SSivaprakash Murugesan frame-number = <2>; 691e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 692e8a7fdc5SSivaprakash Murugesan reg = <0x0b124000 0x1000>; 69333057e16SSricharan R status = "disabled"; 69433057e16SSricharan R }; 69533057e16SSricharan R 696e8a7fdc5SSivaprakash Murugesan frame@b125000 { 697e8a7fdc5SSivaprakash Murugesan frame-number = <3>; 698e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 699e8a7fdc5SSivaprakash Murugesan reg = <0x0b125000 0x1000>; 70033057e16SSricharan R status = "disabled"; 70133057e16SSricharan R }; 70233057e16SSricharan R 703e8a7fdc5SSivaprakash Murugesan frame@b126000 { 704e8a7fdc5SSivaprakash Murugesan frame-number = <4>; 705e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 706e8a7fdc5SSivaprakash Murugesan reg = <0x0b126000 0x1000>; 707e8a7fdc5SSivaprakash Murugesan status = "disabled"; 708e8a7fdc5SSivaprakash Murugesan }; 709e8a7fdc5SSivaprakash Murugesan 710e8a7fdc5SSivaprakash Murugesan frame@b127000 { 711e8a7fdc5SSivaprakash Murugesan frame-number = <5>; 712e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 713e8a7fdc5SSivaprakash Murugesan reg = <0x0b127000 0x1000>; 714e8a7fdc5SSivaprakash Murugesan status = "disabled"; 715e8a7fdc5SSivaprakash Murugesan }; 716e8a7fdc5SSivaprakash Murugesan 717e8a7fdc5SSivaprakash Murugesan frame@b128000 { 718e8a7fdc5SSivaprakash Murugesan frame-number = <6>; 719e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 720e8a7fdc5SSivaprakash Murugesan reg = <0x0b128000 0x1000>; 721e8a7fdc5SSivaprakash Murugesan status = "disabled"; 722e8a7fdc5SSivaprakash Murugesan }; 723e8a7fdc5SSivaprakash Murugesan }; 724e8a7fdc5SSivaprakash Murugesan 72533057e16SSricharan R pcie1: pci@10000000 { 72633057e16SSricharan R compatible = "qcom,pcie-ipq8074"; 72752c9887fSVinod Koul reg = <0x10000000 0xf1d>, 72852c9887fSVinod Koul <0x10000f20 0xa8>, 72952c9887fSVinod Koul <0x00088000 0x2000>, 73052c9887fSVinod Koul <0x10100000 0x1000>; 73133057e16SSricharan R reg-names = "dbi", "elbi", "parf", "config"; 73233057e16SSricharan R device_type = "pci"; 73333057e16SSricharan R linux,pci-domain = <1>; 73433057e16SSricharan R bus-range = <0x00 0xff>; 73533057e16SSricharan R num-lanes = <1>; 73633057e16SSricharan R #address-cells = <3>; 73733057e16SSricharan R #size-cells = <2>; 73833057e16SSricharan R 73933057e16SSricharan R phys = <&pcie_phy1>; 74033057e16SSricharan R phy-names = "pciephy"; 74133057e16SSricharan R 74233057e16SSricharan R ranges = <0x81000000 0 0x10200000 0x10200000 74333057e16SSricharan R 0 0x100000 /* downstream I/O */ 74433057e16SSricharan R 0x82000000 0 0x10300000 0x10300000 74533057e16SSricharan R 0 0xd00000>; /* non-prefetchable memory */ 74633057e16SSricharan R 74733057e16SSricharan R interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 74833057e16SSricharan R interrupt-names = "msi"; 74933057e16SSricharan R #interrupt-cells = <1>; 75033057e16SSricharan R interrupt-map-mask = <0 0 0 0x7>; 75133057e16SSricharan R interrupt-map = <0 0 0 1 &intc 0 142 75233057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 75333057e16SSricharan R <0 0 0 2 &intc 0 143 75433057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 75533057e16SSricharan R <0 0 0 3 &intc 0 144 75633057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 75733057e16SSricharan R <0 0 0 4 &intc 0 145 75833057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 75933057e16SSricharan R 76033057e16SSricharan R clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 76133057e16SSricharan R <&gcc GCC_PCIE1_AXI_M_CLK>, 76233057e16SSricharan R <&gcc GCC_PCIE1_AXI_S_CLK>, 76333057e16SSricharan R <&gcc GCC_PCIE1_AHB_CLK>, 76433057e16SSricharan R <&gcc GCC_PCIE1_AUX_CLK>; 76533057e16SSricharan R clock-names = "iface", 76633057e16SSricharan R "axi_m", 76733057e16SSricharan R "axi_s", 76833057e16SSricharan R "ahb", 76933057e16SSricharan R "aux"; 77033057e16SSricharan R resets = <&gcc GCC_PCIE1_PIPE_ARES>, 77133057e16SSricharan R <&gcc GCC_PCIE1_SLEEP_ARES>, 77233057e16SSricharan R <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 77333057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 77433057e16SSricharan R <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 77533057e16SSricharan R <&gcc GCC_PCIE1_AHB_ARES>, 77633057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 77733057e16SSricharan R reset-names = "pipe", 77833057e16SSricharan R "sleep", 77933057e16SSricharan R "sticky", 78033057e16SSricharan R "axi_m", 78133057e16SSricharan R "axi_s", 78233057e16SSricharan R "ahb", 78333057e16SSricharan R "axi_m_sticky"; 78433057e16SSricharan R status = "disabled"; 78533057e16SSricharan R }; 78641dac73eSVaradarajan Narayanan 787e8a7fdc5SSivaprakash Murugesan pcie0: pci@20000000 { 788e8a7fdc5SSivaprakash Murugesan compatible = "qcom,pcie-ipq8074"; 78952c9887fSVinod Koul reg = <0x20000000 0xf1d>, 79052c9887fSVinod Koul <0x20000f20 0xa8>, 79152c9887fSVinod Koul <0x00080000 0x2000>, 79252c9887fSVinod Koul <0x20100000 0x1000>; 793e8a7fdc5SSivaprakash Murugesan reg-names = "dbi", "elbi", "parf", "config"; 794e8a7fdc5SSivaprakash Murugesan device_type = "pci"; 795e8a7fdc5SSivaprakash Murugesan linux,pci-domain = <0>; 796e8a7fdc5SSivaprakash Murugesan bus-range = <0x00 0xff>; 797e8a7fdc5SSivaprakash Murugesan num-lanes = <1>; 798e8a7fdc5SSivaprakash Murugesan #address-cells = <3>; 799e8a7fdc5SSivaprakash Murugesan #size-cells = <2>; 80041dac73eSVaradarajan Narayanan 801e8a7fdc5SSivaprakash Murugesan phys = <&pcie_phy0>; 802e8a7fdc5SSivaprakash Murugesan phy-names = "pciephy"; 80341dac73eSVaradarajan Narayanan 804e8a7fdc5SSivaprakash Murugesan ranges = <0x81000000 0 0x20200000 0x20200000 805e8a7fdc5SSivaprakash Murugesan 0 0x100000 /* downstream I/O */ 806e8a7fdc5SSivaprakash Murugesan 0x82000000 0 0x20300000 0x20300000 807e8a7fdc5SSivaprakash Murugesan 0 0xd00000>; /* non-prefetchable memory */ 80841dac73eSVaradarajan Narayanan 809e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 810e8a7fdc5SSivaprakash Murugesan interrupt-names = "msi"; 811e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <1>; 812e8a7fdc5SSivaprakash Murugesan interrupt-map-mask = <0 0 0 0x7>; 813e8a7fdc5SSivaprakash Murugesan interrupt-map = <0 0 0 1 &intc 0 75 814e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 815e8a7fdc5SSivaprakash Murugesan <0 0 0 2 &intc 0 78 816e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 817e8a7fdc5SSivaprakash Murugesan <0 0 0 3 &intc 0 79 818e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 819e8a7fdc5SSivaprakash Murugesan <0 0 0 4 &intc 0 83 820e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 82141dac73eSVaradarajan Narayanan 822e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 823e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_M_CLK>, 824e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_S_CLK>, 825e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_CLK>, 826e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AUX_CLK>; 82741dac73eSVaradarajan Narayanan 828e8a7fdc5SSivaprakash Murugesan clock-names = "iface", 829e8a7fdc5SSivaprakash Murugesan "axi_m", 830e8a7fdc5SSivaprakash Murugesan "axi_s", 831e8a7fdc5SSivaprakash Murugesan "ahb", 832e8a7fdc5SSivaprakash Murugesan "aux"; 833e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PIPE_ARES>, 834e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_SLEEP_ARES>, 835e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 836e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 837e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 838e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_ARES>, 839e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 840e8a7fdc5SSivaprakash Murugesan reset-names = "pipe", 841e8a7fdc5SSivaprakash Murugesan "sleep", 842e8a7fdc5SSivaprakash Murugesan "sticky", 843e8a7fdc5SSivaprakash Murugesan "axi_m", 844e8a7fdc5SSivaprakash Murugesan "axi_s", 845e8a7fdc5SSivaprakash Murugesan "ahb", 846e8a7fdc5SSivaprakash Murugesan "axi_m_sticky"; 847e8a7fdc5SSivaprakash Murugesan status = "disabled"; 84841dac73eSVaradarajan Narayanan }; 84941dac73eSVaradarajan Narayanan }; 85041dac73eSVaradarajan Narayanan}; 851