197fb5e8dSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 241dac73eSVaradarajan Narayanan/* 341dac73eSVaradarajan Narayanan * Copyright (c) 2017, The Linux Foundation. All rights reserved. 441dac73eSVaradarajan Narayanan */ 541dac73eSVaradarajan Narayanan 641dac73eSVaradarajan Narayanan#include <dt-bindings/interrupt-controller/arm-gic.h> 741dac73eSVaradarajan Narayanan#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 841dac73eSVaradarajan Narayanan 941dac73eSVaradarajan Narayanan/ { 1041dac73eSVaradarajan Narayanan model = "Qualcomm Technologies, Inc. IPQ8074"; 1141dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074"; 1241dac73eSVaradarajan Narayanan 13e8a7fdc5SSivaprakash Murugesan clocks { 14e8a7fdc5SSivaprakash Murugesan sleep_clk: sleep_clk { 15e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 16e8a7fdc5SSivaprakash Murugesan clock-frequency = <32000>; 17e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 18e8a7fdc5SSivaprakash Murugesan }; 19e8a7fdc5SSivaprakash Murugesan 20e8a7fdc5SSivaprakash Murugesan xo: xo { 21e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 22e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 23e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 24e8a7fdc5SSivaprakash Murugesan }; 25e8a7fdc5SSivaprakash Murugesan }; 26e8a7fdc5SSivaprakash Murugesan 27e8a7fdc5SSivaprakash Murugesan cpus { 28e8a7fdc5SSivaprakash Murugesan #address-cells = <0x1>; 29e8a7fdc5SSivaprakash Murugesan #size-cells = <0x0>; 30e8a7fdc5SSivaprakash Murugesan 31e8a7fdc5SSivaprakash Murugesan CPU0: cpu@0 { 32e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 33e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 34e8a7fdc5SSivaprakash Murugesan reg = <0x0>; 35e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 36e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 37e8a7fdc5SSivaprakash Murugesan }; 38e8a7fdc5SSivaprakash Murugesan 39e8a7fdc5SSivaprakash Murugesan CPU1: cpu@1 { 40e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 41e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 42e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 43e8a7fdc5SSivaprakash Murugesan reg = <0x1>; 44e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 45e8a7fdc5SSivaprakash Murugesan }; 46e8a7fdc5SSivaprakash Murugesan 47e8a7fdc5SSivaprakash Murugesan CPU2: cpu@2 { 48e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 49e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 50e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 51e8a7fdc5SSivaprakash Murugesan reg = <0x2>; 52e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 53e8a7fdc5SSivaprakash Murugesan }; 54e8a7fdc5SSivaprakash Murugesan 55e8a7fdc5SSivaprakash Murugesan CPU3: cpu@3 { 56e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 57e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 58e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 59e8a7fdc5SSivaprakash Murugesan reg = <0x3>; 60e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 61e8a7fdc5SSivaprakash Murugesan }; 62e8a7fdc5SSivaprakash Murugesan 63e8a7fdc5SSivaprakash Murugesan L2_0: l2-cache { 64e8a7fdc5SSivaprakash Murugesan compatible = "cache"; 65e8a7fdc5SSivaprakash Murugesan cache-level = <0x2>; 66e8a7fdc5SSivaprakash Murugesan }; 67e8a7fdc5SSivaprakash Murugesan }; 68e8a7fdc5SSivaprakash Murugesan 69e8a7fdc5SSivaprakash Murugesan pmu { 70292b1874SKathiravan T compatible = "arm,cortex-a53-pmu"; 71e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72e8a7fdc5SSivaprakash Murugesan }; 73e8a7fdc5SSivaprakash Murugesan 74e8a7fdc5SSivaprakash Murugesan psci { 75e8a7fdc5SSivaprakash Murugesan compatible = "arm,psci-1.0"; 76e8a7fdc5SSivaprakash Murugesan method = "smc"; 77e8a7fdc5SSivaprakash Murugesan }; 78e8a7fdc5SSivaprakash Murugesan 79*6df9102fSGokul Sriram Palanisamy firmware { 80*6df9102fSGokul Sriram Palanisamy scm { 81*6df9102fSGokul Sriram Palanisamy compatible = "qcom,scm-ipq8074", "qcom,scm"; 82*6df9102fSGokul Sriram Palanisamy }; 83*6df9102fSGokul Sriram Palanisamy }; 84*6df9102fSGokul Sriram Palanisamy 8541dac73eSVaradarajan Narayanan soc: soc { 8641dac73eSVaradarajan Narayanan #address-cells = <0x1>; 8741dac73eSVaradarajan Narayanan #size-cells = <0x1>; 8841dac73eSVaradarajan Narayanan ranges = <0 0 0 0xffffffff>; 8941dac73eSVaradarajan Narayanan compatible = "simple-bus"; 9041dac73eSVaradarajan Narayanan 915e09bc51SSivaprakash Murugesan ssphy_1: phy@58000 { 925e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 935e09bc51SSivaprakash Murugesan reg = <0x00058000 0x1c4>; 945e09bc51SSivaprakash Murugesan #clock-cells = <1>; 955e09bc51SSivaprakash Murugesan #address-cells = <1>; 965e09bc51SSivaprakash Murugesan #size-cells = <1>; 975e09bc51SSivaprakash Murugesan ranges; 985e09bc51SSivaprakash Murugesan 995e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_AUX_CLK>, 1005e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1015e09bc51SSivaprakash Murugesan <&xo>; 1025e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1035e09bc51SSivaprakash Murugesan 1045e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_PHY_BCR>, 1055e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_1_PHY_BCR>; 1065e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1075e09bc51SSivaprakash Murugesan status = "disabled"; 1085e09bc51SSivaprakash Murugesan 1095e09bc51SSivaprakash Murugesan usb1_ssphy: lane@58200 { 1105e09bc51SSivaprakash Murugesan reg = <0x00058200 0x130>, /* Tx */ 1115e09bc51SSivaprakash Murugesan <0x00058400 0x200>, /* Rx */ 1125e09bc51SSivaprakash Murugesan <0x00058800 0x1f8>, /* PCS */ 1135e09bc51SSivaprakash Murugesan <0x00058600 0x044>; /* PCS misc*/ 1145e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1155e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PIPE_CLK>; 1165e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1175e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb1_pipe_clk_src"; 1185e09bc51SSivaprakash Murugesan }; 1195e09bc51SSivaprakash Murugesan }; 1205e09bc51SSivaprakash Murugesan 1215e09bc51SSivaprakash Murugesan qusb_phy_1: phy@59000 { 1225e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1235e09bc51SSivaprakash Murugesan reg = <0x00059000 0x180>; 1245e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1255e09bc51SSivaprakash Murugesan 1265e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1275e09bc51SSivaprakash Murugesan <&xo>; 1285e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1295e09bc51SSivaprakash Murugesan 1305e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 1315e09bc51SSivaprakash Murugesan status = "disabled"; 1325e09bc51SSivaprakash Murugesan }; 1335e09bc51SSivaprakash Murugesan 1345e09bc51SSivaprakash Murugesan ssphy_0: phy@78000 { 1355e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1365e09bc51SSivaprakash Murugesan reg = <0x00078000 0x1c4>; 1375e09bc51SSivaprakash Murugesan #clock-cells = <1>; 1385e09bc51SSivaprakash Murugesan #address-cells = <1>; 1395e09bc51SSivaprakash Murugesan #size-cells = <1>; 1405e09bc51SSivaprakash Murugesan ranges; 1415e09bc51SSivaprakash Murugesan 1425e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_AUX_CLK>, 1435e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1445e09bc51SSivaprakash Murugesan <&xo>; 1455e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1465e09bc51SSivaprakash Murugesan 1475e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_PHY_BCR>, 1485e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_0_PHY_BCR>; 1495e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1505e09bc51SSivaprakash Murugesan status = "disabled"; 1515e09bc51SSivaprakash Murugesan 1525e09bc51SSivaprakash Murugesan usb0_ssphy: lane@78200 { 1535e09bc51SSivaprakash Murugesan reg = <0x00078200 0x130>, /* Tx */ 1545e09bc51SSivaprakash Murugesan <0x00078400 0x200>, /* Rx */ 1555e09bc51SSivaprakash Murugesan <0x00078800 0x1f8>, /* PCS */ 1565e09bc51SSivaprakash Murugesan <0x00078600 0x044>; /* PCS misc*/ 1575e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1585e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PIPE_CLK>; 1595e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 1605e09bc51SSivaprakash Murugesan clock-output-names = "gcc_usb0_pipe_clk_src"; 1615e09bc51SSivaprakash Murugesan }; 1625e09bc51SSivaprakash Murugesan }; 1635e09bc51SSivaprakash Murugesan 1645e09bc51SSivaprakash Murugesan qusb_phy_0: phy@79000 { 1655e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1665e09bc51SSivaprakash Murugesan reg = <0x00079000 0x180>; 1675e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1685e09bc51SSivaprakash Murugesan 1695e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1705e09bc51SSivaprakash Murugesan <&xo>; 1715e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1725e09bc51SSivaprakash Murugesan 1735e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 17458b2785dSRobert Marko status = "disabled"; 1755e09bc51SSivaprakash Murugesan }; 1765e09bc51SSivaprakash Murugesan 177e8a7fdc5SSivaprakash Murugesan pcie_phy0: phy@86000 { 178e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 179e8a7fdc5SSivaprakash Murugesan reg = <0x00086000 0x1000>; 180e8a7fdc5SSivaprakash Murugesan #phy-cells = <0>; 181e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 182e8a7fdc5SSivaprakash Murugesan clock-names = "pipe_clk"; 183e8a7fdc5SSivaprakash Murugesan clock-output-names = "pcie20_phy0_pipe_clk"; 184e8a7fdc5SSivaprakash Murugesan 185e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PHY_BCR>, 186e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0PHY_PHY_BCR>; 187e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 188e8a7fdc5SSivaprakash Murugesan "common"; 189e8a7fdc5SSivaprakash Murugesan status = "disabled"; 190e8a7fdc5SSivaprakash Murugesan }; 191e8a7fdc5SSivaprakash Murugesan 192e8a7fdc5SSivaprakash Murugesan pcie_phy1: phy@8e000 { 193e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 194e8a7fdc5SSivaprakash Murugesan reg = <0x0008e000 0x1000>; 195e8a7fdc5SSivaprakash Murugesan #phy-cells = <0>; 196e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 197e8a7fdc5SSivaprakash Murugesan clock-names = "pipe_clk"; 198e8a7fdc5SSivaprakash Murugesan clock-output-names = "pcie20_phy1_pipe_clk"; 199e8a7fdc5SSivaprakash Murugesan 200e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE1_PHY_BCR>, 201e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE1PHY_PHY_BCR>; 202e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 203e8a7fdc5SSivaprakash Murugesan "common"; 204e8a7fdc5SSivaprakash Murugesan status = "disabled"; 205e8a7fdc5SSivaprakash Murugesan }; 206e8a7fdc5SSivaprakash Murugesan 20733057e16SSricharan R tlmm: pinctrl@1000000 { 20841dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074-pinctrl"; 209e8a7fdc5SSivaprakash Murugesan reg = <0x01000000 0x300000>; 21041dac73eSVaradarajan Narayanan interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 21141dac73eSVaradarajan Narayanan gpio-controller; 212297177a4SChristian Lamparter gpio-ranges = <&tlmm 0 0 70>; 21341dac73eSVaradarajan Narayanan #gpio-cells = <0x2>; 21441dac73eSVaradarajan Narayanan interrupt-controller; 21541dac73eSVaradarajan Narayanan #interrupt-cells = <0x2>; 21622592a22SSricharan R 21722592a22SSricharan R serial_4_pins: serial4-pinmux { 21822592a22SSricharan R pins = "gpio23", "gpio24"; 21922592a22SSricharan R function = "blsp4_uart1"; 22022592a22SSricharan R drive-strength = <8>; 22122592a22SSricharan R bias-disable; 22222592a22SSricharan R }; 22322592a22SSricharan R 22422592a22SSricharan R i2c_0_pins: i2c-0-pinmux { 22522592a22SSricharan R pins = "gpio42", "gpio43"; 22622592a22SSricharan R function = "blsp1_i2c"; 22722592a22SSricharan R drive-strength = <8>; 22822592a22SSricharan R bias-disable; 22922592a22SSricharan R }; 23022592a22SSricharan R 23122592a22SSricharan R spi_0_pins: spi-0-pins { 23222592a22SSricharan R pins = "gpio38", "gpio39", "gpio40", "gpio41"; 23322592a22SSricharan R function = "blsp0_spi"; 23422592a22SSricharan R drive-strength = <8>; 23522592a22SSricharan R bias-disable; 23622592a22SSricharan R }; 23722592a22SSricharan R 23822592a22SSricharan R hsuart_pins: hsuart-pins { 23922592a22SSricharan R pins = "gpio46", "gpio47", "gpio48", "gpio49"; 24022592a22SSricharan R function = "blsp2_uart"; 24122592a22SSricharan R drive-strength = <8>; 24222592a22SSricharan R bias-disable; 24322592a22SSricharan R }; 24422592a22SSricharan R 24522592a22SSricharan R qpic_pins: qpic-pins { 24622592a22SSricharan R pins = "gpio1", "gpio3", "gpio4", 24722592a22SSricharan R "gpio5", "gpio6", "gpio7", 24822592a22SSricharan R "gpio8", "gpio10", "gpio11", 24922592a22SSricharan R "gpio12", "gpio13", "gpio14", 25022592a22SSricharan R "gpio15", "gpio16", "gpio17"; 25122592a22SSricharan R function = "qpic"; 25222592a22SSricharan R drive-strength = <8>; 25322592a22SSricharan R bias-disable; 25422592a22SSricharan R }; 25541dac73eSVaradarajan Narayanan }; 25641dac73eSVaradarajan Narayanan 25741dac73eSVaradarajan Narayanan gcc: gcc@1800000 { 25841dac73eSVaradarajan Narayanan compatible = "qcom,gcc-ipq8074"; 259e8a7fdc5SSivaprakash Murugesan reg = <0x01800000 0x80000>; 26041dac73eSVaradarajan Narayanan #clock-cells = <0x1>; 26141dac73eSVaradarajan Narayanan #reset-cells = <0x1>; 26241dac73eSVaradarajan Narayanan }; 26341dac73eSVaradarajan Narayanan 264cbc142c8SSivaprakash Murugesan sdhc_1: sdhci@7824900 { 265cbc142c8SSivaprakash Murugesan compatible = "qcom,sdhci-msm-v4"; 266cbc142c8SSivaprakash Murugesan reg = <0x7824900 0x500>, <0x7824000 0x800>; 267cbc142c8SSivaprakash Murugesan reg-names = "hc_mem", "core_mem"; 268cbc142c8SSivaprakash Murugesan 269cbc142c8SSivaprakash Murugesan interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 270cbc142c8SSivaprakash Murugesan <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 271cbc142c8SSivaprakash Murugesan interrupt-names = "hc_irq", "pwr_irq"; 272cbc142c8SSivaprakash Murugesan 273cbc142c8SSivaprakash Murugesan clocks = <&xo>, 274cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_AHB_CLK>, 275cbc142c8SSivaprakash Murugesan <&gcc GCC_SDCC1_APPS_CLK>; 276cbc142c8SSivaprakash Murugesan clock-names = "xo", "iface", "core"; 277cbc142c8SSivaprakash Murugesan max-frequency = <384000000>; 278cbc142c8SSivaprakash Murugesan mmc-ddr-1_8v; 279cbc142c8SSivaprakash Murugesan mmc-hs200-1_8v; 280cbc142c8SSivaprakash Murugesan mmc-hs400-1_8v; 281cbc142c8SSivaprakash Murugesan bus-width = <8>; 282cbc142c8SSivaprakash Murugesan 283cbc142c8SSivaprakash Murugesan status = "disabled"; 284cbc142c8SSivaprakash Murugesan }; 285cbc142c8SSivaprakash Murugesan 286b7fbf46cSVinod Koul blsp_dma: dma-controller@7884000 { 28722592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 288e8a7fdc5SSivaprakash Murugesan reg = <0x07884000 0x2b000>; 28922592a22SSricharan R interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 29022592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>; 29122592a22SSricharan R clock-names = "bam_clk"; 29222592a22SSricharan R #dma-cells = <1>; 29322592a22SSricharan R qcom,ee = <0>; 29422592a22SSricharan R }; 29522592a22SSricharan R 29622592a22SSricharan R blsp1_uart1: serial@78af000 { 29722592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 298e8a7fdc5SSivaprakash Murugesan reg = <0x078af000 0x200>; 29922592a22SSricharan R interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 30022592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 30122592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 30222592a22SSricharan R clock-names = "core", "iface"; 30322592a22SSricharan R status = "disabled"; 30422592a22SSricharan R }; 30522592a22SSricharan R 30622592a22SSricharan R blsp1_uart3: serial@78b1000 { 30722592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 308e8a7fdc5SSivaprakash Murugesan reg = <0x078b1000 0x200>; 30922592a22SSricharan R interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 31022592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 31122592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 31222592a22SSricharan R clock-names = "core", "iface"; 31322592a22SSricharan R dmas = <&blsp_dma 4>, 31422592a22SSricharan R <&blsp_dma 5>; 31522592a22SSricharan R dma-names = "tx", "rx"; 31622592a22SSricharan R pinctrl-0 = <&hsuart_pins>; 31722592a22SSricharan R pinctrl-names = "default"; 31822592a22SSricharan R status = "disabled"; 31922592a22SSricharan R }; 32022592a22SSricharan R 321e8a7fdc5SSivaprakash Murugesan blsp1_uart5: serial@78b3000 { 322e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 323e8a7fdc5SSivaprakash Murugesan reg = <0x078b3000 0x200>; 324e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 325e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 326e8a7fdc5SSivaprakash Murugesan <&gcc GCC_BLSP1_AHB_CLK>; 327e8a7fdc5SSivaprakash Murugesan clock-names = "core", "iface"; 328e8a7fdc5SSivaprakash Murugesan pinctrl-0 = <&serial_4_pins>; 329e8a7fdc5SSivaprakash Murugesan pinctrl-names = "default"; 330e8a7fdc5SSivaprakash Murugesan status = "disabled"; 331e8a7fdc5SSivaprakash Murugesan }; 332e8a7fdc5SSivaprakash Murugesan 33322592a22SSricharan R blsp1_spi1: spi@78b5000 { 33422592a22SSricharan R compatible = "qcom,spi-qup-v2.2.1"; 33522592a22SSricharan R #address-cells = <1>; 33622592a22SSricharan R #size-cells = <0>; 337e8a7fdc5SSivaprakash Murugesan reg = <0x078b5000 0x600>; 33822592a22SSricharan R interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 33922592a22SSricharan R spi-max-frequency = <50000000>; 34022592a22SSricharan R clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 34122592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 34222592a22SSricharan R clock-names = "core", "iface"; 34322592a22SSricharan R dmas = <&blsp_dma 12>, <&blsp_dma 13>; 34422592a22SSricharan R dma-names = "tx", "rx"; 34522592a22SSricharan R pinctrl-0 = <&spi_0_pins>; 34622592a22SSricharan R pinctrl-names = "default"; 34722592a22SSricharan R status = "disabled"; 34822592a22SSricharan R }; 34922592a22SSricharan R 35022592a22SSricharan R blsp1_i2c2: i2c@78b6000 { 35122592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 35222592a22SSricharan R #address-cells = <1>; 35322592a22SSricharan R #size-cells = <0>; 354e8a7fdc5SSivaprakash Murugesan reg = <0x078b6000 0x600>; 35522592a22SSricharan R interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 35622592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 35722592a22SSricharan R <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 35822592a22SSricharan R clock-names = "iface", "core"; 35922592a22SSricharan R clock-frequency = <400000>; 36022592a22SSricharan R dmas = <&blsp_dma 15>, <&blsp_dma 14>; 36122592a22SSricharan R dma-names = "rx", "tx"; 36222592a22SSricharan R pinctrl-0 = <&i2c_0_pins>; 36322592a22SSricharan R pinctrl-names = "default"; 36422592a22SSricharan R status = "disabled"; 36522592a22SSricharan R }; 36622592a22SSricharan R 36722592a22SSricharan R blsp1_i2c3: i2c@78b7000 { 36822592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 36922592a22SSricharan R #address-cells = <1>; 37022592a22SSricharan R #size-cells = <0>; 371e8a7fdc5SSivaprakash Murugesan reg = <0x078b7000 0x600>; 37222592a22SSricharan R interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 37322592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>, 37422592a22SSricharan R <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 37522592a22SSricharan R clock-names = "iface", "core"; 37622592a22SSricharan R clock-frequency = <100000>; 37722592a22SSricharan R dmas = <&blsp_dma 17>, <&blsp_dma 16>; 37822592a22SSricharan R dma-names = "rx", "tx"; 37922592a22SSricharan R status = "disabled"; 38022592a22SSricharan R }; 38122592a22SSricharan R 382abe66bb7SRobert Marko blsp1_i2c6: i2c@78ba000 { 383abe66bb7SRobert Marko compatible = "qcom,i2c-qup-v2.2.1"; 384abe66bb7SRobert Marko #address-cells = <1>; 385abe66bb7SRobert Marko #size-cells = <0>; 386abe66bb7SRobert Marko reg = <0x078ba000 0x600>; 387abe66bb7SRobert Marko interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 388abe66bb7SRobert Marko clocks = <&gcc GCC_BLSP1_AHB_CLK>, 389abe66bb7SRobert Marko <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 390abe66bb7SRobert Marko clock-names = "iface", "core"; 391abe66bb7SRobert Marko clock-frequency = <100000>; 392abe66bb7SRobert Marko dmas = <&blsp_dma 23>, <&blsp_dma 22>; 393abe66bb7SRobert Marko dma-names = "rx", "tx"; 394abe66bb7SRobert Marko status = "disabled"; 395abe66bb7SRobert Marko }; 396abe66bb7SRobert Marko 397b7fbf46cSVinod Koul qpic_bam: dma-controller@7984000 { 39822592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 399e8a7fdc5SSivaprakash Murugesan reg = <0x07984000 0x1a000>; 40022592a22SSricharan R interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 40122592a22SSricharan R clocks = <&gcc GCC_QPIC_AHB_CLK>; 40222592a22SSricharan R clock-names = "bam_clk"; 40322592a22SSricharan R #dma-cells = <1>; 40422592a22SSricharan R qcom,ee = <0>; 40522592a22SSricharan R status = "disabled"; 40622592a22SSricharan R }; 40722592a22SSricharan R 40822592a22SSricharan R qpic_nand: nand@79b0000 { 40922592a22SSricharan R compatible = "qcom,ipq8074-nand"; 410e8a7fdc5SSivaprakash Murugesan reg = <0x079b0000 0x10000>; 41122592a22SSricharan R #address-cells = <1>; 41222592a22SSricharan R #size-cells = <0>; 41322592a22SSricharan R clocks = <&gcc GCC_QPIC_CLK>, 41422592a22SSricharan R <&gcc GCC_QPIC_AHB_CLK>; 41522592a22SSricharan R clock-names = "core", "aon"; 41622592a22SSricharan R 41722592a22SSricharan R dmas = <&qpic_bam 0>, 41822592a22SSricharan R <&qpic_bam 1>, 41922592a22SSricharan R <&qpic_bam 2>; 42022592a22SSricharan R dma-names = "tx", "rx", "cmd"; 42122592a22SSricharan R pinctrl-0 = <&qpic_pins>; 42222592a22SSricharan R pinctrl-names = "default"; 42341dac73eSVaradarajan Narayanan status = "disabled"; 42441dac73eSVaradarajan Narayanan }; 42533057e16SSricharan R 4265e09bc51SSivaprakash Murugesan usb_0: usb@8af8800 { 4275e09bc51SSivaprakash Murugesan compatible = "qcom,dwc3"; 4285e09bc51SSivaprakash Murugesan reg = <0x08af8800 0x400>; 4295e09bc51SSivaprakash Murugesan #address-cells = <1>; 4305e09bc51SSivaprakash Murugesan #size-cells = <1>; 4315e09bc51SSivaprakash Murugesan ranges; 4325e09bc51SSivaprakash Murugesan 4335e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 4345e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 4355e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_SLEEP_CLK>, 4365e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 4375e09bc51SSivaprakash Murugesan clock-names = "sys_noc_axi", 4385e09bc51SSivaprakash Murugesan "master", 4395e09bc51SSivaprakash Murugesan "sleep", 4405e09bc51SSivaprakash Murugesan "mock_utmi"; 4415e09bc51SSivaprakash Murugesan 4425e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 4435e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 4445e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 4455e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 4465e09bc51SSivaprakash Murugesan <133330000>, 4475e09bc51SSivaprakash Murugesan <19200000>; 4485e09bc51SSivaprakash Murugesan 4495e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_BCR>; 4505e09bc51SSivaprakash Murugesan status = "disabled"; 4515e09bc51SSivaprakash Murugesan 452eb9b7bfdSSerge Semin dwc_0: usb@8a00000 { 4535e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 4545e09bc51SSivaprakash Murugesan reg = <0x8a00000 0xcd00>; 4555e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4565e09bc51SSivaprakash Murugesan phys = <&qusb_phy_0>, <&usb0_ssphy>; 4575e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 4585e09bc51SSivaprakash Murugesan tx-fifo-resize; 4595e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 4605e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 4615e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 4625e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 4635e09bc51SSivaprakash Murugesan dr_mode = "host"; 4645e09bc51SSivaprakash Murugesan }; 4655e09bc51SSivaprakash Murugesan }; 4665e09bc51SSivaprakash Murugesan 4675e09bc51SSivaprakash Murugesan usb_1: usb@8cf8800 { 4685e09bc51SSivaprakash Murugesan compatible = "qcom,dwc3"; 4695e09bc51SSivaprakash Murugesan reg = <0x08cf8800 0x400>; 4705e09bc51SSivaprakash Murugesan #address-cells = <1>; 4715e09bc51SSivaprakash Murugesan #size-cells = <1>; 4725e09bc51SSivaprakash Murugesan ranges; 4735e09bc51SSivaprakash Murugesan 4745e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 4755e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 4765e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_SLEEP_CLK>, 4775e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 4785e09bc51SSivaprakash Murugesan clock-names = "sys_noc_axi", 4795e09bc51SSivaprakash Murugesan "master", 4805e09bc51SSivaprakash Murugesan "sleep", 4815e09bc51SSivaprakash Murugesan "mock_utmi"; 4825e09bc51SSivaprakash Murugesan 4835e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 4845e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 4855e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 4865e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 4875e09bc51SSivaprakash Murugesan <133330000>, 4885e09bc51SSivaprakash Murugesan <19200000>; 4895e09bc51SSivaprakash Murugesan 4905e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_BCR>; 4915e09bc51SSivaprakash Murugesan status = "disabled"; 4925e09bc51SSivaprakash Murugesan 493eb9b7bfdSSerge Semin dwc_1: usb@8c00000 { 4945e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 4955e09bc51SSivaprakash Murugesan reg = <0x8c00000 0xcd00>; 4965e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 4975e09bc51SSivaprakash Murugesan phys = <&qusb_phy_1>, <&usb1_ssphy>; 4985e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 4995e09bc51SSivaprakash Murugesan tx-fifo-resize; 5005e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 5015e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 5025e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 5035e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 5045e09bc51SSivaprakash Murugesan dr_mode = "host"; 5055e09bc51SSivaprakash Murugesan }; 5065e09bc51SSivaprakash Murugesan }; 5075e09bc51SSivaprakash Murugesan 508e8a7fdc5SSivaprakash Murugesan intc: interrupt-controller@b000000 { 509e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-qgic2"; 510e8a7fdc5SSivaprakash Murugesan interrupt-controller; 511e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <0x3>; 512e8a7fdc5SSivaprakash Murugesan reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 513e8a7fdc5SSivaprakash Murugesan }; 51433057e16SSricharan R 515e8a7fdc5SSivaprakash Murugesan timer { 516e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv8-timer"; 517e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 518e8a7fdc5SSivaprakash Murugesan <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 519e8a7fdc5SSivaprakash Murugesan <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 520e8a7fdc5SSivaprakash Murugesan <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 521e8a7fdc5SSivaprakash Murugesan }; 522e8a7fdc5SSivaprakash Murugesan 523949766e0SKathiravan T watchdog: watchdog@b017000 { 524949766e0SKathiravan T compatible = "qcom,kpss-wdt"; 525949766e0SKathiravan T reg = <0xb017000 0x1000>; 526949766e0SKathiravan T interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 527949766e0SKathiravan T clocks = <&sleep_clk>; 528949766e0SKathiravan T timeout-sec = <30>; 529949766e0SKathiravan T }; 530949766e0SKathiravan T 531e8a7fdc5SSivaprakash Murugesan timer@b120000 { 532e8a7fdc5SSivaprakash Murugesan #address-cells = <1>; 533e8a7fdc5SSivaprakash Murugesan #size-cells = <1>; 534e8a7fdc5SSivaprakash Murugesan ranges; 535e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv7-timer-mem"; 536e8a7fdc5SSivaprakash Murugesan reg = <0x0b120000 0x1000>; 537e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 538e8a7fdc5SSivaprakash Murugesan 539e8a7fdc5SSivaprakash Murugesan frame@b120000 { 540e8a7fdc5SSivaprakash Murugesan frame-number = <0>; 541e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 542e8a7fdc5SSivaprakash Murugesan <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 543e8a7fdc5SSivaprakash Murugesan reg = <0x0b121000 0x1000>, 544e8a7fdc5SSivaprakash Murugesan <0x0b122000 0x1000>; 545e8a7fdc5SSivaprakash Murugesan }; 546e8a7fdc5SSivaprakash Murugesan 547e8a7fdc5SSivaprakash Murugesan frame@b123000 { 548e8a7fdc5SSivaprakash Murugesan frame-number = <1>; 549e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 550e8a7fdc5SSivaprakash Murugesan reg = <0x0b123000 0x1000>; 55133057e16SSricharan R status = "disabled"; 55233057e16SSricharan R }; 55333057e16SSricharan R 554e8a7fdc5SSivaprakash Murugesan frame@b124000 { 555e8a7fdc5SSivaprakash Murugesan frame-number = <2>; 556e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 557e8a7fdc5SSivaprakash Murugesan reg = <0x0b124000 0x1000>; 55833057e16SSricharan R status = "disabled"; 55933057e16SSricharan R }; 56033057e16SSricharan R 561e8a7fdc5SSivaprakash Murugesan frame@b125000 { 562e8a7fdc5SSivaprakash Murugesan frame-number = <3>; 563e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 564e8a7fdc5SSivaprakash Murugesan reg = <0x0b125000 0x1000>; 56533057e16SSricharan R status = "disabled"; 56633057e16SSricharan R }; 56733057e16SSricharan R 568e8a7fdc5SSivaprakash Murugesan frame@b126000 { 569e8a7fdc5SSivaprakash Murugesan frame-number = <4>; 570e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 571e8a7fdc5SSivaprakash Murugesan reg = <0x0b126000 0x1000>; 572e8a7fdc5SSivaprakash Murugesan status = "disabled"; 573e8a7fdc5SSivaprakash Murugesan }; 574e8a7fdc5SSivaprakash Murugesan 575e8a7fdc5SSivaprakash Murugesan frame@b127000 { 576e8a7fdc5SSivaprakash Murugesan frame-number = <5>; 577e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 578e8a7fdc5SSivaprakash Murugesan reg = <0x0b127000 0x1000>; 579e8a7fdc5SSivaprakash Murugesan status = "disabled"; 580e8a7fdc5SSivaprakash Murugesan }; 581e8a7fdc5SSivaprakash Murugesan 582e8a7fdc5SSivaprakash Murugesan frame@b128000 { 583e8a7fdc5SSivaprakash Murugesan frame-number = <6>; 584e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 585e8a7fdc5SSivaprakash Murugesan reg = <0x0b128000 0x1000>; 586e8a7fdc5SSivaprakash Murugesan status = "disabled"; 587e8a7fdc5SSivaprakash Murugesan }; 588e8a7fdc5SSivaprakash Murugesan }; 589e8a7fdc5SSivaprakash Murugesan 59033057e16SSricharan R pcie1: pci@10000000 { 59133057e16SSricharan R compatible = "qcom,pcie-ipq8074"; 59233057e16SSricharan R reg = <0x10000000 0xf1d 59333057e16SSricharan R 0x10000f20 0xa8 594e8a7fdc5SSivaprakash Murugesan 0x00088000 0x2000 59533057e16SSricharan R 0x10100000 0x1000>; 59633057e16SSricharan R reg-names = "dbi", "elbi", "parf", "config"; 59733057e16SSricharan R device_type = "pci"; 59833057e16SSricharan R linux,pci-domain = <1>; 59933057e16SSricharan R bus-range = <0x00 0xff>; 60033057e16SSricharan R num-lanes = <1>; 60133057e16SSricharan R #address-cells = <3>; 60233057e16SSricharan R #size-cells = <2>; 60333057e16SSricharan R 60433057e16SSricharan R phys = <&pcie_phy1>; 60533057e16SSricharan R phy-names = "pciephy"; 60633057e16SSricharan R 60733057e16SSricharan R ranges = <0x81000000 0 0x10200000 0x10200000 60833057e16SSricharan R 0 0x100000 /* downstream I/O */ 60933057e16SSricharan R 0x82000000 0 0x10300000 0x10300000 61033057e16SSricharan R 0 0xd00000>; /* non-prefetchable memory */ 61133057e16SSricharan R 61233057e16SSricharan R interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 61333057e16SSricharan R interrupt-names = "msi"; 61433057e16SSricharan R #interrupt-cells = <1>; 61533057e16SSricharan R interrupt-map-mask = <0 0 0 0x7>; 61633057e16SSricharan R interrupt-map = <0 0 0 1 &intc 0 142 61733057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 61833057e16SSricharan R <0 0 0 2 &intc 0 143 61933057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 62033057e16SSricharan R <0 0 0 3 &intc 0 144 62133057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 62233057e16SSricharan R <0 0 0 4 &intc 0 145 62333057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 62433057e16SSricharan R 62533057e16SSricharan R clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 62633057e16SSricharan R <&gcc GCC_PCIE1_AXI_M_CLK>, 62733057e16SSricharan R <&gcc GCC_PCIE1_AXI_S_CLK>, 62833057e16SSricharan R <&gcc GCC_PCIE1_AHB_CLK>, 62933057e16SSricharan R <&gcc GCC_PCIE1_AUX_CLK>; 63033057e16SSricharan R clock-names = "iface", 63133057e16SSricharan R "axi_m", 63233057e16SSricharan R "axi_s", 63333057e16SSricharan R "ahb", 63433057e16SSricharan R "aux"; 63533057e16SSricharan R resets = <&gcc GCC_PCIE1_PIPE_ARES>, 63633057e16SSricharan R <&gcc GCC_PCIE1_SLEEP_ARES>, 63733057e16SSricharan R <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 63833057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 63933057e16SSricharan R <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 64033057e16SSricharan R <&gcc GCC_PCIE1_AHB_ARES>, 64133057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 64233057e16SSricharan R reset-names = "pipe", 64333057e16SSricharan R "sleep", 64433057e16SSricharan R "sticky", 64533057e16SSricharan R "axi_m", 64633057e16SSricharan R "axi_s", 64733057e16SSricharan R "ahb", 64833057e16SSricharan R "axi_m_sticky"; 64933057e16SSricharan R status = "disabled"; 65033057e16SSricharan R }; 65141dac73eSVaradarajan Narayanan 652e8a7fdc5SSivaprakash Murugesan pcie0: pci@20000000 { 653e8a7fdc5SSivaprakash Murugesan compatible = "qcom,pcie-ipq8074"; 654e8a7fdc5SSivaprakash Murugesan reg = <0x20000000 0xf1d 655e8a7fdc5SSivaprakash Murugesan 0x20000f20 0xa8 656e8a7fdc5SSivaprakash Murugesan 0x00080000 0x2000 657e8a7fdc5SSivaprakash Murugesan 0x20100000 0x1000>; 658e8a7fdc5SSivaprakash Murugesan reg-names = "dbi", "elbi", "parf", "config"; 659e8a7fdc5SSivaprakash Murugesan device_type = "pci"; 660e8a7fdc5SSivaprakash Murugesan linux,pci-domain = <0>; 661e8a7fdc5SSivaprakash Murugesan bus-range = <0x00 0xff>; 662e8a7fdc5SSivaprakash Murugesan num-lanes = <1>; 663e8a7fdc5SSivaprakash Murugesan #address-cells = <3>; 664e8a7fdc5SSivaprakash Murugesan #size-cells = <2>; 66541dac73eSVaradarajan Narayanan 666e8a7fdc5SSivaprakash Murugesan phys = <&pcie_phy0>; 667e8a7fdc5SSivaprakash Murugesan phy-names = "pciephy"; 66841dac73eSVaradarajan Narayanan 669e8a7fdc5SSivaprakash Murugesan ranges = <0x81000000 0 0x20200000 0x20200000 670e8a7fdc5SSivaprakash Murugesan 0 0x100000 /* downstream I/O */ 671e8a7fdc5SSivaprakash Murugesan 0x82000000 0 0x20300000 0x20300000 672e8a7fdc5SSivaprakash Murugesan 0 0xd00000>; /* non-prefetchable memory */ 67341dac73eSVaradarajan Narayanan 674e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 675e8a7fdc5SSivaprakash Murugesan interrupt-names = "msi"; 676e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <1>; 677e8a7fdc5SSivaprakash Murugesan interrupt-map-mask = <0 0 0 0x7>; 678e8a7fdc5SSivaprakash Murugesan interrupt-map = <0 0 0 1 &intc 0 75 679e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 680e8a7fdc5SSivaprakash Murugesan <0 0 0 2 &intc 0 78 681e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 682e8a7fdc5SSivaprakash Murugesan <0 0 0 3 &intc 0 79 683e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 684e8a7fdc5SSivaprakash Murugesan <0 0 0 4 &intc 0 83 685e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 68641dac73eSVaradarajan Narayanan 687e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 688e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_M_CLK>, 689e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_S_CLK>, 690e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_CLK>, 691e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AUX_CLK>; 69241dac73eSVaradarajan Narayanan 693e8a7fdc5SSivaprakash Murugesan clock-names = "iface", 694e8a7fdc5SSivaprakash Murugesan "axi_m", 695e8a7fdc5SSivaprakash Murugesan "axi_s", 696e8a7fdc5SSivaprakash Murugesan "ahb", 697e8a7fdc5SSivaprakash Murugesan "aux"; 698e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PIPE_ARES>, 699e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_SLEEP_ARES>, 700e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 701e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 702e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 703e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_ARES>, 704e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 705e8a7fdc5SSivaprakash Murugesan reset-names = "pipe", 706e8a7fdc5SSivaprakash Murugesan "sleep", 707e8a7fdc5SSivaprakash Murugesan "sticky", 708e8a7fdc5SSivaprakash Murugesan "axi_m", 709e8a7fdc5SSivaprakash Murugesan "axi_s", 710e8a7fdc5SSivaprakash Murugesan "ahb", 711e8a7fdc5SSivaprakash Murugesan "axi_m_sticky"; 712e8a7fdc5SSivaprakash Murugesan status = "disabled"; 71341dac73eSVaradarajan Narayanan }; 71441dac73eSVaradarajan Narayanan }; 71541dac73eSVaradarajan Narayanan}; 716