197fb5e8dSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 241dac73eSVaradarajan Narayanan/* 341dac73eSVaradarajan Narayanan * Copyright (c) 2017, The Linux Foundation. All rights reserved. 441dac73eSVaradarajan Narayanan */ 541dac73eSVaradarajan Narayanan 641dac73eSVaradarajan Narayanan#include <dt-bindings/interrupt-controller/arm-gic.h> 741dac73eSVaradarajan Narayanan#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 841dac73eSVaradarajan Narayanan 941dac73eSVaradarajan Narayanan/ { 10f3266045SRobert Marko #address-cells = <2>; 11f3266045SRobert Marko #size-cells = <2>; 12f3266045SRobert Marko 1341dac73eSVaradarajan Narayanan model = "Qualcomm Technologies, Inc. IPQ8074"; 1441dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074"; 15b97e6ffaSRobert Marko interrupt-parent = <&intc>; 1641dac73eSVaradarajan Narayanan 17e8a7fdc5SSivaprakash Murugesan clocks { 18e8a7fdc5SSivaprakash Murugesan sleep_clk: sleep_clk { 19e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 20f607dd76SKathiravan T clock-frequency = <32768>; 21e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 22e8a7fdc5SSivaprakash Murugesan }; 23e8a7fdc5SSivaprakash Murugesan 24e8a7fdc5SSivaprakash Murugesan xo: xo { 25e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 26e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 27e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 28e8a7fdc5SSivaprakash Murugesan }; 29e8a7fdc5SSivaprakash Murugesan }; 30e8a7fdc5SSivaprakash Murugesan 31e8a7fdc5SSivaprakash Murugesan cpus { 32e8a7fdc5SSivaprakash Murugesan #address-cells = <0x1>; 33e8a7fdc5SSivaprakash Murugesan #size-cells = <0x0>; 34e8a7fdc5SSivaprakash Murugesan 35e8a7fdc5SSivaprakash Murugesan CPU0: cpu@0 { 36e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 37e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 38e8a7fdc5SSivaprakash Murugesan reg = <0x0>; 39e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 40e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 41e8a7fdc5SSivaprakash Murugesan }; 42e8a7fdc5SSivaprakash Murugesan 43e8a7fdc5SSivaprakash Murugesan CPU1: cpu@1 { 44e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 45e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 46e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 47e8a7fdc5SSivaprakash Murugesan reg = <0x1>; 48e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 49e8a7fdc5SSivaprakash Murugesan }; 50e8a7fdc5SSivaprakash Murugesan 51e8a7fdc5SSivaprakash Murugesan CPU2: cpu@2 { 52e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 53e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 54e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 55e8a7fdc5SSivaprakash Murugesan reg = <0x2>; 56e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 57e8a7fdc5SSivaprakash Murugesan }; 58e8a7fdc5SSivaprakash Murugesan 59e8a7fdc5SSivaprakash Murugesan CPU3: cpu@3 { 60e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 61e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 62e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 63e8a7fdc5SSivaprakash Murugesan reg = <0x3>; 64e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 65e8a7fdc5SSivaprakash Murugesan }; 66e8a7fdc5SSivaprakash Murugesan 67e8a7fdc5SSivaprakash Murugesan L2_0: l2-cache { 68e8a7fdc5SSivaprakash Murugesan compatible = "cache"; 69e8a7fdc5SSivaprakash Murugesan cache-level = <0x2>; 70e8a7fdc5SSivaprakash Murugesan }; 71e8a7fdc5SSivaprakash Murugesan }; 72e8a7fdc5SSivaprakash Murugesan 73e8a7fdc5SSivaprakash Murugesan pmu { 74292b1874SKathiravan T compatible = "arm,cortex-a53-pmu"; 75e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 76e8a7fdc5SSivaprakash Murugesan }; 77e8a7fdc5SSivaprakash Murugesan 78e8a7fdc5SSivaprakash Murugesan psci { 79e8a7fdc5SSivaprakash Murugesan compatible = "arm,psci-1.0"; 80e8a7fdc5SSivaprakash Murugesan method = "smc"; 81e8a7fdc5SSivaprakash Murugesan }; 82e8a7fdc5SSivaprakash Murugesan 8342124b94SRobert Marko reserved-memory { 8442124b94SRobert Marko #address-cells = <2>; 8542124b94SRobert Marko #size-cells = <2>; 8642124b94SRobert Marko ranges; 8742124b94SRobert Marko 8842124b94SRobert Marko smem@4ab00000 { 8942124b94SRobert Marko compatible = "qcom,smem"; 9042124b94SRobert Marko reg = <0x0 0x4ab00000 0x0 0x00100000>; 9142124b94SRobert Marko no-map; 9242124b94SRobert Marko 9342124b94SRobert Marko hwlocks = <&tcsr_mutex 0>; 9442124b94SRobert Marko }; 95e4a4fdcfSKathiravan T 96e4a4fdcfSKathiravan T memory@4ac00000 { 97e4a4fdcfSKathiravan T no-map; 98e4a4fdcfSKathiravan T reg = <0x0 0x4ac00000 0x0 0x00400000>; 99e4a4fdcfSKathiravan T }; 10042124b94SRobert Marko }; 10142124b94SRobert Marko 1026df9102fSGokul Sriram Palanisamy firmware { 1036df9102fSGokul Sriram Palanisamy scm { 1046df9102fSGokul Sriram Palanisamy compatible = "qcom,scm-ipq8074", "qcom,scm"; 1056df9102fSGokul Sriram Palanisamy }; 1066df9102fSGokul Sriram Palanisamy }; 1076df9102fSGokul Sriram Palanisamy 10841dac73eSVaradarajan Narayanan soc: soc { 10941dac73eSVaradarajan Narayanan #address-cells = <0x1>; 11041dac73eSVaradarajan Narayanan #size-cells = <0x1>; 11141dac73eSVaradarajan Narayanan ranges = <0 0 0 0xffffffff>; 11241dac73eSVaradarajan Narayanan compatible = "simple-bus"; 11341dac73eSVaradarajan Narayanan 1145e09bc51SSivaprakash Murugesan ssphy_1: phy@58000 { 1155e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1165e09bc51SSivaprakash Murugesan reg = <0x00058000 0x1c4>; 1175e09bc51SSivaprakash Murugesan #address-cells = <1>; 1185e09bc51SSivaprakash Murugesan #size-cells = <1>; 1195e09bc51SSivaprakash Murugesan ranges; 1205e09bc51SSivaprakash Murugesan 1215e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_AUX_CLK>, 1225e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1235e09bc51SSivaprakash Murugesan <&xo>; 1245e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1255e09bc51SSivaprakash Murugesan 1265e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_PHY_BCR>, 1275e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_1_PHY_BCR>; 1285e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1295e09bc51SSivaprakash Murugesan status = "disabled"; 1305e09bc51SSivaprakash Murugesan 1311351512fSShawn Guo usb1_ssphy: phy@58200 { 1325e09bc51SSivaprakash Murugesan reg = <0x00058200 0x130>, /* Tx */ 1335e09bc51SSivaprakash Murugesan <0x00058400 0x200>, /* Rx */ 1345e09bc51SSivaprakash Murugesan <0x00058800 0x1f8>, /* PCS */ 1355e09bc51SSivaprakash Murugesan <0x00058600 0x044>; /* PCS misc */ 1365e09bc51SSivaprakash Murugesan #phy-cells = <0>; 137de9e7f77SJohan Hovold #clock-cells = <0>; 1385e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PIPE_CLK>; 1395e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 140877cff35SRobert Marko clock-output-names = "usb3phy_1_cc_pipe_clk"; 1415e09bc51SSivaprakash Murugesan }; 1425e09bc51SSivaprakash Murugesan }; 1435e09bc51SSivaprakash Murugesan 1445e09bc51SSivaprakash Murugesan qusb_phy_1: phy@59000 { 1455e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1465e09bc51SSivaprakash Murugesan reg = <0x00059000 0x180>; 1475e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1485e09bc51SSivaprakash Murugesan 1495e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1505e09bc51SSivaprakash Murugesan <&xo>; 1515e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1525e09bc51SSivaprakash Murugesan 1535e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 1545e09bc51SSivaprakash Murugesan status = "disabled"; 1555e09bc51SSivaprakash Murugesan }; 1565e09bc51SSivaprakash Murugesan 1575e09bc51SSivaprakash Murugesan ssphy_0: phy@78000 { 1585e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1595e09bc51SSivaprakash Murugesan reg = <0x00078000 0x1c4>; 1605e09bc51SSivaprakash Murugesan #address-cells = <1>; 1615e09bc51SSivaprakash Murugesan #size-cells = <1>; 1625e09bc51SSivaprakash Murugesan ranges; 1635e09bc51SSivaprakash Murugesan 1645e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_AUX_CLK>, 1655e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1665e09bc51SSivaprakash Murugesan <&xo>; 1675e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1685e09bc51SSivaprakash Murugesan 1695e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_PHY_BCR>, 1705e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_0_PHY_BCR>; 1715e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1725e09bc51SSivaprakash Murugesan status = "disabled"; 1735e09bc51SSivaprakash Murugesan 1741351512fSShawn Guo usb0_ssphy: phy@78200 { 1755e09bc51SSivaprakash Murugesan reg = <0x00078200 0x130>, /* Tx */ 1765e09bc51SSivaprakash Murugesan <0x00078400 0x200>, /* Rx */ 1775e09bc51SSivaprakash Murugesan <0x00078800 0x1f8>, /* PCS */ 1785e09bc51SSivaprakash Murugesan <0x00078600 0x044>; /* PCS misc */ 1795e09bc51SSivaprakash Murugesan #phy-cells = <0>; 180de9e7f77SJohan Hovold #clock-cells = <0>; 1815e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PIPE_CLK>; 1825e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 183877cff35SRobert Marko clock-output-names = "usb3phy_0_cc_pipe_clk"; 1845e09bc51SSivaprakash Murugesan }; 1855e09bc51SSivaprakash Murugesan }; 1865e09bc51SSivaprakash Murugesan 1875e09bc51SSivaprakash Murugesan qusb_phy_0: phy@79000 { 1885e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1895e09bc51SSivaprakash Murugesan reg = <0x00079000 0x180>; 1905e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1915e09bc51SSivaprakash Murugesan 1925e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1935e09bc51SSivaprakash Murugesan <&xo>; 1945e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1955e09bc51SSivaprakash Murugesan 1965e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 19758b2785dSRobert Marko status = "disabled"; 1985e09bc51SSivaprakash Murugesan }; 1995e09bc51SSivaprakash Murugesan 2007ba33591SRobert Marko pcie_qmp0: phy@84000 { 2017ba33591SRobert Marko compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 2027ba33591SRobert Marko reg = <0x00084000 0x1bc>; 203942bcd33SShawn Guo #address-cells = <1>; 204942bcd33SShawn Guo #size-cells = <1>; 205942bcd33SShawn Guo ranges; 206e8a7fdc5SSivaprakash Murugesan 207942bcd33SShawn Guo clocks = <&gcc GCC_PCIE0_AUX_CLK>, 208942bcd33SShawn Guo <&gcc GCC_PCIE0_AHB_CLK>; 209942bcd33SShawn Guo clock-names = "aux", "cfg_ahb"; 210e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PHY_BCR>, 211e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0PHY_PHY_BCR>; 212e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 213e8a7fdc5SSivaprakash Murugesan "common"; 214e8a7fdc5SSivaprakash Murugesan status = "disabled"; 215942bcd33SShawn Guo 2167ba33591SRobert Marko pcie_phy0: phy@84200 { 2177ba33591SRobert Marko reg = <0x84200 0x16c>, 2187ba33591SRobert Marko <0x84400 0x200>, 2197ba33591SRobert Marko <0x84800 0x1f0>, 2207ba33591SRobert Marko <0x84c00 0xf4>; 221942bcd33SShawn Guo #phy-cells = <0>; 222942bcd33SShawn Guo #clock-cells = <0>; 223942bcd33SShawn Guo clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 224942bcd33SShawn Guo clock-names = "pipe0"; 225942bcd33SShawn Guo clock-output-names = "pcie_0_pipe_clk"; 226942bcd33SShawn Guo }; 227e8a7fdc5SSivaprakash Murugesan }; 228e8a7fdc5SSivaprakash Murugesan 229942bcd33SShawn Guo pcie_qmp1: phy@8e000 { 230e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 231ed22cc93SJohan Hovold reg = <0x0008e000 0x1c4>; 232942bcd33SShawn Guo #address-cells = <1>; 233942bcd33SShawn Guo #size-cells = <1>; 234942bcd33SShawn Guo ranges; 235e8a7fdc5SSivaprakash Murugesan 236942bcd33SShawn Guo clocks = <&gcc GCC_PCIE1_AUX_CLK>, 237942bcd33SShawn Guo <&gcc GCC_PCIE1_AHB_CLK>; 238942bcd33SShawn Guo clock-names = "aux", "cfg_ahb"; 239e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE1_PHY_BCR>, 240e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE1PHY_PHY_BCR>; 241e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 242e8a7fdc5SSivaprakash Murugesan "common"; 243e8a7fdc5SSivaprakash Murugesan status = "disabled"; 244942bcd33SShawn Guo 245942bcd33SShawn Guo pcie_phy1: phy@8e200 { 246100d9c94SRobert Marko reg = <0x8e200 0x130>, 247942bcd33SShawn Guo <0x8e400 0x200>, 248100d9c94SRobert Marko <0x8e800 0x1f8>; 249942bcd33SShawn Guo #phy-cells = <0>; 250942bcd33SShawn Guo #clock-cells = <0>; 251942bcd33SShawn Guo clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 252942bcd33SShawn Guo clock-names = "pipe0"; 253942bcd33SShawn Guo clock-output-names = "pcie_1_pipe_clk"; 254942bcd33SShawn Guo }; 255e8a7fdc5SSivaprakash Murugesan }; 256e8a7fdc5SSivaprakash Murugesan 257d201f677SRobert Marko mdio: mdio@90000 { 25836e830a5SRobert Marko compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 259d201f677SRobert Marko reg = <0x00090000 0x64>; 260d201f677SRobert Marko #address-cells = <1>; 261d201f677SRobert Marko #size-cells = <0>; 262d201f677SRobert Marko 263d201f677SRobert Marko clocks = <&gcc GCC_MDIO_AHB_CLK>; 264d201f677SRobert Marko clock-names = "gcc_mdio_ahb_clk"; 265d201f677SRobert Marko 266d201f677SRobert Marko status = "disabled"; 267d201f677SRobert Marko }; 268d201f677SRobert Marko 269f26f6a5eSRobert Marko prng: rng@e3000 { 270f26f6a5eSRobert Marko compatible = "qcom,prng-ee"; 271f26f6a5eSRobert Marko reg = <0x000e3000 0x1000>; 272f26f6a5eSRobert Marko clocks = <&gcc GCC_PRNG_AHB_CLK>; 273f26f6a5eSRobert Marko clock-names = "core"; 274f26f6a5eSRobert Marko status = "disabled"; 275f26f6a5eSRobert Marko }; 276f26f6a5eSRobert Marko 277887ac089SRobert Marko tsens: thermal-sensor@4a9000 { 278887ac089SRobert Marko compatible = "qcom,ipq8074-tsens"; 279887ac089SRobert Marko reg = <0x4a9000 0x1000>, /* TM */ 280887ac089SRobert Marko <0x4a8000 0x1000>; /* SROT */ 281887ac089SRobert Marko interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 282887ac089SRobert Marko interrupt-names = "combined"; 283887ac089SRobert Marko #qcom,sensors = <16>; 284887ac089SRobert Marko #thermal-sensor-cells = <1>; 285887ac089SRobert Marko }; 286887ac089SRobert Marko 287bbef0142SShawn Guo cryptobam: dma-controller@704000 { 288f9e2df82SRobert Marko compatible = "qcom,bam-v1.7.0"; 289f9e2df82SRobert Marko reg = <0x00704000 0x20000>; 290f9e2df82SRobert Marko interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 291f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 292f9e2df82SRobert Marko clock-names = "bam_clk"; 293f9e2df82SRobert Marko #dma-cells = <1>; 294f9e2df82SRobert Marko qcom,ee = <1>; 2958c97f0acSShawn Guo qcom,controlled-remotely; 296f9e2df82SRobert Marko status = "disabled"; 297f9e2df82SRobert Marko }; 298f9e2df82SRobert Marko 299f9e2df82SRobert Marko crypto: crypto@73a000 { 300f9e2df82SRobert Marko compatible = "qcom,crypto-v5.1"; 301f9e2df82SRobert Marko reg = <0x0073a000 0x6000>; 302f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 303f9e2df82SRobert Marko <&gcc GCC_CRYPTO_AXI_CLK>, 304f9e2df82SRobert Marko <&gcc GCC_CRYPTO_CLK>; 305f9e2df82SRobert Marko clock-names = "iface", "bus", "core"; 306f9e2df82SRobert Marko dmas = <&cryptobam 2>, <&cryptobam 3>; 307f9e2df82SRobert Marko dma-names = "rx", "tx"; 308f9e2df82SRobert Marko status = "disabled"; 309f9e2df82SRobert Marko }; 310f9e2df82SRobert Marko 31133057e16SSricharan R tlmm: pinctrl@1000000 { 31241dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074-pinctrl"; 313e8a7fdc5SSivaprakash Murugesan reg = <0x01000000 0x300000>; 31441dac73eSVaradarajan Narayanan interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 31541dac73eSVaradarajan Narayanan gpio-controller; 316297177a4SChristian Lamparter gpio-ranges = <&tlmm 0 0 70>; 31741dac73eSVaradarajan Narayanan #gpio-cells = <0x2>; 31841dac73eSVaradarajan Narayanan interrupt-controller; 31941dac73eSVaradarajan Narayanan #interrupt-cells = <0x2>; 32022592a22SSricharan R 3211c3c31a6SKrzysztof Kozlowski serial_4_pins: serial4-state { 32222592a22SSricharan R pins = "gpio23", "gpio24"; 32322592a22SSricharan R function = "blsp4_uart1"; 32422592a22SSricharan R drive-strength = <8>; 32522592a22SSricharan R bias-disable; 32622592a22SSricharan R }; 32722592a22SSricharan R 3281c3c31a6SKrzysztof Kozlowski i2c_0_pins: i2c-0-state { 32922592a22SSricharan R pins = "gpio42", "gpio43"; 33022592a22SSricharan R function = "blsp1_i2c"; 33122592a22SSricharan R drive-strength = <8>; 33222592a22SSricharan R bias-disable; 33322592a22SSricharan R }; 33422592a22SSricharan R 3351c3c31a6SKrzysztof Kozlowski spi_0_pins: spi-0-state { 33622592a22SSricharan R pins = "gpio38", "gpio39", "gpio40", "gpio41"; 33722592a22SSricharan R function = "blsp0_spi"; 33822592a22SSricharan R drive-strength = <8>; 33922592a22SSricharan R bias-disable; 34022592a22SSricharan R }; 34122592a22SSricharan R 3421c3c31a6SKrzysztof Kozlowski hsuart_pins: hsuart-state { 34322592a22SSricharan R pins = "gpio46", "gpio47", "gpio48", "gpio49"; 34422592a22SSricharan R function = "blsp2_uart"; 34522592a22SSricharan R drive-strength = <8>; 34622592a22SSricharan R bias-disable; 34722592a22SSricharan R }; 34822592a22SSricharan R 3491c3c31a6SKrzysztof Kozlowski qpic_pins: qpic-state { 35022592a22SSricharan R pins = "gpio1", "gpio3", "gpio4", 35122592a22SSricharan R "gpio5", "gpio6", "gpio7", 35222592a22SSricharan R "gpio8", "gpio10", "gpio11", 35322592a22SSricharan R "gpio12", "gpio13", "gpio14", 35422592a22SSricharan R "gpio15", "gpio16", "gpio17"; 35522592a22SSricharan R function = "qpic"; 35622592a22SSricharan R drive-strength = <8>; 35722592a22SSricharan R bias-disable; 35822592a22SSricharan R }; 35941dac73eSVaradarajan Narayanan }; 36041dac73eSVaradarajan Narayanan 36141dac73eSVaradarajan Narayanan gcc: gcc@1800000 { 36241dac73eSVaradarajan Narayanan compatible = "qcom,gcc-ipq8074"; 363e8a7fdc5SSivaprakash Murugesan reg = <0x01800000 0x80000>; 3643aa0b8cdSRobert Marko clocks = <&xo>, <&sleep_clk>; 3653aa0b8cdSRobert Marko clock-names = "xo", "sleep_clk"; 3663aa0b8cdSRobert Marko #clock-cells = <1>; 3678bbda511SRobert Marko #power-domain-cells = <1>; 3683aa0b8cdSRobert Marko #reset-cells = <1>; 36941dac73eSVaradarajan Narayanan }; 37041dac73eSVaradarajan Narayanan 37142124b94SRobert Marko tcsr_mutex: hwlock@1905000 { 37242124b94SRobert Marko compatible = "qcom,tcsr-mutex"; 37342124b94SRobert Marko reg = <0x01905000 0x20000>; 37442124b94SRobert Marko #hwlock-cells = <1>; 37542124b94SRobert Marko }; 37642124b94SRobert Marko 37763750607SRobert Marko spmi_bus: spmi@200f000 { 37863750607SRobert Marko compatible = "qcom,spmi-pmic-arb"; 37963750607SRobert Marko reg = <0x0200f000 0x001000>, 38063750607SRobert Marko <0x02400000 0x800000>, 38163750607SRobert Marko <0x02c00000 0x800000>, 38263750607SRobert Marko <0x03800000 0x200000>, 38363750607SRobert Marko <0x0200a000 0x000700>; 38463750607SRobert Marko reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 38563750607SRobert Marko interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 38663750607SRobert Marko interrupt-names = "periph_irq"; 38763750607SRobert Marko qcom,ee = <0>; 38863750607SRobert Marko qcom,channel = <0>; 38963750607SRobert Marko #address-cells = <2>; 39063750607SRobert Marko #size-cells = <0>; 39163750607SRobert Marko interrupt-controller; 39263750607SRobert Marko #interrupt-cells = <4>; 39363750607SRobert Marko cell-index = <0>; 39463750607SRobert Marko }; 39563750607SRobert Marko 39696bb736fSBhupesh Sharma sdhc_1: mmc@7824900 { 397cbc142c8SSivaprakash Murugesan compatible = "qcom,sdhci-msm-v4"; 398cbc142c8SSivaprakash Murugesan reg = <0x7824900 0x500>, <0x7824000 0x800>; 399eddc917dSKrzysztof Kozlowski reg-names = "hc", "core"; 400cbc142c8SSivaprakash Murugesan 401cbc142c8SSivaprakash Murugesan interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 402cbc142c8SSivaprakash Murugesan <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 403cbc142c8SSivaprakash Murugesan interrupt-names = "hc_irq", "pwr_irq"; 404cbc142c8SSivaprakash Murugesan 4054ff12270SBhupesh Sharma clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4064ff12270SBhupesh Sharma <&gcc GCC_SDCC1_APPS_CLK>, 4074ff12270SBhupesh Sharma <&xo>; 4084ff12270SBhupesh Sharma clock-names = "iface", "core", "xo"; 409730d55d8SRobert Marko resets = <&gcc GCC_SDCC1_BCR>; 410cbc142c8SSivaprakash Murugesan max-frequency = <384000000>; 411cbc142c8SSivaprakash Murugesan mmc-ddr-1_8v; 412cbc142c8SSivaprakash Murugesan mmc-hs200-1_8v; 413cbc142c8SSivaprakash Murugesan mmc-hs400-1_8v; 414cbc142c8SSivaprakash Murugesan bus-width = <8>; 415cbc142c8SSivaprakash Murugesan 416cbc142c8SSivaprakash Murugesan status = "disabled"; 417cbc142c8SSivaprakash Murugesan }; 418cbc142c8SSivaprakash Murugesan 419b7fbf46cSVinod Koul blsp_dma: dma-controller@7884000 { 42022592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 421e8a7fdc5SSivaprakash Murugesan reg = <0x07884000 0x2b000>; 42222592a22SSricharan R interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 42322592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>; 42422592a22SSricharan R clock-names = "bam_clk"; 42522592a22SSricharan R #dma-cells = <1>; 42622592a22SSricharan R qcom,ee = <0>; 42722592a22SSricharan R }; 42822592a22SSricharan R 42922592a22SSricharan R blsp1_uart1: serial@78af000 { 43022592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 431e8a7fdc5SSivaprakash Murugesan reg = <0x078af000 0x200>; 43222592a22SSricharan R interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 43322592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 43422592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 43522592a22SSricharan R clock-names = "core", "iface"; 43622592a22SSricharan R status = "disabled"; 43722592a22SSricharan R }; 43822592a22SSricharan R 43922592a22SSricharan R blsp1_uart3: serial@78b1000 { 44022592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 441e8a7fdc5SSivaprakash Murugesan reg = <0x078b1000 0x200>; 44222592a22SSricharan R interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 44322592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 44422592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 44522592a22SSricharan R clock-names = "core", "iface"; 44622592a22SSricharan R dmas = <&blsp_dma 4>, 44722592a22SSricharan R <&blsp_dma 5>; 44822592a22SSricharan R dma-names = "tx", "rx"; 44922592a22SSricharan R pinctrl-0 = <&hsuart_pins>; 45022592a22SSricharan R pinctrl-names = "default"; 45122592a22SSricharan R status = "disabled"; 45222592a22SSricharan R }; 45322592a22SSricharan R 454e8a7fdc5SSivaprakash Murugesan blsp1_uart5: serial@78b3000 { 455e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 456e8a7fdc5SSivaprakash Murugesan reg = <0x078b3000 0x200>; 457e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 458e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 459e8a7fdc5SSivaprakash Murugesan <&gcc GCC_BLSP1_AHB_CLK>; 460e8a7fdc5SSivaprakash Murugesan clock-names = "core", "iface"; 461e8a7fdc5SSivaprakash Murugesan pinctrl-0 = <&serial_4_pins>; 462e8a7fdc5SSivaprakash Murugesan pinctrl-names = "default"; 463e8a7fdc5SSivaprakash Murugesan status = "disabled"; 464e8a7fdc5SSivaprakash Murugesan }; 465e8a7fdc5SSivaprakash Murugesan 46622592a22SSricharan R blsp1_spi1: spi@78b5000 { 46722592a22SSricharan R compatible = "qcom,spi-qup-v2.2.1"; 46822592a22SSricharan R #address-cells = <1>; 46922592a22SSricharan R #size-cells = <0>; 470e8a7fdc5SSivaprakash Murugesan reg = <0x078b5000 0x600>; 47122592a22SSricharan R interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 47222592a22SSricharan R spi-max-frequency = <50000000>; 47322592a22SSricharan R clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 47422592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 47522592a22SSricharan R clock-names = "core", "iface"; 47622592a22SSricharan R dmas = <&blsp_dma 12>, <&blsp_dma 13>; 47722592a22SSricharan R dma-names = "tx", "rx"; 47822592a22SSricharan R pinctrl-0 = <&spi_0_pins>; 47922592a22SSricharan R pinctrl-names = "default"; 48022592a22SSricharan R status = "disabled"; 48122592a22SSricharan R }; 48222592a22SSricharan R 48322592a22SSricharan R blsp1_i2c2: i2c@78b6000 { 48422592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 48522592a22SSricharan R #address-cells = <1>; 48622592a22SSricharan R #size-cells = <0>; 487e8a7fdc5SSivaprakash Murugesan reg = <0x078b6000 0x600>; 48822592a22SSricharan R interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 4892374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 4902374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 4912374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 49222592a22SSricharan R clock-frequency = <400000>; 4930e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 14>, <&blsp_dma 15>; 4940e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 49522592a22SSricharan R pinctrl-0 = <&i2c_0_pins>; 49622592a22SSricharan R pinctrl-names = "default"; 49722592a22SSricharan R status = "disabled"; 49822592a22SSricharan R }; 49922592a22SSricharan R 50022592a22SSricharan R blsp1_i2c3: i2c@78b7000 { 50122592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 50222592a22SSricharan R #address-cells = <1>; 50322592a22SSricharan R #size-cells = <0>; 504e8a7fdc5SSivaprakash Murugesan reg = <0x078b7000 0x600>; 50522592a22SSricharan R interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 5062374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 5072374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 5082374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 50922592a22SSricharan R clock-frequency = <100000>; 5100e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 16>, <&blsp_dma 17>; 5110e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 51222592a22SSricharan R status = "disabled"; 51322592a22SSricharan R }; 51422592a22SSricharan R 5159c0bd8e5SChukun Pan blsp1_i2c5: i2c@78b9000 { 5169c0bd8e5SChukun Pan compatible = "qcom,i2c-qup-v2.2.1"; 5179c0bd8e5SChukun Pan #address-cells = <1>; 5189c0bd8e5SChukun Pan #size-cells = <0>; 5199c0bd8e5SChukun Pan reg = <0x78b9000 0x600>; 5209c0bd8e5SChukun Pan interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 5212374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 5222374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 5232374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 5249c0bd8e5SChukun Pan clock-frequency = <400000>; 5250e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 20>, <&blsp_dma 21>; 5260e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 5279c0bd8e5SChukun Pan status = "disabled"; 5289c0bd8e5SChukun Pan }; 5299c0bd8e5SChukun Pan 530abe66bb7SRobert Marko blsp1_i2c6: i2c@78ba000 { 531abe66bb7SRobert Marko compatible = "qcom,i2c-qup-v2.2.1"; 532abe66bb7SRobert Marko #address-cells = <1>; 533abe66bb7SRobert Marko #size-cells = <0>; 534abe66bb7SRobert Marko reg = <0x078ba000 0x600>; 535abe66bb7SRobert Marko interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 5362374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 5372374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 5382374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 539abe66bb7SRobert Marko clock-frequency = <100000>; 5400e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 22>, <&blsp_dma 23>; 5410e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 542abe66bb7SRobert Marko status = "disabled"; 543abe66bb7SRobert Marko }; 544abe66bb7SRobert Marko 545b7fbf46cSVinod Koul qpic_bam: dma-controller@7984000 { 54622592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 547e8a7fdc5SSivaprakash Murugesan reg = <0x07984000 0x1a000>; 54822592a22SSricharan R interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 54922592a22SSricharan R clocks = <&gcc GCC_QPIC_AHB_CLK>; 55022592a22SSricharan R clock-names = "bam_clk"; 55122592a22SSricharan R #dma-cells = <1>; 55222592a22SSricharan R qcom,ee = <0>; 55322592a22SSricharan R status = "disabled"; 55422592a22SSricharan R }; 55522592a22SSricharan R 556b3996165SRobert Marko qpic_nand: nand-controller@79b0000 { 55722592a22SSricharan R compatible = "qcom,ipq8074-nand"; 558e8a7fdc5SSivaprakash Murugesan reg = <0x079b0000 0x10000>; 55922592a22SSricharan R #address-cells = <1>; 56022592a22SSricharan R #size-cells = <0>; 56122592a22SSricharan R clocks = <&gcc GCC_QPIC_CLK>, 56222592a22SSricharan R <&gcc GCC_QPIC_AHB_CLK>; 56322592a22SSricharan R clock-names = "core", "aon"; 56422592a22SSricharan R 56522592a22SSricharan R dmas = <&qpic_bam 0>, 56622592a22SSricharan R <&qpic_bam 1>, 56722592a22SSricharan R <&qpic_bam 2>; 56822592a22SSricharan R dma-names = "tx", "rx", "cmd"; 56922592a22SSricharan R pinctrl-0 = <&qpic_pins>; 57022592a22SSricharan R pinctrl-names = "default"; 57141dac73eSVaradarajan Narayanan status = "disabled"; 57241dac73eSVaradarajan Narayanan }; 57333057e16SSricharan R 5745e09bc51SSivaprakash Murugesan usb_0: usb@8af8800 { 5753a6b8bf1SKrzysztof Kozlowski compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 5765e09bc51SSivaprakash Murugesan reg = <0x08af8800 0x400>; 5775e09bc51SSivaprakash Murugesan #address-cells = <1>; 5785e09bc51SSivaprakash Murugesan #size-cells = <1>; 5795e09bc51SSivaprakash Murugesan ranges; 5805e09bc51SSivaprakash Murugesan 5815e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 5825e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 5835e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_SLEEP_CLK>, 5845e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 5858d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 5868d5fd4e4SKrzysztof Kozlowski "core", 5875e09bc51SSivaprakash Murugesan "sleep", 5885e09bc51SSivaprakash Murugesan "mock_utmi"; 5895e09bc51SSivaprakash Murugesan 5905e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 5915e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 5925e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 5935e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 5945e09bc51SSivaprakash Murugesan <133330000>, 5955e09bc51SSivaprakash Murugesan <19200000>; 5965e09bc51SSivaprakash Murugesan 5978bbda511SRobert Marko power-domains = <&gcc USB0_GDSC>; 5988bbda511SRobert Marko 5995e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_BCR>; 6005e09bc51SSivaprakash Murugesan status = "disabled"; 6015e09bc51SSivaprakash Murugesan 602b77a1c4dSKrzysztof Kozlowski dwc_0: usb@8a00000 { 6035e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 6045e09bc51SSivaprakash Murugesan reg = <0x8a00000 0xcd00>; 6055e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 6065e09bc51SSivaprakash Murugesan phys = <&qusb_phy_0>, <&usb0_ssphy>; 6075e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 6085e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 6095e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 6105e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 6115e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 6125e09bc51SSivaprakash Murugesan dr_mode = "host"; 6135e09bc51SSivaprakash Murugesan }; 6145e09bc51SSivaprakash Murugesan }; 6155e09bc51SSivaprakash Murugesan 6165e09bc51SSivaprakash Murugesan usb_1: usb@8cf8800 { 6173a6b8bf1SKrzysztof Kozlowski compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 6185e09bc51SSivaprakash Murugesan reg = <0x08cf8800 0x400>; 6195e09bc51SSivaprakash Murugesan #address-cells = <1>; 6205e09bc51SSivaprakash Murugesan #size-cells = <1>; 6215e09bc51SSivaprakash Murugesan ranges; 6225e09bc51SSivaprakash Murugesan 6235e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 6245e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 6255e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_SLEEP_CLK>, 6265e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 6278d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 6288d5fd4e4SKrzysztof Kozlowski "core", 6295e09bc51SSivaprakash Murugesan "sleep", 6305e09bc51SSivaprakash Murugesan "mock_utmi"; 6315e09bc51SSivaprakash Murugesan 6325e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 6335e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 6345e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 6355e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 6365e09bc51SSivaprakash Murugesan <133330000>, 6375e09bc51SSivaprakash Murugesan <19200000>; 6385e09bc51SSivaprakash Murugesan 6398bbda511SRobert Marko power-domains = <&gcc USB1_GDSC>; 6408bbda511SRobert Marko 6415e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_BCR>; 6425e09bc51SSivaprakash Murugesan status = "disabled"; 6435e09bc51SSivaprakash Murugesan 644b77a1c4dSKrzysztof Kozlowski dwc_1: usb@8c00000 { 6455e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 6465e09bc51SSivaprakash Murugesan reg = <0x8c00000 0xcd00>; 6475e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 6485e09bc51SSivaprakash Murugesan phys = <&qusb_phy_1>, <&usb1_ssphy>; 6495e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 6505e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 6515e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 6525e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 6535e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 6545e09bc51SSivaprakash Murugesan dr_mode = "host"; 6555e09bc51SSivaprakash Murugesan }; 6565e09bc51SSivaprakash Murugesan }; 6575e09bc51SSivaprakash Murugesan 658e8a7fdc5SSivaprakash Murugesan intc: interrupt-controller@b000000 { 659e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-qgic2"; 66059892de9SKathiravan T #address-cells = <1>; 66159892de9SKathiravan T #size-cells = <1>; 662e8a7fdc5SSivaprakash Murugesan interrupt-controller; 663e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <0x3>; 664e8a7fdc5SSivaprakash Murugesan reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 66559892de9SKathiravan T ranges = <0 0xb00a000 0xffd>; 66659892de9SKathiravan T 66759892de9SKathiravan T v2m@0 { 66859892de9SKathiravan T compatible = "arm,gic-v2m-frame"; 66959892de9SKathiravan T msi-controller; 67059892de9SKathiravan T reg = <0x0 0xffd>; 67159892de9SKathiravan T }; 672e8a7fdc5SSivaprakash Murugesan }; 67333057e16SSricharan R 674949766e0SKathiravan T watchdog: watchdog@b017000 { 675949766e0SKathiravan T compatible = "qcom,kpss-wdt"; 676949766e0SKathiravan T reg = <0xb017000 0x1000>; 677949766e0SKathiravan T interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 678949766e0SKathiravan T clocks = <&sleep_clk>; 679949766e0SKathiravan T timeout-sec = <30>; 680949766e0SKathiravan T }; 681949766e0SKathiravan T 68250ed9fffSRobert Marko apcs_glb: mailbox@b111000 { 68350ed9fffSRobert Marko compatible = "qcom,ipq8074-apcs-apps-global"; 68440b21d46SRobert Marko reg = <0x0b111000 0x1000>; 685fd8bdb45SRobert Marko clocks = <&a53pll>, <&xo>; 686fd8bdb45SRobert Marko clock-names = "pll", "xo"; 68750ed9fffSRobert Marko 68850ed9fffSRobert Marko #clock-cells = <1>; 68950ed9fffSRobert Marko #mbox-cells = <1>; 69050ed9fffSRobert Marko }; 69150ed9fffSRobert Marko 692fe6d5b8dSRobert Marko a53pll: clock@b116000 { 693fe6d5b8dSRobert Marko compatible = "qcom,ipq8074-a53pll"; 694fe6d5b8dSRobert Marko reg = <0x0b116000 0x40>; 695fe6d5b8dSRobert Marko #clock-cells = <0>; 696fe6d5b8dSRobert Marko clocks = <&xo>; 697fe6d5b8dSRobert Marko clock-names = "xo"; 698fe6d5b8dSRobert Marko }; 699fe6d5b8dSRobert Marko 700e8a7fdc5SSivaprakash Murugesan timer@b120000 { 701e8a7fdc5SSivaprakash Murugesan #address-cells = <1>; 702e8a7fdc5SSivaprakash Murugesan #size-cells = <1>; 703e8a7fdc5SSivaprakash Murugesan ranges; 704e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv7-timer-mem"; 705e8a7fdc5SSivaprakash Murugesan reg = <0x0b120000 0x1000>; 706e8a7fdc5SSivaprakash Murugesan 707e8a7fdc5SSivaprakash Murugesan frame@b120000 { 708e8a7fdc5SSivaprakash Murugesan frame-number = <0>; 709e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 710e8a7fdc5SSivaprakash Murugesan <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 711e8a7fdc5SSivaprakash Murugesan reg = <0x0b121000 0x1000>, 712e8a7fdc5SSivaprakash Murugesan <0x0b122000 0x1000>; 713e8a7fdc5SSivaprakash Murugesan }; 714e8a7fdc5SSivaprakash Murugesan 715e8a7fdc5SSivaprakash Murugesan frame@b123000 { 716e8a7fdc5SSivaprakash Murugesan frame-number = <1>; 717e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 718e8a7fdc5SSivaprakash Murugesan reg = <0x0b123000 0x1000>; 71933057e16SSricharan R status = "disabled"; 72033057e16SSricharan R }; 72133057e16SSricharan R 722e8a7fdc5SSivaprakash Murugesan frame@b124000 { 723e8a7fdc5SSivaprakash Murugesan frame-number = <2>; 724e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 725e8a7fdc5SSivaprakash Murugesan reg = <0x0b124000 0x1000>; 72633057e16SSricharan R status = "disabled"; 72733057e16SSricharan R }; 72833057e16SSricharan R 729e8a7fdc5SSivaprakash Murugesan frame@b125000 { 730e8a7fdc5SSivaprakash Murugesan frame-number = <3>; 731e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 732e8a7fdc5SSivaprakash Murugesan reg = <0x0b125000 0x1000>; 73333057e16SSricharan R status = "disabled"; 73433057e16SSricharan R }; 73533057e16SSricharan R 736e8a7fdc5SSivaprakash Murugesan frame@b126000 { 737e8a7fdc5SSivaprakash Murugesan frame-number = <4>; 738e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 739e8a7fdc5SSivaprakash Murugesan reg = <0x0b126000 0x1000>; 740e8a7fdc5SSivaprakash Murugesan status = "disabled"; 741e8a7fdc5SSivaprakash Murugesan }; 742e8a7fdc5SSivaprakash Murugesan 743e8a7fdc5SSivaprakash Murugesan frame@b127000 { 744e8a7fdc5SSivaprakash Murugesan frame-number = <5>; 745e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 746e8a7fdc5SSivaprakash Murugesan reg = <0x0b127000 0x1000>; 747e8a7fdc5SSivaprakash Murugesan status = "disabled"; 748e8a7fdc5SSivaprakash Murugesan }; 749e8a7fdc5SSivaprakash Murugesan 750e8a7fdc5SSivaprakash Murugesan frame@b128000 { 751e8a7fdc5SSivaprakash Murugesan frame-number = <6>; 752e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 753e8a7fdc5SSivaprakash Murugesan reg = <0x0b128000 0x1000>; 754e8a7fdc5SSivaprakash Murugesan status = "disabled"; 755e8a7fdc5SSivaprakash Murugesan }; 756e8a7fdc5SSivaprakash Murugesan }; 757e8a7fdc5SSivaprakash Murugesan 75833057e16SSricharan R pcie1: pci@10000000 { 75933057e16SSricharan R compatible = "qcom,pcie-ipq8074"; 76052c9887fSVinod Koul reg = <0x10000000 0xf1d>, 76152c9887fSVinod Koul <0x10000f20 0xa8>, 76252c9887fSVinod Koul <0x00088000 0x2000>, 76352c9887fSVinod Koul <0x10100000 0x1000>; 76433057e16SSricharan R reg-names = "dbi", "elbi", "parf", "config"; 76533057e16SSricharan R device_type = "pci"; 76633057e16SSricharan R linux,pci-domain = <1>; 76733057e16SSricharan R bus-range = <0x00 0xff>; 76833057e16SSricharan R num-lanes = <1>; 769b6059031SRobert Marko max-link-speed = <2>; 77033057e16SSricharan R #address-cells = <3>; 77133057e16SSricharan R #size-cells = <2>; 77233057e16SSricharan R 77333057e16SSricharan R phys = <&pcie_phy1>; 77433057e16SSricharan R phy-names = "pciephy"; 77533057e16SSricharan R 77633057e16SSricharan R ranges = <0x81000000 0 0x10200000 0x10200000 7772055cb7dSRobert Marko 0 0x10000>, /* downstream I/O */ 7782055cb7dSRobert Marko <0x82000000 0 0x10220000 0x10220000 7792055cb7dSRobert Marko 0 0xfde0000>; /* non-prefetchable memory */ 78033057e16SSricharan R 78133057e16SSricharan R interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 78233057e16SSricharan R interrupt-names = "msi"; 78333057e16SSricharan R #interrupt-cells = <1>; 78433057e16SSricharan R interrupt-map-mask = <0 0 0 0x7>; 78533057e16SSricharan R interrupt-map = <0 0 0 1 &intc 0 142 78633057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 78733057e16SSricharan R <0 0 0 2 &intc 0 143 78833057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 78933057e16SSricharan R <0 0 0 3 &intc 0 144 79033057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 79133057e16SSricharan R <0 0 0 4 &intc 0 145 79233057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 79333057e16SSricharan R 79433057e16SSricharan R clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 79533057e16SSricharan R <&gcc GCC_PCIE1_AXI_M_CLK>, 79633057e16SSricharan R <&gcc GCC_PCIE1_AXI_S_CLK>, 79733057e16SSricharan R <&gcc GCC_PCIE1_AHB_CLK>, 79833057e16SSricharan R <&gcc GCC_PCIE1_AUX_CLK>; 79933057e16SSricharan R clock-names = "iface", 80033057e16SSricharan R "axi_m", 80133057e16SSricharan R "axi_s", 80233057e16SSricharan R "ahb", 80333057e16SSricharan R "aux"; 80433057e16SSricharan R resets = <&gcc GCC_PCIE1_PIPE_ARES>, 80533057e16SSricharan R <&gcc GCC_PCIE1_SLEEP_ARES>, 80633057e16SSricharan R <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 80733057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 80833057e16SSricharan R <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 80933057e16SSricharan R <&gcc GCC_PCIE1_AHB_ARES>, 81033057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 81133057e16SSricharan R reset-names = "pipe", 81233057e16SSricharan R "sleep", 81333057e16SSricharan R "sticky", 81433057e16SSricharan R "axi_m", 81533057e16SSricharan R "axi_s", 81633057e16SSricharan R "ahb", 81733057e16SSricharan R "axi_m_sticky"; 81833057e16SSricharan R status = "disabled"; 81933057e16SSricharan R }; 82041dac73eSVaradarajan Narayanan 821e8a7fdc5SSivaprakash Murugesan pcie0: pci@20000000 { 822*3e83a9c4SRobert Marko compatible = "qcom,pcie-ipq8074-gen3"; 82352c9887fSVinod Koul reg = <0x20000000 0xf1d>, 82452c9887fSVinod Koul <0x20000f20 0xa8>, 825*3e83a9c4SRobert Marko <0x20001000 0x1000>, 826*3e83a9c4SRobert Marko <0x00080000 0x4000>, 82752c9887fSVinod Koul <0x20100000 0x1000>; 828*3e83a9c4SRobert Marko reg-names = "dbi", "elbi", "atu", "parf", "config"; 829e8a7fdc5SSivaprakash Murugesan device_type = "pci"; 830e8a7fdc5SSivaprakash Murugesan linux,pci-domain = <0>; 831e8a7fdc5SSivaprakash Murugesan bus-range = <0x00 0xff>; 832e8a7fdc5SSivaprakash Murugesan num-lanes = <1>; 833*3e83a9c4SRobert Marko max-link-speed = <3>; 834e8a7fdc5SSivaprakash Murugesan #address-cells = <3>; 835e8a7fdc5SSivaprakash Murugesan #size-cells = <2>; 83641dac73eSVaradarajan Narayanan 837e8a7fdc5SSivaprakash Murugesan phys = <&pcie_phy0>; 838e8a7fdc5SSivaprakash Murugesan phy-names = "pciephy"; 83941dac73eSVaradarajan Narayanan 840e8a7fdc5SSivaprakash Murugesan ranges = <0x81000000 0 0x20200000 0x20200000 841*3e83a9c4SRobert Marko 0 0x10000>, /* downstream I/O */ 842*3e83a9c4SRobert Marko <0x82000000 0 0x20220000 0x20220000 843*3e83a9c4SRobert Marko 0 0xfde0000>; /* non-prefetchable memory */ 84441dac73eSVaradarajan Narayanan 845e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 846e8a7fdc5SSivaprakash Murugesan interrupt-names = "msi"; 847e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <1>; 848e8a7fdc5SSivaprakash Murugesan interrupt-map-mask = <0 0 0 0x7>; 849e8a7fdc5SSivaprakash Murugesan interrupt-map = <0 0 0 1 &intc 0 75 850e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 851e8a7fdc5SSivaprakash Murugesan <0 0 0 2 &intc 0 78 852e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 853e8a7fdc5SSivaprakash Murugesan <0 0 0 3 &intc 0 79 854e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 855e8a7fdc5SSivaprakash Murugesan <0 0 0 4 &intc 0 83 856e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 85741dac73eSVaradarajan Narayanan 858e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 859e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_M_CLK>, 860e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_S_CLK>, 861*3e83a9c4SRobert Marko <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 862*3e83a9c4SRobert Marko <&gcc GCC_PCIE0_RCHNG_CLK>; 863e8a7fdc5SSivaprakash Murugesan clock-names = "iface", 864e8a7fdc5SSivaprakash Murugesan "axi_m", 865e8a7fdc5SSivaprakash Murugesan "axi_s", 866*3e83a9c4SRobert Marko "axi_bridge", 867*3e83a9c4SRobert Marko "rchng"; 868*3e83a9c4SRobert Marko 869e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PIPE_ARES>, 870e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_SLEEP_ARES>, 871e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 872e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 873e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 874e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_ARES>, 875*3e83a9c4SRobert Marko <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 876*3e83a9c4SRobert Marko <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 877e8a7fdc5SSivaprakash Murugesan reset-names = "pipe", 878e8a7fdc5SSivaprakash Murugesan "sleep", 879e8a7fdc5SSivaprakash Murugesan "sticky", 880e8a7fdc5SSivaprakash Murugesan "axi_m", 881e8a7fdc5SSivaprakash Murugesan "axi_s", 882e8a7fdc5SSivaprakash Murugesan "ahb", 883*3e83a9c4SRobert Marko "axi_m_sticky", 884*3e83a9c4SRobert Marko "axi_s_sticky"; 885e8a7fdc5SSivaprakash Murugesan status = "disabled"; 88641dac73eSVaradarajan Narayanan }; 88741dac73eSVaradarajan Narayanan }; 8887d9c1da9SRobert Marko 8897d9c1da9SRobert Marko timer { 8907d9c1da9SRobert Marko compatible = "arm,armv8-timer"; 8917d9c1da9SRobert Marko interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 8927d9c1da9SRobert Marko <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 8937d9c1da9SRobert Marko <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 8947d9c1da9SRobert Marko <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 8957d9c1da9SRobert Marko }; 896887ac089SRobert Marko 897887ac089SRobert Marko thermal-zones { 898887ac089SRobert Marko nss-top-thermal { 899887ac089SRobert Marko polling-delay-passive = <250>; 900887ac089SRobert Marko polling-delay = <1000>; 901887ac089SRobert Marko 902887ac089SRobert Marko thermal-sensors = <&tsens 4>; 903887ac089SRobert Marko }; 904887ac089SRobert Marko 905887ac089SRobert Marko nss0-thermal { 906887ac089SRobert Marko polling-delay-passive = <250>; 907887ac089SRobert Marko polling-delay = <1000>; 908887ac089SRobert Marko 909887ac089SRobert Marko thermal-sensors = <&tsens 5>; 910887ac089SRobert Marko }; 911887ac089SRobert Marko 912887ac089SRobert Marko nss1-thermal { 913887ac089SRobert Marko polling-delay-passive = <250>; 914887ac089SRobert Marko polling-delay = <1000>; 915887ac089SRobert Marko 916887ac089SRobert Marko thermal-sensors = <&tsens 6>; 917887ac089SRobert Marko }; 918887ac089SRobert Marko 919887ac089SRobert Marko wcss-phya0-thermal { 920887ac089SRobert Marko polling-delay-passive = <250>; 921887ac089SRobert Marko polling-delay = <1000>; 922887ac089SRobert Marko 923887ac089SRobert Marko thermal-sensors = <&tsens 7>; 924887ac089SRobert Marko }; 925887ac089SRobert Marko 926887ac089SRobert Marko wcss-phya1-thermal { 927887ac089SRobert Marko polling-delay-passive = <250>; 928887ac089SRobert Marko polling-delay = <1000>; 929887ac089SRobert Marko 930887ac089SRobert Marko thermal-sensors = <&tsens 8>; 931887ac089SRobert Marko }; 932887ac089SRobert Marko 933887ac089SRobert Marko cpu0_thermal: cpu0-thermal { 934887ac089SRobert Marko polling-delay-passive = <250>; 935887ac089SRobert Marko polling-delay = <1000>; 936887ac089SRobert Marko 937887ac089SRobert Marko thermal-sensors = <&tsens 9>; 938887ac089SRobert Marko }; 939887ac089SRobert Marko 940887ac089SRobert Marko cpu1_thermal: cpu1-thermal { 941887ac089SRobert Marko polling-delay-passive = <250>; 942887ac089SRobert Marko polling-delay = <1000>; 943887ac089SRobert Marko 944887ac089SRobert Marko thermal-sensors = <&tsens 10>; 945887ac089SRobert Marko }; 946887ac089SRobert Marko 947887ac089SRobert Marko cpu2_thermal: cpu2-thermal { 948887ac089SRobert Marko polling-delay-passive = <250>; 949887ac089SRobert Marko polling-delay = <1000>; 950887ac089SRobert Marko 951887ac089SRobert Marko thermal-sensors = <&tsens 11>; 952887ac089SRobert Marko }; 953887ac089SRobert Marko 954887ac089SRobert Marko cpu3_thermal: cpu3-thermal { 955887ac089SRobert Marko polling-delay-passive = <250>; 956887ac089SRobert Marko polling-delay = <1000>; 957887ac089SRobert Marko 958887ac089SRobert Marko thermal-sensors = <&tsens 12>; 959887ac089SRobert Marko }; 960887ac089SRobert Marko 961887ac089SRobert Marko cluster_thermal: cluster-thermal { 962887ac089SRobert Marko polling-delay-passive = <250>; 963887ac089SRobert Marko polling-delay = <1000>; 964887ac089SRobert Marko 965887ac089SRobert Marko thermal-sensors = <&tsens 13>; 966887ac089SRobert Marko }; 967887ac089SRobert Marko 968887ac089SRobert Marko wcss-phyb0-thermal { 969887ac089SRobert Marko polling-delay-passive = <250>; 970887ac089SRobert Marko polling-delay = <1000>; 971887ac089SRobert Marko 972887ac089SRobert Marko thermal-sensors = <&tsens 14>; 973887ac089SRobert Marko }; 974887ac089SRobert Marko 975887ac089SRobert Marko wcss-phyb1-thermal { 976887ac089SRobert Marko polling-delay-passive = <250>; 977887ac089SRobert Marko polling-delay = <1000>; 978887ac089SRobert Marko 979887ac089SRobert Marko thermal-sensors = <&tsens 15>; 980887ac089SRobert Marko }; 981887ac089SRobert Marko }; 98241dac73eSVaradarajan Narayanan}; 983