197fb5e8dSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 241dac73eSVaradarajan Narayanan/* 341dac73eSVaradarajan Narayanan * Copyright (c) 2017, The Linux Foundation. All rights reserved. 441dac73eSVaradarajan Narayanan */ 541dac73eSVaradarajan Narayanan 641dac73eSVaradarajan Narayanan#include <dt-bindings/interrupt-controller/arm-gic.h> 741dac73eSVaradarajan Narayanan#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 841dac73eSVaradarajan Narayanan 941dac73eSVaradarajan Narayanan/ { 10f3266045SRobert Marko #address-cells = <2>; 11f3266045SRobert Marko #size-cells = <2>; 12f3266045SRobert Marko 1341dac73eSVaradarajan Narayanan model = "Qualcomm Technologies, Inc. IPQ8074"; 1441dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074"; 15b97e6ffaSRobert Marko interrupt-parent = <&intc>; 1641dac73eSVaradarajan Narayanan 17e8a7fdc5SSivaprakash Murugesan clocks { 18e8a7fdc5SSivaprakash Murugesan sleep_clk: sleep_clk { 19e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 20f607dd76SKathiravan T clock-frequency = <32768>; 21e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 22e8a7fdc5SSivaprakash Murugesan }; 23e8a7fdc5SSivaprakash Murugesan 24e8a7fdc5SSivaprakash Murugesan xo: xo { 25e8a7fdc5SSivaprakash Murugesan compatible = "fixed-clock"; 26e8a7fdc5SSivaprakash Murugesan clock-frequency = <19200000>; 27e8a7fdc5SSivaprakash Murugesan #clock-cells = <0>; 28e8a7fdc5SSivaprakash Murugesan }; 29e8a7fdc5SSivaprakash Murugesan }; 30e8a7fdc5SSivaprakash Murugesan 31e8a7fdc5SSivaprakash Murugesan cpus { 32674631c3SAndrew Halaney #address-cells = <1>; 33674631c3SAndrew Halaney #size-cells = <0>; 34e8a7fdc5SSivaprakash Murugesan 35e8a7fdc5SSivaprakash Murugesan CPU0: cpu@0 { 36e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 37e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 38e8a7fdc5SSivaprakash Murugesan reg = <0x0>; 39e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 40e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 41e8a7fdc5SSivaprakash Murugesan }; 42e8a7fdc5SSivaprakash Murugesan 43e8a7fdc5SSivaprakash Murugesan CPU1: cpu@1 { 44e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 45e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 46e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 47e8a7fdc5SSivaprakash Murugesan reg = <0x1>; 48e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 49e8a7fdc5SSivaprakash Murugesan }; 50e8a7fdc5SSivaprakash Murugesan 51e8a7fdc5SSivaprakash Murugesan CPU2: cpu@2 { 52e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 53e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 54e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 55e8a7fdc5SSivaprakash Murugesan reg = <0x2>; 56e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 57e8a7fdc5SSivaprakash Murugesan }; 58e8a7fdc5SSivaprakash Murugesan 59e8a7fdc5SSivaprakash Murugesan CPU3: cpu@3 { 60e8a7fdc5SSivaprakash Murugesan device_type = "cpu"; 61e8a7fdc5SSivaprakash Murugesan compatible = "arm,cortex-a53"; 62e8a7fdc5SSivaprakash Murugesan enable-method = "psci"; 63e8a7fdc5SSivaprakash Murugesan reg = <0x3>; 64e8a7fdc5SSivaprakash Murugesan next-level-cache = <&L2_0>; 65e8a7fdc5SSivaprakash Murugesan }; 66e8a7fdc5SSivaprakash Murugesan 67e8a7fdc5SSivaprakash Murugesan L2_0: l2-cache { 68e8a7fdc5SSivaprakash Murugesan compatible = "cache"; 69e8a7fdc5SSivaprakash Murugesan cache-level = <0x2>; 70e8a7fdc5SSivaprakash Murugesan }; 71e8a7fdc5SSivaprakash Murugesan }; 72e8a7fdc5SSivaprakash Murugesan 73e8a7fdc5SSivaprakash Murugesan pmu { 74292b1874SKathiravan T compatible = "arm,cortex-a53-pmu"; 75e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 76e8a7fdc5SSivaprakash Murugesan }; 77e8a7fdc5SSivaprakash Murugesan 78e8a7fdc5SSivaprakash Murugesan psci { 79e8a7fdc5SSivaprakash Murugesan compatible = "arm,psci-1.0"; 80e8a7fdc5SSivaprakash Murugesan method = "smc"; 81e8a7fdc5SSivaprakash Murugesan }; 82e8a7fdc5SSivaprakash Murugesan 8342124b94SRobert Marko reserved-memory { 8442124b94SRobert Marko #address-cells = <2>; 8542124b94SRobert Marko #size-cells = <2>; 8642124b94SRobert Marko ranges; 8742124b94SRobert Marko 88*0cd4e90cSVignesh Viswanathan bootloader@4a600000 { 89*0cd4e90cSVignesh Viswanathan reg = <0x0 0x4a600000 0x0 0x400000>; 90*0cd4e90cSVignesh Viswanathan no-map; 91*0cd4e90cSVignesh Viswanathan }; 92*0cd4e90cSVignesh Viswanathan 93*0cd4e90cSVignesh Viswanathan sbl@4aa00000 { 94*0cd4e90cSVignesh Viswanathan reg = <0x0 0x4aa00000 0x0 0x100000>; 95*0cd4e90cSVignesh Viswanathan no-map; 96*0cd4e90cSVignesh Viswanathan }; 97*0cd4e90cSVignesh Viswanathan 9842124b94SRobert Marko smem@4ab00000 { 9942124b94SRobert Marko compatible = "qcom,smem"; 100*0cd4e90cSVignesh Viswanathan reg = <0x0 0x4ab00000 0x0 0x100000>; 10142124b94SRobert Marko no-map; 10242124b94SRobert Marko 10342124b94SRobert Marko hwlocks = <&tcsr_mutex 0>; 10442124b94SRobert Marko }; 105e4a4fdcfSKathiravan T 106e4a4fdcfSKathiravan T memory@4ac00000 { 107*0cd4e90cSVignesh Viswanathan reg = <0x0 0x4ac00000 0x0 0x400000>; 108e4a4fdcfSKathiravan T no-map; 109e4a4fdcfSKathiravan T }; 11042124b94SRobert Marko }; 11142124b94SRobert Marko 1126df9102fSGokul Sriram Palanisamy firmware { 1136df9102fSGokul Sriram Palanisamy scm { 1146df9102fSGokul Sriram Palanisamy compatible = "qcom,scm-ipq8074", "qcom,scm"; 1159b2406aaSVignesh Viswanathan qcom,dload-mode = <&tcsr 0x6100>; 1166df9102fSGokul Sriram Palanisamy }; 1176df9102fSGokul Sriram Palanisamy }; 1186df9102fSGokul Sriram Palanisamy 119da6aa111SKrzysztof Kozlowski soc: soc@0 { 120674631c3SAndrew Halaney #address-cells = <1>; 121674631c3SAndrew Halaney #size-cells = <1>; 12241dac73eSVaradarajan Narayanan ranges = <0 0 0 0xffffffff>; 12341dac73eSVaradarajan Narayanan compatible = "simple-bus"; 12441dac73eSVaradarajan Narayanan 1255e09bc51SSivaprakash Murugesan ssphy_1: phy@58000 { 1265e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1275e09bc51SSivaprakash Murugesan reg = <0x00058000 0x1c4>; 1285e09bc51SSivaprakash Murugesan #address-cells = <1>; 1295e09bc51SSivaprakash Murugesan #size-cells = <1>; 1305e09bc51SSivaprakash Murugesan ranges; 1315e09bc51SSivaprakash Murugesan 1325e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_AUX_CLK>, 1335e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1345e09bc51SSivaprakash Murugesan <&xo>; 1355e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1365e09bc51SSivaprakash Murugesan 1375e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_PHY_BCR>, 1385e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_1_PHY_BCR>; 1395e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1405e09bc51SSivaprakash Murugesan status = "disabled"; 1415e09bc51SSivaprakash Murugesan 1421351512fSShawn Guo usb1_ssphy: phy@58200 { 1435e09bc51SSivaprakash Murugesan reg = <0x00058200 0x130>, /* Tx */ 1445e09bc51SSivaprakash Murugesan <0x00058400 0x200>, /* Rx */ 1455e09bc51SSivaprakash Murugesan <0x00058800 0x1f8>, /* PCS */ 1465e09bc51SSivaprakash Murugesan <0x00058600 0x044>; /* PCS misc */ 1475e09bc51SSivaprakash Murugesan #phy-cells = <0>; 148de9e7f77SJohan Hovold #clock-cells = <0>; 1495e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PIPE_CLK>; 1505e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 151877cff35SRobert Marko clock-output-names = "usb3phy_1_cc_pipe_clk"; 1525e09bc51SSivaprakash Murugesan }; 1535e09bc51SSivaprakash Murugesan }; 1545e09bc51SSivaprakash Murugesan 1555e09bc51SSivaprakash Murugesan qusb_phy_1: phy@59000 { 1565e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 1575e09bc51SSivaprakash Murugesan reg = <0x00059000 0x180>; 1585e09bc51SSivaprakash Murugesan #phy-cells = <0>; 1595e09bc51SSivaprakash Murugesan 1605e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 1615e09bc51SSivaprakash Murugesan <&xo>; 1625e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 1635e09bc51SSivaprakash Murugesan 1645e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 1655e09bc51SSivaprakash Murugesan status = "disabled"; 1665e09bc51SSivaprakash Murugesan }; 1675e09bc51SSivaprakash Murugesan 1685e09bc51SSivaprakash Murugesan ssphy_0: phy@78000 { 1695e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-usb3-phy"; 1705e09bc51SSivaprakash Murugesan reg = <0x00078000 0x1c4>; 1715e09bc51SSivaprakash Murugesan #address-cells = <1>; 1725e09bc51SSivaprakash Murugesan #size-cells = <1>; 1735e09bc51SSivaprakash Murugesan ranges; 1745e09bc51SSivaprakash Murugesan 1755e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_AUX_CLK>, 1765e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 1775e09bc51SSivaprakash Murugesan <&xo>; 1785e09bc51SSivaprakash Murugesan clock-names = "aux", "cfg_ahb", "ref"; 1795e09bc51SSivaprakash Murugesan 1805e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_PHY_BCR>, 1815e09bc51SSivaprakash Murugesan <&gcc GCC_USB3PHY_0_PHY_BCR>; 1825e09bc51SSivaprakash Murugesan reset-names = "phy","common"; 1835e09bc51SSivaprakash Murugesan status = "disabled"; 1845e09bc51SSivaprakash Murugesan 1851351512fSShawn Guo usb0_ssphy: phy@78200 { 1865e09bc51SSivaprakash Murugesan reg = <0x00078200 0x130>, /* Tx */ 1875e09bc51SSivaprakash Murugesan <0x00078400 0x200>, /* Rx */ 1885e09bc51SSivaprakash Murugesan <0x00078800 0x1f8>, /* PCS */ 1895e09bc51SSivaprakash Murugesan <0x00078600 0x044>; /* PCS misc */ 1905e09bc51SSivaprakash Murugesan #phy-cells = <0>; 191de9e7f77SJohan Hovold #clock-cells = <0>; 1925e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PIPE_CLK>; 1935e09bc51SSivaprakash Murugesan clock-names = "pipe0"; 194877cff35SRobert Marko clock-output-names = "usb3phy_0_cc_pipe_clk"; 1955e09bc51SSivaprakash Murugesan }; 1965e09bc51SSivaprakash Murugesan }; 1975e09bc51SSivaprakash Murugesan 1985e09bc51SSivaprakash Murugesan qusb_phy_0: phy@79000 { 1995e09bc51SSivaprakash Murugesan compatible = "qcom,ipq8074-qusb2-phy"; 2005e09bc51SSivaprakash Murugesan reg = <0x00079000 0x180>; 2015e09bc51SSivaprakash Murugesan #phy-cells = <0>; 2025e09bc51SSivaprakash Murugesan 2035e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 2045e09bc51SSivaprakash Murugesan <&xo>; 2055e09bc51SSivaprakash Murugesan clock-names = "cfg_ahb", "ref"; 2065e09bc51SSivaprakash Murugesan 2075e09bc51SSivaprakash Murugesan resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 20858b2785dSRobert Marko status = "disabled"; 2095e09bc51SSivaprakash Murugesan }; 2105e09bc51SSivaprakash Murugesan 2117ba33591SRobert Marko pcie_qmp0: phy@84000 { 2127ba33591SRobert Marko compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 2137ba33591SRobert Marko reg = <0x00084000 0x1bc>; 214942bcd33SShawn Guo #address-cells = <1>; 215942bcd33SShawn Guo #size-cells = <1>; 216942bcd33SShawn Guo ranges; 217e8a7fdc5SSivaprakash Murugesan 218942bcd33SShawn Guo clocks = <&gcc GCC_PCIE0_AUX_CLK>, 219942bcd33SShawn Guo <&gcc GCC_PCIE0_AHB_CLK>; 220942bcd33SShawn Guo clock-names = "aux", "cfg_ahb"; 221e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PHY_BCR>, 222e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0PHY_PHY_BCR>; 223e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 224e8a7fdc5SSivaprakash Murugesan "common"; 225e8a7fdc5SSivaprakash Murugesan status = "disabled"; 226942bcd33SShawn Guo 2277ba33591SRobert Marko pcie_phy0: phy@84200 { 2287ba33591SRobert Marko reg = <0x84200 0x16c>, 2297ba33591SRobert Marko <0x84400 0x200>, 2307ba33591SRobert Marko <0x84800 0x1f0>, 2317ba33591SRobert Marko <0x84c00 0xf4>; 232942bcd33SShawn Guo #phy-cells = <0>; 233942bcd33SShawn Guo #clock-cells = <0>; 234942bcd33SShawn Guo clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 235942bcd33SShawn Guo clock-names = "pipe0"; 2360e8b90c0SRobert Marko clock-output-names = "pcie20_phy0_pipe_clk"; 237942bcd33SShawn Guo }; 238e8a7fdc5SSivaprakash Murugesan }; 239e8a7fdc5SSivaprakash Murugesan 240942bcd33SShawn Guo pcie_qmp1: phy@8e000 { 241e8a7fdc5SSivaprakash Murugesan compatible = "qcom,ipq8074-qmp-pcie-phy"; 242ed22cc93SJohan Hovold reg = <0x0008e000 0x1c4>; 243942bcd33SShawn Guo #address-cells = <1>; 244942bcd33SShawn Guo #size-cells = <1>; 245942bcd33SShawn Guo ranges; 246e8a7fdc5SSivaprakash Murugesan 247942bcd33SShawn Guo clocks = <&gcc GCC_PCIE1_AUX_CLK>, 248942bcd33SShawn Guo <&gcc GCC_PCIE1_AHB_CLK>; 249942bcd33SShawn Guo clock-names = "aux", "cfg_ahb"; 250e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE1_PHY_BCR>, 251e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE1PHY_PHY_BCR>; 252e8a7fdc5SSivaprakash Murugesan reset-names = "phy", 253e8a7fdc5SSivaprakash Murugesan "common"; 254e8a7fdc5SSivaprakash Murugesan status = "disabled"; 255942bcd33SShawn Guo 256942bcd33SShawn Guo pcie_phy1: phy@8e200 { 257100d9c94SRobert Marko reg = <0x8e200 0x130>, 258942bcd33SShawn Guo <0x8e400 0x200>, 259100d9c94SRobert Marko <0x8e800 0x1f8>; 260942bcd33SShawn Guo #phy-cells = <0>; 261942bcd33SShawn Guo #clock-cells = <0>; 262942bcd33SShawn Guo clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 263942bcd33SShawn Guo clock-names = "pipe0"; 2640e8b90c0SRobert Marko clock-output-names = "pcie20_phy1_pipe_clk"; 265942bcd33SShawn Guo }; 266e8a7fdc5SSivaprakash Murugesan }; 267e8a7fdc5SSivaprakash Murugesan 268d201f677SRobert Marko mdio: mdio@90000 { 26936e830a5SRobert Marko compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 270d201f677SRobert Marko reg = <0x00090000 0x64>; 271d201f677SRobert Marko #address-cells = <1>; 272d201f677SRobert Marko #size-cells = <0>; 273d201f677SRobert Marko 274d201f677SRobert Marko clocks = <&gcc GCC_MDIO_AHB_CLK>; 275d201f677SRobert Marko clock-names = "gcc_mdio_ahb_clk"; 276d201f677SRobert Marko 277d201f677SRobert Marko status = "disabled"; 278d201f677SRobert Marko }; 279d201f677SRobert Marko 280a1ab3827SRobert Marko qfprom: efuse@a4000 { 281a1ab3827SRobert Marko compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 282a1ab3827SRobert Marko reg = <0x000a4000 0x2000>; 283a1ab3827SRobert Marko #address-cells = <1>; 284a1ab3827SRobert Marko #size-cells = <1>; 285a1ab3827SRobert Marko }; 286a1ab3827SRobert Marko 287f26f6a5eSRobert Marko prng: rng@e3000 { 288f26f6a5eSRobert Marko compatible = "qcom,prng-ee"; 289f26f6a5eSRobert Marko reg = <0x000e3000 0x1000>; 290f26f6a5eSRobert Marko clocks = <&gcc GCC_PRNG_AHB_CLK>; 291f26f6a5eSRobert Marko clock-names = "core"; 292f26f6a5eSRobert Marko status = "disabled"; 293f26f6a5eSRobert Marko }; 294f26f6a5eSRobert Marko 295887ac089SRobert Marko tsens: thermal-sensor@4a9000 { 296887ac089SRobert Marko compatible = "qcom,ipq8074-tsens"; 297887ac089SRobert Marko reg = <0x4a9000 0x1000>, /* TM */ 298887ac089SRobert Marko <0x4a8000 0x1000>; /* SROT */ 299887ac089SRobert Marko interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 300887ac089SRobert Marko interrupt-names = "combined"; 301887ac089SRobert Marko #qcom,sensors = <16>; 302887ac089SRobert Marko #thermal-sensor-cells = <1>; 303887ac089SRobert Marko }; 304887ac089SRobert Marko 305bbef0142SShawn Guo cryptobam: dma-controller@704000 { 306f9e2df82SRobert Marko compatible = "qcom,bam-v1.7.0"; 307f9e2df82SRobert Marko reg = <0x00704000 0x20000>; 308f9e2df82SRobert Marko interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 309f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 310f9e2df82SRobert Marko clock-names = "bam_clk"; 311f9e2df82SRobert Marko #dma-cells = <1>; 312f9e2df82SRobert Marko qcom,ee = <1>; 3138c97f0acSShawn Guo qcom,controlled-remotely; 314f9e2df82SRobert Marko status = "disabled"; 315f9e2df82SRobert Marko }; 316f9e2df82SRobert Marko 317f9e2df82SRobert Marko crypto: crypto@73a000 { 318f9e2df82SRobert Marko compatible = "qcom,crypto-v5.1"; 319f9e2df82SRobert Marko reg = <0x0073a000 0x6000>; 320f9e2df82SRobert Marko clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 321f9e2df82SRobert Marko <&gcc GCC_CRYPTO_AXI_CLK>, 322f9e2df82SRobert Marko <&gcc GCC_CRYPTO_CLK>; 323f9e2df82SRobert Marko clock-names = "iface", "bus", "core"; 324f9e2df82SRobert Marko dmas = <&cryptobam 2>, <&cryptobam 3>; 325f9e2df82SRobert Marko dma-names = "rx", "tx"; 326f9e2df82SRobert Marko status = "disabled"; 327f9e2df82SRobert Marko }; 328f9e2df82SRobert Marko 32933057e16SSricharan R tlmm: pinctrl@1000000 { 33041dac73eSVaradarajan Narayanan compatible = "qcom,ipq8074-pinctrl"; 331e8a7fdc5SSivaprakash Murugesan reg = <0x01000000 0x300000>; 33241dac73eSVaradarajan Narayanan interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 33341dac73eSVaradarajan Narayanan gpio-controller; 334297177a4SChristian Lamparter gpio-ranges = <&tlmm 0 0 70>; 335674631c3SAndrew Halaney #gpio-cells = <2>; 33641dac73eSVaradarajan Narayanan interrupt-controller; 337674631c3SAndrew Halaney #interrupt-cells = <2>; 33822592a22SSricharan R 3391c3c31a6SKrzysztof Kozlowski serial_4_pins: serial4-state { 34022592a22SSricharan R pins = "gpio23", "gpio24"; 34122592a22SSricharan R function = "blsp4_uart1"; 34222592a22SSricharan R drive-strength = <8>; 34322592a22SSricharan R bias-disable; 34422592a22SSricharan R }; 34522592a22SSricharan R 3461c3c31a6SKrzysztof Kozlowski i2c_0_pins: i2c-0-state { 34722592a22SSricharan R pins = "gpio42", "gpio43"; 34822592a22SSricharan R function = "blsp1_i2c"; 34922592a22SSricharan R drive-strength = <8>; 35022592a22SSricharan R bias-disable; 35122592a22SSricharan R }; 35222592a22SSricharan R 3531c3c31a6SKrzysztof Kozlowski spi_0_pins: spi-0-state { 35422592a22SSricharan R pins = "gpio38", "gpio39", "gpio40", "gpio41"; 35522592a22SSricharan R function = "blsp0_spi"; 35622592a22SSricharan R drive-strength = <8>; 35722592a22SSricharan R bias-disable; 35822592a22SSricharan R }; 35922592a22SSricharan R 3601c3c31a6SKrzysztof Kozlowski hsuart_pins: hsuart-state { 36122592a22SSricharan R pins = "gpio46", "gpio47", "gpio48", "gpio49"; 36222592a22SSricharan R function = "blsp2_uart"; 36322592a22SSricharan R drive-strength = <8>; 36422592a22SSricharan R bias-disable; 36522592a22SSricharan R }; 36622592a22SSricharan R 3671c3c31a6SKrzysztof Kozlowski qpic_pins: qpic-state { 36822592a22SSricharan R pins = "gpio1", "gpio3", "gpio4", 36922592a22SSricharan R "gpio5", "gpio6", "gpio7", 37022592a22SSricharan R "gpio8", "gpio10", "gpio11", 37122592a22SSricharan R "gpio12", "gpio13", "gpio14", 37222592a22SSricharan R "gpio15", "gpio16", "gpio17"; 37322592a22SSricharan R function = "qpic"; 37422592a22SSricharan R drive-strength = <8>; 37522592a22SSricharan R bias-disable; 37622592a22SSricharan R }; 37741dac73eSVaradarajan Narayanan }; 37841dac73eSVaradarajan Narayanan 37941dac73eSVaradarajan Narayanan gcc: gcc@1800000 { 38041dac73eSVaradarajan Narayanan compatible = "qcom,gcc-ipq8074"; 381e8a7fdc5SSivaprakash Murugesan reg = <0x01800000 0x80000>; 3823aa0b8cdSRobert Marko clocks = <&xo>, <&sleep_clk>; 3833aa0b8cdSRobert Marko clock-names = "xo", "sleep_clk"; 3843aa0b8cdSRobert Marko #clock-cells = <1>; 3858bbda511SRobert Marko #power-domain-cells = <1>; 3863aa0b8cdSRobert Marko #reset-cells = <1>; 38741dac73eSVaradarajan Narayanan }; 38841dac73eSVaradarajan Narayanan 38942124b94SRobert Marko tcsr_mutex: hwlock@1905000 { 39042124b94SRobert Marko compatible = "qcom,tcsr-mutex"; 39142124b94SRobert Marko reg = <0x01905000 0x20000>; 39242124b94SRobert Marko #hwlock-cells = <1>; 39342124b94SRobert Marko }; 39442124b94SRobert Marko 3959b2406aaSVignesh Viswanathan tcsr: syscon@1937000 { 3969b2406aaSVignesh Viswanathan compatible = "qcom,tcsr-ipq8074", "syscon"; 3979b2406aaSVignesh Viswanathan reg = <0x01937000 0x21000>; 3989b2406aaSVignesh Viswanathan }; 3999b2406aaSVignesh Viswanathan 40063750607SRobert Marko spmi_bus: spmi@200f000 { 40163750607SRobert Marko compatible = "qcom,spmi-pmic-arb"; 40263750607SRobert Marko reg = <0x0200f000 0x001000>, 40363750607SRobert Marko <0x02400000 0x800000>, 40463750607SRobert Marko <0x02c00000 0x800000>, 40563750607SRobert Marko <0x03800000 0x200000>, 40663750607SRobert Marko <0x0200a000 0x000700>; 40763750607SRobert Marko reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 40863750607SRobert Marko interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 40963750607SRobert Marko interrupt-names = "periph_irq"; 41063750607SRobert Marko qcom,ee = <0>; 41163750607SRobert Marko qcom,channel = <0>; 41263750607SRobert Marko #address-cells = <2>; 41363750607SRobert Marko #size-cells = <0>; 41463750607SRobert Marko interrupt-controller; 41563750607SRobert Marko #interrupt-cells = <4>; 41663750607SRobert Marko }; 41763750607SRobert Marko 41896bb736fSBhupesh Sharma sdhc_1: mmc@7824900 { 419cbc142c8SSivaprakash Murugesan compatible = "qcom,sdhci-msm-v4"; 420cbc142c8SSivaprakash Murugesan reg = <0x7824900 0x500>, <0x7824000 0x800>; 421eddc917dSKrzysztof Kozlowski reg-names = "hc", "core"; 422cbc142c8SSivaprakash Murugesan 423cbc142c8SSivaprakash Murugesan interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 424cbc142c8SSivaprakash Murugesan <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 425cbc142c8SSivaprakash Murugesan interrupt-names = "hc_irq", "pwr_irq"; 426cbc142c8SSivaprakash Murugesan 4274ff12270SBhupesh Sharma clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4284ff12270SBhupesh Sharma <&gcc GCC_SDCC1_APPS_CLK>, 4294ff12270SBhupesh Sharma <&xo>; 4304ff12270SBhupesh Sharma clock-names = "iface", "core", "xo"; 431730d55d8SRobert Marko resets = <&gcc GCC_SDCC1_BCR>; 432cbc142c8SSivaprakash Murugesan max-frequency = <384000000>; 433cbc142c8SSivaprakash Murugesan mmc-ddr-1_8v; 434cbc142c8SSivaprakash Murugesan mmc-hs200-1_8v; 435cbc142c8SSivaprakash Murugesan mmc-hs400-1_8v; 436cbc142c8SSivaprakash Murugesan bus-width = <8>; 437cbc142c8SSivaprakash Murugesan 438cbc142c8SSivaprakash Murugesan status = "disabled"; 439cbc142c8SSivaprakash Murugesan }; 440cbc142c8SSivaprakash Murugesan 441b7fbf46cSVinod Koul blsp_dma: dma-controller@7884000 { 44222592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 443e8a7fdc5SSivaprakash Murugesan reg = <0x07884000 0x2b000>; 44422592a22SSricharan R interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 44522592a22SSricharan R clocks = <&gcc GCC_BLSP1_AHB_CLK>; 44622592a22SSricharan R clock-names = "bam_clk"; 44722592a22SSricharan R #dma-cells = <1>; 44822592a22SSricharan R qcom,ee = <0>; 44922592a22SSricharan R }; 45022592a22SSricharan R 45122592a22SSricharan R blsp1_uart1: serial@78af000 { 45222592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 453e8a7fdc5SSivaprakash Murugesan reg = <0x078af000 0x200>; 45422592a22SSricharan R interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 45522592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 45622592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 45722592a22SSricharan R clock-names = "core", "iface"; 45822592a22SSricharan R status = "disabled"; 45922592a22SSricharan R }; 46022592a22SSricharan R 46122592a22SSricharan R blsp1_uart3: serial@78b1000 { 46222592a22SSricharan R compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 463e8a7fdc5SSivaprakash Murugesan reg = <0x078b1000 0x200>; 46422592a22SSricharan R interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 46522592a22SSricharan R clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 46622592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 46722592a22SSricharan R clock-names = "core", "iface"; 46822592a22SSricharan R dmas = <&blsp_dma 4>, 46922592a22SSricharan R <&blsp_dma 5>; 47022592a22SSricharan R dma-names = "tx", "rx"; 47122592a22SSricharan R pinctrl-0 = <&hsuart_pins>; 47222592a22SSricharan R pinctrl-names = "default"; 47322592a22SSricharan R status = "disabled"; 47422592a22SSricharan R }; 47522592a22SSricharan R 476e8a7fdc5SSivaprakash Murugesan blsp1_uart5: serial@78b3000 { 477e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 478e8a7fdc5SSivaprakash Murugesan reg = <0x078b3000 0x200>; 479e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 480e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 481e8a7fdc5SSivaprakash Murugesan <&gcc GCC_BLSP1_AHB_CLK>; 482e8a7fdc5SSivaprakash Murugesan clock-names = "core", "iface"; 483e8a7fdc5SSivaprakash Murugesan pinctrl-0 = <&serial_4_pins>; 484e8a7fdc5SSivaprakash Murugesan pinctrl-names = "default"; 485e8a7fdc5SSivaprakash Murugesan status = "disabled"; 486e8a7fdc5SSivaprakash Murugesan }; 487e8a7fdc5SSivaprakash Murugesan 48822592a22SSricharan R blsp1_spi1: spi@78b5000 { 48922592a22SSricharan R compatible = "qcom,spi-qup-v2.2.1"; 49022592a22SSricharan R #address-cells = <1>; 49122592a22SSricharan R #size-cells = <0>; 492e8a7fdc5SSivaprakash Murugesan reg = <0x078b5000 0x600>; 49322592a22SSricharan R interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 49422592a22SSricharan R spi-max-frequency = <50000000>; 49522592a22SSricharan R clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 49622592a22SSricharan R <&gcc GCC_BLSP1_AHB_CLK>; 49722592a22SSricharan R clock-names = "core", "iface"; 49822592a22SSricharan R dmas = <&blsp_dma 12>, <&blsp_dma 13>; 49922592a22SSricharan R dma-names = "tx", "rx"; 50022592a22SSricharan R pinctrl-0 = <&spi_0_pins>; 50122592a22SSricharan R pinctrl-names = "default"; 50222592a22SSricharan R status = "disabled"; 50322592a22SSricharan R }; 50422592a22SSricharan R 50522592a22SSricharan R blsp1_i2c2: i2c@78b6000 { 50622592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 50722592a22SSricharan R #address-cells = <1>; 50822592a22SSricharan R #size-cells = <0>; 509e8a7fdc5SSivaprakash Murugesan reg = <0x078b6000 0x600>; 51022592a22SSricharan R interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 5112374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 5122374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 5132374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 51422592a22SSricharan R clock-frequency = <400000>; 5150e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 14>, <&blsp_dma 15>; 5160e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 51722592a22SSricharan R pinctrl-0 = <&i2c_0_pins>; 51822592a22SSricharan R pinctrl-names = "default"; 51922592a22SSricharan R status = "disabled"; 52022592a22SSricharan R }; 52122592a22SSricharan R 52222592a22SSricharan R blsp1_i2c3: i2c@78b7000 { 52322592a22SSricharan R compatible = "qcom,i2c-qup-v2.2.1"; 52422592a22SSricharan R #address-cells = <1>; 52522592a22SSricharan R #size-cells = <0>; 526e8a7fdc5SSivaprakash Murugesan reg = <0x078b7000 0x600>; 52722592a22SSricharan R interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 5282374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 5292374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 5302374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 53122592a22SSricharan R clock-frequency = <100000>; 5320e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 16>, <&blsp_dma 17>; 5330e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 53422592a22SSricharan R status = "disabled"; 53522592a22SSricharan R }; 53622592a22SSricharan R 5379c0bd8e5SChukun Pan blsp1_i2c5: i2c@78b9000 { 5389c0bd8e5SChukun Pan compatible = "qcom,i2c-qup-v2.2.1"; 5399c0bd8e5SChukun Pan #address-cells = <1>; 5409c0bd8e5SChukun Pan #size-cells = <0>; 5419c0bd8e5SChukun Pan reg = <0x78b9000 0x600>; 5429c0bd8e5SChukun Pan interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 5432374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 5442374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 5452374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 5469c0bd8e5SChukun Pan clock-frequency = <400000>; 5470e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 20>, <&blsp_dma 21>; 5480e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 5499c0bd8e5SChukun Pan status = "disabled"; 5509c0bd8e5SChukun Pan }; 5519c0bd8e5SChukun Pan 552cb0c14daSRobert Marko blsp1_spi5: spi@78b9000 { 553cb0c14daSRobert Marko compatible = "qcom,spi-qup-v2.2.1"; 554cb0c14daSRobert Marko #address-cells = <1>; 555cb0c14daSRobert Marko #size-cells = <0>; 556cb0c14daSRobert Marko reg = <0x78b9000 0x600>; 557cb0c14daSRobert Marko interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 558cb0c14daSRobert Marko clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 559cb0c14daSRobert Marko <&gcc GCC_BLSP1_AHB_CLK>; 560cb0c14daSRobert Marko clock-names = "core", "iface"; 561cb0c14daSRobert Marko dmas = <&blsp_dma 20>, <&blsp_dma 21>; 562cb0c14daSRobert Marko dma-names = "tx", "rx"; 563cb0c14daSRobert Marko status = "disabled"; 564cb0c14daSRobert Marko }; 565cb0c14daSRobert Marko 566abe66bb7SRobert Marko blsp1_i2c6: i2c@78ba000 { 567abe66bb7SRobert Marko compatible = "qcom,i2c-qup-v2.2.1"; 568abe66bb7SRobert Marko #address-cells = <1>; 569abe66bb7SRobert Marko #size-cells = <0>; 570abe66bb7SRobert Marko reg = <0x078ba000 0x600>; 571abe66bb7SRobert Marko interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 5722374b99eSKrzysztof Kozlowski clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 5732374b99eSKrzysztof Kozlowski <&gcc GCC_BLSP1_AHB_CLK>; 5742374b99eSKrzysztof Kozlowski clock-names = "core", "iface"; 575abe66bb7SRobert Marko clock-frequency = <100000>; 5760e1b27f4SKrzysztof Kozlowski dmas = <&blsp_dma 22>, <&blsp_dma 23>; 5770e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 578abe66bb7SRobert Marko status = "disabled"; 579abe66bb7SRobert Marko }; 580abe66bb7SRobert Marko 581b7fbf46cSVinod Koul qpic_bam: dma-controller@7984000 { 58222592a22SSricharan R compatible = "qcom,bam-v1.7.0"; 583e8a7fdc5SSivaprakash Murugesan reg = <0x07984000 0x1a000>; 58422592a22SSricharan R interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 58522592a22SSricharan R clocks = <&gcc GCC_QPIC_AHB_CLK>; 58622592a22SSricharan R clock-names = "bam_clk"; 58722592a22SSricharan R #dma-cells = <1>; 58822592a22SSricharan R qcom,ee = <0>; 58922592a22SSricharan R status = "disabled"; 59022592a22SSricharan R }; 59122592a22SSricharan R 592b3996165SRobert Marko qpic_nand: nand-controller@79b0000 { 59322592a22SSricharan R compatible = "qcom,ipq8074-nand"; 594e8a7fdc5SSivaprakash Murugesan reg = <0x079b0000 0x10000>; 59522592a22SSricharan R #address-cells = <1>; 59622592a22SSricharan R #size-cells = <0>; 59722592a22SSricharan R clocks = <&gcc GCC_QPIC_CLK>, 59822592a22SSricharan R <&gcc GCC_QPIC_AHB_CLK>; 59922592a22SSricharan R clock-names = "core", "aon"; 60022592a22SSricharan R 60122592a22SSricharan R dmas = <&qpic_bam 0>, 60222592a22SSricharan R <&qpic_bam 1>, 60322592a22SSricharan R <&qpic_bam 2>; 60422592a22SSricharan R dma-names = "tx", "rx", "cmd"; 60522592a22SSricharan R pinctrl-0 = <&qpic_pins>; 60622592a22SSricharan R pinctrl-names = "default"; 60741dac73eSVaradarajan Narayanan status = "disabled"; 60841dac73eSVaradarajan Narayanan }; 60933057e16SSricharan R 6105e09bc51SSivaprakash Murugesan usb_0: usb@8af8800 { 6113a6b8bf1SKrzysztof Kozlowski compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 6125e09bc51SSivaprakash Murugesan reg = <0x08af8800 0x400>; 6135e09bc51SSivaprakash Murugesan #address-cells = <1>; 6145e09bc51SSivaprakash Murugesan #size-cells = <1>; 6155e09bc51SSivaprakash Murugesan ranges; 6165e09bc51SSivaprakash Murugesan 6175e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 6185e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 6195e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_SLEEP_CLK>, 6205e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 6218d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 6228d5fd4e4SKrzysztof Kozlowski "core", 6235e09bc51SSivaprakash Murugesan "sleep", 6245e09bc51SSivaprakash Murugesan "mock_utmi"; 6255e09bc51SSivaprakash Murugesan 6265e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 6275e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MASTER_CLK>, 6285e09bc51SSivaprakash Murugesan <&gcc GCC_USB0_MOCK_UTMI_CLK>; 6295e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 6305e09bc51SSivaprakash Murugesan <133330000>, 6315e09bc51SSivaprakash Murugesan <19200000>; 6325e09bc51SSivaprakash Murugesan 6338bbda511SRobert Marko power-domains = <&gcc USB0_GDSC>; 6348bbda511SRobert Marko 6355e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB0_BCR>; 6365e09bc51SSivaprakash Murugesan status = "disabled"; 6375e09bc51SSivaprakash Murugesan 638b77a1c4dSKrzysztof Kozlowski dwc_0: usb@8a00000 { 6395e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 6405e09bc51SSivaprakash Murugesan reg = <0x8a00000 0xcd00>; 6415e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 6425e09bc51SSivaprakash Murugesan phys = <&qusb_phy_0>, <&usb0_ssphy>; 6435e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 6445e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 6455e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 6465e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 6475e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 6485e09bc51SSivaprakash Murugesan dr_mode = "host"; 6495e09bc51SSivaprakash Murugesan }; 6505e09bc51SSivaprakash Murugesan }; 6515e09bc51SSivaprakash Murugesan 6525e09bc51SSivaprakash Murugesan usb_1: usb@8cf8800 { 6533a6b8bf1SKrzysztof Kozlowski compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 6545e09bc51SSivaprakash Murugesan reg = <0x08cf8800 0x400>; 6555e09bc51SSivaprakash Murugesan #address-cells = <1>; 6565e09bc51SSivaprakash Murugesan #size-cells = <1>; 6575e09bc51SSivaprakash Murugesan ranges; 6585e09bc51SSivaprakash Murugesan 6595e09bc51SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 6605e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 6615e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_SLEEP_CLK>, 6625e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 6638d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 6648d5fd4e4SKrzysztof Kozlowski "core", 6655e09bc51SSivaprakash Murugesan "sleep", 6665e09bc51SSivaprakash Murugesan "mock_utmi"; 6675e09bc51SSivaprakash Murugesan 6685e09bc51SSivaprakash Murugesan assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 6695e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MASTER_CLK>, 6705e09bc51SSivaprakash Murugesan <&gcc GCC_USB1_MOCK_UTMI_CLK>; 6715e09bc51SSivaprakash Murugesan assigned-clock-rates = <133330000>, 6725e09bc51SSivaprakash Murugesan <133330000>, 6735e09bc51SSivaprakash Murugesan <19200000>; 6745e09bc51SSivaprakash Murugesan 6758bbda511SRobert Marko power-domains = <&gcc USB1_GDSC>; 6768bbda511SRobert Marko 6775e09bc51SSivaprakash Murugesan resets = <&gcc GCC_USB1_BCR>; 6785e09bc51SSivaprakash Murugesan status = "disabled"; 6795e09bc51SSivaprakash Murugesan 680b77a1c4dSKrzysztof Kozlowski dwc_1: usb@8c00000 { 6815e09bc51SSivaprakash Murugesan compatible = "snps,dwc3"; 6825e09bc51SSivaprakash Murugesan reg = <0x8c00000 0xcd00>; 6835e09bc51SSivaprakash Murugesan interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 6845e09bc51SSivaprakash Murugesan phys = <&qusb_phy_1>, <&usb1_ssphy>; 6855e09bc51SSivaprakash Murugesan phy-names = "usb2-phy", "usb3-phy"; 6865e09bc51SSivaprakash Murugesan snps,is-utmi-l1-suspend; 6875e09bc51SSivaprakash Murugesan snps,hird-threshold = /bits/ 8 <0x0>; 6885e09bc51SSivaprakash Murugesan snps,dis_u2_susphy_quirk; 6895e09bc51SSivaprakash Murugesan snps,dis_u3_susphy_quirk; 6905e09bc51SSivaprakash Murugesan dr_mode = "host"; 6915e09bc51SSivaprakash Murugesan }; 6925e09bc51SSivaprakash Murugesan }; 6935e09bc51SSivaprakash Murugesan 694e8a7fdc5SSivaprakash Murugesan intc: interrupt-controller@b000000 { 695e8a7fdc5SSivaprakash Murugesan compatible = "qcom,msm-qgic2"; 69659892de9SKathiravan T #address-cells = <1>; 69759892de9SKathiravan T #size-cells = <1>; 698e8a7fdc5SSivaprakash Murugesan interrupt-controller; 699674631c3SAndrew Halaney #interrupt-cells = <3>; 700e8a7fdc5SSivaprakash Murugesan reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 70159892de9SKathiravan T ranges = <0 0xb00a000 0xffd>; 70259892de9SKathiravan T 70359892de9SKathiravan T v2m@0 { 70459892de9SKathiravan T compatible = "arm,gic-v2m-frame"; 70559892de9SKathiravan T msi-controller; 70659892de9SKathiravan T reg = <0x0 0xffd>; 70759892de9SKathiravan T }; 708e8a7fdc5SSivaprakash Murugesan }; 70933057e16SSricharan R 710949766e0SKathiravan T watchdog: watchdog@b017000 { 711949766e0SKathiravan T compatible = "qcom,kpss-wdt"; 712949766e0SKathiravan T reg = <0xb017000 0x1000>; 713949766e0SKathiravan T interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 714949766e0SKathiravan T clocks = <&sleep_clk>; 715949766e0SKathiravan T timeout-sec = <30>; 716949766e0SKathiravan T }; 717949766e0SKathiravan T 71850ed9fffSRobert Marko apcs_glb: mailbox@b111000 { 719d93bd463SKrzysztof Kozlowski compatible = "qcom,ipq8074-apcs-apps-global", 720d93bd463SKrzysztof Kozlowski "qcom,ipq6018-apcs-apps-global"; 72140b21d46SRobert Marko reg = <0x0b111000 0x1000>; 722fd8bdb45SRobert Marko clocks = <&a53pll>, <&xo>; 723fd8bdb45SRobert Marko clock-names = "pll", "xo"; 72450ed9fffSRobert Marko 72550ed9fffSRobert Marko #clock-cells = <1>; 72650ed9fffSRobert Marko #mbox-cells = <1>; 72750ed9fffSRobert Marko }; 72850ed9fffSRobert Marko 729fe6d5b8dSRobert Marko a53pll: clock@b116000 { 730fe6d5b8dSRobert Marko compatible = "qcom,ipq8074-a53pll"; 731fe6d5b8dSRobert Marko reg = <0x0b116000 0x40>; 732fe6d5b8dSRobert Marko #clock-cells = <0>; 733fe6d5b8dSRobert Marko clocks = <&xo>; 734fe6d5b8dSRobert Marko clock-names = "xo"; 735fe6d5b8dSRobert Marko }; 736fe6d5b8dSRobert Marko 737e8a7fdc5SSivaprakash Murugesan timer@b120000 { 738e8a7fdc5SSivaprakash Murugesan #address-cells = <1>; 739e8a7fdc5SSivaprakash Murugesan #size-cells = <1>; 740e8a7fdc5SSivaprakash Murugesan ranges; 741e8a7fdc5SSivaprakash Murugesan compatible = "arm,armv7-timer-mem"; 742e8a7fdc5SSivaprakash Murugesan reg = <0x0b120000 0x1000>; 743e8a7fdc5SSivaprakash Murugesan 744e8a7fdc5SSivaprakash Murugesan frame@b120000 { 745e8a7fdc5SSivaprakash Murugesan frame-number = <0>; 746e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 747e8a7fdc5SSivaprakash Murugesan <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 748e8a7fdc5SSivaprakash Murugesan reg = <0x0b121000 0x1000>, 749e8a7fdc5SSivaprakash Murugesan <0x0b122000 0x1000>; 750e8a7fdc5SSivaprakash Murugesan }; 751e8a7fdc5SSivaprakash Murugesan 752e8a7fdc5SSivaprakash Murugesan frame@b123000 { 753e8a7fdc5SSivaprakash Murugesan frame-number = <1>; 754e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 755e8a7fdc5SSivaprakash Murugesan reg = <0x0b123000 0x1000>; 75633057e16SSricharan R status = "disabled"; 75733057e16SSricharan R }; 75833057e16SSricharan R 759e8a7fdc5SSivaprakash Murugesan frame@b124000 { 760e8a7fdc5SSivaprakash Murugesan frame-number = <2>; 761e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 762e8a7fdc5SSivaprakash Murugesan reg = <0x0b124000 0x1000>; 76333057e16SSricharan R status = "disabled"; 76433057e16SSricharan R }; 76533057e16SSricharan R 766e8a7fdc5SSivaprakash Murugesan frame@b125000 { 767e8a7fdc5SSivaprakash Murugesan frame-number = <3>; 768e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 769e8a7fdc5SSivaprakash Murugesan reg = <0x0b125000 0x1000>; 77033057e16SSricharan R status = "disabled"; 77133057e16SSricharan R }; 77233057e16SSricharan R 773e8a7fdc5SSivaprakash Murugesan frame@b126000 { 774e8a7fdc5SSivaprakash Murugesan frame-number = <4>; 775e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 776e8a7fdc5SSivaprakash Murugesan reg = <0x0b126000 0x1000>; 777e8a7fdc5SSivaprakash Murugesan status = "disabled"; 778e8a7fdc5SSivaprakash Murugesan }; 779e8a7fdc5SSivaprakash Murugesan 780e8a7fdc5SSivaprakash Murugesan frame@b127000 { 781e8a7fdc5SSivaprakash Murugesan frame-number = <5>; 782e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 783e8a7fdc5SSivaprakash Murugesan reg = <0x0b127000 0x1000>; 784e8a7fdc5SSivaprakash Murugesan status = "disabled"; 785e8a7fdc5SSivaprakash Murugesan }; 786e8a7fdc5SSivaprakash Murugesan 787e8a7fdc5SSivaprakash Murugesan frame@b128000 { 788e8a7fdc5SSivaprakash Murugesan frame-number = <6>; 789e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 790e8a7fdc5SSivaprakash Murugesan reg = <0x0b128000 0x1000>; 791e8a7fdc5SSivaprakash Murugesan status = "disabled"; 792e8a7fdc5SSivaprakash Murugesan }; 793e8a7fdc5SSivaprakash Murugesan }; 794e8a7fdc5SSivaprakash Murugesan 79533057e16SSricharan R pcie1: pci@10000000 { 79633057e16SSricharan R compatible = "qcom,pcie-ipq8074"; 79752c9887fSVinod Koul reg = <0x10000000 0xf1d>, 79852c9887fSVinod Koul <0x10000f20 0xa8>, 79952c9887fSVinod Koul <0x00088000 0x2000>, 80052c9887fSVinod Koul <0x10100000 0x1000>; 80133057e16SSricharan R reg-names = "dbi", "elbi", "parf", "config"; 80233057e16SSricharan R device_type = "pci"; 80333057e16SSricharan R linux,pci-domain = <1>; 80433057e16SSricharan R bus-range = <0x00 0xff>; 80533057e16SSricharan R num-lanes = <1>; 806b6059031SRobert Marko max-link-speed = <2>; 80733057e16SSricharan R #address-cells = <3>; 80833057e16SSricharan R #size-cells = <2>; 80933057e16SSricharan R 81033057e16SSricharan R phys = <&pcie_phy1>; 81133057e16SSricharan R phy-names = "pciephy"; 81233057e16SSricharan R 813e49eafefSManivannan Sadhasivam ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 814e49eafefSManivannan Sadhasivam <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 81533057e16SSricharan R 81633057e16SSricharan R interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 81733057e16SSricharan R interrupt-names = "msi"; 81833057e16SSricharan R #interrupt-cells = <1>; 81933057e16SSricharan R interrupt-map-mask = <0 0 0 0x7>; 82033057e16SSricharan R interrupt-map = <0 0 0 1 &intc 0 142 82133057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 82233057e16SSricharan R <0 0 0 2 &intc 0 143 82333057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 82433057e16SSricharan R <0 0 0 3 &intc 0 144 82533057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 82633057e16SSricharan R <0 0 0 4 &intc 0 145 82733057e16SSricharan R IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 82833057e16SSricharan R 82933057e16SSricharan R clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 83033057e16SSricharan R <&gcc GCC_PCIE1_AXI_M_CLK>, 83133057e16SSricharan R <&gcc GCC_PCIE1_AXI_S_CLK>, 83233057e16SSricharan R <&gcc GCC_PCIE1_AHB_CLK>, 83333057e16SSricharan R <&gcc GCC_PCIE1_AUX_CLK>; 83433057e16SSricharan R clock-names = "iface", 83533057e16SSricharan R "axi_m", 83633057e16SSricharan R "axi_s", 83733057e16SSricharan R "ahb", 83833057e16SSricharan R "aux"; 83933057e16SSricharan R resets = <&gcc GCC_PCIE1_PIPE_ARES>, 84033057e16SSricharan R <&gcc GCC_PCIE1_SLEEP_ARES>, 84133057e16SSricharan R <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 84233057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 84333057e16SSricharan R <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 84433057e16SSricharan R <&gcc GCC_PCIE1_AHB_ARES>, 84533057e16SSricharan R <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 84633057e16SSricharan R reset-names = "pipe", 84733057e16SSricharan R "sleep", 84833057e16SSricharan R "sticky", 84933057e16SSricharan R "axi_m", 85033057e16SSricharan R "axi_s", 85133057e16SSricharan R "ahb", 85233057e16SSricharan R "axi_m_sticky"; 85333057e16SSricharan R status = "disabled"; 85433057e16SSricharan R }; 85541dac73eSVaradarajan Narayanan 856e8a7fdc5SSivaprakash Murugesan pcie0: pci@20000000 { 8573e83a9c4SRobert Marko compatible = "qcom,pcie-ipq8074-gen3"; 85852c9887fSVinod Koul reg = <0x20000000 0xf1d>, 85952c9887fSVinod Koul <0x20000f20 0xa8>, 8603e83a9c4SRobert Marko <0x20001000 0x1000>, 8613e83a9c4SRobert Marko <0x00080000 0x4000>, 86252c9887fSVinod Koul <0x20100000 0x1000>; 8633e83a9c4SRobert Marko reg-names = "dbi", "elbi", "atu", "parf", "config"; 864e8a7fdc5SSivaprakash Murugesan device_type = "pci"; 865e8a7fdc5SSivaprakash Murugesan linux,pci-domain = <0>; 866e8a7fdc5SSivaprakash Murugesan bus-range = <0x00 0xff>; 867e8a7fdc5SSivaprakash Murugesan num-lanes = <1>; 8683e83a9c4SRobert Marko max-link-speed = <3>; 869e8a7fdc5SSivaprakash Murugesan #address-cells = <3>; 870e8a7fdc5SSivaprakash Murugesan #size-cells = <2>; 87141dac73eSVaradarajan Narayanan 872e8a7fdc5SSivaprakash Murugesan phys = <&pcie_phy0>; 873e8a7fdc5SSivaprakash Murugesan phy-names = "pciephy"; 87441dac73eSVaradarajan Narayanan 875e49eafefSManivannan Sadhasivam ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 876e49eafefSManivannan Sadhasivam <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 87741dac73eSVaradarajan Narayanan 878e8a7fdc5SSivaprakash Murugesan interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 879e8a7fdc5SSivaprakash Murugesan interrupt-names = "msi"; 880e8a7fdc5SSivaprakash Murugesan #interrupt-cells = <1>; 881e8a7fdc5SSivaprakash Murugesan interrupt-map-mask = <0 0 0 0x7>; 882e8a7fdc5SSivaprakash Murugesan interrupt-map = <0 0 0 1 &intc 0 75 883e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 884e8a7fdc5SSivaprakash Murugesan <0 0 0 2 &intc 0 78 885e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 886e8a7fdc5SSivaprakash Murugesan <0 0 0 3 &intc 0 79 887e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 888e8a7fdc5SSivaprakash Murugesan <0 0 0 4 &intc 0 83 889e8a7fdc5SSivaprakash Murugesan IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 89041dac73eSVaradarajan Narayanan 891e8a7fdc5SSivaprakash Murugesan clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 892e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_M_CLK>, 893e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_S_CLK>, 8943e83a9c4SRobert Marko <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 8953e83a9c4SRobert Marko <&gcc GCC_PCIE0_RCHNG_CLK>; 896e8a7fdc5SSivaprakash Murugesan clock-names = "iface", 897e8a7fdc5SSivaprakash Murugesan "axi_m", 898e8a7fdc5SSivaprakash Murugesan "axi_s", 8993e83a9c4SRobert Marko "axi_bridge", 9003e83a9c4SRobert Marko "rchng"; 9013e83a9c4SRobert Marko 902e8a7fdc5SSivaprakash Murugesan resets = <&gcc GCC_PCIE0_PIPE_ARES>, 903e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_SLEEP_ARES>, 904e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 905e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 906e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 907e8a7fdc5SSivaprakash Murugesan <&gcc GCC_PCIE0_AHB_ARES>, 9083e83a9c4SRobert Marko <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 9093e83a9c4SRobert Marko <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 910e8a7fdc5SSivaprakash Murugesan reset-names = "pipe", 911e8a7fdc5SSivaprakash Murugesan "sleep", 912e8a7fdc5SSivaprakash Murugesan "sticky", 913e8a7fdc5SSivaprakash Murugesan "axi_m", 914e8a7fdc5SSivaprakash Murugesan "axi_s", 915e8a7fdc5SSivaprakash Murugesan "ahb", 9163e83a9c4SRobert Marko "axi_m_sticky", 9173e83a9c4SRobert Marko "axi_s_sticky"; 918e8a7fdc5SSivaprakash Murugesan status = "disabled"; 91941dac73eSVaradarajan Narayanan }; 92041dac73eSVaradarajan Narayanan }; 9217d9c1da9SRobert Marko 9227d9c1da9SRobert Marko timer { 9237d9c1da9SRobert Marko compatible = "arm,armv8-timer"; 9247d9c1da9SRobert Marko interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 9257d9c1da9SRobert Marko <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 9267d9c1da9SRobert Marko <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 9277d9c1da9SRobert Marko <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 9287d9c1da9SRobert Marko }; 929887ac089SRobert Marko 930887ac089SRobert Marko thermal-zones { 931887ac089SRobert Marko nss-top-thermal { 932887ac089SRobert Marko polling-delay-passive = <250>; 933887ac089SRobert Marko polling-delay = <1000>; 934887ac089SRobert Marko 935887ac089SRobert Marko thermal-sensors = <&tsens 4>; 936887ac089SRobert Marko }; 937887ac089SRobert Marko 938887ac089SRobert Marko nss0-thermal { 939887ac089SRobert Marko polling-delay-passive = <250>; 940887ac089SRobert Marko polling-delay = <1000>; 941887ac089SRobert Marko 942887ac089SRobert Marko thermal-sensors = <&tsens 5>; 943887ac089SRobert Marko }; 944887ac089SRobert Marko 945887ac089SRobert Marko nss1-thermal { 946887ac089SRobert Marko polling-delay-passive = <250>; 947887ac089SRobert Marko polling-delay = <1000>; 948887ac089SRobert Marko 949887ac089SRobert Marko thermal-sensors = <&tsens 6>; 950887ac089SRobert Marko }; 951887ac089SRobert Marko 952887ac089SRobert Marko wcss-phya0-thermal { 953887ac089SRobert Marko polling-delay-passive = <250>; 954887ac089SRobert Marko polling-delay = <1000>; 955887ac089SRobert Marko 956887ac089SRobert Marko thermal-sensors = <&tsens 7>; 957887ac089SRobert Marko }; 958887ac089SRobert Marko 959887ac089SRobert Marko wcss-phya1-thermal { 960887ac089SRobert Marko polling-delay-passive = <250>; 961887ac089SRobert Marko polling-delay = <1000>; 962887ac089SRobert Marko 963887ac089SRobert Marko thermal-sensors = <&tsens 8>; 964887ac089SRobert Marko }; 965887ac089SRobert Marko 966887ac089SRobert Marko cpu0_thermal: cpu0-thermal { 967887ac089SRobert Marko polling-delay-passive = <250>; 968887ac089SRobert Marko polling-delay = <1000>; 969887ac089SRobert Marko 970887ac089SRobert Marko thermal-sensors = <&tsens 9>; 971887ac089SRobert Marko }; 972887ac089SRobert Marko 973887ac089SRobert Marko cpu1_thermal: cpu1-thermal { 974887ac089SRobert Marko polling-delay-passive = <250>; 975887ac089SRobert Marko polling-delay = <1000>; 976887ac089SRobert Marko 977887ac089SRobert Marko thermal-sensors = <&tsens 10>; 978887ac089SRobert Marko }; 979887ac089SRobert Marko 980887ac089SRobert Marko cpu2_thermal: cpu2-thermal { 981887ac089SRobert Marko polling-delay-passive = <250>; 982887ac089SRobert Marko polling-delay = <1000>; 983887ac089SRobert Marko 984887ac089SRobert Marko thermal-sensors = <&tsens 11>; 985887ac089SRobert Marko }; 986887ac089SRobert Marko 987887ac089SRobert Marko cpu3_thermal: cpu3-thermal { 988887ac089SRobert Marko polling-delay-passive = <250>; 989887ac089SRobert Marko polling-delay = <1000>; 990887ac089SRobert Marko 991887ac089SRobert Marko thermal-sensors = <&tsens 12>; 992887ac089SRobert Marko }; 993887ac089SRobert Marko 994887ac089SRobert Marko cluster_thermal: cluster-thermal { 995887ac089SRobert Marko polling-delay-passive = <250>; 996887ac089SRobert Marko polling-delay = <1000>; 997887ac089SRobert Marko 998887ac089SRobert Marko thermal-sensors = <&tsens 13>; 999887ac089SRobert Marko }; 1000887ac089SRobert Marko 1001887ac089SRobert Marko wcss-phyb0-thermal { 1002887ac089SRobert Marko polling-delay-passive = <250>; 1003887ac089SRobert Marko polling-delay = <1000>; 1004887ac089SRobert Marko 1005887ac089SRobert Marko thermal-sensors = <&tsens 14>; 1006887ac089SRobert Marko }; 1007887ac089SRobert Marko 1008887ac089SRobert Marko wcss-phyb1-thermal { 1009887ac089SRobert Marko polling-delay-passive = <250>; 1010887ac089SRobert Marko polling-delay = <1000>; 1011887ac089SRobert Marko 1012887ac089SRobert Marko thermal-sensors = <&tsens 15>; 1013887ac089SRobert Marko }; 1014887ac089SRobert Marko }; 101541dac73eSVaradarajan Narayanan}; 1016