1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 clocks { 18 sleep_clk: sleep-clk { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 }; 22 23 xo_board: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 CPU0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&L2_0>; 39 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 40 operating-points-v2 = <&cpu_opp_table>; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 50 operating-points-v2 = <&cpu_opp_table>; 51 }; 52 53 CPU2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x2>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 63 CPU3: cpu@3 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x3>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 operating-points-v2 = <&cpu_opp_table>; 71 }; 72 73 L2_0: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 cache-unified; 77 }; 78 }; 79 80 firmware { 81 scm { 82 compatible = "qcom,scm-ipq5332", "qcom,scm"; 83 qcom,dload-mode = <&tcsr 0x6100>; 84 }; 85 }; 86 87 memory@40000000 { 88 device_type = "memory"; 89 /* We expect the bootloader to fill in the size */ 90 reg = <0x0 0x40000000 0x0 0x0>; 91 }; 92 93 cpu_opp_table: opp-table-cpu { 94 compatible = "operating-points-v2"; 95 opp-shared; 96 97 opp-1488000000 { 98 opp-hz = /bits/ 64 <1488000000>; 99 clock-latency-ns = <200000>; 100 }; 101 }; 102 103 pmu { 104 compatible = "arm,cortex-a53-pmu"; 105 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0"; 110 method = "smc"; 111 }; 112 113 reserved-memory { 114 #address-cells = <2>; 115 #size-cells = <2>; 116 ranges; 117 118 tz_mem: tz@4a600000 { 119 reg = <0x0 0x4a600000 0x0 0x200000>; 120 no-map; 121 }; 122 123 smem@4a800000 { 124 compatible = "qcom,smem"; 125 reg = <0x0 0x4a800000 0x0 0x00100000>; 126 no-map; 127 128 hwlocks = <&tcsr_mutex 0>; 129 }; 130 }; 131 132 soc@0 { 133 compatible = "simple-bus"; 134 #address-cells = <1>; 135 #size-cells = <1>; 136 ranges = <0 0 0 0xffffffff>; 137 138 rng: rng@e3000 { 139 compatible = "qcom,prng-ee"; 140 reg = <0x000e3000 0x1000>; 141 clocks = <&gcc GCC_PRNG_AHB_CLK>; 142 clock-names = "core"; 143 }; 144 145 tlmm: pinctrl@1000000 { 146 compatible = "qcom,ipq5332-tlmm"; 147 reg = <0x01000000 0x300000>; 148 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 149 gpio-controller; 150 #gpio-cells = <2>; 151 gpio-ranges = <&tlmm 0 0 53>; 152 interrupt-controller; 153 #interrupt-cells = <2>; 154 155 serial_0_pins: serial0-state { 156 pins = "gpio18", "gpio19"; 157 function = "blsp0_uart0"; 158 drive-strength = <8>; 159 bias-pull-up; 160 }; 161 }; 162 163 gcc: clock-controller@1800000 { 164 compatible = "qcom,ipq5332-gcc"; 165 reg = <0x01800000 0x80000>; 166 #clock-cells = <1>; 167 #reset-cells = <1>; 168 #power-domain-cells = <1>; 169 clocks = <&xo_board>, 170 <&sleep_clk>, 171 <0>, 172 <0>, 173 <0>; 174 }; 175 176 tcsr_mutex: hwlock@1905000 { 177 compatible = "qcom,tcsr-mutex"; 178 reg = <0x01905000 0x20000>; 179 #hwlock-cells = <1>; 180 }; 181 182 tcsr: syscon@1937000 { 183 compatible = "qcom,tcsr-ipq5332", "syscon"; 184 reg = <0x01937000 0x21000>; 185 }; 186 187 sdhc: mmc@7804000 { 188 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 189 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 190 191 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "hc_irq", "pwr_irq"; 194 195 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 196 <&gcc GCC_SDCC1_APPS_CLK>, 197 <&xo_board>; 198 clock-names = "iface", "core", "xo"; 199 status = "disabled"; 200 }; 201 202 blsp_dma: dma-controller@7884000 { 203 compatible = "qcom,bam-v1.7.0"; 204 reg = <0x07884000 0x1d000>; 205 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 207 clock-names = "bam_clk"; 208 #dma-cells = <1>; 209 qcom,ee = <0>; 210 }; 211 212 blsp1_uart0: serial@78af000 { 213 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 214 reg = <0x078af000 0x200>; 215 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 217 <&gcc GCC_BLSP1_AHB_CLK>; 218 clock-names = "core", "iface"; 219 status = "disabled"; 220 }; 221 222 blsp1_spi0: spi@78b5000 { 223 compatible = "qcom,spi-qup-v2.2.1"; 224 reg = <0x078b5000 0x600>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 229 <&gcc GCC_BLSP1_AHB_CLK>; 230 clock-names = "core", "iface"; 231 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 232 dma-names = "tx", "rx"; 233 status = "disabled"; 234 }; 235 236 blsp1_i2c1: i2c@78b6000 { 237 compatible = "qcom,i2c-qup-v2.2.1"; 238 reg = <0x078b6000 0x600>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 243 <&gcc GCC_BLSP1_AHB_CLK>; 244 clock-names = "core", "iface"; 245 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 blsp1_spi2: spi@78b7000 { 251 compatible = "qcom,spi-qup-v2.2.1"; 252 reg = <0x078b7000 0x600>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 257 <&gcc GCC_BLSP1_AHB_CLK>; 258 clock-names = "core", "iface"; 259 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 260 dma-names = "tx", "rx"; 261 status = "disabled"; 262 }; 263 264 intc: interrupt-controller@b000000 { 265 compatible = "qcom,msm-qgic2"; 266 reg = <0x0b000000 0x1000>, /* GICD */ 267 <0x0b002000 0x1000>, /* GICC */ 268 <0x0b001000 0x1000>, /* GICH */ 269 <0x0b004000 0x1000>; /* GICV */ 270 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-controller; 272 #interrupt-cells = <3>; 273 #address-cells = <1>; 274 #size-cells = <1>; 275 ranges = <0 0x0b00c000 0x3000>; 276 277 v2m0: v2m@0 { 278 compatible = "arm,gic-v2m-frame"; 279 reg = <0x00000000 0xffd>; 280 msi-controller; 281 }; 282 283 v2m1: v2m@1000 { 284 compatible = "arm,gic-v2m-frame"; 285 reg = <0x00001000 0xffd>; 286 msi-controller; 287 }; 288 289 v2m2: v2m@2000 { 290 compatible = "arm,gic-v2m-frame"; 291 reg = <0x00002000 0xffd>; 292 msi-controller; 293 }; 294 }; 295 296 watchdog: watchdog@b017000 { 297 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 298 reg = <0x0b017000 0x1000>; 299 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 300 clocks = <&sleep_clk>; 301 timeout-sec = <30>; 302 }; 303 304 apcs_glb: mailbox@b111000 { 305 compatible = "qcom,ipq5332-apcs-apps-global", 306 "qcom,ipq6018-apcs-apps-global"; 307 reg = <0x0b111000 0x1000>; 308 #clock-cells = <1>; 309 clocks = <&a53pll>, <&xo_board>; 310 clock-names = "pll", "xo"; 311 #mbox-cells = <1>; 312 }; 313 314 a53pll: clock@b116000 { 315 compatible = "qcom,ipq5332-a53pll"; 316 reg = <0x0b116000 0x40>; 317 #clock-cells = <0>; 318 clocks = <&xo_board>; 319 clock-names = "xo"; 320 }; 321 322 timer@b120000 { 323 compatible = "arm,armv7-timer-mem"; 324 reg = <0x0b120000 0x1000>; 325 #address-cells = <1>; 326 #size-cells = <1>; 327 ranges; 328 329 frame@b120000 { 330 reg = <0x0b121000 0x1000>, 331 <0x0b122000 0x1000>; 332 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 334 frame-number = <0>; 335 }; 336 337 frame@b123000 { 338 reg = <0x0b123000 0x1000>; 339 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 340 frame-number = <1>; 341 status = "disabled"; 342 }; 343 344 frame@b124000 { 345 reg = <0x0b124000 0x1000>; 346 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 347 frame-number = <2>; 348 status = "disabled"; 349 }; 350 351 frame@b125000 { 352 reg = <0x0b125000 0x1000>; 353 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 354 frame-number = <3>; 355 status = "disabled"; 356 }; 357 358 frame@b126000 { 359 reg = <0x0b126000 0x1000>; 360 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 361 frame-number = <4>; 362 status = "disabled"; 363 }; 364 365 frame@b127000 { 366 reg = <0x0b127000 0x1000>; 367 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 368 frame-number = <5>; 369 status = "disabled"; 370 }; 371 372 frame@b128000 { 373 reg = <0x0b128000 0x1000>; 374 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 375 frame-number = <6>; 376 status = "disabled"; 377 }; 378 }; 379 }; 380 381 timer { 382 compatible = "arm,armv8-timer"; 383 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 384 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 385 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 386 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 387 }; 388}; 389