1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 clocks { 18 sleep_clk: sleep-clk { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 }; 22 23 xo_board: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 CPU0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&L2_0>; 39 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 40 operating-points-v2 = <&cpu_opp_table>; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 50 operating-points-v2 = <&cpu_opp_table>; 51 }; 52 53 CPU2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x2>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 63 CPU3: cpu@3 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x3>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 operating-points-v2 = <&cpu_opp_table>; 71 }; 72 73 L2_0: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 }; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq5332", "qcom,scm"; 82 qcom,dload-mode = <&tcsr 0x6100>; 83 }; 84 }; 85 86 memory@40000000 { 87 device_type = "memory"; 88 /* We expect the bootloader to fill in the size */ 89 reg = <0x0 0x40000000 0x0 0x0>; 90 }; 91 92 cpu_opp_table: opp-table-cpu { 93 compatible = "operating-points-v2"; 94 opp-shared; 95 96 opp-1488000000 { 97 opp-hz = /bits/ 64 <1488000000>; 98 clock-latency-ns = <200000>; 99 }; 100 }; 101 102 pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0"; 109 method = "smc"; 110 }; 111 112 reserved-memory { 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 bootloader@4a100000 { 118 reg = <0x0 0x4a100000 0x0 0x400000>; 119 no-map; 120 }; 121 122 sbl@4a500000 { 123 reg = <0x0 0x4a500000 0x0 0x100000>; 124 no-map; 125 }; 126 127 tz_mem: tz@4a600000 { 128 reg = <0x0 0x4a600000 0x0 0x200000>; 129 no-map; 130 }; 131 132 smem@4a800000 { 133 compatible = "qcom,smem"; 134 reg = <0x0 0x4a800000 0x0 0x100000>; 135 no-map; 136 137 hwlocks = <&tcsr_mutex 0>; 138 }; 139 }; 140 141 soc@0 { 142 compatible = "simple-bus"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges = <0 0 0 0xffffffff>; 146 147 qfprom: efuse@a4000 { 148 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; 149 reg = <0x000a4000 0x721>; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 }; 153 154 rng: rng@e3000 { 155 compatible = "qcom,prng-ee"; 156 reg = <0x000e3000 0x1000>; 157 clocks = <&gcc GCC_PRNG_AHB_CLK>; 158 clock-names = "core"; 159 }; 160 161 tlmm: pinctrl@1000000 { 162 compatible = "qcom,ipq5332-tlmm"; 163 reg = <0x01000000 0x300000>; 164 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 165 gpio-controller; 166 #gpio-cells = <2>; 167 gpio-ranges = <&tlmm 0 0 53>; 168 interrupt-controller; 169 #interrupt-cells = <2>; 170 171 serial_0_pins: serial0-state { 172 pins = "gpio18", "gpio19"; 173 function = "blsp0_uart0"; 174 drive-strength = <8>; 175 bias-pull-up; 176 }; 177 }; 178 179 gcc: clock-controller@1800000 { 180 compatible = "qcom,ipq5332-gcc"; 181 reg = <0x01800000 0x80000>; 182 #clock-cells = <1>; 183 #reset-cells = <1>; 184 #power-domain-cells = <1>; 185 clocks = <&xo_board>, 186 <&sleep_clk>, 187 <0>, 188 <0>, 189 <0>; 190 }; 191 192 tcsr_mutex: hwlock@1905000 { 193 compatible = "qcom,tcsr-mutex"; 194 reg = <0x01905000 0x20000>; 195 #hwlock-cells = <1>; 196 }; 197 198 tcsr: syscon@1937000 { 199 compatible = "qcom,tcsr-ipq5332", "syscon"; 200 reg = <0x01937000 0x21000>; 201 }; 202 203 sdhc: mmc@7804000 { 204 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 205 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 206 207 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 209 interrupt-names = "hc_irq", "pwr_irq"; 210 211 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 212 <&gcc GCC_SDCC1_APPS_CLK>, 213 <&xo_board>; 214 clock-names = "iface", "core", "xo"; 215 status = "disabled"; 216 }; 217 218 blsp_dma: dma-controller@7884000 { 219 compatible = "qcom,bam-v1.7.0"; 220 reg = <0x07884000 0x1d000>; 221 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 223 clock-names = "bam_clk"; 224 #dma-cells = <1>; 225 qcom,ee = <0>; 226 }; 227 228 blsp1_uart0: serial@78af000 { 229 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 230 reg = <0x078af000 0x200>; 231 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 233 <&gcc GCC_BLSP1_AHB_CLK>; 234 clock-names = "core", "iface"; 235 status = "disabled"; 236 }; 237 238 blsp1_uart1: serial@78b0000 { 239 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 240 reg = <0x078b0000 0x200>; 241 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 243 <&gcc GCC_BLSP1_AHB_CLK>; 244 clock-names = "core", "iface"; 245 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 blsp1_spi0: spi@78b5000 { 251 compatible = "qcom,spi-qup-v2.2.1"; 252 reg = <0x078b5000 0x600>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 257 <&gcc GCC_BLSP1_AHB_CLK>; 258 clock-names = "core", "iface"; 259 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 260 dma-names = "tx", "rx"; 261 status = "disabled"; 262 }; 263 264 blsp1_i2c1: i2c@78b6000 { 265 compatible = "qcom,i2c-qup-v2.2.1"; 266 reg = <0x078b6000 0x600>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 271 <&gcc GCC_BLSP1_AHB_CLK>; 272 clock-names = "core", "iface"; 273 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 274 dma-names = "tx", "rx"; 275 status = "disabled"; 276 }; 277 278 blsp1_spi2: spi@78b7000 { 279 compatible = "qcom,spi-qup-v2.2.1"; 280 reg = <0x078b7000 0x600>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 285 <&gcc GCC_BLSP1_AHB_CLK>; 286 clock-names = "core", "iface"; 287 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 288 dma-names = "tx", "rx"; 289 status = "disabled"; 290 }; 291 292 intc: interrupt-controller@b000000 { 293 compatible = "qcom,msm-qgic2"; 294 reg = <0x0b000000 0x1000>, /* GICD */ 295 <0x0b002000 0x1000>, /* GICC */ 296 <0x0b001000 0x1000>, /* GICH */ 297 <0x0b004000 0x1000>; /* GICV */ 298 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-controller; 300 #interrupt-cells = <3>; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0 0x0b00c000 0x3000>; 304 305 v2m0: v2m@0 { 306 compatible = "arm,gic-v2m-frame"; 307 reg = <0x00000000 0xffd>; 308 msi-controller; 309 }; 310 311 v2m1: v2m@1000 { 312 compatible = "arm,gic-v2m-frame"; 313 reg = <0x00001000 0xffd>; 314 msi-controller; 315 }; 316 317 v2m2: v2m@2000 { 318 compatible = "arm,gic-v2m-frame"; 319 reg = <0x00002000 0xffd>; 320 msi-controller; 321 }; 322 }; 323 324 watchdog: watchdog@b017000 { 325 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 326 reg = <0x0b017000 0x1000>; 327 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 328 clocks = <&sleep_clk>; 329 timeout-sec = <30>; 330 }; 331 332 apcs_glb: mailbox@b111000 { 333 compatible = "qcom,ipq5332-apcs-apps-global", 334 "qcom,ipq6018-apcs-apps-global"; 335 reg = <0x0b111000 0x1000>; 336 #clock-cells = <1>; 337 clocks = <&a53pll>, <&xo_board>; 338 clock-names = "pll", "xo"; 339 #mbox-cells = <1>; 340 }; 341 342 a53pll: clock@b116000 { 343 compatible = "qcom,ipq5332-a53pll"; 344 reg = <0x0b116000 0x40>; 345 #clock-cells = <0>; 346 clocks = <&xo_board>; 347 clock-names = "xo"; 348 }; 349 350 timer@b120000 { 351 compatible = "arm,armv7-timer-mem"; 352 reg = <0x0b120000 0x1000>; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 ranges; 356 357 frame@b120000 { 358 reg = <0x0b121000 0x1000>, 359 <0x0b122000 0x1000>; 360 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 362 frame-number = <0>; 363 }; 364 365 frame@b123000 { 366 reg = <0x0b123000 0x1000>; 367 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 368 frame-number = <1>; 369 status = "disabled"; 370 }; 371 372 frame@b124000 { 373 reg = <0x0b124000 0x1000>; 374 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 375 frame-number = <2>; 376 status = "disabled"; 377 }; 378 379 frame@b125000 { 380 reg = <0x0b125000 0x1000>; 381 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 382 frame-number = <3>; 383 status = "disabled"; 384 }; 385 386 frame@b126000 { 387 reg = <0x0b126000 0x1000>; 388 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 389 frame-number = <4>; 390 status = "disabled"; 391 }; 392 393 frame@b127000 { 394 reg = <0x0b127000 0x1000>; 395 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 396 frame-number = <5>; 397 status = "disabled"; 398 }; 399 400 frame@b128000 { 401 reg = <0x0b128000 0x1000>; 402 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 403 frame-number = <6>; 404 status = "disabled"; 405 }; 406 }; 407 }; 408 409 timer { 410 compatible = "arm,armv8-timer"; 411 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 412 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 413 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 414 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 415 }; 416}; 417