1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * IPQ5332 RDP468 board device tree source
4 *
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 */
7
8/dts-v1/;
9
10#include "ipq5332-rdp-common.dtsi"
11
12/ {
13	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
14	compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
15};
16
17&blsp1_spi0 {
18	pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
19	pinctrl-names = "default";
20	status = "okay";
21
22	flash@0 {
23		compatible = "micron,n25q128a11", "jedec,spi-nor";
24		reg = <0>;
25		#address-cells = <1>;
26		#size-cells = <1>;
27		spi-max-frequency = <50000000>;
28	};
29};
30
31&sdhc {
32	bus-width = <4>;
33	max-frequency = <192000000>;
34	mmc-ddr-1_8v;
35	mmc-hs200-1_8v;
36	non-removable;
37	pinctrl-0 = <&sdc_default_state>;
38	pinctrl-names = "default";
39	status = "okay";
40};
41
42/* PINCTRL */
43
44&tlmm {
45	sdc_default_state: sdc-default-state {
46		clk-pins {
47			pins = "gpio13";
48			function = "sdc_clk";
49			drive-strength = <8>;
50			bias-disable;
51		};
52
53		cmd-pins {
54			pins = "gpio12";
55			function = "sdc_cmd";
56			drive-strength = <8>;
57			bias-pull-up;
58		};
59
60		data-pins {
61			pins = "gpio8", "gpio9", "gpio10", "gpio11";
62			function = "sdc_data";
63			drive-strength = <8>;
64			bias-pull-up;
65		};
66	};
67
68	spi_0_data_clk_pins: spi-0-data-clk-state {
69		pins = "gpio14", "gpio15", "gpio16";
70		function = "blsp0_spi";
71		drive-strength = <2>;
72		bias-pull-down;
73	};
74
75	spi_0_cs_pins: spi-0-cs-state {
76		pins = "gpio17";
77		function = "blsp0_spi";
78		drive-strength = <2>;
79		bias-pull-up;
80	};
81};
82