1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/power/tegra234-powergate.h> 9#include <dt-bindings/reset/tegra234-reset.h> 10 11/ { 12 compatible = "nvidia,tegra234"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 bus@0 { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 ranges = <0x0 0x0 0x0 0x40000000>; 23 24 aconnect@2900000 { 25 compatible = "nvidia,tegra234-aconnect", 26 "nvidia,tegra210-aconnect"; 27 clocks = <&bpmp TEGRA234_CLK_APE>, 28 <&bpmp TEGRA234_CLK_APB2APE>; 29 clock-names = "ape", "apb2ape"; 30 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x02900000 0x02900000 0x200000>; 34 status = "disabled"; 35 36 tegra_ahub: ahub@2900800 { 37 compatible = "nvidia,tegra234-ahub"; 38 reg = <0x02900800 0x800>; 39 clocks = <&bpmp TEGRA234_CLK_AHUB>; 40 clock-names = "ahub"; 41 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 42 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x02900800 0x02900800 0x11800>; 46 status = "disabled"; 47 48 tegra_i2s1: i2s@2901000 { 49 compatible = "nvidia,tegra234-i2s", 50 "nvidia,tegra210-i2s"; 51 reg = <0x2901000 0x100>; 52 clocks = <&bpmp TEGRA234_CLK_I2S1>, 53 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 54 clock-names = "i2s", "sync_input"; 55 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 56 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 57 assigned-clock-rates = <1536000>; 58 sound-name-prefix = "I2S1"; 59 status = "disabled"; 60 }; 61 62 tegra_i2s2: i2s@2901100 { 63 compatible = "nvidia,tegra234-i2s", 64 "nvidia,tegra210-i2s"; 65 reg = <0x2901100 0x100>; 66 clocks = <&bpmp TEGRA234_CLK_I2S2>, 67 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 68 clock-names = "i2s", "sync_input"; 69 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 70 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 71 assigned-clock-rates = <1536000>; 72 sound-name-prefix = "I2S2"; 73 status = "disabled"; 74 }; 75 76 tegra_i2s3: i2s@2901200 { 77 compatible = "nvidia,tegra234-i2s", 78 "nvidia,tegra210-i2s"; 79 reg = <0x2901200 0x100>; 80 clocks = <&bpmp TEGRA234_CLK_I2S3>, 81 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 82 clock-names = "i2s", "sync_input"; 83 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 84 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 85 assigned-clock-rates = <1536000>; 86 sound-name-prefix = "I2S3"; 87 status = "disabled"; 88 }; 89 90 tegra_i2s4: i2s@2901300 { 91 compatible = "nvidia,tegra234-i2s", 92 "nvidia,tegra210-i2s"; 93 reg = <0x2901300 0x100>; 94 clocks = <&bpmp TEGRA234_CLK_I2S4>, 95 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 96 clock-names = "i2s", "sync_input"; 97 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 98 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 99 assigned-clock-rates = <1536000>; 100 sound-name-prefix = "I2S4"; 101 status = "disabled"; 102 }; 103 104 tegra_i2s5: i2s@2901400 { 105 compatible = "nvidia,tegra234-i2s", 106 "nvidia,tegra210-i2s"; 107 reg = <0x2901400 0x100>; 108 clocks = <&bpmp TEGRA234_CLK_I2S5>, 109 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 110 clock-names = "i2s", "sync_input"; 111 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 112 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 113 assigned-clock-rates = <1536000>; 114 sound-name-prefix = "I2S5"; 115 status = "disabled"; 116 }; 117 118 tegra_i2s6: i2s@2901500 { 119 compatible = "nvidia,tegra234-i2s", 120 "nvidia,tegra210-i2s"; 121 reg = <0x2901500 0x100>; 122 clocks = <&bpmp TEGRA234_CLK_I2S6>, 123 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 124 clock-names = "i2s", "sync_input"; 125 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 126 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 127 assigned-clock-rates = <1536000>; 128 sound-name-prefix = "I2S6"; 129 status = "disabled"; 130 }; 131 132 tegra_sfc1: sfc@2902000 { 133 compatible = "nvidia,tegra234-sfc", 134 "nvidia,tegra210-sfc"; 135 reg = <0x2902000 0x200>; 136 sound-name-prefix = "SFC1"; 137 status = "disabled"; 138 }; 139 140 tegra_sfc2: sfc@2902200 { 141 compatible = "nvidia,tegra234-sfc", 142 "nvidia,tegra210-sfc"; 143 reg = <0x2902200 0x200>; 144 sound-name-prefix = "SFC2"; 145 status = "disabled"; 146 }; 147 148 tegra_sfc3: sfc@2902400 { 149 compatible = "nvidia,tegra234-sfc", 150 "nvidia,tegra210-sfc"; 151 reg = <0x2902400 0x200>; 152 sound-name-prefix = "SFC3"; 153 status = "disabled"; 154 }; 155 156 tegra_sfc4: sfc@2902600 { 157 compatible = "nvidia,tegra234-sfc", 158 "nvidia,tegra210-sfc"; 159 reg = <0x2902600 0x200>; 160 sound-name-prefix = "SFC4"; 161 status = "disabled"; 162 }; 163 164 tegra_amx1: amx@2903000 { 165 compatible = "nvidia,tegra234-amx", 166 "nvidia,tegra194-amx"; 167 reg = <0x2903000 0x100>; 168 sound-name-prefix = "AMX1"; 169 status = "disabled"; 170 }; 171 172 tegra_amx2: amx@2903100 { 173 compatible = "nvidia,tegra234-amx", 174 "nvidia,tegra194-amx"; 175 reg = <0x2903100 0x100>; 176 sound-name-prefix = "AMX2"; 177 status = "disabled"; 178 }; 179 180 tegra_amx3: amx@2903200 { 181 compatible = "nvidia,tegra234-amx", 182 "nvidia,tegra194-amx"; 183 reg = <0x2903200 0x100>; 184 sound-name-prefix = "AMX3"; 185 status = "disabled"; 186 }; 187 188 tegra_amx4: amx@2903300 { 189 compatible = "nvidia,tegra234-amx", 190 "nvidia,tegra194-amx"; 191 reg = <0x2903300 0x100>; 192 sound-name-prefix = "AMX4"; 193 status = "disabled"; 194 }; 195 196 tegra_adx1: adx@2903800 { 197 compatible = "nvidia,tegra234-adx", 198 "nvidia,tegra210-adx"; 199 reg = <0x2903800 0x100>; 200 sound-name-prefix = "ADX1"; 201 status = "disabled"; 202 }; 203 204 tegra_adx2: adx@2903900 { 205 compatible = "nvidia,tegra234-adx", 206 "nvidia,tegra210-adx"; 207 reg = <0x2903900 0x100>; 208 sound-name-prefix = "ADX2"; 209 status = "disabled"; 210 }; 211 212 tegra_adx3: adx@2903a00 { 213 compatible = "nvidia,tegra234-adx", 214 "nvidia,tegra210-adx"; 215 reg = <0x2903a00 0x100>; 216 sound-name-prefix = "ADX3"; 217 status = "disabled"; 218 }; 219 220 tegra_adx4: adx@2903b00 { 221 compatible = "nvidia,tegra234-adx", 222 "nvidia,tegra210-adx"; 223 reg = <0x2903b00 0x100>; 224 sound-name-prefix = "ADX4"; 225 status = "disabled"; 226 }; 227 228 229 tegra_dmic1: dmic@2904000 { 230 compatible = "nvidia,tegra234-dmic", 231 "nvidia,tegra210-dmic"; 232 reg = <0x2904000 0x100>; 233 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 234 clock-names = "dmic"; 235 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 236 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 237 assigned-clock-rates = <3072000>; 238 sound-name-prefix = "DMIC1"; 239 status = "disabled"; 240 }; 241 242 tegra_dmic2: dmic@2904100 { 243 compatible = "nvidia,tegra234-dmic", 244 "nvidia,tegra210-dmic"; 245 reg = <0x2904100 0x100>; 246 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 247 clock-names = "dmic"; 248 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 249 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 250 assigned-clock-rates = <3072000>; 251 sound-name-prefix = "DMIC2"; 252 status = "disabled"; 253 }; 254 255 tegra_dmic3: dmic@2904200 { 256 compatible = "nvidia,tegra234-dmic", 257 "nvidia,tegra210-dmic"; 258 reg = <0x2904200 0x100>; 259 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 260 clock-names = "dmic"; 261 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 262 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 263 assigned-clock-rates = <3072000>; 264 sound-name-prefix = "DMIC3"; 265 status = "disabled"; 266 }; 267 268 tegra_dmic4: dmic@2904300 { 269 compatible = "nvidia,tegra234-dmic", 270 "nvidia,tegra210-dmic"; 271 reg = <0x2904300 0x100>; 272 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 273 clock-names = "dmic"; 274 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 275 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 276 assigned-clock-rates = <3072000>; 277 sound-name-prefix = "DMIC4"; 278 status = "disabled"; 279 }; 280 281 tegra_dspk1: dspk@2905000 { 282 compatible = "nvidia,tegra234-dspk", 283 "nvidia,tegra186-dspk"; 284 reg = <0x2905000 0x100>; 285 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 286 clock-names = "dspk"; 287 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 288 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 289 assigned-clock-rates = <12288000>; 290 sound-name-prefix = "DSPK1"; 291 status = "disabled"; 292 }; 293 294 tegra_dspk2: dspk@2905100 { 295 compatible = "nvidia,tegra234-dspk", 296 "nvidia,tegra186-dspk"; 297 reg = <0x2905100 0x100>; 298 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 299 clock-names = "dspk"; 300 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 301 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 302 assigned-clock-rates = <12288000>; 303 sound-name-prefix = "DSPK2"; 304 status = "disabled"; 305 }; 306 307 tegra_mvc1: mvc@290a000 { 308 compatible = "nvidia,tegra234-mvc", 309 "nvidia,tegra210-mvc"; 310 reg = <0x290a000 0x200>; 311 sound-name-prefix = "MVC1"; 312 status = "disabled"; 313 }; 314 315 tegra_mvc2: mvc@290a200 { 316 compatible = "nvidia,tegra234-mvc", 317 "nvidia,tegra210-mvc"; 318 reg = <0x290a200 0x200>; 319 sound-name-prefix = "MVC2"; 320 status = "disabled"; 321 }; 322 323 tegra_amixer: amixer@290bb00 { 324 compatible = "nvidia,tegra234-amixer", 325 "nvidia,tegra210-amixer"; 326 reg = <0x290bb00 0x800>; 327 sound-name-prefix = "MIXER1"; 328 status = "disabled"; 329 }; 330 331 tegra_admaif: admaif@290f000 { 332 compatible = "nvidia,tegra234-admaif", 333 "nvidia,tegra186-admaif"; 334 reg = <0x0290f000 0x1000>; 335 dmas = <&adma 1>, <&adma 1>, 336 <&adma 2>, <&adma 2>, 337 <&adma 3>, <&adma 3>, 338 <&adma 4>, <&adma 4>, 339 <&adma 5>, <&adma 5>, 340 <&adma 6>, <&adma 6>, 341 <&adma 7>, <&adma 7>, 342 <&adma 8>, <&adma 8>, 343 <&adma 9>, <&adma 9>, 344 <&adma 10>, <&adma 10>, 345 <&adma 11>, <&adma 11>, 346 <&adma 12>, <&adma 12>, 347 <&adma 13>, <&adma 13>, 348 <&adma 14>, <&adma 14>, 349 <&adma 15>, <&adma 15>, 350 <&adma 16>, <&adma 16>, 351 <&adma 17>, <&adma 17>, 352 <&adma 18>, <&adma 18>, 353 <&adma 19>, <&adma 19>, 354 <&adma 20>, <&adma 20>; 355 dma-names = "rx1", "tx1", 356 "rx2", "tx2", 357 "rx3", "tx3", 358 "rx4", "tx4", 359 "rx5", "tx5", 360 "rx6", "tx6", 361 "rx7", "tx7", 362 "rx8", "tx8", 363 "rx9", "tx9", 364 "rx10", "tx10", 365 "rx11", "tx11", 366 "rx12", "tx12", 367 "rx13", "tx13", 368 "rx14", "tx14", 369 "rx15", "tx15", 370 "rx16", "tx16", 371 "rx17", "tx17", 372 "rx18", "tx18", 373 "rx19", "tx19", 374 "rx20", "tx20"; 375 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 376 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 377 interconnect-names = "dma-mem", "write"; 378 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 379 status = "disabled"; 380 }; 381 382 tegra_asrc: asrc@2910000 { 383 compatible = "nvidia,tegra234-asrc", 384 "nvidia,tegra186-asrc"; 385 reg = <0x2910000 0x2000>; 386 sound-name-prefix = "ASRC1"; 387 status = "disabled"; 388 }; 389 }; 390 391 adma: dma-controller@2930000 { 392 compatible = "nvidia,tegra234-adma", 393 "nvidia,tegra186-adma"; 394 reg = <0x02930000 0x20000>; 395 interrupt-parent = <&agic>; 396 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 428 #dma-cells = <1>; 429 clocks = <&bpmp TEGRA234_CLK_AHUB>; 430 clock-names = "d_audio"; 431 status = "disabled"; 432 }; 433 434 agic: interrupt-controller@2a40000 { 435 compatible = "nvidia,tegra234-agic", 436 "nvidia,tegra210-agic"; 437 #interrupt-cells = <3>; 438 interrupt-controller; 439 reg = <0x02a41000 0x1000>, 440 <0x02a42000 0x2000>; 441 interrupts = <GIC_SPI 145 442 (GIC_CPU_MASK_SIMPLE(4) | 443 IRQ_TYPE_LEVEL_HIGH)>; 444 clocks = <&bpmp TEGRA234_CLK_APE>; 445 clock-names = "clk"; 446 status = "disabled"; 447 }; 448 }; 449 450 misc@100000 { 451 compatible = "nvidia,tegra234-misc"; 452 reg = <0x00100000 0xf000>, 453 <0x0010f000 0x1000>; 454 status = "okay"; 455 }; 456 457 gpio: gpio@2200000 { 458 compatible = "nvidia,tegra234-gpio"; 459 reg-names = "security", "gpio"; 460 reg = <0x02200000 0x10000>, 461 <0x02210000 0x10000>; 462 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 510 #interrupt-cells = <2>; 511 interrupt-controller; 512 #gpio-cells = <2>; 513 gpio-controller; 514 }; 515 516 mc: memory-controller@2c00000 { 517 compatible = "nvidia,tegra234-mc"; 518 reg = <0x02c00000 0x10000>, /* MC-SID */ 519 <0x02c10000 0x10000>, /* MC Broadcast*/ 520 <0x02c20000 0x10000>, /* MC0 */ 521 <0x02c30000 0x10000>, /* MC1 */ 522 <0x02c40000 0x10000>, /* MC2 */ 523 <0x02c50000 0x10000>, /* MC3 */ 524 <0x02b80000 0x10000>, /* MC4 */ 525 <0x02b90000 0x10000>, /* MC5 */ 526 <0x02ba0000 0x10000>, /* MC6 */ 527 <0x02bb0000 0x10000>, /* MC7 */ 528 <0x01700000 0x10000>, /* MC8 */ 529 <0x01710000 0x10000>, /* MC9 */ 530 <0x01720000 0x10000>, /* MC10 */ 531 <0x01730000 0x10000>, /* MC11 */ 532 <0x01740000 0x10000>, /* MC12 */ 533 <0x01750000 0x10000>, /* MC13 */ 534 <0x01760000 0x10000>, /* MC14 */ 535 <0x01770000 0x10000>; /* MC15 */ 536 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 537 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 538 "ch11", "ch12", "ch13", "ch14", "ch15"; 539 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 540 #interconnect-cells = <1>; 541 status = "okay"; 542 543 #address-cells = <2>; 544 #size-cells = <2>; 545 546 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 547 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 548 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 549 550 /* 551 * Bit 39 of addresses passing through the memory 552 * controller selects the XBAR format used when memory 553 * is accessed. This is used to transparently access 554 * memory in the XBAR format used by the discrete GPU 555 * (bit 39 set) or Tegra (bit 39 clear). 556 * 557 * As a consequence, the operating system must ensure 558 * that bit 39 is never used implicitly, for example 559 * via an I/O virtual address mapping of an IOMMU. If 560 * devices require access to the XBAR switch, their 561 * drivers must set this bit explicitly. 562 * 563 * Limit the DMA range for memory clients to [38:0]. 564 */ 565 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 566 567 emc: external-memory-controller@2c60000 { 568 compatible = "nvidia,tegra234-emc"; 569 reg = <0x0 0x02c60000 0x0 0x90000>, 570 <0x0 0x01780000 0x0 0x80000>; 571 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&bpmp TEGRA234_CLK_EMC>; 573 clock-names = "emc"; 574 status = "okay"; 575 576 #interconnect-cells = <0>; 577 578 nvidia,bpmp = <&bpmp>; 579 }; 580 }; 581 582 uarta: serial@3100000 { 583 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 584 reg = <0x03100000 0x10000>; 585 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&bpmp TEGRA234_CLK_UARTA>; 587 clock-names = "serial"; 588 resets = <&bpmp TEGRA234_RESET_UARTA>; 589 reset-names = "serial"; 590 status = "disabled"; 591 }; 592 593 gen1_i2c: i2c@3160000 { 594 compatible = "nvidia,tegra194-i2c"; 595 reg = <0x3160000 0x100>; 596 status = "disabled"; 597 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 598 clock-frequency = <400000>; 599 clocks = <&bpmp TEGRA234_CLK_I2C1 600 &bpmp TEGRA234_CLK_PLLP_OUT0>; 601 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 602 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 603 clock-names = "div-clk", "parent"; 604 resets = <&bpmp TEGRA234_RESET_I2C1>; 605 reset-names = "i2c"; 606 }; 607 608 cam_i2c: i2c@3180000 { 609 compatible = "nvidia,tegra194-i2c"; 610 reg = <0x3180000 0x100>; 611 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 612 status = "disabled"; 613 clock-frequency = <400000>; 614 clocks = <&bpmp TEGRA234_CLK_I2C3 615 &bpmp TEGRA234_CLK_PLLP_OUT0>; 616 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 617 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 618 clock-names = "div-clk", "parent"; 619 resets = <&bpmp TEGRA234_RESET_I2C3>; 620 reset-names = "i2c"; 621 }; 622 623 dp_aux_ch1_i2c: i2c@3190000 { 624 compatible = "nvidia,tegra194-i2c"; 625 reg = <0x3190000 0x100>; 626 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 627 status = "disabled"; 628 clock-frequency = <100000>; 629 clocks = <&bpmp TEGRA234_CLK_I2C4 630 &bpmp TEGRA234_CLK_PLLP_OUT0>; 631 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 632 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 633 clock-names = "div-clk", "parent"; 634 resets = <&bpmp TEGRA234_RESET_I2C4>; 635 reset-names = "i2c"; 636 }; 637 638 dp_aux_ch0_i2c: i2c@31b0000 { 639 compatible = "nvidia,tegra194-i2c"; 640 reg = <0x31b0000 0x100>; 641 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 642 status = "disabled"; 643 clock-frequency = <100000>; 644 clocks = <&bpmp TEGRA234_CLK_I2C6 645 &bpmp TEGRA234_CLK_PLLP_OUT0>; 646 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 647 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 648 clock-names = "div-clk", "parent"; 649 resets = <&bpmp TEGRA234_RESET_I2C6>; 650 reset-names = "i2c"; 651 }; 652 653 dp_aux_ch2_i2c: i2c@31c0000 { 654 compatible = "nvidia,tegra194-i2c"; 655 reg = <0x31c0000 0x100>; 656 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 657 status = "disabled"; 658 clock-frequency = <100000>; 659 clocks = <&bpmp TEGRA234_CLK_I2C7 660 &bpmp TEGRA234_CLK_PLLP_OUT0>; 661 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 662 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 663 clock-names = "div-clk", "parent"; 664 resets = <&bpmp TEGRA234_RESET_I2C7>; 665 reset-names = "i2c"; 666 }; 667 668 dp_aux_ch3_i2c: i2c@31e0000 { 669 compatible = "nvidia,tegra194-i2c"; 670 reg = <0x31e0000 0x100>; 671 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 672 status = "disabled"; 673 clock-frequency = <100000>; 674 clocks = <&bpmp TEGRA234_CLK_I2C9 675 &bpmp TEGRA234_CLK_PLLP_OUT0>; 676 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 677 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 678 clock-names = "div-clk", "parent"; 679 resets = <&bpmp TEGRA234_RESET_I2C9>; 680 reset-names = "i2c"; 681 }; 682 683 spi@3270000 { 684 compatible = "nvidia,tegra234-qspi"; 685 reg = <0x3270000 0x1000>; 686 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 690 <&bpmp TEGRA234_CLK_QSPI0_PM>; 691 clock-names = "qspi", "qspi_out"; 692 resets = <&bpmp TEGRA234_RESET_QSPI0>; 693 reset-names = "qspi"; 694 status = "disabled"; 695 }; 696 697 pwm1: pwm@3280000 { 698 compatible = "nvidia,tegra194-pwm", 699 "nvidia,tegra186-pwm"; 700 reg = <0x3280000 0x10000>; 701 clocks = <&bpmp TEGRA234_CLK_PWM1>; 702 clock-names = "pwm"; 703 resets = <&bpmp TEGRA234_RESET_PWM1>; 704 reset-names = "pwm"; 705 status = "disabled"; 706 #pwm-cells = <2>; 707 }; 708 709 spi@3300000 { 710 compatible = "nvidia,tegra234-qspi"; 711 reg = <0x3300000 0x1000>; 712 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 716 <&bpmp TEGRA234_CLK_QSPI1_PM>; 717 clock-names = "qspi", "qspi_out"; 718 resets = <&bpmp TEGRA234_RESET_QSPI1>; 719 reset-names = "qspi"; 720 status = "disabled"; 721 }; 722 723 mmc@3460000 { 724 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 725 reg = <0x03460000 0x20000>; 726 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 728 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 729 clock-names = "sdhci", "tmclk"; 730 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 731 <&bpmp TEGRA234_CLK_PLLC4>; 732 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 733 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 734 reset-names = "sdhci"; 735 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 736 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 737 interconnect-names = "dma-mem", "write"; 738 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 739 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 740 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 741 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 742 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 743 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 744 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 745 nvidia,default-tap = <0x8>; 746 nvidia,default-trim = <0x14>; 747 nvidia,dqs-trim = <40>; 748 supports-cqe; 749 status = "disabled"; 750 }; 751 752 hda@3510000 { 753 compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 754 reg = <0x3510000 0x10000>; 755 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 757 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 758 clock-names = "hda", "hda2codec_2x"; 759 resets = <&bpmp TEGRA234_RESET_HDA>, 760 <&bpmp TEGRA234_RESET_HDACODEC>; 761 reset-names = "hda", "hda2codec_2x"; 762 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 763 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 764 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 765 interconnect-names = "dma-mem", "write"; 766 status = "disabled"; 767 }; 768 769 fuse@3810000 { 770 compatible = "nvidia,tegra234-efuse"; 771 reg = <0x03810000 0x10000>; 772 clocks = <&bpmp TEGRA234_CLK_FUSE>; 773 clock-names = "fuse"; 774 }; 775 776 hsp_top0: hsp@3c00000 { 777 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 778 reg = <0x03c00000 0xa0000>; 779 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 789 "shared3", "shared4", "shared5", "shared6", 790 "shared7"; 791 #mbox-cells = <2>; 792 }; 793 794 smmu_niso1: iommu@8000000 { 795 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 796 reg = <0x8000000 0x1000000>, 797 <0x7000000 0x1000000>; 798 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 928 stream-match-mask = <0x7f80>; 929 #global-interrupts = <2>; 930 #iommu-cells = <1>; 931 932 nvidia,memory-controller = <&mc>; 933 status = "okay"; 934 }; 935 936 hsp_aon: hsp@c150000 { 937 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 938 reg = <0x0c150000 0x90000>; 939 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 943 /* 944 * Shared interrupt 0 is routed only to AON/SPE, so 945 * we only have 4 shared interrupts for the CCPLEX. 946 */ 947 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 948 #mbox-cells = <2>; 949 }; 950 951 gen2_i2c: i2c@c240000 { 952 compatible = "nvidia,tegra194-i2c"; 953 reg = <0xc240000 0x100>; 954 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 955 status = "disabled"; 956 clock-frequency = <100000>; 957 clocks = <&bpmp TEGRA234_CLK_I2C2 958 &bpmp TEGRA234_CLK_PLLP_OUT0>; 959 clock-names = "div-clk", "parent"; 960 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 961 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 962 resets = <&bpmp TEGRA234_RESET_I2C2>; 963 reset-names = "i2c"; 964 }; 965 966 gen8_i2c: i2c@c250000 { 967 compatible = "nvidia,tegra194-i2c"; 968 reg = <0xc250000 0x100>; 969 nvidia,hw-instance-id = <0x7>; 970 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 971 status = "disabled"; 972 clock-frequency = <400000>; 973 clocks = <&bpmp TEGRA234_CLK_I2C8 974 &bpmp TEGRA234_CLK_PLLP_OUT0>; 975 clock-names = "div-clk", "parent"; 976 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 977 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 978 resets = <&bpmp TEGRA234_RESET_I2C8>; 979 reset-names = "i2c"; 980 }; 981 982 rtc@c2a0000 { 983 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 984 reg = <0x0c2a0000 0x10000>; 985 interrupt-parent = <&pmc>; 986 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 988 clock-names = "rtc"; 989 status = "disabled"; 990 }; 991 992 gpio_aon: gpio@c2f0000 { 993 compatible = "nvidia,tegra234-gpio-aon"; 994 reg-names = "security", "gpio"; 995 reg = <0x0c2f0000 0x1000>, 996 <0x0c2f1000 0x1000>; 997 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1001 #interrupt-cells = <2>; 1002 interrupt-controller; 1003 #gpio-cells = <2>; 1004 gpio-controller; 1005 }; 1006 1007 pmc: pmc@c360000 { 1008 compatible = "nvidia,tegra234-pmc"; 1009 reg = <0x0c360000 0x10000>, 1010 <0x0c370000 0x10000>, 1011 <0x0c380000 0x10000>, 1012 <0x0c390000 0x10000>, 1013 <0x0c3a0000 0x10000>; 1014 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1015 1016 #interrupt-cells = <2>; 1017 interrupt-controller; 1018 }; 1019 1020 gic: interrupt-controller@f400000 { 1021 compatible = "arm,gic-v3"; 1022 reg = <0x0f400000 0x010000>, /* GICD */ 1023 <0x0f440000 0x200000>; /* GICR */ 1024 interrupt-parent = <&gic>; 1025 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1026 1027 #redistributor-regions = <1>; 1028 #interrupt-cells = <3>; 1029 interrupt-controller; 1030 }; 1031 1032 smmu_iso: iommu@10000000{ 1033 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1034 reg = <0x10000000 0x1000000>; 1035 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1164 stream-match-mask = <0x7f80>; 1165 #global-interrupts = <1>; 1166 #iommu-cells = <1>; 1167 1168 nvidia,memory-controller = <&mc>; 1169 status = "okay"; 1170 }; 1171 1172 smmu_niso0: iommu@12000000 { 1173 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1174 reg = <0x12000000 0x1000000>, 1175 <0x11000000 0x1000000>; 1176 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1306 stream-match-mask = <0x7f80>; 1307 #global-interrupts = <2>; 1308 #iommu-cells = <1>; 1309 1310 nvidia,memory-controller = <&mc>; 1311 status = "okay"; 1312 }; 1313 }; 1314 1315 ccplex@e000000 { 1316 compatible = "nvidia,tegra234-ccplex-cluster"; 1317 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1318 nvidia,bpmp = <&bpmp>; 1319 status = "okay"; 1320 }; 1321 1322 sram@40000000 { 1323 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 1324 reg = <0x0 0x40000000 0x0 0x80000>; 1325 #address-cells = <1>; 1326 #size-cells = <1>; 1327 ranges = <0x0 0x0 0x40000000 0x80000>; 1328 1329 cpu_bpmp_tx: sram@70000 { 1330 reg = <0x70000 0x1000>; 1331 label = "cpu-bpmp-tx"; 1332 pool; 1333 }; 1334 1335 cpu_bpmp_rx: sram@71000 { 1336 reg = <0x71000 0x1000>; 1337 label = "cpu-bpmp-rx"; 1338 pool; 1339 }; 1340 }; 1341 1342 bpmp: bpmp { 1343 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 1344 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1345 TEGRA_HSP_DB_MASTER_BPMP>; 1346 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1347 #clock-cells = <1>; 1348 #reset-cells = <1>; 1349 #power-domain-cells = <1>; 1350 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 1351 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 1352 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 1353 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 1354 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1355 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 1356 1357 bpmp_i2c: i2c { 1358 compatible = "nvidia,tegra186-bpmp-i2c"; 1359 nvidia,bpmp-bus-id = <5>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 }; 1363 }; 1364 1365 cpus { 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 1369 cpu0_0: cpu@0 { 1370 compatible = "arm,cortex-a78"; 1371 device_type = "cpu"; 1372 reg = <0x00000>; 1373 1374 enable-method = "psci"; 1375 1376 i-cache-size = <65536>; 1377 i-cache-line-size = <64>; 1378 i-cache-sets = <256>; 1379 d-cache-size = <65536>; 1380 d-cache-line-size = <64>; 1381 d-cache-sets = <256>; 1382 next-level-cache = <&l2c0_0>; 1383 }; 1384 1385 cpu0_1: cpu@100 { 1386 compatible = "arm,cortex-a78"; 1387 device_type = "cpu"; 1388 reg = <0x00100>; 1389 1390 enable-method = "psci"; 1391 1392 i-cache-size = <65536>; 1393 i-cache-line-size = <64>; 1394 i-cache-sets = <256>; 1395 d-cache-size = <65536>; 1396 d-cache-line-size = <64>; 1397 d-cache-sets = <256>; 1398 next-level-cache = <&l2c0_1>; 1399 }; 1400 1401 cpu0_2: cpu@200 { 1402 compatible = "arm,cortex-a78"; 1403 device_type = "cpu"; 1404 reg = <0x00200>; 1405 1406 enable-method = "psci"; 1407 1408 i-cache-size = <65536>; 1409 i-cache-line-size = <64>; 1410 i-cache-sets = <256>; 1411 d-cache-size = <65536>; 1412 d-cache-line-size = <64>; 1413 d-cache-sets = <256>; 1414 next-level-cache = <&l2c0_2>; 1415 }; 1416 1417 cpu0_3: cpu@300 { 1418 compatible = "arm,cortex-a78"; 1419 device_type = "cpu"; 1420 reg = <0x00300>; 1421 1422 enable-method = "psci"; 1423 1424 i-cache-size = <65536>; 1425 i-cache-line-size = <64>; 1426 i-cache-sets = <256>; 1427 d-cache-size = <65536>; 1428 d-cache-line-size = <64>; 1429 d-cache-sets = <256>; 1430 next-level-cache = <&l2c0_3>; 1431 }; 1432 1433 cpu1_0: cpu@10000 { 1434 compatible = "arm,cortex-a78"; 1435 device_type = "cpu"; 1436 reg = <0x10000>; 1437 1438 enable-method = "psci"; 1439 1440 i-cache-size = <65536>; 1441 i-cache-line-size = <64>; 1442 i-cache-sets = <256>; 1443 d-cache-size = <65536>; 1444 d-cache-line-size = <64>; 1445 d-cache-sets = <256>; 1446 next-level-cache = <&l2c1_0>; 1447 }; 1448 1449 cpu1_1: cpu@10100 { 1450 compatible = "arm,cortex-a78"; 1451 device_type = "cpu"; 1452 reg = <0x10100>; 1453 1454 enable-method = "psci"; 1455 1456 i-cache-size = <65536>; 1457 i-cache-line-size = <64>; 1458 i-cache-sets = <256>; 1459 d-cache-size = <65536>; 1460 d-cache-line-size = <64>; 1461 d-cache-sets = <256>; 1462 next-level-cache = <&l2c1_1>; 1463 }; 1464 1465 cpu1_2: cpu@10200 { 1466 compatible = "arm,cortex-a78"; 1467 device_type = "cpu"; 1468 reg = <0x10200>; 1469 1470 enable-method = "psci"; 1471 1472 i-cache-size = <65536>; 1473 i-cache-line-size = <64>; 1474 i-cache-sets = <256>; 1475 d-cache-size = <65536>; 1476 d-cache-line-size = <64>; 1477 d-cache-sets = <256>; 1478 next-level-cache = <&l2c1_2>; 1479 }; 1480 1481 cpu1_3: cpu@10300 { 1482 compatible = "arm,cortex-a78"; 1483 device_type = "cpu"; 1484 reg = <0x10300>; 1485 1486 enable-method = "psci"; 1487 1488 i-cache-size = <65536>; 1489 i-cache-line-size = <64>; 1490 i-cache-sets = <256>; 1491 d-cache-size = <65536>; 1492 d-cache-line-size = <64>; 1493 d-cache-sets = <256>; 1494 next-level-cache = <&l2c1_3>; 1495 }; 1496 1497 cpu2_0: cpu@20000 { 1498 compatible = "arm,cortex-a78"; 1499 device_type = "cpu"; 1500 reg = <0x20000>; 1501 1502 enable-method = "psci"; 1503 1504 i-cache-size = <65536>; 1505 i-cache-line-size = <64>; 1506 i-cache-sets = <256>; 1507 d-cache-size = <65536>; 1508 d-cache-line-size = <64>; 1509 d-cache-sets = <256>; 1510 next-level-cache = <&l2c2_0>; 1511 }; 1512 1513 cpu2_1: cpu@20100 { 1514 compatible = "arm,cortex-a78"; 1515 device_type = "cpu"; 1516 reg = <0x20100>; 1517 1518 enable-method = "psci"; 1519 1520 i-cache-size = <65536>; 1521 i-cache-line-size = <64>; 1522 i-cache-sets = <256>; 1523 d-cache-size = <65536>; 1524 d-cache-line-size = <64>; 1525 d-cache-sets = <256>; 1526 next-level-cache = <&l2c2_1>; 1527 }; 1528 1529 cpu2_2: cpu@20200 { 1530 compatible = "arm,cortex-a78"; 1531 device_type = "cpu"; 1532 reg = <0x20200>; 1533 1534 enable-method = "psci"; 1535 1536 i-cache-size = <65536>; 1537 i-cache-line-size = <64>; 1538 i-cache-sets = <256>; 1539 d-cache-size = <65536>; 1540 d-cache-line-size = <64>; 1541 d-cache-sets = <256>; 1542 next-level-cache = <&l2c2_2>; 1543 }; 1544 1545 cpu2_3: cpu@20300 { 1546 compatible = "arm,cortex-a78"; 1547 device_type = "cpu"; 1548 reg = <0x20300>; 1549 1550 enable-method = "psci"; 1551 1552 i-cache-size = <65536>; 1553 i-cache-line-size = <64>; 1554 i-cache-sets = <256>; 1555 d-cache-size = <65536>; 1556 d-cache-line-size = <64>; 1557 d-cache-sets = <256>; 1558 next-level-cache = <&l2c2_3>; 1559 }; 1560 1561 cpu-map { 1562 cluster0 { 1563 core0 { 1564 cpu = <&cpu0_0>; 1565 }; 1566 1567 core1 { 1568 cpu = <&cpu0_1>; 1569 }; 1570 1571 core2 { 1572 cpu = <&cpu0_2>; 1573 }; 1574 1575 core3 { 1576 cpu = <&cpu0_3>; 1577 }; 1578 }; 1579 1580 cluster1 { 1581 core0 { 1582 cpu = <&cpu1_0>; 1583 }; 1584 1585 core1 { 1586 cpu = <&cpu1_1>; 1587 }; 1588 1589 core2 { 1590 cpu = <&cpu1_2>; 1591 }; 1592 1593 core3 { 1594 cpu = <&cpu1_3>; 1595 }; 1596 }; 1597 1598 cluster2 { 1599 core0 { 1600 cpu = <&cpu2_0>; 1601 }; 1602 1603 core1 { 1604 cpu = <&cpu2_1>; 1605 }; 1606 1607 core2 { 1608 cpu = <&cpu2_2>; 1609 }; 1610 1611 core3 { 1612 cpu = <&cpu2_3>; 1613 }; 1614 }; 1615 }; 1616 1617 l2c0_0: l2-cache00 { 1618 cache-size = <262144>; 1619 cache-line-size = <64>; 1620 cache-sets = <512>; 1621 cache-unified; 1622 next-level-cache = <&l3c0>; 1623 }; 1624 1625 l2c0_1: l2-cache01 { 1626 cache-size = <262144>; 1627 cache-line-size = <64>; 1628 cache-sets = <512>; 1629 cache-unified; 1630 next-level-cache = <&l3c0>; 1631 }; 1632 1633 l2c0_2: l2-cache02 { 1634 cache-size = <262144>; 1635 cache-line-size = <64>; 1636 cache-sets = <512>; 1637 cache-unified; 1638 next-level-cache = <&l3c0>; 1639 }; 1640 1641 l2c0_3: l2-cache03 { 1642 cache-size = <262144>; 1643 cache-line-size = <64>; 1644 cache-sets = <512>; 1645 cache-unified; 1646 next-level-cache = <&l3c0>; 1647 }; 1648 1649 l2c1_0: l2-cache10 { 1650 cache-size = <262144>; 1651 cache-line-size = <64>; 1652 cache-sets = <512>; 1653 cache-unified; 1654 next-level-cache = <&l3c1>; 1655 }; 1656 1657 l2c1_1: l2-cache11 { 1658 cache-size = <262144>; 1659 cache-line-size = <64>; 1660 cache-sets = <512>; 1661 cache-unified; 1662 next-level-cache = <&l3c1>; 1663 }; 1664 1665 l2c1_2: l2-cache12 { 1666 cache-size = <262144>; 1667 cache-line-size = <64>; 1668 cache-sets = <512>; 1669 cache-unified; 1670 next-level-cache = <&l3c1>; 1671 }; 1672 1673 l2c1_3: l2-cache13 { 1674 cache-size = <262144>; 1675 cache-line-size = <64>; 1676 cache-sets = <512>; 1677 cache-unified; 1678 next-level-cache = <&l3c1>; 1679 }; 1680 1681 l2c2_0: l2-cache20 { 1682 cache-size = <262144>; 1683 cache-line-size = <64>; 1684 cache-sets = <512>; 1685 cache-unified; 1686 next-level-cache = <&l3c2>; 1687 }; 1688 1689 l2c2_1: l2-cache21 { 1690 cache-size = <262144>; 1691 cache-line-size = <64>; 1692 cache-sets = <512>; 1693 cache-unified; 1694 next-level-cache = <&l3c2>; 1695 }; 1696 1697 l2c2_2: l2-cache22 { 1698 cache-size = <262144>; 1699 cache-line-size = <64>; 1700 cache-sets = <512>; 1701 cache-unified; 1702 next-level-cache = <&l3c2>; 1703 }; 1704 1705 l2c2_3: l2-cache23 { 1706 cache-size = <262144>; 1707 cache-line-size = <64>; 1708 cache-sets = <512>; 1709 cache-unified; 1710 next-level-cache = <&l3c2>; 1711 }; 1712 1713 l3c0: l3-cache0 { 1714 cache-size = <2097152>; 1715 cache-line-size = <64>; 1716 cache-sets = <2048>; 1717 }; 1718 1719 l3c1: l3-cache1 { 1720 cache-size = <2097152>; 1721 cache-line-size = <64>; 1722 cache-sets = <2048>; 1723 }; 1724 1725 l3c2: l3-cache2 { 1726 cache-size = <2097152>; 1727 cache-line-size = <64>; 1728 cache-sets = <2048>; 1729 }; 1730 }; 1731 1732 pmu { 1733 compatible = "arm,cortex-a78-pmu"; 1734 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1735 status = "okay"; 1736 }; 1737 1738 psci { 1739 compatible = "arm,psci-1.0"; 1740 status = "okay"; 1741 method = "smc"; 1742 }; 1743 1744 tcu: serial { 1745 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 1746 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1747 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1748 mbox-names = "rx", "tx"; 1749 status = "disabled"; 1750 }; 1751 1752 sound { 1753 status = "disabled"; 1754 1755 clocks = <&bpmp TEGRA234_CLK_PLLA>, 1756 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1757 clock-names = "pll_a", "plla_out0"; 1758 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 1759 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 1760 <&bpmp TEGRA234_CLK_AUD_MCLK>; 1761 assigned-clock-parents = <0>, 1762 <&bpmp TEGRA234_CLK_PLLA>, 1763 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1764 }; 1765 1766 timer { 1767 compatible = "arm,armv8-timer"; 1768 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1769 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1770 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1771 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1772 interrupt-parent = <&gic>; 1773 always-on; 1774 }; 1775}; 1776