1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/power/tegra234-powergate.h> 9#include <dt-bindings/reset/tegra234-reset.h> 10#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 gpcdma: dma-controller@2600000 { 26 compatible = "nvidia,tegra234-gpcdma", 27 "nvidia,tegra186-gpcdma"; 28 reg = <0x2600000 0x210000>; 29 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 30 reset-names = "gpcdma"; 31 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 63 #dma-cells = <1>; 64 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 65 dma-channel-mask = <0xfffffffe>; 66 dma-coherent; 67 }; 68 69 aconnect@2900000 { 70 compatible = "nvidia,tegra234-aconnect", 71 "nvidia,tegra210-aconnect"; 72 clocks = <&bpmp TEGRA234_CLK_APE>, 73 <&bpmp TEGRA234_CLK_APB2APE>; 74 clock-names = "ape", "apb2ape"; 75 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 76 #address-cells = <1>; 77 #size-cells = <1>; 78 ranges = <0x02900000 0x02900000 0x200000>; 79 status = "disabled"; 80 81 tegra_ahub: ahub@2900800 { 82 compatible = "nvidia,tegra234-ahub"; 83 reg = <0x02900800 0x800>; 84 clocks = <&bpmp TEGRA234_CLK_AHUB>; 85 clock-names = "ahub"; 86 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 87 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges = <0x02900800 0x02900800 0x11800>; 91 status = "disabled"; 92 93 tegra_i2s1: i2s@2901000 { 94 compatible = "nvidia,tegra234-i2s", 95 "nvidia,tegra210-i2s"; 96 reg = <0x2901000 0x100>; 97 clocks = <&bpmp TEGRA234_CLK_I2S1>, 98 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 99 clock-names = "i2s", "sync_input"; 100 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 101 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 102 assigned-clock-rates = <1536000>; 103 sound-name-prefix = "I2S1"; 104 status = "disabled"; 105 }; 106 107 tegra_i2s2: i2s@2901100 { 108 compatible = "nvidia,tegra234-i2s", 109 "nvidia,tegra210-i2s"; 110 reg = <0x2901100 0x100>; 111 clocks = <&bpmp TEGRA234_CLK_I2S2>, 112 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 113 clock-names = "i2s", "sync_input"; 114 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 115 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 116 assigned-clock-rates = <1536000>; 117 sound-name-prefix = "I2S2"; 118 status = "disabled"; 119 }; 120 121 tegra_i2s3: i2s@2901200 { 122 compatible = "nvidia,tegra234-i2s", 123 "nvidia,tegra210-i2s"; 124 reg = <0x2901200 0x100>; 125 clocks = <&bpmp TEGRA234_CLK_I2S3>, 126 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 127 clock-names = "i2s", "sync_input"; 128 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 129 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 130 assigned-clock-rates = <1536000>; 131 sound-name-prefix = "I2S3"; 132 status = "disabled"; 133 }; 134 135 tegra_i2s4: i2s@2901300 { 136 compatible = "nvidia,tegra234-i2s", 137 "nvidia,tegra210-i2s"; 138 reg = <0x2901300 0x100>; 139 clocks = <&bpmp TEGRA234_CLK_I2S4>, 140 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 141 clock-names = "i2s", "sync_input"; 142 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 143 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 144 assigned-clock-rates = <1536000>; 145 sound-name-prefix = "I2S4"; 146 status = "disabled"; 147 }; 148 149 tegra_i2s5: i2s@2901400 { 150 compatible = "nvidia,tegra234-i2s", 151 "nvidia,tegra210-i2s"; 152 reg = <0x2901400 0x100>; 153 clocks = <&bpmp TEGRA234_CLK_I2S5>, 154 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 155 clock-names = "i2s", "sync_input"; 156 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 157 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 158 assigned-clock-rates = <1536000>; 159 sound-name-prefix = "I2S5"; 160 status = "disabled"; 161 }; 162 163 tegra_i2s6: i2s@2901500 { 164 compatible = "nvidia,tegra234-i2s", 165 "nvidia,tegra210-i2s"; 166 reg = <0x2901500 0x100>; 167 clocks = <&bpmp TEGRA234_CLK_I2S6>, 168 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 169 clock-names = "i2s", "sync_input"; 170 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 171 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 172 assigned-clock-rates = <1536000>; 173 sound-name-prefix = "I2S6"; 174 status = "disabled"; 175 }; 176 177 tegra_sfc1: sfc@2902000 { 178 compatible = "nvidia,tegra234-sfc", 179 "nvidia,tegra210-sfc"; 180 reg = <0x2902000 0x200>; 181 sound-name-prefix = "SFC1"; 182 status = "disabled"; 183 }; 184 185 tegra_sfc2: sfc@2902200 { 186 compatible = "nvidia,tegra234-sfc", 187 "nvidia,tegra210-sfc"; 188 reg = <0x2902200 0x200>; 189 sound-name-prefix = "SFC2"; 190 status = "disabled"; 191 }; 192 193 tegra_sfc3: sfc@2902400 { 194 compatible = "nvidia,tegra234-sfc", 195 "nvidia,tegra210-sfc"; 196 reg = <0x2902400 0x200>; 197 sound-name-prefix = "SFC3"; 198 status = "disabled"; 199 }; 200 201 tegra_sfc4: sfc@2902600 { 202 compatible = "nvidia,tegra234-sfc", 203 "nvidia,tegra210-sfc"; 204 reg = <0x2902600 0x200>; 205 sound-name-prefix = "SFC4"; 206 status = "disabled"; 207 }; 208 209 tegra_amx1: amx@2903000 { 210 compatible = "nvidia,tegra234-amx", 211 "nvidia,tegra194-amx"; 212 reg = <0x2903000 0x100>; 213 sound-name-prefix = "AMX1"; 214 status = "disabled"; 215 }; 216 217 tegra_amx2: amx@2903100 { 218 compatible = "nvidia,tegra234-amx", 219 "nvidia,tegra194-amx"; 220 reg = <0x2903100 0x100>; 221 sound-name-prefix = "AMX2"; 222 status = "disabled"; 223 }; 224 225 tegra_amx3: amx@2903200 { 226 compatible = "nvidia,tegra234-amx", 227 "nvidia,tegra194-amx"; 228 reg = <0x2903200 0x100>; 229 sound-name-prefix = "AMX3"; 230 status = "disabled"; 231 }; 232 233 tegra_amx4: amx@2903300 { 234 compatible = "nvidia,tegra234-amx", 235 "nvidia,tegra194-amx"; 236 reg = <0x2903300 0x100>; 237 sound-name-prefix = "AMX4"; 238 status = "disabled"; 239 }; 240 241 tegra_adx1: adx@2903800 { 242 compatible = "nvidia,tegra234-adx", 243 "nvidia,tegra210-adx"; 244 reg = <0x2903800 0x100>; 245 sound-name-prefix = "ADX1"; 246 status = "disabled"; 247 }; 248 249 tegra_adx2: adx@2903900 { 250 compatible = "nvidia,tegra234-adx", 251 "nvidia,tegra210-adx"; 252 reg = <0x2903900 0x100>; 253 sound-name-prefix = "ADX2"; 254 status = "disabled"; 255 }; 256 257 tegra_adx3: adx@2903a00 { 258 compatible = "nvidia,tegra234-adx", 259 "nvidia,tegra210-adx"; 260 reg = <0x2903a00 0x100>; 261 sound-name-prefix = "ADX3"; 262 status = "disabled"; 263 }; 264 265 tegra_adx4: adx@2903b00 { 266 compatible = "nvidia,tegra234-adx", 267 "nvidia,tegra210-adx"; 268 reg = <0x2903b00 0x100>; 269 sound-name-prefix = "ADX4"; 270 status = "disabled"; 271 }; 272 273 274 tegra_dmic1: dmic@2904000 { 275 compatible = "nvidia,tegra234-dmic", 276 "nvidia,tegra210-dmic"; 277 reg = <0x2904000 0x100>; 278 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 279 clock-names = "dmic"; 280 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 281 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 282 assigned-clock-rates = <3072000>; 283 sound-name-prefix = "DMIC1"; 284 status = "disabled"; 285 }; 286 287 tegra_dmic2: dmic@2904100 { 288 compatible = "nvidia,tegra234-dmic", 289 "nvidia,tegra210-dmic"; 290 reg = <0x2904100 0x100>; 291 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 292 clock-names = "dmic"; 293 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 294 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 295 assigned-clock-rates = <3072000>; 296 sound-name-prefix = "DMIC2"; 297 status = "disabled"; 298 }; 299 300 tegra_dmic3: dmic@2904200 { 301 compatible = "nvidia,tegra234-dmic", 302 "nvidia,tegra210-dmic"; 303 reg = <0x2904200 0x100>; 304 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 305 clock-names = "dmic"; 306 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 307 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 308 assigned-clock-rates = <3072000>; 309 sound-name-prefix = "DMIC3"; 310 status = "disabled"; 311 }; 312 313 tegra_dmic4: dmic@2904300 { 314 compatible = "nvidia,tegra234-dmic", 315 "nvidia,tegra210-dmic"; 316 reg = <0x2904300 0x100>; 317 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 318 clock-names = "dmic"; 319 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 320 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 321 assigned-clock-rates = <3072000>; 322 sound-name-prefix = "DMIC4"; 323 status = "disabled"; 324 }; 325 326 tegra_dspk1: dspk@2905000 { 327 compatible = "nvidia,tegra234-dspk", 328 "nvidia,tegra186-dspk"; 329 reg = <0x2905000 0x100>; 330 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 331 clock-names = "dspk"; 332 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 333 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 334 assigned-clock-rates = <12288000>; 335 sound-name-prefix = "DSPK1"; 336 status = "disabled"; 337 }; 338 339 tegra_dspk2: dspk@2905100 { 340 compatible = "nvidia,tegra234-dspk", 341 "nvidia,tegra186-dspk"; 342 reg = <0x2905100 0x100>; 343 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 344 clock-names = "dspk"; 345 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 346 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 347 assigned-clock-rates = <12288000>; 348 sound-name-prefix = "DSPK2"; 349 status = "disabled"; 350 }; 351 352 tegra_ope1: processing-engine@2908000 { 353 compatible = "nvidia,tegra234-ope", 354 "nvidia,tegra210-ope"; 355 reg = <0x2908000 0x100>; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges; 359 sound-name-prefix = "OPE1"; 360 status = "disabled"; 361 362 equalizer@2908100 { 363 compatible = "nvidia,tegra234-peq", 364 "nvidia,tegra210-peq"; 365 reg = <0x2908100 0x100>; 366 }; 367 368 dynamic-range-compressor@2908200 { 369 compatible = "nvidia,tegra234-mbdrc", 370 "nvidia,tegra210-mbdrc"; 371 reg = <0x2908200 0x200>; 372 }; 373 }; 374 375 tegra_mvc1: mvc@290a000 { 376 compatible = "nvidia,tegra234-mvc", 377 "nvidia,tegra210-mvc"; 378 reg = <0x290a000 0x200>; 379 sound-name-prefix = "MVC1"; 380 status = "disabled"; 381 }; 382 383 tegra_mvc2: mvc@290a200 { 384 compatible = "nvidia,tegra234-mvc", 385 "nvidia,tegra210-mvc"; 386 reg = <0x290a200 0x200>; 387 sound-name-prefix = "MVC2"; 388 status = "disabled"; 389 }; 390 391 tegra_amixer: amixer@290bb00 { 392 compatible = "nvidia,tegra234-amixer", 393 "nvidia,tegra210-amixer"; 394 reg = <0x290bb00 0x800>; 395 sound-name-prefix = "MIXER1"; 396 status = "disabled"; 397 }; 398 399 tegra_admaif: admaif@290f000 { 400 compatible = "nvidia,tegra234-admaif", 401 "nvidia,tegra186-admaif"; 402 reg = <0x0290f000 0x1000>; 403 dmas = <&adma 1>, <&adma 1>, 404 <&adma 2>, <&adma 2>, 405 <&adma 3>, <&adma 3>, 406 <&adma 4>, <&adma 4>, 407 <&adma 5>, <&adma 5>, 408 <&adma 6>, <&adma 6>, 409 <&adma 7>, <&adma 7>, 410 <&adma 8>, <&adma 8>, 411 <&adma 9>, <&adma 9>, 412 <&adma 10>, <&adma 10>, 413 <&adma 11>, <&adma 11>, 414 <&adma 12>, <&adma 12>, 415 <&adma 13>, <&adma 13>, 416 <&adma 14>, <&adma 14>, 417 <&adma 15>, <&adma 15>, 418 <&adma 16>, <&adma 16>, 419 <&adma 17>, <&adma 17>, 420 <&adma 18>, <&adma 18>, 421 <&adma 19>, <&adma 19>, 422 <&adma 20>, <&adma 20>; 423 dma-names = "rx1", "tx1", 424 "rx2", "tx2", 425 "rx3", "tx3", 426 "rx4", "tx4", 427 "rx5", "tx5", 428 "rx6", "tx6", 429 "rx7", "tx7", 430 "rx8", "tx8", 431 "rx9", "tx9", 432 "rx10", "tx10", 433 "rx11", "tx11", 434 "rx12", "tx12", 435 "rx13", "tx13", 436 "rx14", "tx14", 437 "rx15", "tx15", 438 "rx16", "tx16", 439 "rx17", "tx17", 440 "rx18", "tx18", 441 "rx19", "tx19", 442 "rx20", "tx20"; 443 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 444 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 445 interconnect-names = "dma-mem", "write"; 446 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 447 status = "disabled"; 448 }; 449 450 tegra_asrc: asrc@2910000 { 451 compatible = "nvidia,tegra234-asrc", 452 "nvidia,tegra186-asrc"; 453 reg = <0x2910000 0x2000>; 454 sound-name-prefix = "ASRC1"; 455 status = "disabled"; 456 }; 457 }; 458 459 adma: dma-controller@2930000 { 460 compatible = "nvidia,tegra234-adma", 461 "nvidia,tegra186-adma"; 462 reg = <0x02930000 0x20000>; 463 interrupt-parent = <&agic>; 464 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 496 #dma-cells = <1>; 497 clocks = <&bpmp TEGRA234_CLK_AHUB>; 498 clock-names = "d_audio"; 499 status = "disabled"; 500 }; 501 502 agic: interrupt-controller@2a40000 { 503 compatible = "nvidia,tegra234-agic", 504 "nvidia,tegra210-agic"; 505 #interrupt-cells = <3>; 506 interrupt-controller; 507 reg = <0x02a41000 0x1000>, 508 <0x02a42000 0x2000>; 509 interrupts = <GIC_SPI 145 510 (GIC_CPU_MASK_SIMPLE(4) | 511 IRQ_TYPE_LEVEL_HIGH)>; 512 clocks = <&bpmp TEGRA234_CLK_APE>; 513 clock-names = "clk"; 514 status = "disabled"; 515 }; 516 }; 517 518 misc@100000 { 519 compatible = "nvidia,tegra234-misc"; 520 reg = <0x00100000 0xf000>, 521 <0x0010f000 0x1000>; 522 status = "okay"; 523 }; 524 525 timer@2080000 { 526 compatible = "nvidia,tegra234-timer"; 527 reg = <0x02080000 0x00121000>; 528 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 544 status = "okay"; 545 }; 546 547 host1x@13e00000 { 548 compatible = "nvidia,tegra234-host1x"; 549 reg = <0x13e00000 0x10000>, 550 <0x13e10000 0x10000>, 551 <0x13e40000 0x10000>; 552 reg-names = "common", "hypervisor", "vm"; 553 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 563 "syncpt5", "syncpt6", "syncpt7", "host1x"; 564 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 565 clock-names = "host1x"; 566 567 #address-cells = <1>; 568 #size-cells = <1>; 569 570 ranges = <0x14800000 0x14800000 0x02000000>; 571 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 572 interconnect-names = "dma-mem"; 573 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 574 575 /* Context isolation domains */ 576 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 577 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 578 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 579 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 580 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 581 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 582 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 583 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 584 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 585 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 586 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 587 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 588 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 589 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 590 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 591 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 592 593 vic@15340000 { 594 compatible = "nvidia,tegra234-vic"; 595 reg = <0x15340000 0x00040000>; 596 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&bpmp TEGRA234_CLK_VIC>; 598 clock-names = "vic"; 599 resets = <&bpmp TEGRA234_RESET_VIC>; 600 reset-names = "vic"; 601 602 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 603 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 604 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 605 interconnect-names = "dma-mem", "write"; 606 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 607 dma-coherent; 608 }; 609 610 nvdec@15480000 { 611 compatible = "nvidia,tegra234-nvdec"; 612 reg = <0x15480000 0x00040000>; 613 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 614 <&bpmp TEGRA234_CLK_FUSE>, 615 <&bpmp TEGRA234_CLK_TSEC_PKA>; 616 clock-names = "nvdec", "fuse", "tsec_pka"; 617 resets = <&bpmp TEGRA234_RESET_NVDEC>; 618 reset-names = "nvdec"; 619 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 620 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 621 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 622 interconnect-names = "dma-mem", "write"; 623 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 624 dma-coherent; 625 626 nvidia,memory-controller = <&mc>; 627 628 /* 629 * Placeholder values that firmware needs to update with the real 630 * offsets parsed from the microcode headers. 631 */ 632 nvidia,bl-manifest-offset = <0>; 633 nvidia,bl-data-offset = <0>; 634 nvidia,bl-code-offset = <0>; 635 nvidia,os-manifest-offset = <0>; 636 nvidia,os-data-offset = <0>; 637 nvidia,os-code-offset = <0>; 638 639 /* 640 * Firmware needs to set this to "okay" once the above values have 641 * been updated. 642 */ 643 status = "disabled"; 644 }; 645 }; 646 647 gpio: gpio@2200000 { 648 compatible = "nvidia,tegra234-gpio"; 649 reg-names = "security", "gpio"; 650 reg = <0x02200000 0x10000>, 651 <0x02210000 0x10000>; 652 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 700 #interrupt-cells = <2>; 701 interrupt-controller; 702 #gpio-cells = <2>; 703 gpio-controller; 704 }; 705 706 mc: memory-controller@2c00000 { 707 compatible = "nvidia,tegra234-mc"; 708 reg = <0x02c00000 0x10000>, /* MC-SID */ 709 <0x02c10000 0x10000>, /* MC Broadcast*/ 710 <0x02c20000 0x10000>, /* MC0 */ 711 <0x02c30000 0x10000>, /* MC1 */ 712 <0x02c40000 0x10000>, /* MC2 */ 713 <0x02c50000 0x10000>, /* MC3 */ 714 <0x02b80000 0x10000>, /* MC4 */ 715 <0x02b90000 0x10000>, /* MC5 */ 716 <0x02ba0000 0x10000>, /* MC6 */ 717 <0x02bb0000 0x10000>, /* MC7 */ 718 <0x01700000 0x10000>, /* MC8 */ 719 <0x01710000 0x10000>, /* MC9 */ 720 <0x01720000 0x10000>, /* MC10 */ 721 <0x01730000 0x10000>, /* MC11 */ 722 <0x01740000 0x10000>, /* MC12 */ 723 <0x01750000 0x10000>, /* MC13 */ 724 <0x01760000 0x10000>, /* MC14 */ 725 <0x01770000 0x10000>; /* MC15 */ 726 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 727 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 728 "ch11", "ch12", "ch13", "ch14", "ch15"; 729 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 730 #interconnect-cells = <1>; 731 status = "okay"; 732 733 #address-cells = <2>; 734 #size-cells = <2>; 735 736 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 737 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 738 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 739 740 /* 741 * Bit 39 of addresses passing through the memory 742 * controller selects the XBAR format used when memory 743 * is accessed. This is used to transparently access 744 * memory in the XBAR format used by the discrete GPU 745 * (bit 39 set) or Tegra (bit 39 clear). 746 * 747 * As a consequence, the operating system must ensure 748 * that bit 39 is never used implicitly, for example 749 * via an I/O virtual address mapping of an IOMMU. If 750 * devices require access to the XBAR switch, their 751 * drivers must set this bit explicitly. 752 * 753 * Limit the DMA range for memory clients to [38:0]. 754 */ 755 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 756 757 emc: external-memory-controller@2c60000 { 758 compatible = "nvidia,tegra234-emc"; 759 reg = <0x0 0x02c60000 0x0 0x90000>, 760 <0x0 0x01780000 0x0 0x80000>; 761 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&bpmp TEGRA234_CLK_EMC>; 763 clock-names = "emc"; 764 status = "okay"; 765 766 #interconnect-cells = <0>; 767 768 nvidia,bpmp = <&bpmp>; 769 }; 770 }; 771 772 uarta: serial@3100000 { 773 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 774 reg = <0x03100000 0x10000>; 775 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&bpmp TEGRA234_CLK_UARTA>; 777 clock-names = "serial"; 778 resets = <&bpmp TEGRA234_RESET_UARTA>; 779 reset-names = "serial"; 780 status = "disabled"; 781 }; 782 783 gen1_i2c: i2c@3160000 { 784 compatible = "nvidia,tegra194-i2c"; 785 reg = <0x3160000 0x100>; 786 status = "disabled"; 787 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 788 clock-frequency = <400000>; 789 clocks = <&bpmp TEGRA234_CLK_I2C1 790 &bpmp TEGRA234_CLK_PLLP_OUT0>; 791 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 792 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 793 clock-names = "div-clk", "parent"; 794 resets = <&bpmp TEGRA234_RESET_I2C1>; 795 reset-names = "i2c"; 796 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 797 dma-coherent; 798 dmas = <&gpcdma 21>, <&gpcdma 21>; 799 dma-names = "rx", "tx"; 800 }; 801 802 cam_i2c: i2c@3180000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x3180000 0x100>; 805 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 806 status = "disabled"; 807 clock-frequency = <400000>; 808 clocks = <&bpmp TEGRA234_CLK_I2C3 809 &bpmp TEGRA234_CLK_PLLP_OUT0>; 810 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 811 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 812 clock-names = "div-clk", "parent"; 813 resets = <&bpmp TEGRA234_RESET_I2C3>; 814 reset-names = "i2c"; 815 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 816 dma-coherent; 817 dmas = <&gpcdma 23>, <&gpcdma 23>; 818 dma-names = "rx", "tx"; 819 }; 820 821 dp_aux_ch1_i2c: i2c@3190000 { 822 compatible = "nvidia,tegra194-i2c"; 823 reg = <0x3190000 0x100>; 824 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 825 status = "disabled"; 826 clock-frequency = <100000>; 827 clocks = <&bpmp TEGRA234_CLK_I2C4 828 &bpmp TEGRA234_CLK_PLLP_OUT0>; 829 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 830 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 831 clock-names = "div-clk", "parent"; 832 resets = <&bpmp TEGRA234_RESET_I2C4>; 833 reset-names = "i2c"; 834 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 835 dma-coherent; 836 dmas = <&gpcdma 26>, <&gpcdma 26>; 837 dma-names = "rx", "tx"; 838 }; 839 840 dp_aux_ch0_i2c: i2c@31b0000 { 841 compatible = "nvidia,tegra194-i2c"; 842 reg = <0x31b0000 0x100>; 843 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 844 status = "disabled"; 845 clock-frequency = <100000>; 846 clocks = <&bpmp TEGRA234_CLK_I2C6 847 &bpmp TEGRA234_CLK_PLLP_OUT0>; 848 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 849 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 850 clock-names = "div-clk", "parent"; 851 resets = <&bpmp TEGRA234_RESET_I2C6>; 852 reset-names = "i2c"; 853 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 854 dma-coherent; 855 dmas = <&gpcdma 30>, <&gpcdma 30>; 856 dma-names = "rx", "tx"; 857 }; 858 859 dp_aux_ch2_i2c: i2c@31c0000 { 860 compatible = "nvidia,tegra194-i2c"; 861 reg = <0x31c0000 0x100>; 862 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 863 status = "disabled"; 864 clock-frequency = <100000>; 865 clocks = <&bpmp TEGRA234_CLK_I2C7 866 &bpmp TEGRA234_CLK_PLLP_OUT0>; 867 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 868 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 869 clock-names = "div-clk", "parent"; 870 resets = <&bpmp TEGRA234_RESET_I2C7>; 871 reset-names = "i2c"; 872 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 873 dma-coherent; 874 dmas = <&gpcdma 27>, <&gpcdma 27>; 875 dma-names = "rx", "tx"; 876 }; 877 878 uarti: serial@31d0000 { 879 compatible = "arm,sbsa-uart"; 880 reg = <0x31d0000 0x10000>; 881 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 882 status = "disabled"; 883 }; 884 885 dp_aux_ch3_i2c: i2c@31e0000 { 886 compatible = "nvidia,tegra194-i2c"; 887 reg = <0x31e0000 0x100>; 888 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 889 status = "disabled"; 890 clock-frequency = <100000>; 891 clocks = <&bpmp TEGRA234_CLK_I2C9 892 &bpmp TEGRA234_CLK_PLLP_OUT0>; 893 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 894 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 895 clock-names = "div-clk", "parent"; 896 resets = <&bpmp TEGRA234_RESET_I2C9>; 897 reset-names = "i2c"; 898 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 899 dma-coherent; 900 dmas = <&gpcdma 31>, <&gpcdma 31>; 901 dma-names = "rx", "tx"; 902 }; 903 904 spi@3270000 { 905 compatible = "nvidia,tegra234-qspi"; 906 reg = <0x3270000 0x1000>; 907 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 911 <&bpmp TEGRA234_CLK_QSPI0_PM>; 912 clock-names = "qspi", "qspi_out"; 913 resets = <&bpmp TEGRA234_RESET_QSPI0>; 914 status = "disabled"; 915 }; 916 917 pwm1: pwm@3280000 { 918 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 919 reg = <0x3280000 0x10000>; 920 clocks = <&bpmp TEGRA234_CLK_PWM1>; 921 resets = <&bpmp TEGRA234_RESET_PWM1>; 922 reset-names = "pwm"; 923 status = "disabled"; 924 #pwm-cells = <2>; 925 }; 926 927 pwm2: pwm@3290000 { 928 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 929 reg = <0x3290000 0x10000>; 930 clocks = <&bpmp TEGRA234_CLK_PWM2>; 931 resets = <&bpmp TEGRA234_RESET_PWM2>; 932 reset-names = "pwm"; 933 status = "disabled"; 934 #pwm-cells = <2>; 935 }; 936 937 pwm3: pwm@32a0000 { 938 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 939 reg = <0x32a0000 0x10000>; 940 clocks = <&bpmp TEGRA234_CLK_PWM3>; 941 resets = <&bpmp TEGRA234_RESET_PWM3>; 942 reset-names = "pwm"; 943 status = "disabled"; 944 #pwm-cells = <2>; 945 }; 946 947 pwm5: pwm@32c0000 { 948 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 949 reg = <0x32c0000 0x10000>; 950 clocks = <&bpmp TEGRA234_CLK_PWM5>; 951 resets = <&bpmp TEGRA234_RESET_PWM5>; 952 reset-names = "pwm"; 953 status = "disabled"; 954 #pwm-cells = <2>; 955 }; 956 957 pwm6: pwm@32d0000 { 958 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 959 reg = <0x32d0000 0x10000>; 960 clocks = <&bpmp TEGRA234_CLK_PWM6>; 961 resets = <&bpmp TEGRA234_RESET_PWM6>; 962 reset-names = "pwm"; 963 status = "disabled"; 964 #pwm-cells = <2>; 965 }; 966 967 pwm7: pwm@32e0000 { 968 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 969 reg = <0x32e0000 0x10000>; 970 clocks = <&bpmp TEGRA234_CLK_PWM7>; 971 resets = <&bpmp TEGRA234_RESET_PWM7>; 972 reset-names = "pwm"; 973 status = "disabled"; 974 #pwm-cells = <2>; 975 }; 976 977 pwm8: pwm@32f0000 { 978 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 979 reg = <0x32f0000 0x10000>; 980 clocks = <&bpmp TEGRA234_CLK_PWM8>; 981 resets = <&bpmp TEGRA234_RESET_PWM8>; 982 reset-names = "pwm"; 983 status = "disabled"; 984 #pwm-cells = <2>; 985 }; 986 987 spi@3300000 { 988 compatible = "nvidia,tegra234-qspi"; 989 reg = <0x3300000 0x1000>; 990 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 994 <&bpmp TEGRA234_CLK_QSPI1_PM>; 995 clock-names = "qspi", "qspi_out"; 996 resets = <&bpmp TEGRA234_RESET_QSPI1>; 997 status = "disabled"; 998 }; 999 1000 mmc@3400000 { 1001 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 1002 reg = <0x03400000 0x20000>; 1003 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 1005 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 1006 clock-names = "sdhci", "tmclk"; 1007 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 1008 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 1009 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 1010 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 1011 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 1012 reset-names = "sdhci"; 1013 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 1014 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 1015 interconnect-names = "dma-mem", "write"; 1016 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 1017 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1018 pinctrl-0 = <&sdmmc1_3v3>; 1019 pinctrl-1 = <&sdmmc1_1v8>; 1020 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1021 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 1022 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1023 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 1024 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1025 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1026 nvidia,default-tap = <14>; 1027 nvidia,default-trim = <0x8>; 1028 sd-uhs-sdr25; 1029 sd-uhs-sdr50; 1030 sd-uhs-ddr50; 1031 sd-uhs-sdr104; 1032 status = "disabled"; 1033 }; 1034 1035 mmc@3460000 { 1036 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 1037 reg = <0x03460000 0x20000>; 1038 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1040 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 1041 clock-names = "sdhci", "tmclk"; 1042 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1043 <&bpmp TEGRA234_CLK_PLLC4>; 1044 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 1045 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 1046 reset-names = "sdhci"; 1047 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 1048 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 1049 interconnect-names = "dma-mem", "write"; 1050 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 1051 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1052 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1053 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1054 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 1055 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1056 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 1057 nvidia,default-tap = <0x8>; 1058 nvidia,default-trim = <0x14>; 1059 nvidia,dqs-trim = <40>; 1060 supports-cqe; 1061 status = "disabled"; 1062 }; 1063 1064 hda@3510000 { 1065 compatible = "nvidia,tegra234-hda"; 1066 reg = <0x3510000 0x10000>; 1067 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 1069 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 1070 clock-names = "hda", "hda2codec_2x"; 1071 resets = <&bpmp TEGRA234_RESET_HDA>, 1072 <&bpmp TEGRA234_RESET_HDACODEC>; 1073 reset-names = "hda", "hda2codec_2x"; 1074 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 1075 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 1076 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 1077 interconnect-names = "dma-mem", "write"; 1078 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 1079 status = "disabled"; 1080 }; 1081 1082 fuse@3810000 { 1083 compatible = "nvidia,tegra234-efuse"; 1084 reg = <0x03810000 0x10000>; 1085 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1086 clock-names = "fuse"; 1087 }; 1088 1089 hsp_top0: hsp@3c00000 { 1090 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1091 reg = <0x03c00000 0xa0000>; 1092 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1102 "shared3", "shared4", "shared5", "shared6", 1103 "shared7"; 1104 #mbox-cells = <2>; 1105 }; 1106 1107 p2u_hsio_0: phy@3e00000 { 1108 compatible = "nvidia,tegra234-p2u"; 1109 reg = <0x03e00000 0x10000>; 1110 reg-names = "ctl"; 1111 1112 #phy-cells = <0>; 1113 }; 1114 1115 p2u_hsio_1: phy@3e10000 { 1116 compatible = "nvidia,tegra234-p2u"; 1117 reg = <0x03e10000 0x10000>; 1118 reg-names = "ctl"; 1119 1120 #phy-cells = <0>; 1121 }; 1122 1123 p2u_hsio_2: phy@3e20000 { 1124 compatible = "nvidia,tegra234-p2u"; 1125 reg = <0x03e20000 0x10000>; 1126 reg-names = "ctl"; 1127 1128 #phy-cells = <0>; 1129 }; 1130 1131 p2u_hsio_3: phy@3e30000 { 1132 compatible = "nvidia,tegra234-p2u"; 1133 reg = <0x03e30000 0x10000>; 1134 reg-names = "ctl"; 1135 1136 #phy-cells = <0>; 1137 }; 1138 1139 p2u_hsio_4: phy@3e40000 { 1140 compatible = "nvidia,tegra234-p2u"; 1141 reg = <0x03e40000 0x10000>; 1142 reg-names = "ctl"; 1143 1144 #phy-cells = <0>; 1145 }; 1146 1147 p2u_hsio_5: phy@3e50000 { 1148 compatible = "nvidia,tegra234-p2u"; 1149 reg = <0x03e50000 0x10000>; 1150 reg-names = "ctl"; 1151 1152 #phy-cells = <0>; 1153 }; 1154 1155 p2u_hsio_6: phy@3e60000 { 1156 compatible = "nvidia,tegra234-p2u"; 1157 reg = <0x03e60000 0x10000>; 1158 reg-names = "ctl"; 1159 1160 #phy-cells = <0>; 1161 }; 1162 1163 p2u_hsio_7: phy@3e70000 { 1164 compatible = "nvidia,tegra234-p2u"; 1165 reg = <0x03e70000 0x10000>; 1166 reg-names = "ctl"; 1167 1168 #phy-cells = <0>; 1169 }; 1170 1171 p2u_nvhs_0: phy@3e90000 { 1172 compatible = "nvidia,tegra234-p2u"; 1173 reg = <0x03e90000 0x10000>; 1174 reg-names = "ctl"; 1175 1176 #phy-cells = <0>; 1177 }; 1178 1179 p2u_nvhs_1: phy@3ea0000 { 1180 compatible = "nvidia,tegra234-p2u"; 1181 reg = <0x03ea0000 0x10000>; 1182 reg-names = "ctl"; 1183 1184 #phy-cells = <0>; 1185 }; 1186 1187 p2u_nvhs_2: phy@3eb0000 { 1188 compatible = "nvidia,tegra234-p2u"; 1189 reg = <0x03eb0000 0x10000>; 1190 reg-names = "ctl"; 1191 1192 #phy-cells = <0>; 1193 }; 1194 1195 p2u_nvhs_3: phy@3ec0000 { 1196 compatible = "nvidia,tegra234-p2u"; 1197 reg = <0x03ec0000 0x10000>; 1198 reg-names = "ctl"; 1199 1200 #phy-cells = <0>; 1201 }; 1202 1203 p2u_nvhs_4: phy@3ed0000 { 1204 compatible = "nvidia,tegra234-p2u"; 1205 reg = <0x03ed0000 0x10000>; 1206 reg-names = "ctl"; 1207 1208 #phy-cells = <0>; 1209 }; 1210 1211 p2u_nvhs_5: phy@3ee0000 { 1212 compatible = "nvidia,tegra234-p2u"; 1213 reg = <0x03ee0000 0x10000>; 1214 reg-names = "ctl"; 1215 1216 #phy-cells = <0>; 1217 }; 1218 1219 p2u_nvhs_6: phy@3ef0000 { 1220 compatible = "nvidia,tegra234-p2u"; 1221 reg = <0x03ef0000 0x10000>; 1222 reg-names = "ctl"; 1223 1224 #phy-cells = <0>; 1225 }; 1226 1227 p2u_nvhs_7: phy@3f00000 { 1228 compatible = "nvidia,tegra234-p2u"; 1229 reg = <0x03f00000 0x10000>; 1230 reg-names = "ctl"; 1231 1232 #phy-cells = <0>; 1233 }; 1234 1235 p2u_gbe_0: phy@3f20000 { 1236 compatible = "nvidia,tegra234-p2u"; 1237 reg = <0x03f20000 0x10000>; 1238 reg-names = "ctl"; 1239 1240 #phy-cells = <0>; 1241 }; 1242 1243 p2u_gbe_1: phy@3f30000 { 1244 compatible = "nvidia,tegra234-p2u"; 1245 reg = <0x03f30000 0x10000>; 1246 reg-names = "ctl"; 1247 1248 #phy-cells = <0>; 1249 }; 1250 1251 p2u_gbe_2: phy@3f40000 { 1252 compatible = "nvidia,tegra234-p2u"; 1253 reg = <0x03f40000 0x10000>; 1254 reg-names = "ctl"; 1255 1256 #phy-cells = <0>; 1257 }; 1258 1259 p2u_gbe_3: phy@3f50000 { 1260 compatible = "nvidia,tegra234-p2u"; 1261 reg = <0x03f50000 0x10000>; 1262 reg-names = "ctl"; 1263 1264 #phy-cells = <0>; 1265 }; 1266 1267 p2u_gbe_4: phy@3f60000 { 1268 compatible = "nvidia,tegra234-p2u"; 1269 reg = <0x03f60000 0x10000>; 1270 reg-names = "ctl"; 1271 1272 #phy-cells = <0>; 1273 }; 1274 1275 p2u_gbe_5: phy@3f70000 { 1276 compatible = "nvidia,tegra234-p2u"; 1277 reg = <0x03f70000 0x10000>; 1278 reg-names = "ctl"; 1279 1280 #phy-cells = <0>; 1281 }; 1282 1283 p2u_gbe_6: phy@3f80000 { 1284 compatible = "nvidia,tegra234-p2u"; 1285 reg = <0x03f80000 0x10000>; 1286 reg-names = "ctl"; 1287 1288 #phy-cells = <0>; 1289 }; 1290 1291 p2u_gbe_7: phy@3f90000 { 1292 compatible = "nvidia,tegra234-p2u"; 1293 reg = <0x03f90000 0x10000>; 1294 reg-names = "ctl"; 1295 1296 #phy-cells = <0>; 1297 }; 1298 1299 ethernet@6800000 { 1300 compatible = "nvidia,tegra234-mgbe"; 1301 reg = <0x06800000 0x10000>, 1302 <0x06810000 0x10000>, 1303 <0x068a0000 0x10000>; 1304 reg-names = "hypervisor", "mac", "xpcs"; 1305 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1306 interrupt-names = "common"; 1307 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1308 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1309 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1310 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1311 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1312 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1313 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1314 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1315 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1316 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1317 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1318 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1319 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1320 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1321 "rx-pcs", "tx-pcs"; 1322 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1323 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1324 reset-names = "mac", "pcs"; 1325 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1326 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1327 interconnect-names = "dma-mem", "write"; 1328 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1329 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1330 status = "disabled"; 1331 }; 1332 1333 ethernet@6900000 { 1334 compatible = "nvidia,tegra234-mgbe"; 1335 reg = <0x06900000 0x10000>, 1336 <0x06910000 0x10000>, 1337 <0x069a0000 0x10000>; 1338 reg-names = "hypervisor", "mac", "xpcs"; 1339 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1340 interrupt-names = "common"; 1341 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1342 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1343 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1344 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1345 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1346 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1347 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1348 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1349 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1350 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1351 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1352 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1353 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1354 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1355 "rx-pcs", "tx-pcs"; 1356 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1357 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1358 reset-names = "mac", "pcs"; 1359 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1360 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1361 interconnect-names = "dma-mem", "write"; 1362 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1363 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1364 status = "disabled"; 1365 }; 1366 1367 ethernet@6a00000 { 1368 compatible = "nvidia,tegra234-mgbe"; 1369 reg = <0x06a00000 0x10000>, 1370 <0x06a10000 0x10000>, 1371 <0x06aa0000 0x10000>; 1372 reg-names = "hypervisor", "mac", "xpcs"; 1373 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1374 interrupt-names = "common"; 1375 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1376 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1377 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1378 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1379 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1380 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1381 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1382 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1383 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1384 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1385 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1386 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1387 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1388 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1389 "rx-pcs", "tx-pcs"; 1390 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1391 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1392 reset-names = "mac", "pcs"; 1393 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1394 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1395 interconnect-names = "dma-mem", "write"; 1396 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1397 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1398 status = "disabled"; 1399 }; 1400 1401 ethernet@6b00000 { 1402 compatible = "nvidia,tegra234-mgbe"; 1403 reg = <0x06b00000 0x10000>, 1404 <0x06b10000 0x10000>, 1405 <0x06ba0000 0x10000>; 1406 reg-names = "hypervisor", "mac", "xpcs"; 1407 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1408 interrupt-names = "common"; 1409 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1410 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1411 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1412 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1413 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1414 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1415 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1416 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1417 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1418 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1419 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1420 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1421 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1422 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1423 "rx-pcs", "tx-pcs"; 1424 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1425 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1426 reset-names = "mac", "pcs"; 1427 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1428 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1429 interconnect-names = "dma-mem", "write"; 1430 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1431 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1432 status = "disabled"; 1433 }; 1434 1435 smmu_niso1: iommu@8000000 { 1436 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1437 reg = <0x8000000 0x1000000>, 1438 <0x7000000 0x1000000>; 1439 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1569 stream-match-mask = <0x7f80>; 1570 #global-interrupts = <2>; 1571 #iommu-cells = <1>; 1572 1573 nvidia,memory-controller = <&mc>; 1574 status = "okay"; 1575 }; 1576 1577 sce-fabric@b600000 { 1578 compatible = "nvidia,tegra234-sce-fabric"; 1579 reg = <0xb600000 0x40000>; 1580 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1581 status = "okay"; 1582 }; 1583 1584 rce-fabric@be00000 { 1585 compatible = "nvidia,tegra234-rce-fabric"; 1586 reg = <0xbe00000 0x40000>; 1587 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1588 status = "okay"; 1589 }; 1590 1591 hsp_aon: hsp@c150000 { 1592 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1593 reg = <0x0c150000 0x90000>; 1594 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1598 /* 1599 * Shared interrupt 0 is routed only to AON/SPE, so 1600 * we only have 4 shared interrupts for the CCPLEX. 1601 */ 1602 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1603 #mbox-cells = <2>; 1604 }; 1605 1606 gen2_i2c: i2c@c240000 { 1607 compatible = "nvidia,tegra194-i2c"; 1608 reg = <0xc240000 0x100>; 1609 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1610 status = "disabled"; 1611 clock-frequency = <100000>; 1612 clocks = <&bpmp TEGRA234_CLK_I2C2 1613 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1614 clock-names = "div-clk", "parent"; 1615 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1616 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1617 resets = <&bpmp TEGRA234_RESET_I2C2>; 1618 reset-names = "i2c"; 1619 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1620 dma-coherent; 1621 dmas = <&gpcdma 22>, <&gpcdma 22>; 1622 dma-names = "rx", "tx"; 1623 }; 1624 1625 gen8_i2c: i2c@c250000 { 1626 compatible = "nvidia,tegra194-i2c"; 1627 reg = <0xc250000 0x100>; 1628 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1629 status = "disabled"; 1630 clock-frequency = <400000>; 1631 clocks = <&bpmp TEGRA234_CLK_I2C8 1632 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1633 clock-names = "div-clk", "parent"; 1634 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1635 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1636 resets = <&bpmp TEGRA234_RESET_I2C8>; 1637 reset-names = "i2c"; 1638 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1639 dma-coherent; 1640 dmas = <&gpcdma 0>, <&gpcdma 0>; 1641 dma-names = "rx", "tx"; 1642 }; 1643 1644 rtc@c2a0000 { 1645 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1646 reg = <0x0c2a0000 0x10000>; 1647 interrupt-parent = <&pmc>; 1648 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1649 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1650 clock-names = "rtc"; 1651 status = "disabled"; 1652 }; 1653 1654 gpio_aon: gpio@c2f0000 { 1655 compatible = "nvidia,tegra234-gpio-aon"; 1656 reg-names = "security", "gpio"; 1657 reg = <0x0c2f0000 0x1000>, 1658 <0x0c2f1000 0x1000>; 1659 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1663 #interrupt-cells = <2>; 1664 interrupt-controller; 1665 #gpio-cells = <2>; 1666 gpio-controller; 1667 }; 1668 1669 pwm4: pwm@c340000 { 1670 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1671 reg = <0xc340000 0x10000>; 1672 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1673 resets = <&bpmp TEGRA234_RESET_PWM4>; 1674 reset-names = "pwm"; 1675 status = "disabled"; 1676 #pwm-cells = <2>; 1677 }; 1678 1679 pmc: pmc@c360000 { 1680 compatible = "nvidia,tegra234-pmc"; 1681 reg = <0x0c360000 0x10000>, 1682 <0x0c370000 0x10000>, 1683 <0x0c380000 0x10000>, 1684 <0x0c390000 0x10000>, 1685 <0x0c3a0000 0x10000>; 1686 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1687 1688 #interrupt-cells = <2>; 1689 interrupt-controller; 1690 1691 sdmmc1_3v3: sdmmc1-3v3 { 1692 pins = "sdmmc1-hv"; 1693 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1694 }; 1695 1696 sdmmc1_1v8: sdmmc1-1v8 { 1697 pins = "sdmmc1-hv"; 1698 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1699 }; 1700 1701 sdmmc3_3v3: sdmmc3-3v3 { 1702 pins = "sdmmc3-hv"; 1703 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1704 }; 1705 1706 sdmmc3_1v8: sdmmc3-1v8 { 1707 pins = "sdmmc3-hv"; 1708 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1709 }; 1710 }; 1711 1712 aon-fabric@c600000 { 1713 compatible = "nvidia,tegra234-aon-fabric"; 1714 reg = <0xc600000 0x40000>; 1715 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1716 status = "okay"; 1717 }; 1718 1719 bpmp-fabric@d600000 { 1720 compatible = "nvidia,tegra234-bpmp-fabric"; 1721 reg = <0xd600000 0x40000>; 1722 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1723 status = "okay"; 1724 }; 1725 1726 dce-fabric@de00000 { 1727 compatible = "nvidia,tegra234-sce-fabric"; 1728 reg = <0xde00000 0x40000>; 1729 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1730 status = "okay"; 1731 }; 1732 1733 gic: interrupt-controller@f400000 { 1734 compatible = "arm,gic-v3"; 1735 reg = <0x0f400000 0x010000>, /* GICD */ 1736 <0x0f440000 0x200000>; /* GICR */ 1737 interrupt-parent = <&gic>; 1738 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1739 1740 #redistributor-regions = <1>; 1741 #interrupt-cells = <3>; 1742 interrupt-controller; 1743 }; 1744 1745 smmu_iso: iommu@10000000 { 1746 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1747 reg = <0x10000000 0x1000000>; 1748 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1877 stream-match-mask = <0x7f80>; 1878 #global-interrupts = <1>; 1879 #iommu-cells = <1>; 1880 1881 nvidia,memory-controller = <&mc>; 1882 status = "okay"; 1883 }; 1884 1885 smmu_niso0: iommu@12000000 { 1886 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1887 reg = <0x12000000 0x1000000>, 1888 <0x11000000 0x1000000>; 1889 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2019 stream-match-mask = <0x7f80>; 2020 #global-interrupts = <2>; 2021 #iommu-cells = <1>; 2022 2023 nvidia,memory-controller = <&mc>; 2024 status = "okay"; 2025 }; 2026 2027 cbb-fabric@13a00000 { 2028 compatible = "nvidia,tegra234-cbb-fabric"; 2029 reg = <0x13a00000 0x400000>; 2030 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2031 status = "okay"; 2032 }; 2033 }; 2034 2035 ccplex@e000000 { 2036 compatible = "nvidia,tegra234-ccplex-cluster"; 2037 reg = <0x0 0x0e000000 0x0 0x5ffff>; 2038 nvidia,bpmp = <&bpmp>; 2039 status = "okay"; 2040 }; 2041 2042 pcie@140a0000 { 2043 compatible = "nvidia,tegra234-pcie"; 2044 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2045 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2046 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2047 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2048 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2049 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2050 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2051 2052 #address-cells = <3>; 2053 #size-cells = <2>; 2054 device_type = "pci"; 2055 num-lanes = <4>; 2056 num-viewport = <8>; 2057 linux,pci-domain = <8>; 2058 2059 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2060 clock-names = "core"; 2061 2062 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2063 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2064 reset-names = "apb", "core"; 2065 2066 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2067 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2068 interrupt-names = "intr", "msi"; 2069 2070 #interrupt-cells = <1>; 2071 interrupt-map-mask = <0 0 0 0>; 2072 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2073 2074 nvidia,bpmp = <&bpmp 8>; 2075 2076 nvidia,aspm-cmrt-us = <60>; 2077 nvidia,aspm-pwr-on-t-us = <20>; 2078 nvidia,aspm-l0s-entrance-latency-us = <3>; 2079 2080 bus-range = <0x0 0xff>; 2081 2082 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2083 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2084 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2085 2086 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2087 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2088 interconnect-names = "dma-mem", "write"; 2089 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2090 iommu-map-mask = <0x0>; 2091 dma-coherent; 2092 2093 status = "disabled"; 2094 }; 2095 2096 pcie@140c0000 { 2097 compatible = "nvidia,tegra234-pcie"; 2098 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2099 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2100 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2101 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2102 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2103 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2104 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2105 2106 #address-cells = <3>; 2107 #size-cells = <2>; 2108 device_type = "pci"; 2109 num-lanes = <4>; 2110 num-viewport = <8>; 2111 linux,pci-domain = <9>; 2112 2113 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2114 clock-names = "core"; 2115 2116 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2117 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2118 reset-names = "apb", "core"; 2119 2120 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2121 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2122 interrupt-names = "intr", "msi"; 2123 2124 #interrupt-cells = <1>; 2125 interrupt-map-mask = <0 0 0 0>; 2126 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2127 2128 nvidia,bpmp = <&bpmp 9>; 2129 2130 nvidia,aspm-cmrt-us = <60>; 2131 nvidia,aspm-pwr-on-t-us = <20>; 2132 nvidia,aspm-l0s-entrance-latency-us = <3>; 2133 2134 bus-range = <0x0 0xff>; 2135 2136 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2137 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2138 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2139 2140 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2141 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2142 interconnect-names = "dma-mem", "write"; 2143 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2144 iommu-map-mask = <0x0>; 2145 dma-coherent; 2146 2147 status = "disabled"; 2148 }; 2149 2150 pcie@140e0000 { 2151 compatible = "nvidia,tegra234-pcie"; 2152 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2153 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2154 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2155 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2156 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2157 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2158 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2159 2160 #address-cells = <3>; 2161 #size-cells = <2>; 2162 device_type = "pci"; 2163 num-lanes = <4>; 2164 num-viewport = <8>; 2165 linux,pci-domain = <10>; 2166 2167 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2168 clock-names = "core"; 2169 2170 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2171 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2172 reset-names = "apb", "core"; 2173 2174 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2175 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2176 interrupt-names = "intr", "msi"; 2177 2178 #interrupt-cells = <1>; 2179 interrupt-map-mask = <0 0 0 0>; 2180 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2181 2182 nvidia,bpmp = <&bpmp 10>; 2183 2184 nvidia,aspm-cmrt-us = <60>; 2185 nvidia,aspm-pwr-on-t-us = <20>; 2186 nvidia,aspm-l0s-entrance-latency-us = <3>; 2187 2188 bus-range = <0x0 0xff>; 2189 2190 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2191 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2192 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2193 2194 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2195 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2196 interconnect-names = "dma-mem", "write"; 2197 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2198 iommu-map-mask = <0x0>; 2199 dma-coherent; 2200 2201 status = "disabled"; 2202 }; 2203 2204 pcie@14100000 { 2205 compatible = "nvidia,tegra234-pcie"; 2206 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2207 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2208 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2209 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2210 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2211 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2212 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2213 2214 #address-cells = <3>; 2215 #size-cells = <2>; 2216 device_type = "pci"; 2217 num-lanes = <1>; 2218 num-viewport = <8>; 2219 linux,pci-domain = <1>; 2220 2221 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2222 clock-names = "core"; 2223 2224 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2225 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2226 reset-names = "apb", "core"; 2227 2228 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2229 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2230 interrupt-names = "intr", "msi"; 2231 2232 #interrupt-cells = <1>; 2233 interrupt-map-mask = <0 0 0 0>; 2234 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2235 2236 nvidia,bpmp = <&bpmp 1>; 2237 2238 nvidia,aspm-cmrt-us = <60>; 2239 nvidia,aspm-pwr-on-t-us = <20>; 2240 nvidia,aspm-l0s-entrance-latency-us = <3>; 2241 2242 bus-range = <0x0 0xff>; 2243 2244 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2245 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2246 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2247 2248 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2249 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2250 interconnect-names = "dma-mem", "write"; 2251 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2252 iommu-map-mask = <0x0>; 2253 dma-coherent; 2254 2255 status = "disabled"; 2256 }; 2257 2258 pcie@14120000 { 2259 compatible = "nvidia,tegra234-pcie"; 2260 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2261 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2262 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2263 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2264 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2265 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2266 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2267 2268 #address-cells = <3>; 2269 #size-cells = <2>; 2270 device_type = "pci"; 2271 num-lanes = <1>; 2272 num-viewport = <8>; 2273 linux,pci-domain = <2>; 2274 2275 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2276 clock-names = "core"; 2277 2278 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2279 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2280 reset-names = "apb", "core"; 2281 2282 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2283 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2284 interrupt-names = "intr", "msi"; 2285 2286 #interrupt-cells = <1>; 2287 interrupt-map-mask = <0 0 0 0>; 2288 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2289 2290 nvidia,bpmp = <&bpmp 2>; 2291 2292 nvidia,aspm-cmrt-us = <60>; 2293 nvidia,aspm-pwr-on-t-us = <20>; 2294 nvidia,aspm-l0s-entrance-latency-us = <3>; 2295 2296 bus-range = <0x0 0xff>; 2297 2298 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2299 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2300 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2301 2302 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2303 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2304 interconnect-names = "dma-mem", "write"; 2305 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2306 iommu-map-mask = <0x0>; 2307 dma-coherent; 2308 2309 status = "disabled"; 2310 }; 2311 2312 pcie@14140000 { 2313 compatible = "nvidia,tegra234-pcie"; 2314 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2315 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2316 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2317 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2318 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2319 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2320 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2321 2322 #address-cells = <3>; 2323 #size-cells = <2>; 2324 device_type = "pci"; 2325 num-lanes = <1>; 2326 num-viewport = <8>; 2327 linux,pci-domain = <3>; 2328 2329 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2330 clock-names = "core"; 2331 2332 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2333 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2334 reset-names = "apb", "core"; 2335 2336 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2337 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2338 interrupt-names = "intr", "msi"; 2339 2340 #interrupt-cells = <1>; 2341 interrupt-map-mask = <0 0 0 0>; 2342 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2343 2344 nvidia,bpmp = <&bpmp 3>; 2345 2346 nvidia,aspm-cmrt-us = <60>; 2347 nvidia,aspm-pwr-on-t-us = <20>; 2348 nvidia,aspm-l0s-entrance-latency-us = <3>; 2349 2350 bus-range = <0x0 0xff>; 2351 2352 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2353 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2354 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2355 2356 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2357 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2358 interconnect-names = "dma-mem", "write"; 2359 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2360 iommu-map-mask = <0x0>; 2361 dma-coherent; 2362 2363 status = "disabled"; 2364 }; 2365 2366 pcie@14160000 { 2367 compatible = "nvidia,tegra234-pcie"; 2368 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2369 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2370 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2371 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2372 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2373 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2374 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2375 2376 #address-cells = <3>; 2377 #size-cells = <2>; 2378 device_type = "pci"; 2379 num-lanes = <4>; 2380 num-viewport = <8>; 2381 linux,pci-domain = <4>; 2382 2383 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2384 clock-names = "core"; 2385 2386 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2387 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2388 reset-names = "apb", "core"; 2389 2390 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2391 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2392 interrupt-names = "intr", "msi"; 2393 2394 #interrupt-cells = <1>; 2395 interrupt-map-mask = <0 0 0 0>; 2396 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2397 2398 nvidia,bpmp = <&bpmp 4>; 2399 2400 nvidia,aspm-cmrt-us = <60>; 2401 nvidia,aspm-pwr-on-t-us = <20>; 2402 nvidia,aspm-l0s-entrance-latency-us = <3>; 2403 2404 bus-range = <0x0 0xff>; 2405 2406 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2407 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2408 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2409 2410 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2411 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2412 interconnect-names = "dma-mem", "write"; 2413 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2414 iommu-map-mask = <0x0>; 2415 dma-coherent; 2416 2417 status = "disabled"; 2418 }; 2419 2420 pcie@14180000 { 2421 compatible = "nvidia,tegra234-pcie"; 2422 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2423 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2424 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2425 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2426 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2427 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2428 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2429 2430 #address-cells = <3>; 2431 #size-cells = <2>; 2432 device_type = "pci"; 2433 num-lanes = <4>; 2434 num-viewport = <8>; 2435 linux,pci-domain = <0>; 2436 2437 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2438 clock-names = "core"; 2439 2440 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2441 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2442 reset-names = "apb", "core"; 2443 2444 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2445 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2446 interrupt-names = "intr", "msi"; 2447 2448 #interrupt-cells = <1>; 2449 interrupt-map-mask = <0 0 0 0>; 2450 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2451 2452 nvidia,bpmp = <&bpmp 0>; 2453 2454 nvidia,aspm-cmrt-us = <60>; 2455 nvidia,aspm-pwr-on-t-us = <20>; 2456 nvidia,aspm-l0s-entrance-latency-us = <3>; 2457 2458 bus-range = <0x0 0xff>; 2459 2460 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2461 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2462 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2463 2464 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2465 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2466 interconnect-names = "dma-mem", "write"; 2467 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2468 iommu-map-mask = <0x0>; 2469 dma-coherent; 2470 2471 status = "disabled"; 2472 }; 2473 2474 pcie@141a0000 { 2475 compatible = "nvidia,tegra234-pcie"; 2476 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2477 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2478 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2479 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2480 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2481 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2482 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2483 2484 #address-cells = <3>; 2485 #size-cells = <2>; 2486 device_type = "pci"; 2487 num-lanes = <8>; 2488 num-viewport = <8>; 2489 linux,pci-domain = <5>; 2490 2491 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2492 clock-names = "core"; 2493 2494 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2495 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2496 reset-names = "apb", "core"; 2497 2498 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2499 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2500 interrupt-names = "intr", "msi"; 2501 2502 #interrupt-cells = <1>; 2503 interrupt-map-mask = <0 0 0 0>; 2504 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2505 2506 nvidia,bpmp = <&bpmp 5>; 2507 2508 nvidia,aspm-cmrt-us = <60>; 2509 nvidia,aspm-pwr-on-t-us = <20>; 2510 nvidia,aspm-l0s-entrance-latency-us = <3>; 2511 2512 bus-range = <0x0 0xff>; 2513 2514 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2515 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2516 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2517 2518 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2519 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2520 interconnect-names = "dma-mem", "write"; 2521 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2522 iommu-map-mask = <0x0>; 2523 dma-coherent; 2524 2525 status = "disabled"; 2526 }; 2527 2528 pcie@141c0000 { 2529 compatible = "nvidia,tegra234-pcie"; 2530 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2531 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2532 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2533 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2534 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2535 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2536 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2537 2538 #address-cells = <3>; 2539 #size-cells = <2>; 2540 device_type = "pci"; 2541 num-lanes = <4>; 2542 num-viewport = <8>; 2543 linux,pci-domain = <6>; 2544 2545 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2546 clock-names = "core"; 2547 2548 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2549 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2550 reset-names = "apb", "core"; 2551 2552 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2553 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2554 interrupt-names = "intr", "msi"; 2555 2556 #interrupt-cells = <1>; 2557 interrupt-map-mask = <0 0 0 0>; 2558 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2559 2560 nvidia,bpmp = <&bpmp 6>; 2561 2562 nvidia,aspm-cmrt-us = <60>; 2563 nvidia,aspm-pwr-on-t-us = <20>; 2564 nvidia,aspm-l0s-entrance-latency-us = <3>; 2565 2566 bus-range = <0x0 0xff>; 2567 2568 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2569 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2570 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2571 2572 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2573 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2574 interconnect-names = "dma-mem", "write"; 2575 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2576 iommu-map-mask = <0x0>; 2577 dma-coherent; 2578 2579 status = "disabled"; 2580 }; 2581 2582 pcie@141e0000 { 2583 compatible = "nvidia,tegra234-pcie"; 2584 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2585 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2586 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2587 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2588 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2589 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2590 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2591 2592 #address-cells = <3>; 2593 #size-cells = <2>; 2594 device_type = "pci"; 2595 num-lanes = <8>; 2596 num-viewport = <8>; 2597 linux,pci-domain = <7>; 2598 2599 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2600 clock-names = "core"; 2601 2602 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2603 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2604 reset-names = "apb", "core"; 2605 2606 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2607 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2608 interrupt-names = "intr", "msi"; 2609 2610 #interrupt-cells = <1>; 2611 interrupt-map-mask = <0 0 0 0>; 2612 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2613 2614 nvidia,bpmp = <&bpmp 7>; 2615 2616 nvidia,aspm-cmrt-us = <60>; 2617 nvidia,aspm-pwr-on-t-us = <20>; 2618 nvidia,aspm-l0s-entrance-latency-us = <3>; 2619 2620 bus-range = <0x0 0xff>; 2621 2622 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2623 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2624 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2625 2626 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2627 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2628 interconnect-names = "dma-mem", "write"; 2629 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2630 iommu-map-mask = <0x0>; 2631 dma-coherent; 2632 2633 status = "disabled"; 2634 }; 2635 2636 pcie-ep@141a0000 { 2637 compatible = "nvidia,tegra234-pcie-ep"; 2638 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2639 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2640 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2641 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2642 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2643 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2644 2645 num-lanes = <8>; 2646 2647 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2648 clock-names = "core"; 2649 2650 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2651 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2652 reset-names = "apb", "core"; 2653 2654 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2655 interrupt-names = "intr"; 2656 2657 nvidia,bpmp = <&bpmp 5>; 2658 2659 nvidia,enable-ext-refclk; 2660 nvidia,aspm-cmrt-us = <60>; 2661 nvidia,aspm-pwr-on-t-us = <20>; 2662 nvidia,aspm-l0s-entrance-latency-us = <3>; 2663 2664 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2665 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2666 interconnect-names = "dma-mem", "write"; 2667 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2668 iommu-map-mask = <0x0>; 2669 dma-coherent; 2670 2671 status = "disabled"; 2672 }; 2673 2674 pcie-ep@141c0000{ 2675 compatible = "nvidia,tegra234-pcie-ep"; 2676 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2677 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2678 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2679 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2680 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2681 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2682 2683 num-lanes = <4>; 2684 2685 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2686 clock-names = "core"; 2687 2688 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2689 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2690 reset-names = "apb", "core"; 2691 2692 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2693 interrupt-names = "intr"; 2694 2695 nvidia,bpmp = <&bpmp 6>; 2696 2697 nvidia,enable-ext-refclk; 2698 nvidia,aspm-cmrt-us = <60>; 2699 nvidia,aspm-pwr-on-t-us = <20>; 2700 nvidia,aspm-l0s-entrance-latency-us = <3>; 2701 2702 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2703 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2704 interconnect-names = "dma-mem", "write"; 2705 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2706 iommu-map-mask = <0x0>; 2707 dma-coherent; 2708 2709 status = "disabled"; 2710 }; 2711 2712 pcie-ep@141e0000{ 2713 compatible = "nvidia,tegra234-pcie-ep"; 2714 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2715 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2716 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2717 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2718 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2719 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2720 2721 num-lanes = <8>; 2722 2723 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2724 clock-names = "core"; 2725 2726 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2727 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2728 reset-names = "apb", "core"; 2729 2730 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2731 interrupt-names = "intr"; 2732 2733 nvidia,bpmp = <&bpmp 7>; 2734 2735 nvidia,enable-ext-refclk; 2736 nvidia,aspm-cmrt-us = <60>; 2737 nvidia,aspm-pwr-on-t-us = <20>; 2738 nvidia,aspm-l0s-entrance-latency-us = <3>; 2739 2740 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2741 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2742 interconnect-names = "dma-mem", "write"; 2743 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2744 iommu-map-mask = <0x0>; 2745 dma-coherent; 2746 2747 status = "disabled"; 2748 }; 2749 2750 pcie-ep@140e0000{ 2751 compatible = "nvidia,tegra234-pcie-ep"; 2752 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2753 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2754 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2755 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2756 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2757 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2758 2759 num-lanes = <4>; 2760 2761 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2762 clock-names = "core"; 2763 2764 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2765 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2766 reset-names = "apb", "core"; 2767 2768 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2769 interrupt-names = "intr"; 2770 2771 nvidia,bpmp = <&bpmp 10>; 2772 2773 nvidia,enable-ext-refclk; 2774 nvidia,aspm-cmrt-us = <60>; 2775 nvidia,aspm-pwr-on-t-us = <20>; 2776 nvidia,aspm-l0s-entrance-latency-us = <3>; 2777 2778 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2779 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2780 interconnect-names = "dma-mem", "write"; 2781 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2782 iommu-map-mask = <0x0>; 2783 dma-coherent; 2784 2785 status = "disabled"; 2786 }; 2787 2788 sram@40000000 { 2789 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2790 reg = <0x0 0x40000000 0x0 0x80000>; 2791 #address-cells = <1>; 2792 #size-cells = <1>; 2793 ranges = <0x0 0x0 0x40000000 0x80000>; 2794 no-memory-wc; 2795 2796 cpu_bpmp_tx: sram@70000 { 2797 reg = <0x70000 0x1000>; 2798 label = "cpu-bpmp-tx"; 2799 pool; 2800 }; 2801 2802 cpu_bpmp_rx: sram@71000 { 2803 reg = <0x71000 0x1000>; 2804 label = "cpu-bpmp-rx"; 2805 pool; 2806 }; 2807 }; 2808 2809 bpmp: bpmp { 2810 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2811 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2812 TEGRA_HSP_DB_MASTER_BPMP>; 2813 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2814 #clock-cells = <1>; 2815 #reset-cells = <1>; 2816 #power-domain-cells = <1>; 2817 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 2818 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 2819 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 2820 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 2821 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2822 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 2823 2824 bpmp_i2c: i2c { 2825 compatible = "nvidia,tegra186-bpmp-i2c"; 2826 nvidia,bpmp-bus-id = <5>; 2827 #address-cells = <1>; 2828 #size-cells = <0>; 2829 }; 2830 }; 2831 2832 cpus { 2833 #address-cells = <1>; 2834 #size-cells = <0>; 2835 2836 cpu0_0: cpu@0 { 2837 compatible = "arm,cortex-a78"; 2838 device_type = "cpu"; 2839 reg = <0x00000>; 2840 2841 enable-method = "psci"; 2842 2843 i-cache-size = <65536>; 2844 i-cache-line-size = <64>; 2845 i-cache-sets = <256>; 2846 d-cache-size = <65536>; 2847 d-cache-line-size = <64>; 2848 d-cache-sets = <256>; 2849 next-level-cache = <&l2c0_0>; 2850 }; 2851 2852 cpu0_1: cpu@100 { 2853 compatible = "arm,cortex-a78"; 2854 device_type = "cpu"; 2855 reg = <0x00100>; 2856 2857 enable-method = "psci"; 2858 2859 i-cache-size = <65536>; 2860 i-cache-line-size = <64>; 2861 i-cache-sets = <256>; 2862 d-cache-size = <65536>; 2863 d-cache-line-size = <64>; 2864 d-cache-sets = <256>; 2865 next-level-cache = <&l2c0_1>; 2866 }; 2867 2868 cpu0_2: cpu@200 { 2869 compatible = "arm,cortex-a78"; 2870 device_type = "cpu"; 2871 reg = <0x00200>; 2872 2873 enable-method = "psci"; 2874 2875 i-cache-size = <65536>; 2876 i-cache-line-size = <64>; 2877 i-cache-sets = <256>; 2878 d-cache-size = <65536>; 2879 d-cache-line-size = <64>; 2880 d-cache-sets = <256>; 2881 next-level-cache = <&l2c0_2>; 2882 }; 2883 2884 cpu0_3: cpu@300 { 2885 compatible = "arm,cortex-a78"; 2886 device_type = "cpu"; 2887 reg = <0x00300>; 2888 2889 enable-method = "psci"; 2890 2891 i-cache-size = <65536>; 2892 i-cache-line-size = <64>; 2893 i-cache-sets = <256>; 2894 d-cache-size = <65536>; 2895 d-cache-line-size = <64>; 2896 d-cache-sets = <256>; 2897 next-level-cache = <&l2c0_3>; 2898 }; 2899 2900 cpu1_0: cpu@10000 { 2901 compatible = "arm,cortex-a78"; 2902 device_type = "cpu"; 2903 reg = <0x10000>; 2904 2905 enable-method = "psci"; 2906 2907 i-cache-size = <65536>; 2908 i-cache-line-size = <64>; 2909 i-cache-sets = <256>; 2910 d-cache-size = <65536>; 2911 d-cache-line-size = <64>; 2912 d-cache-sets = <256>; 2913 next-level-cache = <&l2c1_0>; 2914 }; 2915 2916 cpu1_1: cpu@10100 { 2917 compatible = "arm,cortex-a78"; 2918 device_type = "cpu"; 2919 reg = <0x10100>; 2920 2921 enable-method = "psci"; 2922 2923 i-cache-size = <65536>; 2924 i-cache-line-size = <64>; 2925 i-cache-sets = <256>; 2926 d-cache-size = <65536>; 2927 d-cache-line-size = <64>; 2928 d-cache-sets = <256>; 2929 next-level-cache = <&l2c1_1>; 2930 }; 2931 2932 cpu1_2: cpu@10200 { 2933 compatible = "arm,cortex-a78"; 2934 device_type = "cpu"; 2935 reg = <0x10200>; 2936 2937 enable-method = "psci"; 2938 2939 i-cache-size = <65536>; 2940 i-cache-line-size = <64>; 2941 i-cache-sets = <256>; 2942 d-cache-size = <65536>; 2943 d-cache-line-size = <64>; 2944 d-cache-sets = <256>; 2945 next-level-cache = <&l2c1_2>; 2946 }; 2947 2948 cpu1_3: cpu@10300 { 2949 compatible = "arm,cortex-a78"; 2950 device_type = "cpu"; 2951 reg = <0x10300>; 2952 2953 enable-method = "psci"; 2954 2955 i-cache-size = <65536>; 2956 i-cache-line-size = <64>; 2957 i-cache-sets = <256>; 2958 d-cache-size = <65536>; 2959 d-cache-line-size = <64>; 2960 d-cache-sets = <256>; 2961 next-level-cache = <&l2c1_3>; 2962 }; 2963 2964 cpu2_0: cpu@20000 { 2965 compatible = "arm,cortex-a78"; 2966 device_type = "cpu"; 2967 reg = <0x20000>; 2968 2969 enable-method = "psci"; 2970 2971 i-cache-size = <65536>; 2972 i-cache-line-size = <64>; 2973 i-cache-sets = <256>; 2974 d-cache-size = <65536>; 2975 d-cache-line-size = <64>; 2976 d-cache-sets = <256>; 2977 next-level-cache = <&l2c2_0>; 2978 }; 2979 2980 cpu2_1: cpu@20100 { 2981 compatible = "arm,cortex-a78"; 2982 device_type = "cpu"; 2983 reg = <0x20100>; 2984 2985 enable-method = "psci"; 2986 2987 i-cache-size = <65536>; 2988 i-cache-line-size = <64>; 2989 i-cache-sets = <256>; 2990 d-cache-size = <65536>; 2991 d-cache-line-size = <64>; 2992 d-cache-sets = <256>; 2993 next-level-cache = <&l2c2_1>; 2994 }; 2995 2996 cpu2_2: cpu@20200 { 2997 compatible = "arm,cortex-a78"; 2998 device_type = "cpu"; 2999 reg = <0x20200>; 3000 3001 enable-method = "psci"; 3002 3003 i-cache-size = <65536>; 3004 i-cache-line-size = <64>; 3005 i-cache-sets = <256>; 3006 d-cache-size = <65536>; 3007 d-cache-line-size = <64>; 3008 d-cache-sets = <256>; 3009 next-level-cache = <&l2c2_2>; 3010 }; 3011 3012 cpu2_3: cpu@20300 { 3013 compatible = "arm,cortex-a78"; 3014 device_type = "cpu"; 3015 reg = <0x20300>; 3016 3017 enable-method = "psci"; 3018 3019 i-cache-size = <65536>; 3020 i-cache-line-size = <64>; 3021 i-cache-sets = <256>; 3022 d-cache-size = <65536>; 3023 d-cache-line-size = <64>; 3024 d-cache-sets = <256>; 3025 next-level-cache = <&l2c2_3>; 3026 }; 3027 3028 cpu-map { 3029 cluster0 { 3030 core0 { 3031 cpu = <&cpu0_0>; 3032 }; 3033 3034 core1 { 3035 cpu = <&cpu0_1>; 3036 }; 3037 3038 core2 { 3039 cpu = <&cpu0_2>; 3040 }; 3041 3042 core3 { 3043 cpu = <&cpu0_3>; 3044 }; 3045 }; 3046 3047 cluster1 { 3048 core0 { 3049 cpu = <&cpu1_0>; 3050 }; 3051 3052 core1 { 3053 cpu = <&cpu1_1>; 3054 }; 3055 3056 core2 { 3057 cpu = <&cpu1_2>; 3058 }; 3059 3060 core3 { 3061 cpu = <&cpu1_3>; 3062 }; 3063 }; 3064 3065 cluster2 { 3066 core0 { 3067 cpu = <&cpu2_0>; 3068 }; 3069 3070 core1 { 3071 cpu = <&cpu2_1>; 3072 }; 3073 3074 core2 { 3075 cpu = <&cpu2_2>; 3076 }; 3077 3078 core3 { 3079 cpu = <&cpu2_3>; 3080 }; 3081 }; 3082 }; 3083 3084 l2c0_0: l2-cache00 { 3085 compatible = "cache"; 3086 cache-size = <262144>; 3087 cache-line-size = <64>; 3088 cache-sets = <512>; 3089 cache-unified; 3090 cache-level = <2>; 3091 next-level-cache = <&l3c0>; 3092 }; 3093 3094 l2c0_1: l2-cache01 { 3095 compatible = "cache"; 3096 cache-size = <262144>; 3097 cache-line-size = <64>; 3098 cache-sets = <512>; 3099 cache-unified; 3100 cache-level = <2>; 3101 next-level-cache = <&l3c0>; 3102 }; 3103 3104 l2c0_2: l2-cache02 { 3105 compatible = "cache"; 3106 cache-size = <262144>; 3107 cache-line-size = <64>; 3108 cache-sets = <512>; 3109 cache-unified; 3110 cache-level = <2>; 3111 next-level-cache = <&l3c0>; 3112 }; 3113 3114 l2c0_3: l2-cache03 { 3115 compatible = "cache"; 3116 cache-size = <262144>; 3117 cache-line-size = <64>; 3118 cache-sets = <512>; 3119 cache-unified; 3120 cache-level = <2>; 3121 next-level-cache = <&l3c0>; 3122 }; 3123 3124 l2c1_0: l2-cache10 { 3125 compatible = "cache"; 3126 cache-size = <262144>; 3127 cache-line-size = <64>; 3128 cache-sets = <512>; 3129 cache-unified; 3130 cache-level = <2>; 3131 next-level-cache = <&l3c1>; 3132 }; 3133 3134 l2c1_1: l2-cache11 { 3135 compatible = "cache"; 3136 cache-size = <262144>; 3137 cache-line-size = <64>; 3138 cache-sets = <512>; 3139 cache-unified; 3140 cache-level = <2>; 3141 next-level-cache = <&l3c1>; 3142 }; 3143 3144 l2c1_2: l2-cache12 { 3145 compatible = "cache"; 3146 cache-size = <262144>; 3147 cache-line-size = <64>; 3148 cache-sets = <512>; 3149 cache-unified; 3150 cache-level = <2>; 3151 next-level-cache = <&l3c1>; 3152 }; 3153 3154 l2c1_3: l2-cache13 { 3155 compatible = "cache"; 3156 cache-size = <262144>; 3157 cache-line-size = <64>; 3158 cache-sets = <512>; 3159 cache-unified; 3160 cache-level = <2>; 3161 next-level-cache = <&l3c1>; 3162 }; 3163 3164 l2c2_0: l2-cache20 { 3165 compatible = "cache"; 3166 cache-size = <262144>; 3167 cache-line-size = <64>; 3168 cache-sets = <512>; 3169 cache-unified; 3170 cache-level = <2>; 3171 next-level-cache = <&l3c2>; 3172 }; 3173 3174 l2c2_1: l2-cache21 { 3175 compatible = "cache"; 3176 cache-size = <262144>; 3177 cache-line-size = <64>; 3178 cache-sets = <512>; 3179 cache-unified; 3180 cache-level = <2>; 3181 next-level-cache = <&l3c2>; 3182 }; 3183 3184 l2c2_2: l2-cache22 { 3185 compatible = "cache"; 3186 cache-size = <262144>; 3187 cache-line-size = <64>; 3188 cache-sets = <512>; 3189 cache-unified; 3190 cache-level = <2>; 3191 next-level-cache = <&l3c2>; 3192 }; 3193 3194 l2c2_3: l2-cache23 { 3195 compatible = "cache"; 3196 cache-size = <262144>; 3197 cache-line-size = <64>; 3198 cache-sets = <512>; 3199 cache-unified; 3200 cache-level = <2>; 3201 next-level-cache = <&l3c2>; 3202 }; 3203 3204 l3c0: l3-cache0 { 3205 compatible = "cache"; 3206 cache-unified; 3207 cache-size = <2097152>; 3208 cache-line-size = <64>; 3209 cache-sets = <2048>; 3210 cache-level = <3>; 3211 }; 3212 3213 l3c1: l3-cache1 { 3214 compatible = "cache"; 3215 cache-unified; 3216 cache-size = <2097152>; 3217 cache-line-size = <64>; 3218 cache-sets = <2048>; 3219 cache-level = <3>; 3220 }; 3221 3222 l3c2: l3-cache2 { 3223 compatible = "cache"; 3224 cache-unified; 3225 cache-size = <2097152>; 3226 cache-line-size = <64>; 3227 cache-sets = <2048>; 3228 cache-level = <3>; 3229 }; 3230 }; 3231 3232 pmu { 3233 compatible = "arm,cortex-a78-pmu"; 3234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3235 status = "okay"; 3236 }; 3237 3238 psci { 3239 compatible = "arm,psci-1.0"; 3240 status = "okay"; 3241 method = "smc"; 3242 }; 3243 3244 tcu: serial { 3245 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3246 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3247 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3248 mbox-names = "rx", "tx"; 3249 status = "disabled"; 3250 }; 3251 3252 sound { 3253 status = "disabled"; 3254 3255 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3256 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3257 clock-names = "pll_a", "plla_out0"; 3258 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3259 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3260 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3261 assigned-clock-parents = <0>, 3262 <&bpmp TEGRA234_CLK_PLLA>, 3263 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3264 }; 3265 3266 timer { 3267 compatible = "arm,armv8-timer"; 3268 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3269 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3270 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3271 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3272 interrupt-parent = <&gic>; 3273 always-on; 3274 }; 3275}; 3276