1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra234-misc"; 27 reg = <0x0 0x00100000 0x0 0xf000>, 28 <0x0 0x0010f000 0x0 0x1000>; 29 status = "okay"; 30 }; 31 32 timer@2080000 { 33 compatible = "nvidia,tegra234-timer"; 34 reg = <0x0 0x02080000 0x0 0x00121000>; 35 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51 status = "okay"; 52 }; 53 54 gpio: gpio@2200000 { 55 compatible = "nvidia,tegra234-gpio"; 56 reg-names = "security", "gpio"; 57 reg = <0x0 0x02200000 0x0 0x10000>, 58 <0x0 0x02210000 0x0 0x10000>; 59 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 #gpio-cells = <2>; 110 gpio-controller; 111 }; 112 113 gpcdma: dma-controller@2600000 { 114 compatible = "nvidia,tegra234-gpcdma", 115 "nvidia,tegra186-gpcdma"; 116 reg = <0x0 0x2600000 0x0 0x210000>; 117 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 118 reset-names = "gpcdma"; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153 dma-channel-mask = <0xfffffffe>; 154 dma-coherent; 155 }; 156 157 aconnect@2900000 { 158 compatible = "nvidia,tegra234-aconnect", 159 "nvidia,tegra210-aconnect"; 160 clocks = <&bpmp TEGRA234_CLK_APE>, 161 <&bpmp TEGRA234_CLK_APB2APE>; 162 clock-names = "ape", "apb2ape"; 163 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164 status = "disabled"; 165 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 169 170 tegra_ahub: ahub@2900800 { 171 compatible = "nvidia,tegra234-ahub"; 172 reg = <0x0 0x02900800 0x0 0x800>; 173 clocks = <&bpmp TEGRA234_CLK_AHUB>; 174 clock-names = "ahub"; 175 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177 status = "disabled"; 178 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 182 183 tegra_i2s1: i2s@2901000 { 184 compatible = "nvidia,tegra234-i2s", 185 "nvidia,tegra210-i2s"; 186 reg = <0x0 0x2901000 0x0 0x100>; 187 clocks = <&bpmp TEGRA234_CLK_I2S1>, 188 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189 clock-names = "i2s", "sync_input"; 190 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192 assigned-clock-rates = <1536000>; 193 sound-name-prefix = "I2S1"; 194 status = "disabled"; 195 }; 196 197 tegra_i2s2: i2s@2901100 { 198 compatible = "nvidia,tegra234-i2s", 199 "nvidia,tegra210-i2s"; 200 reg = <0x0 0x2901100 0x0 0x100>; 201 clocks = <&bpmp TEGRA234_CLK_I2S2>, 202 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203 clock-names = "i2s", "sync_input"; 204 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206 assigned-clock-rates = <1536000>; 207 sound-name-prefix = "I2S2"; 208 status = "disabled"; 209 }; 210 211 tegra_i2s3: i2s@2901200 { 212 compatible = "nvidia,tegra234-i2s", 213 "nvidia,tegra210-i2s"; 214 reg = <0x0 0x2901200 0x0 0x100>; 215 clocks = <&bpmp TEGRA234_CLK_I2S3>, 216 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217 clock-names = "i2s", "sync_input"; 218 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220 assigned-clock-rates = <1536000>; 221 sound-name-prefix = "I2S3"; 222 status = "disabled"; 223 }; 224 225 tegra_i2s4: i2s@2901300 { 226 compatible = "nvidia,tegra234-i2s", 227 "nvidia,tegra210-i2s"; 228 reg = <0x0 0x2901300 0x0 0x100>; 229 clocks = <&bpmp TEGRA234_CLK_I2S4>, 230 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231 clock-names = "i2s", "sync_input"; 232 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234 assigned-clock-rates = <1536000>; 235 sound-name-prefix = "I2S4"; 236 status = "disabled"; 237 }; 238 239 tegra_i2s5: i2s@2901400 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901400 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S5>, 244 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S5"; 250 status = "disabled"; 251 }; 252 253 tegra_i2s6: i2s@2901500 { 254 compatible = "nvidia,tegra234-i2s", 255 "nvidia,tegra210-i2s"; 256 reg = <0x0 0x2901500 0x0 0x100>; 257 clocks = <&bpmp TEGRA234_CLK_I2S6>, 258 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S6"; 264 status = "disabled"; 265 }; 266 267 tegra_sfc1: sfc@2902000 { 268 compatible = "nvidia,tegra234-sfc", 269 "nvidia,tegra210-sfc"; 270 reg = <0x0 0x2902000 0x0 0x200>; 271 sound-name-prefix = "SFC1"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc2: sfc@2902200 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902200 0x0 0x200>; 279 sound-name-prefix = "SFC2"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc3: sfc@2902400 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902400 0x0 0x200>; 287 sound-name-prefix = "SFC3"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc4: sfc@2902600 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902600 0x0 0x200>; 295 sound-name-prefix = "SFC4"; 296 status = "disabled"; 297 }; 298 299 tegra_amx1: amx@2903000 { 300 compatible = "nvidia,tegra234-amx", 301 "nvidia,tegra194-amx"; 302 reg = <0x0 0x2903000 0x0 0x100>; 303 sound-name-prefix = "AMX1"; 304 status = "disabled"; 305 }; 306 307 tegra_amx2: amx@2903100 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903100 0x0 0x100>; 311 sound-name-prefix = "AMX2"; 312 status = "disabled"; 313 }; 314 315 tegra_amx3: amx@2903200 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903200 0x0 0x100>; 319 sound-name-prefix = "AMX3"; 320 status = "disabled"; 321 }; 322 323 tegra_amx4: amx@2903300 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903300 0x0 0x100>; 327 sound-name-prefix = "AMX4"; 328 status = "disabled"; 329 }; 330 331 tegra_adx1: adx@2903800 { 332 compatible = "nvidia,tegra234-adx", 333 "nvidia,tegra210-adx"; 334 reg = <0x0 0x2903800 0x0 0x100>; 335 sound-name-prefix = "ADX1"; 336 status = "disabled"; 337 }; 338 339 tegra_adx2: adx@2903900 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903900 0x0 0x100>; 343 sound-name-prefix = "ADX2"; 344 status = "disabled"; 345 }; 346 347 tegra_adx3: adx@2903a00 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903a00 0x0 0x100>; 351 sound-name-prefix = "ADX3"; 352 status = "disabled"; 353 }; 354 355 tegra_adx4: adx@2903b00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903b00 0x0 0x100>; 359 sound-name-prefix = "ADX4"; 360 status = "disabled"; 361 }; 362 363 364 tegra_dmic1: dmic@2904000 { 365 compatible = "nvidia,tegra234-dmic", 366 "nvidia,tegra210-dmic"; 367 reg = <0x0 0x2904000 0x0 0x100>; 368 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369 clock-names = "dmic"; 370 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372 assigned-clock-rates = <3072000>; 373 sound-name-prefix = "DMIC1"; 374 status = "disabled"; 375 }; 376 377 tegra_dmic2: dmic@2904100 { 378 compatible = "nvidia,tegra234-dmic", 379 "nvidia,tegra210-dmic"; 380 reg = <0x0 0x2904100 0x0 0x100>; 381 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382 clock-names = "dmic"; 383 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385 assigned-clock-rates = <3072000>; 386 sound-name-prefix = "DMIC2"; 387 status = "disabled"; 388 }; 389 390 tegra_dmic3: dmic@2904200 { 391 compatible = "nvidia,tegra234-dmic", 392 "nvidia,tegra210-dmic"; 393 reg = <0x0 0x2904200 0x0 0x100>; 394 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395 clock-names = "dmic"; 396 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <3072000>; 399 sound-name-prefix = "DMIC3"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic4: dmic@2904300 { 404 compatible = "nvidia,tegra234-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x0 0x2904300 0x0 0x100>; 407 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC4"; 413 status = "disabled"; 414 }; 415 416 tegra_dspk1: dspk@2905000 { 417 compatible = "nvidia,tegra234-dspk", 418 "nvidia,tegra186-dspk"; 419 reg = <0x0 0x2905000 0x0 0x100>; 420 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421 clock-names = "dspk"; 422 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <12288000>; 425 sound-name-prefix = "DSPK1"; 426 status = "disabled"; 427 }; 428 429 tegra_dspk2: dspk@2905100 { 430 compatible = "nvidia,tegra234-dspk", 431 "nvidia,tegra186-dspk"; 432 reg = <0x0 0x2905100 0x0 0x100>; 433 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434 clock-names = "dspk"; 435 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <12288000>; 438 sound-name-prefix = "DSPK2"; 439 status = "disabled"; 440 }; 441 442 tegra_ope1: processing-engine@2908000 { 443 compatible = "nvidia,tegra234-ope", 444 "nvidia,tegra210-ope"; 445 reg = <0x0 0x2908000 0x0 0x100>; 446 sound-name-prefix = "OPE1"; 447 status = "disabled"; 448 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 equalizer@2908100 { 454 compatible = "nvidia,tegra234-peq", 455 "nvidia,tegra210-peq"; 456 reg = <0x0 0x2908100 0x0 0x100>; 457 }; 458 459 dynamic-range-compressor@2908200 { 460 compatible = "nvidia,tegra234-mbdrc", 461 "nvidia,tegra210-mbdrc"; 462 reg = <0x0 0x2908200 0x0 0x200>; 463 }; 464 }; 465 466 tegra_mvc1: mvc@290a000 { 467 compatible = "nvidia,tegra234-mvc", 468 "nvidia,tegra210-mvc"; 469 reg = <0x0 0x290a000 0x0 0x200>; 470 sound-name-prefix = "MVC1"; 471 status = "disabled"; 472 }; 473 474 tegra_mvc2: mvc@290a200 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a200 0x0 0x200>; 478 sound-name-prefix = "MVC2"; 479 status = "disabled"; 480 }; 481 482 tegra_amixer: amixer@290bb00 { 483 compatible = "nvidia,tegra234-amixer", 484 "nvidia,tegra210-amixer"; 485 reg = <0x0 0x290bb00 0x0 0x800>; 486 sound-name-prefix = "MIXER1"; 487 status = "disabled"; 488 }; 489 490 tegra_admaif: admaif@290f000 { 491 compatible = "nvidia,tegra234-admaif", 492 "nvidia,tegra186-admaif"; 493 reg = <0x0 0x0290f000 0x0 0x1000>; 494 dmas = <&adma 1>, <&adma 1>, 495 <&adma 2>, <&adma 2>, 496 <&adma 3>, <&adma 3>, 497 <&adma 4>, <&adma 4>, 498 <&adma 5>, <&adma 5>, 499 <&adma 6>, <&adma 6>, 500 <&adma 7>, <&adma 7>, 501 <&adma 8>, <&adma 8>, 502 <&adma 9>, <&adma 9>, 503 <&adma 10>, <&adma 10>, 504 <&adma 11>, <&adma 11>, 505 <&adma 12>, <&adma 12>, 506 <&adma 13>, <&adma 13>, 507 <&adma 14>, <&adma 14>, 508 <&adma 15>, <&adma 15>, 509 <&adma 16>, <&adma 16>, 510 <&adma 17>, <&adma 17>, 511 <&adma 18>, <&adma 18>, 512 <&adma 19>, <&adma 19>, 513 <&adma 20>, <&adma 20>; 514 dma-names = "rx1", "tx1", 515 "rx2", "tx2", 516 "rx3", "tx3", 517 "rx4", "tx4", 518 "rx5", "tx5", 519 "rx6", "tx6", 520 "rx7", "tx7", 521 "rx8", "tx8", 522 "rx9", "tx9", 523 "rx10", "tx10", 524 "rx11", "tx11", 525 "rx12", "tx12", 526 "rx13", "tx13", 527 "rx14", "tx14", 528 "rx15", "tx15", 529 "rx16", "tx16", 530 "rx17", "tx17", 531 "rx18", "tx18", 532 "rx19", "tx19", 533 "rx20", "tx20"; 534 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536 interconnect-names = "dma-mem", "write"; 537 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538 status = "disabled"; 539 }; 540 541 tegra_asrc: asrc@2910000 { 542 compatible = "nvidia,tegra234-asrc", 543 "nvidia,tegra186-asrc"; 544 reg = <0x0 0x2910000 0x0 0x2000>; 545 sound-name-prefix = "ASRC1"; 546 status = "disabled"; 547 }; 548 }; 549 550 adma: dma-controller@2930000 { 551 compatible = "nvidia,tegra234-adma", 552 "nvidia,tegra186-adma"; 553 reg = <0x0 0x02930000 0x0 0x20000>; 554 interrupt-parent = <&agic>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587 #dma-cells = <1>; 588 clocks = <&bpmp TEGRA234_CLK_AHUB>; 589 clock-names = "d_audio"; 590 status = "disabled"; 591 }; 592 593 agic: interrupt-controller@2a40000 { 594 compatible = "nvidia,tegra234-agic", 595 "nvidia,tegra210-agic"; 596 #interrupt-cells = <3>; 597 interrupt-controller; 598 reg = <0x0 0x02a41000 0x0 0x1000>, 599 <0x0 0x02a42000 0x0 0x2000>; 600 interrupts = <GIC_SPI 145 601 (GIC_CPU_MASK_SIMPLE(4) | 602 IRQ_TYPE_LEVEL_HIGH)>; 603 clocks = <&bpmp TEGRA234_CLK_APE>; 604 clock-names = "clk"; 605 status = "disabled"; 606 }; 607 }; 608 609 mc: memory-controller@2c00000 { 610 compatible = "nvidia,tegra234-mc"; 611 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 612 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 613 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 614 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 615 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 616 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 617 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 618 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 619 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 620 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 621 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 622 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 623 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 624 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 625 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 626 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 627 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 628 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631 "ch11", "ch12", "ch13", "ch14", "ch15"; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 #interconnect-cells = <1>; 634 status = "okay"; 635 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 639 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 640 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641 642 /* 643 * Bit 39 of addresses passing through the memory 644 * controller selects the XBAR format used when memory 645 * is accessed. This is used to transparently access 646 * memory in the XBAR format used by the discrete GPU 647 * (bit 39 set) or Tegra (bit 39 clear). 648 * 649 * As a consequence, the operating system must ensure 650 * that bit 39 is never used implicitly, for example 651 * via an I/O virtual address mapping of an IOMMU. If 652 * devices require access to the XBAR switch, their 653 * drivers must set this bit explicitly. 654 * 655 * Limit the DMA range for memory clients to [38:0]. 656 */ 657 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658 659 emc: external-memory-controller@2c60000 { 660 compatible = "nvidia,tegra234-emc"; 661 reg = <0x0 0x02c60000 0x0 0x90000>, 662 <0x0 0x01780000 0x0 0x80000>; 663 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA234_CLK_EMC>; 665 clock-names = "emc"; 666 status = "okay"; 667 668 #interconnect-cells = <0>; 669 670 nvidia,bpmp = <&bpmp>; 671 }; 672 }; 673 674 uarta: serial@3100000 { 675 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 676 reg = <0x0 0x03100000 0x0 0x10000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&bpmp TEGRA234_CLK_UARTA>; 679 clock-names = "serial"; 680 resets = <&bpmp TEGRA234_RESET_UARTA>; 681 reset-names = "serial"; 682 status = "disabled"; 683 }; 684 685 gen1_i2c: i2c@3160000 { 686 compatible = "nvidia,tegra194-i2c"; 687 reg = <0x0 0x3160000 0x0 0x100>; 688 status = "disabled"; 689 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 clock-frequency = <400000>; 693 clocks = <&bpmp TEGRA234_CLK_I2C1 694 &bpmp TEGRA234_CLK_PLLP_OUT0>; 695 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 696 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 697 clock-names = "div-clk", "parent"; 698 resets = <&bpmp TEGRA234_RESET_I2C1>; 699 reset-names = "i2c"; 700 dmas = <&gpcdma 21>, <&gpcdma 21>; 701 dma-names = "rx", "tx"; 702 }; 703 704 cam_i2c: i2c@3180000 { 705 compatible = "nvidia,tegra194-i2c"; 706 reg = <0x0 0x3180000 0x0 0x100>; 707 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 status = "disabled"; 711 clock-frequency = <400000>; 712 clocks = <&bpmp TEGRA234_CLK_I2C3 713 &bpmp TEGRA234_CLK_PLLP_OUT0>; 714 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 715 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 716 clock-names = "div-clk", "parent"; 717 resets = <&bpmp TEGRA234_RESET_I2C3>; 718 reset-names = "i2c"; 719 dmas = <&gpcdma 23>, <&gpcdma 23>; 720 dma-names = "rx", "tx"; 721 }; 722 723 dp_aux_ch1_i2c: i2c@3190000 { 724 compatible = "nvidia,tegra194-i2c"; 725 reg = <0x0 0x3190000 0x0 0x100>; 726 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 status = "disabled"; 730 clock-frequency = <100000>; 731 clocks = <&bpmp TEGRA234_CLK_I2C4 732 &bpmp TEGRA234_CLK_PLLP_OUT0>; 733 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 734 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 735 clock-names = "div-clk", "parent"; 736 resets = <&bpmp TEGRA234_RESET_I2C4>; 737 reset-names = "i2c"; 738 dmas = <&gpcdma 26>, <&gpcdma 26>; 739 dma-names = "rx", "tx"; 740 }; 741 742 dp_aux_ch0_i2c: i2c@31b0000 { 743 compatible = "nvidia,tegra194-i2c"; 744 reg = <0x0 0x31b0000 0x0 0x100>; 745 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 status = "disabled"; 749 clock-frequency = <100000>; 750 clocks = <&bpmp TEGRA234_CLK_I2C6 751 &bpmp TEGRA234_CLK_PLLP_OUT0>; 752 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 753 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 754 clock-names = "div-clk", "parent"; 755 resets = <&bpmp TEGRA234_RESET_I2C6>; 756 reset-names = "i2c"; 757 dmas = <&gpcdma 30>, <&gpcdma 30>; 758 dma-names = "rx", "tx"; 759 }; 760 761 dp_aux_ch2_i2c: i2c@31c0000 { 762 compatible = "nvidia,tegra194-i2c"; 763 reg = <0x0 0x31c0000 0x0 0x100>; 764 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 status = "disabled"; 768 clock-frequency = <100000>; 769 clocks = <&bpmp TEGRA234_CLK_I2C7 770 &bpmp TEGRA234_CLK_PLLP_OUT0>; 771 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 772 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 773 clock-names = "div-clk", "parent"; 774 resets = <&bpmp TEGRA234_RESET_I2C7>; 775 reset-names = "i2c"; 776 dmas = <&gpcdma 27>, <&gpcdma 27>; 777 dma-names = "rx", "tx"; 778 }; 779 780 uarti: serial@31d0000 { 781 compatible = "arm,sbsa-uart"; 782 reg = <0x0 0x31d0000 0x0 0x10000>; 783 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 784 status = "disabled"; 785 }; 786 787 dp_aux_ch3_i2c: i2c@31e0000 { 788 compatible = "nvidia,tegra194-i2c"; 789 reg = <0x0 0x31e0000 0x0 0x100>; 790 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 status = "disabled"; 794 clock-frequency = <100000>; 795 clocks = <&bpmp TEGRA234_CLK_I2C9 796 &bpmp TEGRA234_CLK_PLLP_OUT0>; 797 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 798 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 799 clock-names = "div-clk", "parent"; 800 resets = <&bpmp TEGRA234_RESET_I2C9>; 801 reset-names = "i2c"; 802 dmas = <&gpcdma 31>, <&gpcdma 31>; 803 dma-names = "rx", "tx"; 804 }; 805 806 spi@3270000 { 807 compatible = "nvidia,tegra234-qspi"; 808 reg = <0x0 0x3270000 0x0 0x1000>; 809 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 813 <&bpmp TEGRA234_CLK_QSPI0_PM>; 814 clock-names = "qspi", "qspi_out"; 815 resets = <&bpmp TEGRA234_RESET_QSPI0>; 816 status = "disabled"; 817 }; 818 819 pwm1: pwm@3280000 { 820 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 821 reg = <0x0 0x3280000 0x0 0x10000>; 822 clocks = <&bpmp TEGRA234_CLK_PWM1>; 823 resets = <&bpmp TEGRA234_RESET_PWM1>; 824 reset-names = "pwm"; 825 status = "disabled"; 826 #pwm-cells = <2>; 827 }; 828 829 pwm2: pwm@3290000 { 830 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 831 reg = <0x0 0x3290000 0x0 0x10000>; 832 clocks = <&bpmp TEGRA234_CLK_PWM2>; 833 resets = <&bpmp TEGRA234_RESET_PWM2>; 834 reset-names = "pwm"; 835 status = "disabled"; 836 #pwm-cells = <2>; 837 }; 838 839 pwm3: pwm@32a0000 { 840 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 841 reg = <0x0 0x32a0000 0x0 0x10000>; 842 clocks = <&bpmp TEGRA234_CLK_PWM3>; 843 resets = <&bpmp TEGRA234_RESET_PWM3>; 844 reset-names = "pwm"; 845 status = "disabled"; 846 #pwm-cells = <2>; 847 }; 848 849 pwm5: pwm@32c0000 { 850 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 851 reg = <0x0 0x32c0000 0x0 0x10000>; 852 clocks = <&bpmp TEGRA234_CLK_PWM5>; 853 resets = <&bpmp TEGRA234_RESET_PWM5>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 pwm6: pwm@32d0000 { 860 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 861 reg = <0x0 0x32d0000 0x0 0x10000>; 862 clocks = <&bpmp TEGRA234_CLK_PWM6>; 863 resets = <&bpmp TEGRA234_RESET_PWM6>; 864 reset-names = "pwm"; 865 status = "disabled"; 866 #pwm-cells = <2>; 867 }; 868 869 pwm7: pwm@32e0000 { 870 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 871 reg = <0x0 0x32e0000 0x0 0x10000>; 872 clocks = <&bpmp TEGRA234_CLK_PWM7>; 873 resets = <&bpmp TEGRA234_RESET_PWM7>; 874 reset-names = "pwm"; 875 status = "disabled"; 876 #pwm-cells = <2>; 877 }; 878 879 pwm8: pwm@32f0000 { 880 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 881 reg = <0x0 0x32f0000 0x0 0x10000>; 882 clocks = <&bpmp TEGRA234_CLK_PWM8>; 883 resets = <&bpmp TEGRA234_RESET_PWM8>; 884 reset-names = "pwm"; 885 status = "disabled"; 886 #pwm-cells = <2>; 887 }; 888 889 spi@3300000 { 890 compatible = "nvidia,tegra234-qspi"; 891 reg = <0x0 0x3300000 0x0 0x1000>; 892 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 896 <&bpmp TEGRA234_CLK_QSPI1_PM>; 897 clock-names = "qspi", "qspi_out"; 898 resets = <&bpmp TEGRA234_RESET_QSPI1>; 899 status = "disabled"; 900 }; 901 902 mmc@3400000 { 903 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 904 reg = <0x0 0x03400000 0x0 0x20000>; 905 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 907 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 908 clock-names = "sdhci", "tmclk"; 909 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 910 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 911 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 912 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 913 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 914 reset-names = "sdhci"; 915 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 916 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 917 interconnect-names = "dma-mem", "write"; 918 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 919 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 920 pinctrl-0 = <&sdmmc1_3v3>; 921 pinctrl-1 = <&sdmmc1_1v8>; 922 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 923 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 924 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 925 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 926 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 927 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 928 nvidia,default-tap = <14>; 929 nvidia,default-trim = <0x8>; 930 sd-uhs-sdr25; 931 sd-uhs-sdr50; 932 sd-uhs-ddr50; 933 sd-uhs-sdr104; 934 status = "disabled"; 935 }; 936 937 mmc@3460000 { 938 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 939 reg = <0x0 0x03460000 0x0 0x20000>; 940 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 942 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 943 clock-names = "sdhci", "tmclk"; 944 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 945 <&bpmp TEGRA234_CLK_PLLC4>; 946 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 947 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 948 reset-names = "sdhci"; 949 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 950 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 951 interconnect-names = "dma-mem", "write"; 952 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 953 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 954 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 955 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 956 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 957 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 958 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 959 nvidia,default-tap = <0x8>; 960 nvidia,default-trim = <0x14>; 961 nvidia,dqs-trim = <40>; 962 supports-cqe; 963 status = "disabled"; 964 }; 965 966 hda@3510000 { 967 compatible = "nvidia,tegra234-hda"; 968 reg = <0x0 0x3510000 0x0 0x10000>; 969 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 971 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 972 clock-names = "hda", "hda2codec_2x"; 973 resets = <&bpmp TEGRA234_RESET_HDA>, 974 <&bpmp TEGRA234_RESET_HDACODEC>; 975 reset-names = "hda", "hda2codec_2x"; 976 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 977 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 978 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 979 interconnect-names = "dma-mem", "write"; 980 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 981 status = "disabled"; 982 }; 983 984 xusb_padctl: padctl@3520000 { 985 compatible = "nvidia,tegra234-xusb-padctl"; 986 reg = <0x0 0x03520000 0x0 0x20000>, 987 <0x0 0x03540000 0x0 0x10000>; 988 reg-names = "padctl", "ao"; 989 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 990 991 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 992 reset-names = "padctl"; 993 994 status = "disabled"; 995 996 pads { 997 usb2 { 998 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 999 clock-names = "trk"; 1000 1001 lanes { 1002 usb2-0 { 1003 nvidia,function = "xusb"; 1004 status = "disabled"; 1005 #phy-cells = <0>; 1006 }; 1007 1008 usb2-1 { 1009 nvidia,function = "xusb"; 1010 status = "disabled"; 1011 #phy-cells = <0>; 1012 }; 1013 1014 usb2-2 { 1015 nvidia,function = "xusb"; 1016 status = "disabled"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 usb2-3 { 1021 nvidia,function = "xusb"; 1022 status = "disabled"; 1023 #phy-cells = <0>; 1024 }; 1025 }; 1026 }; 1027 1028 usb3 { 1029 lanes { 1030 usb3-0 { 1031 nvidia,function = "xusb"; 1032 status = "disabled"; 1033 #phy-cells = <0>; 1034 }; 1035 1036 usb3-1 { 1037 nvidia,function = "xusb"; 1038 status = "disabled"; 1039 #phy-cells = <0>; 1040 }; 1041 1042 usb3-2 { 1043 nvidia,function = "xusb"; 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 1048 usb3-3 { 1049 nvidia,function = "xusb"; 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 }; 1054 }; 1055 }; 1056 1057 ports { 1058 usb2-0 { 1059 status = "disabled"; 1060 }; 1061 1062 usb2-1 { 1063 status = "disabled"; 1064 }; 1065 1066 usb2-2 { 1067 status = "disabled"; 1068 }; 1069 1070 usb2-3 { 1071 status = "disabled"; 1072 }; 1073 1074 usb3-0 { 1075 status = "disabled"; 1076 }; 1077 1078 usb3-1 { 1079 status = "disabled"; 1080 }; 1081 1082 usb3-2 { 1083 status = "disabled"; 1084 }; 1085 1086 usb3-3 { 1087 status = "disabled"; 1088 }; 1089 }; 1090 }; 1091 1092 usb@3550000 { 1093 compatible = "nvidia,tegra234-xudc"; 1094 reg = <0x0 0x03550000 0x0 0x8000>, 1095 <0x0 0x03558000 0x0 0x8000>; 1096 reg-names = "base", "fpci"; 1097 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1099 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1100 <&bpmp TEGRA234_CLK_XUSB_SS>, 1101 <&bpmp TEGRA234_CLK_XUSB_FS>; 1102 clock-names = "dev", "ss", "ss_src", "fs_src"; 1103 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1104 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1105 interconnect-names = "dma-mem", "write"; 1106 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1107 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1108 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1109 power-domain-names = "dev", "ss"; 1110 nvidia,xusb-padctl = <&xusb_padctl>; 1111 dma-coherent; 1112 status = "disabled"; 1113 }; 1114 1115 usb@3610000 { 1116 compatible = "nvidia,tegra234-xusb"; 1117 reg = <0x0 0x03610000 0x0 0x40000>, 1118 <0x0 0x03600000 0x0 0x10000>, 1119 <0x0 0x03650000 0x0 0x10000>; 1120 reg-names = "hcd", "fpci", "bar2"; 1121 1122 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1124 1125 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1126 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1127 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1128 <&bpmp TEGRA234_CLK_XUSB_SS>, 1129 <&bpmp TEGRA234_CLK_CLK_M>, 1130 <&bpmp TEGRA234_CLK_XUSB_FS>, 1131 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1132 <&bpmp TEGRA234_CLK_CLK_M>, 1133 <&bpmp TEGRA234_CLK_PLLE>; 1134 clock-names = "xusb_host", "xusb_falcon_src", 1135 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1136 "xusb_fs_src", "pll_u_480m", "clk_m", 1137 "pll_e"; 1138 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1139 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1140 interconnect-names = "dma-mem", "write"; 1141 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1142 1143 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1144 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1145 power-domain-names = "xusb_host", "xusb_ss"; 1146 1147 nvidia,xusb-padctl = <&xusb_padctl>; 1148 dma-coherent; 1149 status = "disabled"; 1150 }; 1151 1152 fuse@3810000 { 1153 compatible = "nvidia,tegra234-efuse"; 1154 reg = <0x0 0x03810000 0x0 0x10000>; 1155 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1156 clock-names = "fuse"; 1157 }; 1158 1159 hte_lic: hardware-timestamp@3aa0000 { 1160 compatible = "nvidia,tegra234-gte-lic"; 1161 reg = <0x0 0x3aa0000 0x0 0x10000>; 1162 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1163 nvidia,int-threshold = <1>; 1164 #timestamp-cells = <1>; 1165 }; 1166 1167 hsp_top0: hsp@3c00000 { 1168 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1169 reg = <0x0 0x03c00000 0x0 0xa0000>; 1170 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1179 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1180 "shared3", "shared4", "shared5", "shared6", 1181 "shared7"; 1182 #mbox-cells = <2>; 1183 }; 1184 1185 p2u_hsio_0: phy@3e00000 { 1186 compatible = "nvidia,tegra234-p2u"; 1187 reg = <0x0 0x03e00000 0x0 0x10000>; 1188 reg-names = "ctl"; 1189 1190 #phy-cells = <0>; 1191 }; 1192 1193 p2u_hsio_1: phy@3e10000 { 1194 compatible = "nvidia,tegra234-p2u"; 1195 reg = <0x0 0x03e10000 0x0 0x10000>; 1196 reg-names = "ctl"; 1197 1198 #phy-cells = <0>; 1199 }; 1200 1201 p2u_hsio_2: phy@3e20000 { 1202 compatible = "nvidia,tegra234-p2u"; 1203 reg = <0x0 0x03e20000 0x0 0x10000>; 1204 reg-names = "ctl"; 1205 1206 #phy-cells = <0>; 1207 }; 1208 1209 p2u_hsio_3: phy@3e30000 { 1210 compatible = "nvidia,tegra234-p2u"; 1211 reg = <0x0 0x03e30000 0x0 0x10000>; 1212 reg-names = "ctl"; 1213 1214 #phy-cells = <0>; 1215 }; 1216 1217 p2u_hsio_4: phy@3e40000 { 1218 compatible = "nvidia,tegra234-p2u"; 1219 reg = <0x0 0x03e40000 0x0 0x10000>; 1220 reg-names = "ctl"; 1221 1222 #phy-cells = <0>; 1223 }; 1224 1225 p2u_hsio_5: phy@3e50000 { 1226 compatible = "nvidia,tegra234-p2u"; 1227 reg = <0x0 0x03e50000 0x0 0x10000>; 1228 reg-names = "ctl"; 1229 1230 #phy-cells = <0>; 1231 }; 1232 1233 p2u_hsio_6: phy@3e60000 { 1234 compatible = "nvidia,tegra234-p2u"; 1235 reg = <0x0 0x03e60000 0x0 0x10000>; 1236 reg-names = "ctl"; 1237 1238 #phy-cells = <0>; 1239 }; 1240 1241 p2u_hsio_7: phy@3e70000 { 1242 compatible = "nvidia,tegra234-p2u"; 1243 reg = <0x0 0x03e70000 0x0 0x10000>; 1244 reg-names = "ctl"; 1245 1246 #phy-cells = <0>; 1247 }; 1248 1249 p2u_nvhs_0: phy@3e90000 { 1250 compatible = "nvidia,tegra234-p2u"; 1251 reg = <0x0 0x03e90000 0x0 0x10000>; 1252 reg-names = "ctl"; 1253 1254 #phy-cells = <0>; 1255 }; 1256 1257 p2u_nvhs_1: phy@3ea0000 { 1258 compatible = "nvidia,tegra234-p2u"; 1259 reg = <0x0 0x03ea0000 0x0 0x10000>; 1260 reg-names = "ctl"; 1261 1262 #phy-cells = <0>; 1263 }; 1264 1265 p2u_nvhs_2: phy@3eb0000 { 1266 compatible = "nvidia,tegra234-p2u"; 1267 reg = <0x0 0x03eb0000 0x0 0x10000>; 1268 reg-names = "ctl"; 1269 1270 #phy-cells = <0>; 1271 }; 1272 1273 p2u_nvhs_3: phy@3ec0000 { 1274 compatible = "nvidia,tegra234-p2u"; 1275 reg = <0x0 0x03ec0000 0x0 0x10000>; 1276 reg-names = "ctl"; 1277 1278 #phy-cells = <0>; 1279 }; 1280 1281 p2u_nvhs_4: phy@3ed0000 { 1282 compatible = "nvidia,tegra234-p2u"; 1283 reg = <0x0 0x03ed0000 0x0 0x10000>; 1284 reg-names = "ctl"; 1285 1286 #phy-cells = <0>; 1287 }; 1288 1289 p2u_nvhs_5: phy@3ee0000 { 1290 compatible = "nvidia,tegra234-p2u"; 1291 reg = <0x0 0x03ee0000 0x0 0x10000>; 1292 reg-names = "ctl"; 1293 1294 #phy-cells = <0>; 1295 }; 1296 1297 p2u_nvhs_6: phy@3ef0000 { 1298 compatible = "nvidia,tegra234-p2u"; 1299 reg = <0x0 0x03ef0000 0x0 0x10000>; 1300 reg-names = "ctl"; 1301 1302 #phy-cells = <0>; 1303 }; 1304 1305 p2u_nvhs_7: phy@3f00000 { 1306 compatible = "nvidia,tegra234-p2u"; 1307 reg = <0x0 0x03f00000 0x0 0x10000>; 1308 reg-names = "ctl"; 1309 1310 #phy-cells = <0>; 1311 }; 1312 1313 p2u_gbe_0: phy@3f20000 { 1314 compatible = "nvidia,tegra234-p2u"; 1315 reg = <0x0 0x03f20000 0x0 0x10000>; 1316 reg-names = "ctl"; 1317 1318 #phy-cells = <0>; 1319 }; 1320 1321 p2u_gbe_1: phy@3f30000 { 1322 compatible = "nvidia,tegra234-p2u"; 1323 reg = <0x0 0x03f30000 0x0 0x10000>; 1324 reg-names = "ctl"; 1325 1326 #phy-cells = <0>; 1327 }; 1328 1329 p2u_gbe_2: phy@3f40000 { 1330 compatible = "nvidia,tegra234-p2u"; 1331 reg = <0x0 0x03f40000 0x0 0x10000>; 1332 reg-names = "ctl"; 1333 1334 #phy-cells = <0>; 1335 }; 1336 1337 p2u_gbe_3: phy@3f50000 { 1338 compatible = "nvidia,tegra234-p2u"; 1339 reg = <0x0 0x03f50000 0x0 0x10000>; 1340 reg-names = "ctl"; 1341 1342 #phy-cells = <0>; 1343 }; 1344 1345 p2u_gbe_4: phy@3f60000 { 1346 compatible = "nvidia,tegra234-p2u"; 1347 reg = <0x0 0x03f60000 0x0 0x10000>; 1348 reg-names = "ctl"; 1349 1350 #phy-cells = <0>; 1351 }; 1352 1353 p2u_gbe_5: phy@3f70000 { 1354 compatible = "nvidia,tegra234-p2u"; 1355 reg = <0x0 0x03f70000 0x0 0x10000>; 1356 reg-names = "ctl"; 1357 1358 #phy-cells = <0>; 1359 }; 1360 1361 p2u_gbe_6: phy@3f80000 { 1362 compatible = "nvidia,tegra234-p2u"; 1363 reg = <0x0 0x03f80000 0x0 0x10000>; 1364 reg-names = "ctl"; 1365 1366 #phy-cells = <0>; 1367 }; 1368 1369 p2u_gbe_7: phy@3f90000 { 1370 compatible = "nvidia,tegra234-p2u"; 1371 reg = <0x0 0x03f90000 0x0 0x10000>; 1372 reg-names = "ctl"; 1373 1374 #phy-cells = <0>; 1375 }; 1376 1377 ethernet@6800000 { 1378 compatible = "nvidia,tegra234-mgbe"; 1379 reg = <0x0 0x06800000 0x0 0x10000>, 1380 <0x0 0x06810000 0x0 0x10000>, 1381 <0x0 0x068a0000 0x0 0x10000>; 1382 reg-names = "hypervisor", "mac", "xpcs"; 1383 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1384 interrupt-names = "common"; 1385 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1386 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1387 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1388 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1389 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1390 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1391 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1392 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1393 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1394 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1395 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1396 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1397 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1398 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1399 "rx-pcs", "tx-pcs"; 1400 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1401 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1402 reset-names = "mac", "pcs"; 1403 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1404 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1405 interconnect-names = "dma-mem", "write"; 1406 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1407 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1408 status = "disabled"; 1409 }; 1410 1411 ethernet@6900000 { 1412 compatible = "nvidia,tegra234-mgbe"; 1413 reg = <0x0 0x06900000 0x0 0x10000>, 1414 <0x0 0x06910000 0x0 0x10000>, 1415 <0x0 0x069a0000 0x0 0x10000>; 1416 reg-names = "hypervisor", "mac", "xpcs"; 1417 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1418 interrupt-names = "common"; 1419 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1420 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1421 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1422 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1423 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1424 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1425 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1426 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1427 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1428 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1429 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1430 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1431 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1432 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1433 "rx-pcs", "tx-pcs"; 1434 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1435 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1436 reset-names = "mac", "pcs"; 1437 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1438 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1439 interconnect-names = "dma-mem", "write"; 1440 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1441 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1442 status = "disabled"; 1443 }; 1444 1445 ethernet@6a00000 { 1446 compatible = "nvidia,tegra234-mgbe"; 1447 reg = <0x0 0x06a00000 0x0 0x10000>, 1448 <0x0 0x06a10000 0x0 0x10000>, 1449 <0x0 0x06aa0000 0x0 0x10000>; 1450 reg-names = "hypervisor", "mac", "xpcs"; 1451 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1452 interrupt-names = "common"; 1453 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1454 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1455 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1456 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1457 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1458 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1459 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1460 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1461 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1462 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1463 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1464 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1465 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1466 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1467 "rx-pcs", "tx-pcs"; 1468 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1469 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1470 reset-names = "mac", "pcs"; 1471 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1472 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1473 interconnect-names = "dma-mem", "write"; 1474 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1475 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1476 status = "disabled"; 1477 }; 1478 1479 ethernet@6b00000 { 1480 compatible = "nvidia,tegra234-mgbe"; 1481 reg = <0x0 0x06b00000 0x0 0x10000>, 1482 <0x0 0x06b10000 0x0 0x10000>, 1483 <0x0 0x06ba0000 0x0 0x10000>; 1484 reg-names = "hypervisor", "mac", "xpcs"; 1485 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1486 interrupt-names = "common"; 1487 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1488 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1489 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1490 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1491 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1492 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1493 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1494 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1495 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1496 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1497 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1498 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1499 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1500 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1501 "rx-pcs", "tx-pcs"; 1502 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1503 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1504 reset-names = "mac", "pcs"; 1505 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1506 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1507 interconnect-names = "dma-mem", "write"; 1508 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1509 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1510 status = "disabled"; 1511 }; 1512 1513 smmu_niso1: iommu@8000000 { 1514 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1515 reg = <0x0 0x8000000 0x0 0x1000000>, 1516 <0x0 0x7000000 0x0 0x1000000>; 1517 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1647 stream-match-mask = <0x7f80>; 1648 #global-interrupts = <2>; 1649 #iommu-cells = <1>; 1650 1651 nvidia,memory-controller = <&mc>; 1652 status = "okay"; 1653 }; 1654 1655 sce-fabric@b600000 { 1656 compatible = "nvidia,tegra234-sce-fabric"; 1657 reg = <0x0 0xb600000 0x0 0x40000>; 1658 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1659 status = "okay"; 1660 }; 1661 1662 rce-fabric@be00000 { 1663 compatible = "nvidia,tegra234-rce-fabric"; 1664 reg = <0x0 0xbe00000 0x0 0x40000>; 1665 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1666 status = "okay"; 1667 }; 1668 1669 hsp_aon: hsp@c150000 { 1670 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1671 reg = <0x0 0x0c150000 0x0 0x90000>; 1672 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1676 /* 1677 * Shared interrupt 0 is routed only to AON/SPE, so 1678 * we only have 4 shared interrupts for the CCPLEX. 1679 */ 1680 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1681 #mbox-cells = <2>; 1682 }; 1683 1684 hte_aon: hardware-timestamp@c1e0000 { 1685 compatible = "nvidia,tegra234-gte-aon"; 1686 reg = <0x0 0xc1e0000 0x0 0x10000>; 1687 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1688 nvidia,int-threshold = <1>; 1689 nvidia,gpio-controller = <&gpio_aon>; 1690 #timestamp-cells = <1>; 1691 }; 1692 1693 gen2_i2c: i2c@c240000 { 1694 compatible = "nvidia,tegra194-i2c"; 1695 reg = <0x0 0xc240000 0x0 0x100>; 1696 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 status = "disabled"; 1700 clock-frequency = <100000>; 1701 clocks = <&bpmp TEGRA234_CLK_I2C2 1702 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1703 clock-names = "div-clk", "parent"; 1704 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1705 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1706 resets = <&bpmp TEGRA234_RESET_I2C2>; 1707 reset-names = "i2c"; 1708 dmas = <&gpcdma 22>, <&gpcdma 22>; 1709 dma-names = "rx", "tx"; 1710 }; 1711 1712 gen8_i2c: i2c@c250000 { 1713 compatible = "nvidia,tegra194-i2c"; 1714 reg = <0x0 0xc250000 0x0 0x100>; 1715 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 status = "disabled"; 1719 clock-frequency = <400000>; 1720 clocks = <&bpmp TEGRA234_CLK_I2C8 1721 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1722 clock-names = "div-clk", "parent"; 1723 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1724 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1725 resets = <&bpmp TEGRA234_RESET_I2C8>; 1726 reset-names = "i2c"; 1727 dmas = <&gpcdma 0>, <&gpcdma 0>; 1728 dma-names = "rx", "tx"; 1729 }; 1730 1731 rtc@c2a0000 { 1732 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1733 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1734 interrupt-parent = <&pmc>; 1735 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1736 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1737 clock-names = "rtc"; 1738 status = "disabled"; 1739 }; 1740 1741 gpio_aon: gpio@c2f0000 { 1742 compatible = "nvidia,tegra234-gpio-aon"; 1743 reg-names = "security", "gpio"; 1744 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1745 <0x0 0x0c2f1000 0x0 0x1000>; 1746 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1750 #interrupt-cells = <2>; 1751 interrupt-controller; 1752 #gpio-cells = <2>; 1753 gpio-controller; 1754 }; 1755 1756 pwm4: pwm@c340000 { 1757 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1758 reg = <0x0 0xc340000 0x0 0x10000>; 1759 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1760 resets = <&bpmp TEGRA234_RESET_PWM4>; 1761 reset-names = "pwm"; 1762 status = "disabled"; 1763 #pwm-cells = <2>; 1764 }; 1765 1766 pmc: pmc@c360000 { 1767 compatible = "nvidia,tegra234-pmc"; 1768 reg = <0x0 0x0c360000 0x0 0x10000>, 1769 <0x0 0x0c370000 0x0 0x10000>, 1770 <0x0 0x0c380000 0x0 0x10000>, 1771 <0x0 0x0c390000 0x0 0x10000>, 1772 <0x0 0x0c3a0000 0x0 0x10000>; 1773 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1774 1775 #interrupt-cells = <2>; 1776 interrupt-controller; 1777 1778 sdmmc1_1v8: sdmmc1-1v8 { 1779 pins = "sdmmc1-hv"; 1780 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1781 }; 1782 1783 sdmmc1_3v3: sdmmc1-3v3 { 1784 pins = "sdmmc1-hv"; 1785 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1786 }; 1787 1788 sdmmc3_1v8: sdmmc3-1v8 { 1789 pins = "sdmmc3-hv"; 1790 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1791 }; 1792 1793 sdmmc3_3v3: sdmmc3-3v3 { 1794 pins = "sdmmc3-hv"; 1795 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1796 }; 1797 }; 1798 1799 aon-fabric@c600000 { 1800 compatible = "nvidia,tegra234-aon-fabric"; 1801 reg = <0x0 0xc600000 0x0 0x40000>; 1802 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1803 status = "okay"; 1804 }; 1805 1806 bpmp-fabric@d600000 { 1807 compatible = "nvidia,tegra234-bpmp-fabric"; 1808 reg = <0x0 0xd600000 0x0 0x40000>; 1809 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1810 status = "okay"; 1811 }; 1812 1813 dce-fabric@de00000 { 1814 compatible = "nvidia,tegra234-sce-fabric"; 1815 reg = <0x0 0xde00000 0x0 0x40000>; 1816 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1817 status = "okay"; 1818 }; 1819 1820 ccplex@e000000 { 1821 compatible = "nvidia,tegra234-ccplex-cluster"; 1822 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1823 nvidia,bpmp = <&bpmp>; 1824 status = "okay"; 1825 }; 1826 1827 gic: interrupt-controller@f400000 { 1828 compatible = "arm,gic-v3"; 1829 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1830 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1831 interrupt-parent = <&gic>; 1832 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1833 1834 #redistributor-regions = <1>; 1835 #interrupt-cells = <3>; 1836 interrupt-controller; 1837 }; 1838 1839 smmu_iso: iommu@10000000 { 1840 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1841 reg = <0x0 0x10000000 0x0 0x1000000>; 1842 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1971 stream-match-mask = <0x7f80>; 1972 #global-interrupts = <1>; 1973 #iommu-cells = <1>; 1974 1975 nvidia,memory-controller = <&mc>; 1976 status = "okay"; 1977 }; 1978 1979 smmu_niso0: iommu@12000000 { 1980 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1981 reg = <0x0 0x12000000 0x0 0x1000000>, 1982 <0x0 0x11000000 0x0 0x1000000>; 1983 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2113 stream-match-mask = <0x7f80>; 2114 #global-interrupts = <2>; 2115 #iommu-cells = <1>; 2116 2117 nvidia,memory-controller = <&mc>; 2118 status = "okay"; 2119 }; 2120 2121 cbb-fabric@13a00000 { 2122 compatible = "nvidia,tegra234-cbb-fabric"; 2123 reg = <0x0 0x13a00000 0x0 0x400000>; 2124 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2125 status = "okay"; 2126 }; 2127 2128 host1x@13e00000 { 2129 compatible = "nvidia,tegra234-host1x"; 2130 reg = <0x0 0x13e00000 0x0 0x10000>, 2131 <0x0 0x13e10000 0x0 0x10000>, 2132 <0x0 0x13e40000 0x0 0x10000>; 2133 reg-names = "common", "hypervisor", "vm"; 2134 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2144 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2145 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2146 clock-names = "host1x"; 2147 2148 #address-cells = <2>; 2149 #size-cells = <2>; 2150 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2151 2152 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2153 interconnect-names = "dma-mem"; 2154 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2155 dma-coherent; 2156 2157 /* Context isolation domains */ 2158 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2159 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2160 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2161 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2162 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2163 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2164 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2165 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2166 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2167 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2168 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2169 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2170 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2171 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2172 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2173 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2174 2175 vic@15340000 { 2176 compatible = "nvidia,tegra234-vic"; 2177 reg = <0x0 0x15340000 0x0 0x00040000>; 2178 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2179 clocks = <&bpmp TEGRA234_CLK_VIC>; 2180 clock-names = "vic"; 2181 resets = <&bpmp TEGRA234_RESET_VIC>; 2182 reset-names = "vic"; 2183 2184 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2185 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2186 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2187 interconnect-names = "dma-mem", "write"; 2188 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2189 dma-coherent; 2190 }; 2191 2192 nvdec@15480000 { 2193 compatible = "nvidia,tegra234-nvdec"; 2194 reg = <0x0 0x15480000 0x0 0x00040000>; 2195 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2196 <&bpmp TEGRA234_CLK_FUSE>, 2197 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2198 clock-names = "nvdec", "fuse", "tsec_pka"; 2199 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2200 reset-names = "nvdec"; 2201 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2202 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2203 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2204 interconnect-names = "dma-mem", "write"; 2205 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2206 dma-coherent; 2207 2208 nvidia,memory-controller = <&mc>; 2209 2210 /* 2211 * Placeholder values that firmware needs to update with the real 2212 * offsets parsed from the microcode headers. 2213 */ 2214 nvidia,bl-manifest-offset = <0>; 2215 nvidia,bl-data-offset = <0>; 2216 nvidia,bl-code-offset = <0>; 2217 nvidia,os-manifest-offset = <0>; 2218 nvidia,os-data-offset = <0>; 2219 nvidia,os-code-offset = <0>; 2220 2221 /* 2222 * Firmware needs to set this to "okay" once the above values have 2223 * been updated. 2224 */ 2225 status = "disabled"; 2226 }; 2227 }; 2228 2229 pcie@140a0000 { 2230 compatible = "nvidia,tegra234-pcie"; 2231 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2232 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2233 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2234 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2235 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2236 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2237 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2238 2239 #address-cells = <3>; 2240 #size-cells = <2>; 2241 device_type = "pci"; 2242 num-lanes = <4>; 2243 num-viewport = <8>; 2244 linux,pci-domain = <8>; 2245 2246 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2247 clock-names = "core"; 2248 2249 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2250 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2251 reset-names = "apb", "core"; 2252 2253 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2254 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2255 interrupt-names = "intr", "msi"; 2256 2257 #interrupt-cells = <1>; 2258 interrupt-map-mask = <0 0 0 0>; 2259 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2260 2261 nvidia,bpmp = <&bpmp 8>; 2262 2263 nvidia,aspm-cmrt-us = <60>; 2264 nvidia,aspm-pwr-on-t-us = <20>; 2265 nvidia,aspm-l0s-entrance-latency-us = <3>; 2266 2267 bus-range = <0x0 0xff>; 2268 2269 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2270 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2271 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2272 2273 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2274 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2275 interconnect-names = "dma-mem", "write"; 2276 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2277 iommu-map-mask = <0x0>; 2278 dma-coherent; 2279 2280 status = "disabled"; 2281 }; 2282 2283 pcie@140c0000 { 2284 compatible = "nvidia,tegra234-pcie"; 2285 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2286 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2287 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2288 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2289 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2290 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2291 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2292 2293 #address-cells = <3>; 2294 #size-cells = <2>; 2295 device_type = "pci"; 2296 num-lanes = <4>; 2297 num-viewport = <8>; 2298 linux,pci-domain = <9>; 2299 2300 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2301 clock-names = "core"; 2302 2303 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2304 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2305 reset-names = "apb", "core"; 2306 2307 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2308 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2309 interrupt-names = "intr", "msi"; 2310 2311 #interrupt-cells = <1>; 2312 interrupt-map-mask = <0 0 0 0>; 2313 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2314 2315 nvidia,bpmp = <&bpmp 9>; 2316 2317 nvidia,aspm-cmrt-us = <60>; 2318 nvidia,aspm-pwr-on-t-us = <20>; 2319 nvidia,aspm-l0s-entrance-latency-us = <3>; 2320 2321 bus-range = <0x0 0xff>; 2322 2323 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2324 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2325 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2326 2327 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2328 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2329 interconnect-names = "dma-mem", "write"; 2330 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2331 iommu-map-mask = <0x0>; 2332 dma-coherent; 2333 2334 status = "disabled"; 2335 }; 2336 2337 pcie@140e0000 { 2338 compatible = "nvidia,tegra234-pcie"; 2339 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2340 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2341 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2342 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2343 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2344 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2345 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2346 2347 #address-cells = <3>; 2348 #size-cells = <2>; 2349 device_type = "pci"; 2350 num-lanes = <4>; 2351 num-viewport = <8>; 2352 linux,pci-domain = <10>; 2353 2354 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2355 clock-names = "core"; 2356 2357 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2358 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2359 reset-names = "apb", "core"; 2360 2361 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2362 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2363 interrupt-names = "intr", "msi"; 2364 2365 #interrupt-cells = <1>; 2366 interrupt-map-mask = <0 0 0 0>; 2367 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2368 2369 nvidia,bpmp = <&bpmp 10>; 2370 2371 nvidia,aspm-cmrt-us = <60>; 2372 nvidia,aspm-pwr-on-t-us = <20>; 2373 nvidia,aspm-l0s-entrance-latency-us = <3>; 2374 2375 bus-range = <0x0 0xff>; 2376 2377 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2378 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2379 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2380 2381 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2382 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2383 interconnect-names = "dma-mem", "write"; 2384 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2385 iommu-map-mask = <0x0>; 2386 dma-coherent; 2387 2388 status = "disabled"; 2389 }; 2390 2391 pcie-ep@140e0000 { 2392 compatible = "nvidia,tegra234-pcie-ep"; 2393 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2394 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2395 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2396 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2397 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2398 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2399 2400 num-lanes = <4>; 2401 2402 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2403 clock-names = "core"; 2404 2405 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2406 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2407 reset-names = "apb", "core"; 2408 2409 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2410 interrupt-names = "intr"; 2411 2412 nvidia,bpmp = <&bpmp 10>; 2413 2414 nvidia,enable-ext-refclk; 2415 nvidia,aspm-cmrt-us = <60>; 2416 nvidia,aspm-pwr-on-t-us = <20>; 2417 nvidia,aspm-l0s-entrance-latency-us = <3>; 2418 2419 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2420 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2421 interconnect-names = "dma-mem", "write"; 2422 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2423 iommu-map-mask = <0x0>; 2424 dma-coherent; 2425 2426 status = "disabled"; 2427 }; 2428 2429 pcie@14100000 { 2430 compatible = "nvidia,tegra234-pcie"; 2431 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2432 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2433 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2434 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2435 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2436 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2437 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2438 2439 #address-cells = <3>; 2440 #size-cells = <2>; 2441 device_type = "pci"; 2442 num-lanes = <1>; 2443 num-viewport = <8>; 2444 linux,pci-domain = <1>; 2445 2446 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2447 clock-names = "core"; 2448 2449 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2450 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2451 reset-names = "apb", "core"; 2452 2453 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2454 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2455 interrupt-names = "intr", "msi"; 2456 2457 #interrupt-cells = <1>; 2458 interrupt-map-mask = <0 0 0 0>; 2459 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2460 2461 nvidia,bpmp = <&bpmp 1>; 2462 2463 nvidia,aspm-cmrt-us = <60>; 2464 nvidia,aspm-pwr-on-t-us = <20>; 2465 nvidia,aspm-l0s-entrance-latency-us = <3>; 2466 2467 bus-range = <0x0 0xff>; 2468 2469 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2470 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2471 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2472 2473 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2474 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2475 interconnect-names = "dma-mem", "write"; 2476 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2477 iommu-map-mask = <0x0>; 2478 dma-coherent; 2479 2480 status = "disabled"; 2481 }; 2482 2483 pcie@14120000 { 2484 compatible = "nvidia,tegra234-pcie"; 2485 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2486 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2487 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2488 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2489 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2490 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2491 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2492 2493 #address-cells = <3>; 2494 #size-cells = <2>; 2495 device_type = "pci"; 2496 num-lanes = <1>; 2497 num-viewport = <8>; 2498 linux,pci-domain = <2>; 2499 2500 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2501 clock-names = "core"; 2502 2503 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2504 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2505 reset-names = "apb", "core"; 2506 2507 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2508 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2509 interrupt-names = "intr", "msi"; 2510 2511 #interrupt-cells = <1>; 2512 interrupt-map-mask = <0 0 0 0>; 2513 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2514 2515 nvidia,bpmp = <&bpmp 2>; 2516 2517 nvidia,aspm-cmrt-us = <60>; 2518 nvidia,aspm-pwr-on-t-us = <20>; 2519 nvidia,aspm-l0s-entrance-latency-us = <3>; 2520 2521 bus-range = <0x0 0xff>; 2522 2523 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2524 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2525 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2526 2527 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2528 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2529 interconnect-names = "dma-mem", "write"; 2530 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2531 iommu-map-mask = <0x0>; 2532 dma-coherent; 2533 2534 status = "disabled"; 2535 }; 2536 2537 pcie@14140000 { 2538 compatible = "nvidia,tegra234-pcie"; 2539 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2540 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2541 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2542 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2543 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2544 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2545 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2546 2547 #address-cells = <3>; 2548 #size-cells = <2>; 2549 device_type = "pci"; 2550 num-lanes = <1>; 2551 num-viewport = <8>; 2552 linux,pci-domain = <3>; 2553 2554 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2555 clock-names = "core"; 2556 2557 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2558 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2559 reset-names = "apb", "core"; 2560 2561 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2562 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2563 interrupt-names = "intr", "msi"; 2564 2565 #interrupt-cells = <1>; 2566 interrupt-map-mask = <0 0 0 0>; 2567 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2568 2569 nvidia,bpmp = <&bpmp 3>; 2570 2571 nvidia,aspm-cmrt-us = <60>; 2572 nvidia,aspm-pwr-on-t-us = <20>; 2573 nvidia,aspm-l0s-entrance-latency-us = <3>; 2574 2575 bus-range = <0x0 0xff>; 2576 2577 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2578 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2579 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2580 2581 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2582 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2583 interconnect-names = "dma-mem", "write"; 2584 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2585 iommu-map-mask = <0x0>; 2586 dma-coherent; 2587 2588 status = "disabled"; 2589 }; 2590 2591 pcie@14160000 { 2592 compatible = "nvidia,tegra234-pcie"; 2593 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2594 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2595 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2596 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2597 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2598 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2599 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2600 2601 #address-cells = <3>; 2602 #size-cells = <2>; 2603 device_type = "pci"; 2604 num-lanes = <4>; 2605 num-viewport = <8>; 2606 linux,pci-domain = <4>; 2607 2608 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2609 clock-names = "core"; 2610 2611 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2612 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2613 reset-names = "apb", "core"; 2614 2615 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2616 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2617 interrupt-names = "intr", "msi"; 2618 2619 #interrupt-cells = <1>; 2620 interrupt-map-mask = <0 0 0 0>; 2621 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2622 2623 nvidia,bpmp = <&bpmp 4>; 2624 2625 nvidia,aspm-cmrt-us = <60>; 2626 nvidia,aspm-pwr-on-t-us = <20>; 2627 nvidia,aspm-l0s-entrance-latency-us = <3>; 2628 2629 bus-range = <0x0 0xff>; 2630 2631 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2632 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2633 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2634 2635 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2636 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2637 interconnect-names = "dma-mem", "write"; 2638 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2639 iommu-map-mask = <0x0>; 2640 dma-coherent; 2641 2642 status = "disabled"; 2643 }; 2644 2645 pcie@14180000 { 2646 compatible = "nvidia,tegra234-pcie"; 2647 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2648 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2649 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2650 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2651 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2652 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2653 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2654 2655 #address-cells = <3>; 2656 #size-cells = <2>; 2657 device_type = "pci"; 2658 num-lanes = <4>; 2659 num-viewport = <8>; 2660 linux,pci-domain = <0>; 2661 2662 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2663 clock-names = "core"; 2664 2665 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2666 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2667 reset-names = "apb", "core"; 2668 2669 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2670 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2671 interrupt-names = "intr", "msi"; 2672 2673 #interrupt-cells = <1>; 2674 interrupt-map-mask = <0 0 0 0>; 2675 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2676 2677 nvidia,bpmp = <&bpmp 0>; 2678 2679 nvidia,aspm-cmrt-us = <60>; 2680 nvidia,aspm-pwr-on-t-us = <20>; 2681 nvidia,aspm-l0s-entrance-latency-us = <3>; 2682 2683 bus-range = <0x0 0xff>; 2684 2685 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2686 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2687 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2688 2689 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2690 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2691 interconnect-names = "dma-mem", "write"; 2692 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2693 iommu-map-mask = <0x0>; 2694 dma-coherent; 2695 2696 status = "disabled"; 2697 }; 2698 2699 pcie@141a0000 { 2700 compatible = "nvidia,tegra234-pcie"; 2701 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2702 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2703 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2704 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2705 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2706 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2707 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2708 2709 #address-cells = <3>; 2710 #size-cells = <2>; 2711 device_type = "pci"; 2712 num-lanes = <8>; 2713 num-viewport = <8>; 2714 linux,pci-domain = <5>; 2715 2716 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2717 clock-names = "core"; 2718 2719 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2720 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2721 reset-names = "apb", "core"; 2722 2723 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2724 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2725 interrupt-names = "intr", "msi"; 2726 2727 #interrupt-cells = <1>; 2728 interrupt-map-mask = <0 0 0 0>; 2729 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2730 2731 nvidia,bpmp = <&bpmp 5>; 2732 2733 nvidia,aspm-cmrt-us = <60>; 2734 nvidia,aspm-pwr-on-t-us = <20>; 2735 nvidia,aspm-l0s-entrance-latency-us = <3>; 2736 2737 bus-range = <0x0 0xff>; 2738 2739 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2740 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2741 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2742 2743 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2744 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2745 interconnect-names = "dma-mem", "write"; 2746 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2747 iommu-map-mask = <0x0>; 2748 dma-coherent; 2749 2750 status = "disabled"; 2751 }; 2752 2753 pcie-ep@141a0000 { 2754 compatible = "nvidia,tegra234-pcie-ep"; 2755 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2756 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2757 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2758 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2759 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2760 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2761 2762 num-lanes = <8>; 2763 2764 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2765 clock-names = "core"; 2766 2767 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2768 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2769 reset-names = "apb", "core"; 2770 2771 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2772 interrupt-names = "intr"; 2773 2774 nvidia,bpmp = <&bpmp 5>; 2775 2776 nvidia,enable-ext-refclk; 2777 nvidia,aspm-cmrt-us = <60>; 2778 nvidia,aspm-pwr-on-t-us = <20>; 2779 nvidia,aspm-l0s-entrance-latency-us = <3>; 2780 2781 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2782 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2783 interconnect-names = "dma-mem", "write"; 2784 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2785 iommu-map-mask = <0x0>; 2786 dma-coherent; 2787 2788 status = "disabled"; 2789 }; 2790 2791 pcie@141c0000 { 2792 compatible = "nvidia,tegra234-pcie"; 2793 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2794 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2795 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2796 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2797 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2798 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2799 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2800 2801 #address-cells = <3>; 2802 #size-cells = <2>; 2803 device_type = "pci"; 2804 num-lanes = <4>; 2805 num-viewport = <8>; 2806 linux,pci-domain = <6>; 2807 2808 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2809 clock-names = "core"; 2810 2811 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2812 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2813 reset-names = "apb", "core"; 2814 2815 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2816 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2817 interrupt-names = "intr", "msi"; 2818 2819 #interrupt-cells = <1>; 2820 interrupt-map-mask = <0 0 0 0>; 2821 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2822 2823 nvidia,bpmp = <&bpmp 6>; 2824 2825 nvidia,aspm-cmrt-us = <60>; 2826 nvidia,aspm-pwr-on-t-us = <20>; 2827 nvidia,aspm-l0s-entrance-latency-us = <3>; 2828 2829 bus-range = <0x0 0xff>; 2830 2831 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2832 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2833 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2834 2835 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2836 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2837 interconnect-names = "dma-mem", "write"; 2838 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2839 iommu-map-mask = <0x0>; 2840 dma-coherent; 2841 2842 status = "disabled"; 2843 }; 2844 2845 pcie-ep@141c0000 { 2846 compatible = "nvidia,tegra234-pcie-ep"; 2847 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2848 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2849 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2850 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2851 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2852 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2853 2854 num-lanes = <4>; 2855 2856 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2857 clock-names = "core"; 2858 2859 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2860 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2861 reset-names = "apb", "core"; 2862 2863 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2864 interrupt-names = "intr"; 2865 2866 nvidia,bpmp = <&bpmp 6>; 2867 2868 nvidia,enable-ext-refclk; 2869 nvidia,aspm-cmrt-us = <60>; 2870 nvidia,aspm-pwr-on-t-us = <20>; 2871 nvidia,aspm-l0s-entrance-latency-us = <3>; 2872 2873 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2874 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2875 interconnect-names = "dma-mem", "write"; 2876 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2877 iommu-map-mask = <0x0>; 2878 dma-coherent; 2879 2880 status = "disabled"; 2881 }; 2882 2883 pcie@141e0000 { 2884 compatible = "nvidia,tegra234-pcie"; 2885 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2886 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2887 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2888 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2889 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2890 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2891 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2892 2893 #address-cells = <3>; 2894 #size-cells = <2>; 2895 device_type = "pci"; 2896 num-lanes = <8>; 2897 num-viewport = <8>; 2898 linux,pci-domain = <7>; 2899 2900 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2901 clock-names = "core"; 2902 2903 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2904 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2905 reset-names = "apb", "core"; 2906 2907 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2908 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2909 interrupt-names = "intr", "msi"; 2910 2911 #interrupt-cells = <1>; 2912 interrupt-map-mask = <0 0 0 0>; 2913 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2914 2915 nvidia,bpmp = <&bpmp 7>; 2916 2917 nvidia,aspm-cmrt-us = <60>; 2918 nvidia,aspm-pwr-on-t-us = <20>; 2919 nvidia,aspm-l0s-entrance-latency-us = <3>; 2920 2921 bus-range = <0x0 0xff>; 2922 2923 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2924 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2925 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2926 2927 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2928 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2929 interconnect-names = "dma-mem", "write"; 2930 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2931 iommu-map-mask = <0x0>; 2932 dma-coherent; 2933 2934 status = "disabled"; 2935 }; 2936 2937 pcie-ep@141e0000 { 2938 compatible = "nvidia,tegra234-pcie-ep"; 2939 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2940 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2941 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2942 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2943 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2944 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2945 2946 num-lanes = <8>; 2947 2948 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2949 clock-names = "core"; 2950 2951 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2952 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2953 reset-names = "apb", "core"; 2954 2955 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2956 interrupt-names = "intr"; 2957 2958 nvidia,bpmp = <&bpmp 7>; 2959 2960 nvidia,enable-ext-refclk; 2961 nvidia,aspm-cmrt-us = <60>; 2962 nvidia,aspm-pwr-on-t-us = <20>; 2963 nvidia,aspm-l0s-entrance-latency-us = <3>; 2964 2965 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2966 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2967 interconnect-names = "dma-mem", "write"; 2968 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2969 iommu-map-mask = <0x0>; 2970 dma-coherent; 2971 2972 status = "disabled"; 2973 }; 2974 }; 2975 2976 sram@40000000 { 2977 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2978 reg = <0x0 0x40000000 0x0 0x80000>; 2979 2980 #address-cells = <1>; 2981 #size-cells = <1>; 2982 ranges = <0x0 0x0 0x40000000 0x80000>; 2983 2984 no-memory-wc; 2985 2986 cpu_bpmp_tx: sram@70000 { 2987 reg = <0x70000 0x1000>; 2988 label = "cpu-bpmp-tx"; 2989 pool; 2990 }; 2991 2992 cpu_bpmp_rx: sram@71000 { 2993 reg = <0x71000 0x1000>; 2994 label = "cpu-bpmp-rx"; 2995 pool; 2996 }; 2997 }; 2998 2999 bpmp: bpmp { 3000 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 3001 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 3002 TEGRA_HSP_DB_MASTER_BPMP>; 3003 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 3004 #clock-cells = <1>; 3005 #reset-cells = <1>; 3006 #power-domain-cells = <1>; 3007 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 3008 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 3009 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 3010 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 3011 interconnect-names = "read", "write", "dma-mem", "dma-write"; 3012 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 3013 3014 bpmp_i2c: i2c { 3015 compatible = "nvidia,tegra186-bpmp-i2c"; 3016 nvidia,bpmp-bus-id = <5>; 3017 #address-cells = <1>; 3018 #size-cells = <0>; 3019 }; 3020 }; 3021 3022 cpus { 3023 #address-cells = <1>; 3024 #size-cells = <0>; 3025 3026 cpu0_0: cpu@0 { 3027 compatible = "arm,cortex-a78"; 3028 device_type = "cpu"; 3029 reg = <0x00000>; 3030 3031 enable-method = "psci"; 3032 3033 i-cache-size = <65536>; 3034 i-cache-line-size = <64>; 3035 i-cache-sets = <256>; 3036 d-cache-size = <65536>; 3037 d-cache-line-size = <64>; 3038 d-cache-sets = <256>; 3039 next-level-cache = <&l2c0_0>; 3040 }; 3041 3042 cpu0_1: cpu@100 { 3043 compatible = "arm,cortex-a78"; 3044 device_type = "cpu"; 3045 reg = <0x00100>; 3046 3047 enable-method = "psci"; 3048 3049 i-cache-size = <65536>; 3050 i-cache-line-size = <64>; 3051 i-cache-sets = <256>; 3052 d-cache-size = <65536>; 3053 d-cache-line-size = <64>; 3054 d-cache-sets = <256>; 3055 next-level-cache = <&l2c0_1>; 3056 }; 3057 3058 cpu0_2: cpu@200 { 3059 compatible = "arm,cortex-a78"; 3060 device_type = "cpu"; 3061 reg = <0x00200>; 3062 3063 enable-method = "psci"; 3064 3065 i-cache-size = <65536>; 3066 i-cache-line-size = <64>; 3067 i-cache-sets = <256>; 3068 d-cache-size = <65536>; 3069 d-cache-line-size = <64>; 3070 d-cache-sets = <256>; 3071 next-level-cache = <&l2c0_2>; 3072 }; 3073 3074 cpu0_3: cpu@300 { 3075 compatible = "arm,cortex-a78"; 3076 device_type = "cpu"; 3077 reg = <0x00300>; 3078 3079 enable-method = "psci"; 3080 3081 i-cache-size = <65536>; 3082 i-cache-line-size = <64>; 3083 i-cache-sets = <256>; 3084 d-cache-size = <65536>; 3085 d-cache-line-size = <64>; 3086 d-cache-sets = <256>; 3087 next-level-cache = <&l2c0_3>; 3088 }; 3089 3090 cpu1_0: cpu@10000 { 3091 compatible = "arm,cortex-a78"; 3092 device_type = "cpu"; 3093 reg = <0x10000>; 3094 3095 enable-method = "psci"; 3096 3097 i-cache-size = <65536>; 3098 i-cache-line-size = <64>; 3099 i-cache-sets = <256>; 3100 d-cache-size = <65536>; 3101 d-cache-line-size = <64>; 3102 d-cache-sets = <256>; 3103 next-level-cache = <&l2c1_0>; 3104 }; 3105 3106 cpu1_1: cpu@10100 { 3107 compatible = "arm,cortex-a78"; 3108 device_type = "cpu"; 3109 reg = <0x10100>; 3110 3111 enable-method = "psci"; 3112 3113 i-cache-size = <65536>; 3114 i-cache-line-size = <64>; 3115 i-cache-sets = <256>; 3116 d-cache-size = <65536>; 3117 d-cache-line-size = <64>; 3118 d-cache-sets = <256>; 3119 next-level-cache = <&l2c1_1>; 3120 }; 3121 3122 cpu1_2: cpu@10200 { 3123 compatible = "arm,cortex-a78"; 3124 device_type = "cpu"; 3125 reg = <0x10200>; 3126 3127 enable-method = "psci"; 3128 3129 i-cache-size = <65536>; 3130 i-cache-line-size = <64>; 3131 i-cache-sets = <256>; 3132 d-cache-size = <65536>; 3133 d-cache-line-size = <64>; 3134 d-cache-sets = <256>; 3135 next-level-cache = <&l2c1_2>; 3136 }; 3137 3138 cpu1_3: cpu@10300 { 3139 compatible = "arm,cortex-a78"; 3140 device_type = "cpu"; 3141 reg = <0x10300>; 3142 3143 enable-method = "psci"; 3144 3145 i-cache-size = <65536>; 3146 i-cache-line-size = <64>; 3147 i-cache-sets = <256>; 3148 d-cache-size = <65536>; 3149 d-cache-line-size = <64>; 3150 d-cache-sets = <256>; 3151 next-level-cache = <&l2c1_3>; 3152 }; 3153 3154 cpu2_0: cpu@20000 { 3155 compatible = "arm,cortex-a78"; 3156 device_type = "cpu"; 3157 reg = <0x20000>; 3158 3159 enable-method = "psci"; 3160 3161 i-cache-size = <65536>; 3162 i-cache-line-size = <64>; 3163 i-cache-sets = <256>; 3164 d-cache-size = <65536>; 3165 d-cache-line-size = <64>; 3166 d-cache-sets = <256>; 3167 next-level-cache = <&l2c2_0>; 3168 }; 3169 3170 cpu2_1: cpu@20100 { 3171 compatible = "arm,cortex-a78"; 3172 device_type = "cpu"; 3173 reg = <0x20100>; 3174 3175 enable-method = "psci"; 3176 3177 i-cache-size = <65536>; 3178 i-cache-line-size = <64>; 3179 i-cache-sets = <256>; 3180 d-cache-size = <65536>; 3181 d-cache-line-size = <64>; 3182 d-cache-sets = <256>; 3183 next-level-cache = <&l2c2_1>; 3184 }; 3185 3186 cpu2_2: cpu@20200 { 3187 compatible = "arm,cortex-a78"; 3188 device_type = "cpu"; 3189 reg = <0x20200>; 3190 3191 enable-method = "psci"; 3192 3193 i-cache-size = <65536>; 3194 i-cache-line-size = <64>; 3195 i-cache-sets = <256>; 3196 d-cache-size = <65536>; 3197 d-cache-line-size = <64>; 3198 d-cache-sets = <256>; 3199 next-level-cache = <&l2c2_2>; 3200 }; 3201 3202 cpu2_3: cpu@20300 { 3203 compatible = "arm,cortex-a78"; 3204 device_type = "cpu"; 3205 reg = <0x20300>; 3206 3207 enable-method = "psci"; 3208 3209 i-cache-size = <65536>; 3210 i-cache-line-size = <64>; 3211 i-cache-sets = <256>; 3212 d-cache-size = <65536>; 3213 d-cache-line-size = <64>; 3214 d-cache-sets = <256>; 3215 next-level-cache = <&l2c2_3>; 3216 }; 3217 3218 cpu-map { 3219 cluster0 { 3220 core0 { 3221 cpu = <&cpu0_0>; 3222 }; 3223 3224 core1 { 3225 cpu = <&cpu0_1>; 3226 }; 3227 3228 core2 { 3229 cpu = <&cpu0_2>; 3230 }; 3231 3232 core3 { 3233 cpu = <&cpu0_3>; 3234 }; 3235 }; 3236 3237 cluster1 { 3238 core0 { 3239 cpu = <&cpu1_0>; 3240 }; 3241 3242 core1 { 3243 cpu = <&cpu1_1>; 3244 }; 3245 3246 core2 { 3247 cpu = <&cpu1_2>; 3248 }; 3249 3250 core3 { 3251 cpu = <&cpu1_3>; 3252 }; 3253 }; 3254 3255 cluster2 { 3256 core0 { 3257 cpu = <&cpu2_0>; 3258 }; 3259 3260 core1 { 3261 cpu = <&cpu2_1>; 3262 }; 3263 3264 core2 { 3265 cpu = <&cpu2_2>; 3266 }; 3267 3268 core3 { 3269 cpu = <&cpu2_3>; 3270 }; 3271 }; 3272 }; 3273 3274 l2c0_0: l2-cache00 { 3275 compatible = "cache"; 3276 cache-size = <262144>; 3277 cache-line-size = <64>; 3278 cache-sets = <512>; 3279 cache-unified; 3280 cache-level = <2>; 3281 next-level-cache = <&l3c0>; 3282 }; 3283 3284 l2c0_1: l2-cache01 { 3285 compatible = "cache"; 3286 cache-size = <262144>; 3287 cache-line-size = <64>; 3288 cache-sets = <512>; 3289 cache-unified; 3290 cache-level = <2>; 3291 next-level-cache = <&l3c0>; 3292 }; 3293 3294 l2c0_2: l2-cache02 { 3295 compatible = "cache"; 3296 cache-size = <262144>; 3297 cache-line-size = <64>; 3298 cache-sets = <512>; 3299 cache-unified; 3300 cache-level = <2>; 3301 next-level-cache = <&l3c0>; 3302 }; 3303 3304 l2c0_3: l2-cache03 { 3305 compatible = "cache"; 3306 cache-size = <262144>; 3307 cache-line-size = <64>; 3308 cache-sets = <512>; 3309 cache-unified; 3310 cache-level = <2>; 3311 next-level-cache = <&l3c0>; 3312 }; 3313 3314 l2c1_0: l2-cache10 { 3315 compatible = "cache"; 3316 cache-size = <262144>; 3317 cache-line-size = <64>; 3318 cache-sets = <512>; 3319 cache-unified; 3320 cache-level = <2>; 3321 next-level-cache = <&l3c1>; 3322 }; 3323 3324 l2c1_1: l2-cache11 { 3325 compatible = "cache"; 3326 cache-size = <262144>; 3327 cache-line-size = <64>; 3328 cache-sets = <512>; 3329 cache-unified; 3330 cache-level = <2>; 3331 next-level-cache = <&l3c1>; 3332 }; 3333 3334 l2c1_2: l2-cache12 { 3335 compatible = "cache"; 3336 cache-size = <262144>; 3337 cache-line-size = <64>; 3338 cache-sets = <512>; 3339 cache-unified; 3340 cache-level = <2>; 3341 next-level-cache = <&l3c1>; 3342 }; 3343 3344 l2c1_3: l2-cache13 { 3345 compatible = "cache"; 3346 cache-size = <262144>; 3347 cache-line-size = <64>; 3348 cache-sets = <512>; 3349 cache-unified; 3350 cache-level = <2>; 3351 next-level-cache = <&l3c1>; 3352 }; 3353 3354 l2c2_0: l2-cache20 { 3355 compatible = "cache"; 3356 cache-size = <262144>; 3357 cache-line-size = <64>; 3358 cache-sets = <512>; 3359 cache-unified; 3360 cache-level = <2>; 3361 next-level-cache = <&l3c2>; 3362 }; 3363 3364 l2c2_1: l2-cache21 { 3365 compatible = "cache"; 3366 cache-size = <262144>; 3367 cache-line-size = <64>; 3368 cache-sets = <512>; 3369 cache-unified; 3370 cache-level = <2>; 3371 next-level-cache = <&l3c2>; 3372 }; 3373 3374 l2c2_2: l2-cache22 { 3375 compatible = "cache"; 3376 cache-size = <262144>; 3377 cache-line-size = <64>; 3378 cache-sets = <512>; 3379 cache-unified; 3380 cache-level = <2>; 3381 next-level-cache = <&l3c2>; 3382 }; 3383 3384 l2c2_3: l2-cache23 { 3385 compatible = "cache"; 3386 cache-size = <262144>; 3387 cache-line-size = <64>; 3388 cache-sets = <512>; 3389 cache-unified; 3390 cache-level = <2>; 3391 next-level-cache = <&l3c2>; 3392 }; 3393 3394 l3c0: l3-cache0 { 3395 compatible = "cache"; 3396 cache-unified; 3397 cache-size = <2097152>; 3398 cache-line-size = <64>; 3399 cache-sets = <2048>; 3400 cache-level = <3>; 3401 }; 3402 3403 l3c1: l3-cache1 { 3404 compatible = "cache"; 3405 cache-unified; 3406 cache-size = <2097152>; 3407 cache-line-size = <64>; 3408 cache-sets = <2048>; 3409 cache-level = <3>; 3410 }; 3411 3412 l3c2: l3-cache2 { 3413 compatible = "cache"; 3414 cache-unified; 3415 cache-size = <2097152>; 3416 cache-line-size = <64>; 3417 cache-sets = <2048>; 3418 cache-level = <3>; 3419 }; 3420 }; 3421 3422 pmu { 3423 compatible = "arm,cortex-a78-pmu"; 3424 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3425 status = "okay"; 3426 }; 3427 3428 psci { 3429 compatible = "arm,psci-1.0"; 3430 status = "okay"; 3431 method = "smc"; 3432 }; 3433 3434 tcu: serial { 3435 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3436 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3437 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3438 mbox-names = "rx", "tx"; 3439 status = "disabled"; 3440 }; 3441 3442 sound { 3443 status = "disabled"; 3444 3445 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3446 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3447 clock-names = "pll_a", "plla_out0"; 3448 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3449 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3450 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3451 assigned-clock-parents = <0>, 3452 <&bpmp TEGRA234_CLK_PLLA>, 3453 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3454 }; 3455 3456 timer { 3457 compatible = "arm,armv8-timer"; 3458 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3459 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3460 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3461 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3462 interrupt-parent = <&gic>; 3463 always-on; 3464 }; 3465}; 3466