1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/power/tegra234-powergate.h> 9#include <dt-bindings/reset/tegra234-reset.h> 10 11/ { 12 compatible = "nvidia,tegra234"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 bus@0 { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 ranges = <0x0 0x0 0x0 0x40000000>; 23 24 gpcdma: dma-controller@2600000 { 25 compatible = "nvidia,tegra234-gpcdma", 26 "nvidia,tegra186-gpcdma"; 27 reg = <0x2600000 0x210000>; 28 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 29 reset-names = "gpcdma"; 30 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 61 #dma-cells = <1>; 62 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 63 dma-coherent; 64 }; 65 66 aconnect@2900000 { 67 compatible = "nvidia,tegra234-aconnect", 68 "nvidia,tegra210-aconnect"; 69 clocks = <&bpmp TEGRA234_CLK_APE>, 70 <&bpmp TEGRA234_CLK_APB2APE>; 71 clock-names = "ape", "apb2ape"; 72 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges = <0x02900000 0x02900000 0x200000>; 76 status = "disabled"; 77 78 tegra_ahub: ahub@2900800 { 79 compatible = "nvidia,tegra234-ahub"; 80 reg = <0x02900800 0x800>; 81 clocks = <&bpmp TEGRA234_CLK_AHUB>; 82 clock-names = "ahub"; 83 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 84 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges = <0x02900800 0x02900800 0x11800>; 88 status = "disabled"; 89 90 tegra_i2s1: i2s@2901000 { 91 compatible = "nvidia,tegra234-i2s", 92 "nvidia,tegra210-i2s"; 93 reg = <0x2901000 0x100>; 94 clocks = <&bpmp TEGRA234_CLK_I2S1>, 95 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 96 clock-names = "i2s", "sync_input"; 97 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 98 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 99 assigned-clock-rates = <1536000>; 100 sound-name-prefix = "I2S1"; 101 status = "disabled"; 102 }; 103 104 tegra_i2s2: i2s@2901100 { 105 compatible = "nvidia,tegra234-i2s", 106 "nvidia,tegra210-i2s"; 107 reg = <0x2901100 0x100>; 108 clocks = <&bpmp TEGRA234_CLK_I2S2>, 109 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 110 clock-names = "i2s", "sync_input"; 111 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 112 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 113 assigned-clock-rates = <1536000>; 114 sound-name-prefix = "I2S2"; 115 status = "disabled"; 116 }; 117 118 tegra_i2s3: i2s@2901200 { 119 compatible = "nvidia,tegra234-i2s", 120 "nvidia,tegra210-i2s"; 121 reg = <0x2901200 0x100>; 122 clocks = <&bpmp TEGRA234_CLK_I2S3>, 123 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 124 clock-names = "i2s", "sync_input"; 125 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 126 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 127 assigned-clock-rates = <1536000>; 128 sound-name-prefix = "I2S3"; 129 status = "disabled"; 130 }; 131 132 tegra_i2s4: i2s@2901300 { 133 compatible = "nvidia,tegra234-i2s", 134 "nvidia,tegra210-i2s"; 135 reg = <0x2901300 0x100>; 136 clocks = <&bpmp TEGRA234_CLK_I2S4>, 137 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 138 clock-names = "i2s", "sync_input"; 139 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 140 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 141 assigned-clock-rates = <1536000>; 142 sound-name-prefix = "I2S4"; 143 status = "disabled"; 144 }; 145 146 tegra_i2s5: i2s@2901400 { 147 compatible = "nvidia,tegra234-i2s", 148 "nvidia,tegra210-i2s"; 149 reg = <0x2901400 0x100>; 150 clocks = <&bpmp TEGRA234_CLK_I2S5>, 151 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 152 clock-names = "i2s", "sync_input"; 153 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 154 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 155 assigned-clock-rates = <1536000>; 156 sound-name-prefix = "I2S5"; 157 status = "disabled"; 158 }; 159 160 tegra_i2s6: i2s@2901500 { 161 compatible = "nvidia,tegra234-i2s", 162 "nvidia,tegra210-i2s"; 163 reg = <0x2901500 0x100>; 164 clocks = <&bpmp TEGRA234_CLK_I2S6>, 165 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 166 clock-names = "i2s", "sync_input"; 167 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 168 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 169 assigned-clock-rates = <1536000>; 170 sound-name-prefix = "I2S6"; 171 status = "disabled"; 172 }; 173 174 tegra_sfc1: sfc@2902000 { 175 compatible = "nvidia,tegra234-sfc", 176 "nvidia,tegra210-sfc"; 177 reg = <0x2902000 0x200>; 178 sound-name-prefix = "SFC1"; 179 status = "disabled"; 180 }; 181 182 tegra_sfc2: sfc@2902200 { 183 compatible = "nvidia,tegra234-sfc", 184 "nvidia,tegra210-sfc"; 185 reg = <0x2902200 0x200>; 186 sound-name-prefix = "SFC2"; 187 status = "disabled"; 188 }; 189 190 tegra_sfc3: sfc@2902400 { 191 compatible = "nvidia,tegra234-sfc", 192 "nvidia,tegra210-sfc"; 193 reg = <0x2902400 0x200>; 194 sound-name-prefix = "SFC3"; 195 status = "disabled"; 196 }; 197 198 tegra_sfc4: sfc@2902600 { 199 compatible = "nvidia,tegra234-sfc", 200 "nvidia,tegra210-sfc"; 201 reg = <0x2902600 0x200>; 202 sound-name-prefix = "SFC4"; 203 status = "disabled"; 204 }; 205 206 tegra_amx1: amx@2903000 { 207 compatible = "nvidia,tegra234-amx", 208 "nvidia,tegra194-amx"; 209 reg = <0x2903000 0x100>; 210 sound-name-prefix = "AMX1"; 211 status = "disabled"; 212 }; 213 214 tegra_amx2: amx@2903100 { 215 compatible = "nvidia,tegra234-amx", 216 "nvidia,tegra194-amx"; 217 reg = <0x2903100 0x100>; 218 sound-name-prefix = "AMX2"; 219 status = "disabled"; 220 }; 221 222 tegra_amx3: amx@2903200 { 223 compatible = "nvidia,tegra234-amx", 224 "nvidia,tegra194-amx"; 225 reg = <0x2903200 0x100>; 226 sound-name-prefix = "AMX3"; 227 status = "disabled"; 228 }; 229 230 tegra_amx4: amx@2903300 { 231 compatible = "nvidia,tegra234-amx", 232 "nvidia,tegra194-amx"; 233 reg = <0x2903300 0x100>; 234 sound-name-prefix = "AMX4"; 235 status = "disabled"; 236 }; 237 238 tegra_adx1: adx@2903800 { 239 compatible = "nvidia,tegra234-adx", 240 "nvidia,tegra210-adx"; 241 reg = <0x2903800 0x100>; 242 sound-name-prefix = "ADX1"; 243 status = "disabled"; 244 }; 245 246 tegra_adx2: adx@2903900 { 247 compatible = "nvidia,tegra234-adx", 248 "nvidia,tegra210-adx"; 249 reg = <0x2903900 0x100>; 250 sound-name-prefix = "ADX2"; 251 status = "disabled"; 252 }; 253 254 tegra_adx3: adx@2903a00 { 255 compatible = "nvidia,tegra234-adx", 256 "nvidia,tegra210-adx"; 257 reg = <0x2903a00 0x100>; 258 sound-name-prefix = "ADX3"; 259 status = "disabled"; 260 }; 261 262 tegra_adx4: adx@2903b00 { 263 compatible = "nvidia,tegra234-adx", 264 "nvidia,tegra210-adx"; 265 reg = <0x2903b00 0x100>; 266 sound-name-prefix = "ADX4"; 267 status = "disabled"; 268 }; 269 270 271 tegra_dmic1: dmic@2904000 { 272 compatible = "nvidia,tegra234-dmic", 273 "nvidia,tegra210-dmic"; 274 reg = <0x2904000 0x100>; 275 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 276 clock-names = "dmic"; 277 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 278 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 279 assigned-clock-rates = <3072000>; 280 sound-name-prefix = "DMIC1"; 281 status = "disabled"; 282 }; 283 284 tegra_dmic2: dmic@2904100 { 285 compatible = "nvidia,tegra234-dmic", 286 "nvidia,tegra210-dmic"; 287 reg = <0x2904100 0x100>; 288 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 289 clock-names = "dmic"; 290 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 291 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 292 assigned-clock-rates = <3072000>; 293 sound-name-prefix = "DMIC2"; 294 status = "disabled"; 295 }; 296 297 tegra_dmic3: dmic@2904200 { 298 compatible = "nvidia,tegra234-dmic", 299 "nvidia,tegra210-dmic"; 300 reg = <0x2904200 0x100>; 301 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 302 clock-names = "dmic"; 303 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 304 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 305 assigned-clock-rates = <3072000>; 306 sound-name-prefix = "DMIC3"; 307 status = "disabled"; 308 }; 309 310 tegra_dmic4: dmic@2904300 { 311 compatible = "nvidia,tegra234-dmic", 312 "nvidia,tegra210-dmic"; 313 reg = <0x2904300 0x100>; 314 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 315 clock-names = "dmic"; 316 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 317 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 318 assigned-clock-rates = <3072000>; 319 sound-name-prefix = "DMIC4"; 320 status = "disabled"; 321 }; 322 323 tegra_dspk1: dspk@2905000 { 324 compatible = "nvidia,tegra234-dspk", 325 "nvidia,tegra186-dspk"; 326 reg = <0x2905000 0x100>; 327 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 328 clock-names = "dspk"; 329 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 330 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 331 assigned-clock-rates = <12288000>; 332 sound-name-prefix = "DSPK1"; 333 status = "disabled"; 334 }; 335 336 tegra_dspk2: dspk@2905100 { 337 compatible = "nvidia,tegra234-dspk", 338 "nvidia,tegra186-dspk"; 339 reg = <0x2905100 0x100>; 340 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 341 clock-names = "dspk"; 342 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 343 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 344 assigned-clock-rates = <12288000>; 345 sound-name-prefix = "DSPK2"; 346 status = "disabled"; 347 }; 348 349 tegra_ope1: processing-engine@2908000 { 350 compatible = "nvidia,tegra234-ope", 351 "nvidia,tegra210-ope"; 352 reg = <0x2908000 0x100>; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 ranges; 356 sound-name-prefix = "OPE1"; 357 status = "disabled"; 358 359 equalizer@2908100 { 360 compatible = "nvidia,tegra234-peq", 361 "nvidia,tegra210-peq"; 362 reg = <0x2908100 0x100>; 363 }; 364 365 dynamic-range-compressor@2908200 { 366 compatible = "nvidia,tegra234-mbdrc", 367 "nvidia,tegra210-mbdrc"; 368 reg = <0x2908200 0x200>; 369 }; 370 }; 371 372 tegra_mvc1: mvc@290a000 { 373 compatible = "nvidia,tegra234-mvc", 374 "nvidia,tegra210-mvc"; 375 reg = <0x290a000 0x200>; 376 sound-name-prefix = "MVC1"; 377 status = "disabled"; 378 }; 379 380 tegra_mvc2: mvc@290a200 { 381 compatible = "nvidia,tegra234-mvc", 382 "nvidia,tegra210-mvc"; 383 reg = <0x290a200 0x200>; 384 sound-name-prefix = "MVC2"; 385 status = "disabled"; 386 }; 387 388 tegra_amixer: amixer@290bb00 { 389 compatible = "nvidia,tegra234-amixer", 390 "nvidia,tegra210-amixer"; 391 reg = <0x290bb00 0x800>; 392 sound-name-prefix = "MIXER1"; 393 status = "disabled"; 394 }; 395 396 tegra_admaif: admaif@290f000 { 397 compatible = "nvidia,tegra234-admaif", 398 "nvidia,tegra186-admaif"; 399 reg = <0x0290f000 0x1000>; 400 dmas = <&adma 1>, <&adma 1>, 401 <&adma 2>, <&adma 2>, 402 <&adma 3>, <&adma 3>, 403 <&adma 4>, <&adma 4>, 404 <&adma 5>, <&adma 5>, 405 <&adma 6>, <&adma 6>, 406 <&adma 7>, <&adma 7>, 407 <&adma 8>, <&adma 8>, 408 <&adma 9>, <&adma 9>, 409 <&adma 10>, <&adma 10>, 410 <&adma 11>, <&adma 11>, 411 <&adma 12>, <&adma 12>, 412 <&adma 13>, <&adma 13>, 413 <&adma 14>, <&adma 14>, 414 <&adma 15>, <&adma 15>, 415 <&adma 16>, <&adma 16>, 416 <&adma 17>, <&adma 17>, 417 <&adma 18>, <&adma 18>, 418 <&adma 19>, <&adma 19>, 419 <&adma 20>, <&adma 20>; 420 dma-names = "rx1", "tx1", 421 "rx2", "tx2", 422 "rx3", "tx3", 423 "rx4", "tx4", 424 "rx5", "tx5", 425 "rx6", "tx6", 426 "rx7", "tx7", 427 "rx8", "tx8", 428 "rx9", "tx9", 429 "rx10", "tx10", 430 "rx11", "tx11", 431 "rx12", "tx12", 432 "rx13", "tx13", 433 "rx14", "tx14", 434 "rx15", "tx15", 435 "rx16", "tx16", 436 "rx17", "tx17", 437 "rx18", "tx18", 438 "rx19", "tx19", 439 "rx20", "tx20"; 440 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 441 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 442 interconnect-names = "dma-mem", "write"; 443 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 444 status = "disabled"; 445 }; 446 447 tegra_asrc: asrc@2910000 { 448 compatible = "nvidia,tegra234-asrc", 449 "nvidia,tegra186-asrc"; 450 reg = <0x2910000 0x2000>; 451 sound-name-prefix = "ASRC1"; 452 status = "disabled"; 453 }; 454 }; 455 456 adma: dma-controller@2930000 { 457 compatible = "nvidia,tegra234-adma", 458 "nvidia,tegra186-adma"; 459 reg = <0x02930000 0x20000>; 460 interrupt-parent = <&agic>; 461 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 493 #dma-cells = <1>; 494 clocks = <&bpmp TEGRA234_CLK_AHUB>; 495 clock-names = "d_audio"; 496 status = "disabled"; 497 }; 498 499 agic: interrupt-controller@2a40000 { 500 compatible = "nvidia,tegra234-agic", 501 "nvidia,tegra210-agic"; 502 #interrupt-cells = <3>; 503 interrupt-controller; 504 reg = <0x02a41000 0x1000>, 505 <0x02a42000 0x2000>; 506 interrupts = <GIC_SPI 145 507 (GIC_CPU_MASK_SIMPLE(4) | 508 IRQ_TYPE_LEVEL_HIGH)>; 509 clocks = <&bpmp TEGRA234_CLK_APE>; 510 clock-names = "clk"; 511 status = "disabled"; 512 }; 513 }; 514 515 misc@100000 { 516 compatible = "nvidia,tegra234-misc"; 517 reg = <0x00100000 0xf000>, 518 <0x0010f000 0x1000>; 519 status = "okay"; 520 }; 521 522 timer@2080000 { 523 compatible = "nvidia,tegra234-timer"; 524 reg = <0x02080000 0x00121000>; 525 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 541 status = "okay"; 542 }; 543 544 host1x@13e00000 { 545 compatible = "nvidia,tegra234-host1x"; 546 reg = <0x13e00000 0x10000>, 547 <0x13e10000 0x10000>, 548 <0x13e40000 0x10000>; 549 reg-names = "common", "hypervisor", "vm"; 550 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 559 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 560 "syncpt5", "syncpt6", "syncpt7", "host1x"; 561 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 562 clock-names = "host1x"; 563 564 #address-cells = <1>; 565 #size-cells = <1>; 566 567 ranges = <0x15000000 0x15000000 0x01000000>; 568 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 569 interconnect-names = "dma-mem"; 570 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 571 572 /* Context isolation domains */ 573 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 574 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 575 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 576 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 577 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 578 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 579 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 580 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 581 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 582 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 583 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 584 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 585 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 586 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 587 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 588 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 589 590 vic@15340000 { 591 compatible = "nvidia,tegra234-vic"; 592 reg = <0x15340000 0x00040000>; 593 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&bpmp TEGRA234_CLK_VIC>; 595 clock-names = "vic"; 596 resets = <&bpmp TEGRA234_RESET_VIC>; 597 reset-names = "vic"; 598 599 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 600 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 601 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 602 interconnect-names = "dma-mem", "write"; 603 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 604 dma-coherent; 605 }; 606 }; 607 608 gpio: gpio@2200000 { 609 compatible = "nvidia,tegra234-gpio"; 610 reg-names = "security", "gpio"; 611 reg = <0x02200000 0x10000>, 612 <0x02210000 0x10000>; 613 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 661 #interrupt-cells = <2>; 662 interrupt-controller; 663 #gpio-cells = <2>; 664 gpio-controller; 665 }; 666 667 mc: memory-controller@2c00000 { 668 compatible = "nvidia,tegra234-mc"; 669 reg = <0x02c00000 0x10000>, /* MC-SID */ 670 <0x02c10000 0x10000>, /* MC Broadcast*/ 671 <0x02c20000 0x10000>, /* MC0 */ 672 <0x02c30000 0x10000>, /* MC1 */ 673 <0x02c40000 0x10000>, /* MC2 */ 674 <0x02c50000 0x10000>, /* MC3 */ 675 <0x02b80000 0x10000>, /* MC4 */ 676 <0x02b90000 0x10000>, /* MC5 */ 677 <0x02ba0000 0x10000>, /* MC6 */ 678 <0x02bb0000 0x10000>, /* MC7 */ 679 <0x01700000 0x10000>, /* MC8 */ 680 <0x01710000 0x10000>, /* MC9 */ 681 <0x01720000 0x10000>, /* MC10 */ 682 <0x01730000 0x10000>, /* MC11 */ 683 <0x01740000 0x10000>, /* MC12 */ 684 <0x01750000 0x10000>, /* MC13 */ 685 <0x01760000 0x10000>, /* MC14 */ 686 <0x01770000 0x10000>; /* MC15 */ 687 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 688 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 689 "ch11", "ch12", "ch13", "ch14", "ch15"; 690 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 691 #interconnect-cells = <1>; 692 status = "okay"; 693 694 #address-cells = <2>; 695 #size-cells = <2>; 696 697 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 698 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 699 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 700 701 /* 702 * Bit 39 of addresses passing through the memory 703 * controller selects the XBAR format used when memory 704 * is accessed. This is used to transparently access 705 * memory in the XBAR format used by the discrete GPU 706 * (bit 39 set) or Tegra (bit 39 clear). 707 * 708 * As a consequence, the operating system must ensure 709 * that bit 39 is never used implicitly, for example 710 * via an I/O virtual address mapping of an IOMMU. If 711 * devices require access to the XBAR switch, their 712 * drivers must set this bit explicitly. 713 * 714 * Limit the DMA range for memory clients to [38:0]. 715 */ 716 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 717 718 emc: external-memory-controller@2c60000 { 719 compatible = "nvidia,tegra234-emc"; 720 reg = <0x0 0x02c60000 0x0 0x90000>, 721 <0x0 0x01780000 0x0 0x80000>; 722 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&bpmp TEGRA234_CLK_EMC>; 724 clock-names = "emc"; 725 status = "okay"; 726 727 #interconnect-cells = <0>; 728 729 nvidia,bpmp = <&bpmp>; 730 }; 731 }; 732 733 uarta: serial@3100000 { 734 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 735 reg = <0x03100000 0x10000>; 736 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&bpmp TEGRA234_CLK_UARTA>; 738 clock-names = "serial"; 739 resets = <&bpmp TEGRA234_RESET_UARTA>; 740 reset-names = "serial"; 741 status = "disabled"; 742 }; 743 744 gen1_i2c: i2c@3160000 { 745 compatible = "nvidia,tegra194-i2c"; 746 reg = <0x3160000 0x100>; 747 status = "disabled"; 748 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 749 clock-frequency = <400000>; 750 clocks = <&bpmp TEGRA234_CLK_I2C1 751 &bpmp TEGRA234_CLK_PLLP_OUT0>; 752 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 753 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 754 clock-names = "div-clk", "parent"; 755 resets = <&bpmp TEGRA234_RESET_I2C1>; 756 reset-names = "i2c"; 757 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 758 dma-coherent; 759 dmas = <&gpcdma 21>, <&gpcdma 21>; 760 dma-names = "rx", "tx"; 761 }; 762 763 cam_i2c: i2c@3180000 { 764 compatible = "nvidia,tegra194-i2c"; 765 reg = <0x3180000 0x100>; 766 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 767 status = "disabled"; 768 clock-frequency = <400000>; 769 clocks = <&bpmp TEGRA234_CLK_I2C3 770 &bpmp TEGRA234_CLK_PLLP_OUT0>; 771 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 772 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 773 clock-names = "div-clk", "parent"; 774 resets = <&bpmp TEGRA234_RESET_I2C3>; 775 reset-names = "i2c"; 776 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 777 dma-coherent; 778 dmas = <&gpcdma 23>, <&gpcdma 23>; 779 dma-names = "rx", "tx"; 780 }; 781 782 dp_aux_ch1_i2c: i2c@3190000 { 783 compatible = "nvidia,tegra194-i2c"; 784 reg = <0x3190000 0x100>; 785 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 786 status = "disabled"; 787 clock-frequency = <100000>; 788 clocks = <&bpmp TEGRA234_CLK_I2C4 789 &bpmp TEGRA234_CLK_PLLP_OUT0>; 790 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 791 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 792 clock-names = "div-clk", "parent"; 793 resets = <&bpmp TEGRA234_RESET_I2C4>; 794 reset-names = "i2c"; 795 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 796 dma-coherent; 797 dmas = <&gpcdma 26>, <&gpcdma 26>; 798 dma-names = "rx", "tx"; 799 }; 800 801 dp_aux_ch0_i2c: i2c@31b0000 { 802 compatible = "nvidia,tegra194-i2c"; 803 reg = <0x31b0000 0x100>; 804 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 805 status = "disabled"; 806 clock-frequency = <100000>; 807 clocks = <&bpmp TEGRA234_CLK_I2C6 808 &bpmp TEGRA234_CLK_PLLP_OUT0>; 809 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 810 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 811 clock-names = "div-clk", "parent"; 812 resets = <&bpmp TEGRA234_RESET_I2C6>; 813 reset-names = "i2c"; 814 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 815 dma-coherent; 816 dmas = <&gpcdma 30>, <&gpcdma 30>; 817 dma-names = "rx", "tx"; 818 }; 819 820 dp_aux_ch2_i2c: i2c@31c0000 { 821 compatible = "nvidia,tegra194-i2c"; 822 reg = <0x31c0000 0x100>; 823 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 824 status = "disabled"; 825 clock-frequency = <100000>; 826 clocks = <&bpmp TEGRA234_CLK_I2C7 827 &bpmp TEGRA234_CLK_PLLP_OUT0>; 828 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 829 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 830 clock-names = "div-clk", "parent"; 831 resets = <&bpmp TEGRA234_RESET_I2C7>; 832 reset-names = "i2c"; 833 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 834 dma-coherent; 835 dmas = <&gpcdma 27>, <&gpcdma 27>; 836 dma-names = "rx", "tx"; 837 }; 838 839 dp_aux_ch3_i2c: i2c@31e0000 { 840 compatible = "nvidia,tegra194-i2c"; 841 reg = <0x31e0000 0x100>; 842 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 843 status = "disabled"; 844 clock-frequency = <100000>; 845 clocks = <&bpmp TEGRA234_CLK_I2C9 846 &bpmp TEGRA234_CLK_PLLP_OUT0>; 847 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 848 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 849 clock-names = "div-clk", "parent"; 850 resets = <&bpmp TEGRA234_RESET_I2C9>; 851 reset-names = "i2c"; 852 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 853 dma-coherent; 854 dmas = <&gpcdma 31>, <&gpcdma 31>; 855 dma-names = "rx", "tx"; 856 }; 857 858 spi@3270000 { 859 compatible = "nvidia,tegra234-qspi"; 860 reg = <0x3270000 0x1000>; 861 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 865 <&bpmp TEGRA234_CLK_QSPI0_PM>; 866 clock-names = "qspi", "qspi_out"; 867 resets = <&bpmp TEGRA234_RESET_QSPI0>; 868 reset-names = "qspi"; 869 status = "disabled"; 870 }; 871 872 pwm1: pwm@3280000 { 873 compatible = "nvidia,tegra194-pwm", 874 "nvidia,tegra186-pwm"; 875 reg = <0x3280000 0x10000>; 876 clocks = <&bpmp TEGRA234_CLK_PWM1>; 877 clock-names = "pwm"; 878 resets = <&bpmp TEGRA234_RESET_PWM1>; 879 reset-names = "pwm"; 880 status = "disabled"; 881 #pwm-cells = <2>; 882 }; 883 884 spi@3300000 { 885 compatible = "nvidia,tegra234-qspi"; 886 reg = <0x3300000 0x1000>; 887 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 891 <&bpmp TEGRA234_CLK_QSPI1_PM>; 892 clock-names = "qspi", "qspi_out"; 893 resets = <&bpmp TEGRA234_RESET_QSPI1>; 894 reset-names = "qspi"; 895 status = "disabled"; 896 }; 897 898 mmc@3460000 { 899 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 900 reg = <0x03460000 0x20000>; 901 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 903 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 904 clock-names = "sdhci", "tmclk"; 905 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 906 <&bpmp TEGRA234_CLK_PLLC4>; 907 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 908 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 909 reset-names = "sdhci"; 910 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 911 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 912 interconnect-names = "dma-mem", "write"; 913 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 914 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 915 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 916 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 917 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 918 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 919 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 920 nvidia,default-tap = <0x8>; 921 nvidia,default-trim = <0x14>; 922 nvidia,dqs-trim = <40>; 923 supports-cqe; 924 status = "disabled"; 925 }; 926 927 hda@3510000 { 928 compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 929 reg = <0x3510000 0x10000>; 930 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 932 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 933 clock-names = "hda", "hda2codec_2x"; 934 resets = <&bpmp TEGRA234_RESET_HDA>, 935 <&bpmp TEGRA234_RESET_HDACODEC>; 936 reset-names = "hda", "hda2codec_2x"; 937 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 938 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 939 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 940 interconnect-names = "dma-mem", "write"; 941 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 942 status = "disabled"; 943 }; 944 945 fuse@3810000 { 946 compatible = "nvidia,tegra234-efuse"; 947 reg = <0x03810000 0x10000>; 948 clocks = <&bpmp TEGRA234_CLK_FUSE>; 949 clock-names = "fuse"; 950 }; 951 952 hsp_top0: hsp@3c00000 { 953 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 954 reg = <0x03c00000 0xa0000>; 955 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 964 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 965 "shared3", "shared4", "shared5", "shared6", 966 "shared7"; 967 #mbox-cells = <2>; 968 }; 969 970 ethernet@6800000 { 971 compatible = "nvidia,tegra234-mgbe"; 972 reg = <0x06800000 0x10000>, 973 <0x06810000 0x10000>, 974 <0x068a0000 0x10000>; 975 reg-names = "hypervisor", "mac", "xpcs"; 976 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 977 interrupt-names = "common"; 978 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 979 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 980 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 981 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 982 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 983 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 984 <&bpmp TEGRA234_CLK_MGBE0_TX>, 985 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 986 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 987 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 988 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 989 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 990 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 991 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 992 "rx-pcs", "tx-pcs"; 993 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 994 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 995 reset-names = "mac", "pcs"; 996 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 997 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 998 interconnect-names = "dma-mem", "write"; 999 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1000 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1001 status = "disabled"; 1002 }; 1003 1004 ethernet@6900000 { 1005 compatible = "nvidia,tegra234-mgbe"; 1006 reg = <0x06900000 0x10000>, 1007 <0x06910000 0x10000>, 1008 <0x069a0000 0x10000>; 1009 reg-names = "hypervisor", "mac", "xpcs"; 1010 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "common"; 1012 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1013 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1014 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1015 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1016 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1017 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1018 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1019 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1020 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1021 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1022 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1023 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1024 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1025 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1026 "rx-pcs", "tx-pcs"; 1027 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1028 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1029 reset-names = "mac", "pcs"; 1030 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1031 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1032 interconnect-names = "dma-mem", "write"; 1033 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1034 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1035 status = "disabled"; 1036 }; 1037 1038 ethernet@6a00000 { 1039 compatible = "nvidia,tegra234-mgbe"; 1040 reg = <0x06a00000 0x10000>, 1041 <0x06a10000 0x10000>, 1042 <0x06aa0000 0x10000>; 1043 reg-names = "hypervisor", "mac", "xpcs"; 1044 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1045 interrupt-names = "common"; 1046 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1047 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1048 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1049 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1050 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1051 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1052 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1053 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1054 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1055 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1056 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1057 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1058 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1059 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1060 "rx-pcs", "tx-pcs"; 1061 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1062 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1063 reset-names = "mac", "pcs"; 1064 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1065 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1066 interconnect-names = "dma-mem", "write"; 1067 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1068 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1069 status = "disabled"; 1070 }; 1071 1072 ethernet@6b00000 { 1073 compatible = "nvidia,tegra234-mgbe"; 1074 reg = <0x06b00000 0x10000>, 1075 <0x06b10000 0x10000>, 1076 <0x06ba0000 0x10000>; 1077 reg-names = "hypervisor", "mac", "xpcs"; 1078 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1079 interrupt-names = "common"; 1080 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1081 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1082 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1083 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1084 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1085 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1086 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1087 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1088 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1089 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1090 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1091 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1092 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1093 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1094 "rx-pcs", "tx-pcs"; 1095 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1096 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1097 reset-names = "mac", "pcs"; 1098 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1099 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1100 interconnect-names = "dma-mem", "write"; 1101 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1102 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1103 status = "disabled"; 1104 }; 1105 1106 smmu_niso1: iommu@8000000 { 1107 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1108 reg = <0x8000000 0x1000000>, 1109 <0x7000000 0x1000000>; 1110 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1240 stream-match-mask = <0x7f80>; 1241 #global-interrupts = <2>; 1242 #iommu-cells = <1>; 1243 1244 nvidia,memory-controller = <&mc>; 1245 status = "okay"; 1246 }; 1247 1248 sce-fabric@b600000 { 1249 compatible = "nvidia,tegra234-sce-fabric"; 1250 reg = <0xb600000 0x40000>; 1251 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1252 status = "okay"; 1253 }; 1254 1255 rce-fabric@be00000 { 1256 compatible = "nvidia,tegra234-rce-fabric"; 1257 reg = <0xbe00000 0x40000>; 1258 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1259 status = "okay"; 1260 }; 1261 1262 p2u_hsio_0: phy@3e00000 { 1263 compatible = "nvidia,tegra234-p2u"; 1264 reg = <0x03e00000 0x10000>; 1265 reg-names = "ctl"; 1266 1267 #phy-cells = <0>; 1268 }; 1269 1270 p2u_hsio_1: phy@3e10000 { 1271 compatible = "nvidia,tegra234-p2u"; 1272 reg = <0x03e10000 0x10000>; 1273 reg-names = "ctl"; 1274 1275 #phy-cells = <0>; 1276 }; 1277 1278 p2u_hsio_2: phy@3e20000 { 1279 compatible = "nvidia,tegra234-p2u"; 1280 reg = <0x03e20000 0x10000>; 1281 reg-names = "ctl"; 1282 1283 #phy-cells = <0>; 1284 }; 1285 1286 p2u_hsio_3: phy@3e30000 { 1287 compatible = "nvidia,tegra234-p2u"; 1288 reg = <0x03e30000 0x10000>; 1289 reg-names = "ctl"; 1290 1291 #phy-cells = <0>; 1292 }; 1293 1294 p2u_hsio_4: phy@3e40000 { 1295 compatible = "nvidia,tegra234-p2u"; 1296 reg = <0x03e40000 0x10000>; 1297 reg-names = "ctl"; 1298 1299 #phy-cells = <0>; 1300 }; 1301 1302 p2u_hsio_5: phy@3e50000 { 1303 compatible = "nvidia,tegra234-p2u"; 1304 reg = <0x03e50000 0x10000>; 1305 reg-names = "ctl"; 1306 1307 #phy-cells = <0>; 1308 }; 1309 1310 p2u_hsio_6: phy@3e60000 { 1311 compatible = "nvidia,tegra234-p2u"; 1312 reg = <0x03e60000 0x10000>; 1313 reg-names = "ctl"; 1314 1315 #phy-cells = <0>; 1316 }; 1317 1318 p2u_hsio_7: phy@3e70000 { 1319 compatible = "nvidia,tegra234-p2u"; 1320 reg = <0x03e70000 0x10000>; 1321 reg-names = "ctl"; 1322 1323 #phy-cells = <0>; 1324 }; 1325 1326 p2u_nvhs_0: phy@3e90000 { 1327 compatible = "nvidia,tegra234-p2u"; 1328 reg = <0x03e90000 0x10000>; 1329 reg-names = "ctl"; 1330 1331 #phy-cells = <0>; 1332 }; 1333 1334 p2u_nvhs_1: phy@3ea0000 { 1335 compatible = "nvidia,tegra234-p2u"; 1336 reg = <0x03ea0000 0x10000>; 1337 reg-names = "ctl"; 1338 1339 #phy-cells = <0>; 1340 }; 1341 1342 p2u_nvhs_2: phy@3eb0000 { 1343 compatible = "nvidia,tegra234-p2u"; 1344 reg = <0x03eb0000 0x10000>; 1345 reg-names = "ctl"; 1346 1347 #phy-cells = <0>; 1348 }; 1349 1350 p2u_nvhs_3: phy@3ec0000 { 1351 compatible = "nvidia,tegra234-p2u"; 1352 reg = <0x03ec0000 0x10000>; 1353 reg-names = "ctl"; 1354 1355 #phy-cells = <0>; 1356 }; 1357 1358 p2u_nvhs_4: phy@3ed0000 { 1359 compatible = "nvidia,tegra234-p2u"; 1360 reg = <0x03ed0000 0x10000>; 1361 reg-names = "ctl"; 1362 1363 #phy-cells = <0>; 1364 }; 1365 1366 p2u_nvhs_5: phy@3ee0000 { 1367 compatible = "nvidia,tegra234-p2u"; 1368 reg = <0x03ee0000 0x10000>; 1369 reg-names = "ctl"; 1370 1371 #phy-cells = <0>; 1372 }; 1373 1374 p2u_nvhs_6: phy@3ef0000 { 1375 compatible = "nvidia,tegra234-p2u"; 1376 reg = <0x03ef0000 0x10000>; 1377 reg-names = "ctl"; 1378 1379 #phy-cells = <0>; 1380 }; 1381 1382 p2u_nvhs_7: phy@3f00000 { 1383 compatible = "nvidia,tegra234-p2u"; 1384 reg = <0x03f00000 0x10000>; 1385 reg-names = "ctl"; 1386 1387 #phy-cells = <0>; 1388 }; 1389 1390 p2u_gbe_0: phy@3f20000 { 1391 compatible = "nvidia,tegra234-p2u"; 1392 reg = <0x03f20000 0x10000>; 1393 reg-names = "ctl"; 1394 1395 #phy-cells = <0>; 1396 }; 1397 1398 p2u_gbe_1: phy@3f30000 { 1399 compatible = "nvidia,tegra234-p2u"; 1400 reg = <0x03f30000 0x10000>; 1401 reg-names = "ctl"; 1402 1403 #phy-cells = <0>; 1404 }; 1405 1406 p2u_gbe_2: phy@3f40000 { 1407 compatible = "nvidia,tegra234-p2u"; 1408 reg = <0x03f40000 0x10000>; 1409 reg-names = "ctl"; 1410 1411 #phy-cells = <0>; 1412 }; 1413 1414 p2u_gbe_3: phy@3f50000 { 1415 compatible = "nvidia,tegra234-p2u"; 1416 reg = <0x03f50000 0x10000>; 1417 reg-names = "ctl"; 1418 1419 #phy-cells = <0>; 1420 }; 1421 1422 p2u_gbe_4: phy@3f60000 { 1423 compatible = "nvidia,tegra234-p2u"; 1424 reg = <0x03f60000 0x10000>; 1425 reg-names = "ctl"; 1426 1427 #phy-cells = <0>; 1428 }; 1429 1430 p2u_gbe_5: phy@3f70000 { 1431 compatible = "nvidia,tegra234-p2u"; 1432 reg = <0x03f70000 0x10000>; 1433 reg-names = "ctl"; 1434 1435 #phy-cells = <0>; 1436 }; 1437 1438 p2u_gbe_6: phy@3f80000 { 1439 compatible = "nvidia,tegra234-p2u"; 1440 reg = <0x03f80000 0x10000>; 1441 reg-names = "ctl"; 1442 1443 #phy-cells = <0>; 1444 }; 1445 1446 p2u_gbe_7: phy@3f90000 { 1447 compatible = "nvidia,tegra234-p2u"; 1448 reg = <0x03f90000 0x10000>; 1449 reg-names = "ctl"; 1450 1451 #phy-cells = <0>; 1452 }; 1453 1454 hsp_aon: hsp@c150000 { 1455 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1456 reg = <0x0c150000 0x90000>; 1457 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1461 /* 1462 * Shared interrupt 0 is routed only to AON/SPE, so 1463 * we only have 4 shared interrupts for the CCPLEX. 1464 */ 1465 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1466 #mbox-cells = <2>; 1467 }; 1468 1469 gen2_i2c: i2c@c240000 { 1470 compatible = "nvidia,tegra194-i2c"; 1471 reg = <0xc240000 0x100>; 1472 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1473 status = "disabled"; 1474 clock-frequency = <100000>; 1475 clocks = <&bpmp TEGRA234_CLK_I2C2 1476 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1477 clock-names = "div-clk", "parent"; 1478 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1479 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1480 resets = <&bpmp TEGRA234_RESET_I2C2>; 1481 reset-names = "i2c"; 1482 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1483 dma-coherent; 1484 dmas = <&gpcdma 22>, <&gpcdma 22>; 1485 dma-names = "rx", "tx"; 1486 }; 1487 1488 gen8_i2c: i2c@c250000 { 1489 compatible = "nvidia,tegra194-i2c"; 1490 reg = <0xc250000 0x100>; 1491 nvidia,hw-instance-id = <0x7>; 1492 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1493 status = "disabled"; 1494 clock-frequency = <400000>; 1495 clocks = <&bpmp TEGRA234_CLK_I2C8 1496 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1497 clock-names = "div-clk", "parent"; 1498 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1499 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1500 resets = <&bpmp TEGRA234_RESET_I2C8>; 1501 reset-names = "i2c"; 1502 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1503 dma-coherent; 1504 dmas = <&gpcdma 0>, <&gpcdma 0>; 1505 dma-names = "rx", "tx"; 1506 }; 1507 1508 rtc@c2a0000 { 1509 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1510 reg = <0x0c2a0000 0x10000>; 1511 interrupt-parent = <&pmc>; 1512 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1513 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1514 clock-names = "rtc"; 1515 status = "disabled"; 1516 }; 1517 1518 gpio_aon: gpio@c2f0000 { 1519 compatible = "nvidia,tegra234-gpio-aon"; 1520 reg-names = "security", "gpio"; 1521 reg = <0x0c2f0000 0x1000>, 1522 <0x0c2f1000 0x1000>; 1523 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1527 #interrupt-cells = <2>; 1528 interrupt-controller; 1529 #gpio-cells = <2>; 1530 gpio-controller; 1531 }; 1532 1533 pmc: pmc@c360000 { 1534 compatible = "nvidia,tegra234-pmc"; 1535 reg = <0x0c360000 0x10000>, 1536 <0x0c370000 0x10000>, 1537 <0x0c380000 0x10000>, 1538 <0x0c390000 0x10000>, 1539 <0x0c3a0000 0x10000>; 1540 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1541 1542 #interrupt-cells = <2>; 1543 interrupt-controller; 1544 }; 1545 1546 aon-fabric@c600000 { 1547 compatible = "nvidia,tegra234-aon-fabric"; 1548 reg = <0xc600000 0x40000>; 1549 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1550 status = "okay"; 1551 }; 1552 1553 bpmp-fabric@d600000 { 1554 compatible = "nvidia,tegra234-bpmp-fabric"; 1555 reg = <0xd600000 0x40000>; 1556 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1557 status = "okay"; 1558 }; 1559 1560 dce-fabric@de00000 { 1561 compatible = "nvidia,tegra234-sce-fabric"; 1562 reg = <0xde00000 0x40000>; 1563 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1564 status = "okay"; 1565 }; 1566 1567 gic: interrupt-controller@f400000 { 1568 compatible = "arm,gic-v3"; 1569 reg = <0x0f400000 0x010000>, /* GICD */ 1570 <0x0f440000 0x200000>; /* GICR */ 1571 interrupt-parent = <&gic>; 1572 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1573 1574 #redistributor-regions = <1>; 1575 #interrupt-cells = <3>; 1576 interrupt-controller; 1577 }; 1578 1579 smmu_iso: iommu@10000000{ 1580 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1581 reg = <0x10000000 0x1000000>; 1582 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1711 stream-match-mask = <0x7f80>; 1712 #global-interrupts = <1>; 1713 #iommu-cells = <1>; 1714 1715 nvidia,memory-controller = <&mc>; 1716 status = "okay"; 1717 }; 1718 1719 smmu_niso0: iommu@12000000 { 1720 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1721 reg = <0x12000000 0x1000000>, 1722 <0x11000000 0x1000000>; 1723 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1853 stream-match-mask = <0x7f80>; 1854 #global-interrupts = <2>; 1855 #iommu-cells = <1>; 1856 1857 nvidia,memory-controller = <&mc>; 1858 status = "okay"; 1859 }; 1860 1861 cbb-fabric@13a00000 { 1862 compatible = "nvidia,tegra234-cbb-fabric"; 1863 reg = <0x13a00000 0x400000>; 1864 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1865 status = "okay"; 1866 }; 1867 }; 1868 1869 ccplex@e000000 { 1870 compatible = "nvidia,tegra234-ccplex-cluster"; 1871 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1872 nvidia,bpmp = <&bpmp>; 1873 status = "okay"; 1874 }; 1875 1876 pcie@140a0000 { 1877 compatible = "nvidia,tegra234-pcie"; 1878 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 1879 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 1880 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 1881 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1882 <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1883 reg-names = "appl", "config", "atu_dma", "dbi"; 1884 1885 #address-cells = <3>; 1886 #size-cells = <2>; 1887 device_type = "pci"; 1888 num-lanes = <4>; 1889 num-viewport = <8>; 1890 linux,pci-domain = <8>; 1891 1892 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 1893 clock-names = "core"; 1894 1895 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 1896 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 1897 reset-names = "apb", "core"; 1898 1899 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1900 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1901 interrupt-names = "intr", "msi"; 1902 1903 #interrupt-cells = <1>; 1904 interrupt-map-mask = <0 0 0 0>; 1905 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1906 1907 nvidia,bpmp = <&bpmp 8>; 1908 1909 nvidia,aspm-cmrt-us = <60>; 1910 nvidia,aspm-pwr-on-t-us = <20>; 1911 nvidia,aspm-l0s-entrance-latency-us = <3>; 1912 1913 bus-range = <0x0 0xff>; 1914 1915 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1916 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1917 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1918 1919 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 1920 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 1921 interconnect-names = "dma-mem", "write"; 1922 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 1923 iommu-map-mask = <0x0>; 1924 dma-coherent; 1925 1926 status = "disabled"; 1927 }; 1928 1929 pcie@140c0000 { 1930 compatible = "nvidia,tegra234-pcie"; 1931 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 1932 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 1933 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 1934 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1935 <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1936 reg-names = "appl", "config", "atu_dma", "dbi"; 1937 1938 #address-cells = <3>; 1939 #size-cells = <2>; 1940 device_type = "pci"; 1941 num-lanes = <4>; 1942 num-viewport = <8>; 1943 linux,pci-domain = <9>; 1944 1945 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 1946 clock-names = "core"; 1947 1948 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 1949 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 1950 reset-names = "apb", "core"; 1951 1952 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1953 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1954 interrupt-names = "intr", "msi"; 1955 1956 #interrupt-cells = <1>; 1957 interrupt-map-mask = <0 0 0 0>; 1958 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1959 1960 nvidia,bpmp = <&bpmp 9>; 1961 1962 nvidia,aspm-cmrt-us = <60>; 1963 nvidia,aspm-pwr-on-t-us = <20>; 1964 nvidia,aspm-l0s-entrance-latency-us = <3>; 1965 1966 bus-range = <0x0 0xff>; 1967 1968 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1969 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 1970 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 1971 1972 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 1973 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 1974 interconnect-names = "dma-mem", "write"; 1975 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 1976 iommu-map-mask = <0x0>; 1977 dma-coherent; 1978 1979 status = "disabled"; 1980 }; 1981 1982 pcie@140e0000 { 1983 compatible = "nvidia,tegra234-pcie"; 1984 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 1985 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 1986 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 1987 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1988 <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1989 reg-names = "appl", "config", "atu_dma", "dbi"; 1990 1991 #address-cells = <3>; 1992 #size-cells = <2>; 1993 device_type = "pci"; 1994 num-lanes = <4>; 1995 num-viewport = <8>; 1996 linux,pci-domain = <10>; 1997 1998 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 1999 clock-names = "core"; 2000 2001 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2002 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2003 reset-names = "apb", "core"; 2004 2005 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2006 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2007 interrupt-names = "intr", "msi"; 2008 2009 #interrupt-cells = <1>; 2010 interrupt-map-mask = <0 0 0 0>; 2011 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2012 2013 nvidia,bpmp = <&bpmp 10>; 2014 2015 nvidia,aspm-cmrt-us = <60>; 2016 nvidia,aspm-pwr-on-t-us = <20>; 2017 nvidia,aspm-l0s-entrance-latency-us = <3>; 2018 2019 bus-range = <0x0 0xff>; 2020 2021 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2022 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2023 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2024 2025 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2026 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2027 interconnect-names = "dma-mem", "write"; 2028 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2029 iommu-map-mask = <0x0>; 2030 dma-coherent; 2031 2032 status = "disabled"; 2033 }; 2034 2035 pcie@14100000 { 2036 compatible = "nvidia,tegra234-pcie"; 2037 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2038 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2039 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2040 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2041 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2042 reg-names = "appl", "config", "atu_dma", "dbi"; 2043 2044 #address-cells = <3>; 2045 #size-cells = <2>; 2046 device_type = "pci"; 2047 num-lanes = <1>; 2048 num-viewport = <8>; 2049 linux,pci-domain = <1>; 2050 2051 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2052 clock-names = "core"; 2053 2054 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2055 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2056 reset-names = "apb", "core"; 2057 2058 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2059 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2060 interrupt-names = "intr", "msi"; 2061 2062 #interrupt-cells = <1>; 2063 interrupt-map-mask = <0 0 0 0>; 2064 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2065 2066 nvidia,bpmp = <&bpmp 1>; 2067 2068 nvidia,aspm-cmrt-us = <60>; 2069 nvidia,aspm-pwr-on-t-us = <20>; 2070 nvidia,aspm-l0s-entrance-latency-us = <3>; 2071 2072 bus-range = <0x0 0xff>; 2073 2074 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2075 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2076 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2077 2078 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2079 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2080 interconnect-names = "dma-mem", "write"; 2081 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2082 iommu-map-mask = <0x0>; 2083 dma-coherent; 2084 2085 status = "disabled"; 2086 }; 2087 2088 pcie@14120000 { 2089 compatible = "nvidia,tegra234-pcie"; 2090 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2091 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2092 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2093 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2094 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2095 reg-names = "appl", "config", "atu_dma", "dbi"; 2096 2097 #address-cells = <3>; 2098 #size-cells = <2>; 2099 device_type = "pci"; 2100 num-lanes = <1>; 2101 num-viewport = <8>; 2102 linux,pci-domain = <2>; 2103 2104 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2105 clock-names = "core"; 2106 2107 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2108 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2109 reset-names = "apb", "core"; 2110 2111 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2112 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2113 interrupt-names = "intr", "msi"; 2114 2115 #interrupt-cells = <1>; 2116 interrupt-map-mask = <0 0 0 0>; 2117 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2118 2119 nvidia,bpmp = <&bpmp 2>; 2120 2121 nvidia,aspm-cmrt-us = <60>; 2122 nvidia,aspm-pwr-on-t-us = <20>; 2123 nvidia,aspm-l0s-entrance-latency-us = <3>; 2124 2125 bus-range = <0x0 0xff>; 2126 2127 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2128 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2129 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2130 2131 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2132 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2133 interconnect-names = "dma-mem", "write"; 2134 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2135 iommu-map-mask = <0x0>; 2136 dma-coherent; 2137 2138 status = "disabled"; 2139 }; 2140 2141 pcie@14140000 { 2142 compatible = "nvidia,tegra234-pcie"; 2143 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2144 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2145 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2146 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2147 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2148 reg-names = "appl", "config", "atu_dma", "dbi"; 2149 2150 #address-cells = <3>; 2151 #size-cells = <2>; 2152 device_type = "pci"; 2153 num-lanes = <1>; 2154 num-viewport = <8>; 2155 linux,pci-domain = <3>; 2156 2157 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2158 clock-names = "core"; 2159 2160 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2161 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2162 reset-names = "apb", "core"; 2163 2164 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2165 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2166 interrupt-names = "intr", "msi"; 2167 2168 #interrupt-cells = <1>; 2169 interrupt-map-mask = <0 0 0 0>; 2170 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2171 2172 nvidia,bpmp = <&bpmp 3>; 2173 2174 nvidia,aspm-cmrt-us = <60>; 2175 nvidia,aspm-pwr-on-t-us = <20>; 2176 nvidia,aspm-l0s-entrance-latency-us = <3>; 2177 2178 bus-range = <0x0 0xff>; 2179 2180 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2181 <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2182 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2183 2184 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2185 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2186 interconnect-names = "dma-mem", "write"; 2187 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2188 iommu-map-mask = <0x0>; 2189 dma-coherent; 2190 2191 status = "disabled"; 2192 }; 2193 2194 pcie@14160000 { 2195 compatible = "nvidia,tegra234-pcie"; 2196 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2197 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2198 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2199 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2200 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2201 reg-names = "appl", "config", "atu_dma", "dbi"; 2202 2203 #address-cells = <3>; 2204 #size-cells = <2>; 2205 device_type = "pci"; 2206 num-lanes = <4>; 2207 num-viewport = <8>; 2208 linux,pci-domain = <4>; 2209 2210 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2211 clock-names = "core"; 2212 2213 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2214 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2215 reset-names = "apb", "core"; 2216 2217 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2218 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2219 interrupt-names = "intr", "msi"; 2220 2221 #interrupt-cells = <1>; 2222 interrupt-map-mask = <0 0 0 0>; 2223 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2224 2225 nvidia,bpmp = <&bpmp 4>; 2226 2227 nvidia,aspm-cmrt-us = <60>; 2228 nvidia,aspm-pwr-on-t-us = <20>; 2229 nvidia,aspm-l0s-entrance-latency-us = <3>; 2230 2231 bus-range = <0x0 0xff>; 2232 2233 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2234 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2235 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2236 2237 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2238 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2239 interconnect-names = "dma-mem", "write"; 2240 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2241 iommu-map-mask = <0x0>; 2242 dma-coherent; 2243 2244 status = "disabled"; 2245 }; 2246 2247 pcie@14180000 { 2248 compatible = "nvidia,tegra234-pcie"; 2249 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2250 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2251 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2252 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2253 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2254 reg-names = "appl", "config", "atu_dma", "dbi"; 2255 2256 #address-cells = <3>; 2257 #size-cells = <2>; 2258 device_type = "pci"; 2259 num-lanes = <4>; 2260 num-viewport = <8>; 2261 linux,pci-domain = <0>; 2262 2263 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2264 clock-names = "core"; 2265 2266 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2267 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2268 reset-names = "apb", "core"; 2269 2270 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2271 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2272 interrupt-names = "intr", "msi"; 2273 2274 #interrupt-cells = <1>; 2275 interrupt-map-mask = <0 0 0 0>; 2276 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2277 2278 nvidia,bpmp = <&bpmp 0>; 2279 2280 nvidia,aspm-cmrt-us = <60>; 2281 nvidia,aspm-pwr-on-t-us = <20>; 2282 nvidia,aspm-l0s-entrance-latency-us = <3>; 2283 2284 bus-range = <0x0 0xff>; 2285 2286 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2287 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2288 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2289 2290 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2291 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2292 interconnect-names = "dma-mem", "write"; 2293 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2294 iommu-map-mask = <0x0>; 2295 dma-coherent; 2296 2297 status = "disabled"; 2298 }; 2299 2300 pcie@141a0000 { 2301 compatible = "nvidia,tegra234-pcie"; 2302 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2303 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2304 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2305 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2306 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2307 reg-names = "appl", "config", "atu_dma", "dbi"; 2308 2309 #address-cells = <3>; 2310 #size-cells = <2>; 2311 device_type = "pci"; 2312 num-lanes = <8>; 2313 num-viewport = <8>; 2314 linux,pci-domain = <5>; 2315 2316 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2317 clock-names = "core"; 2318 2319 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2320 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2321 reset-names = "apb", "core"; 2322 2323 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2324 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2325 interrupt-names = "intr", "msi"; 2326 2327 #interrupt-cells = <1>; 2328 interrupt-map-mask = <0 0 0 0>; 2329 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2330 2331 nvidia,bpmp = <&bpmp 5>; 2332 2333 nvidia,aspm-cmrt-us = <60>; 2334 nvidia,aspm-pwr-on-t-us = <20>; 2335 nvidia,aspm-l0s-entrance-latency-us = <3>; 2336 2337 bus-range = <0x0 0xff>; 2338 2339 ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2340 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2341 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2342 2343 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2344 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2345 interconnect-names = "dma-mem", "write"; 2346 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2347 iommu-map-mask = <0x0>; 2348 dma-coherent; 2349 2350 status = "disabled"; 2351 }; 2352 2353 pcie@141c0000 { 2354 compatible = "nvidia,tegra234-pcie"; 2355 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2356 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2357 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2358 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2359 <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2360 reg-names = "appl", "config", "atu_dma", "dbi"; 2361 2362 #address-cells = <3>; 2363 #size-cells = <2>; 2364 device_type = "pci"; 2365 num-lanes = <4>; 2366 num-viewport = <8>; 2367 linux,pci-domain = <6>; 2368 2369 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2370 clock-names = "core"; 2371 2372 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2373 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2374 reset-names = "apb", "core"; 2375 2376 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2377 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2378 interrupt-names = "intr", "msi"; 2379 2380 #interrupt-cells = <1>; 2381 interrupt-map-mask = <0 0 0 0>; 2382 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2383 2384 nvidia,bpmp = <&bpmp 6>; 2385 2386 nvidia,aspm-cmrt-us = <60>; 2387 nvidia,aspm-pwr-on-t-us = <20>; 2388 nvidia,aspm-l0s-entrance-latency-us = <3>; 2389 2390 bus-range = <0x0 0xff>; 2391 2392 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2393 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2394 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2395 2396 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2397 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2398 interconnect-names = "dma-mem", "write"; 2399 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2400 iommu-map-mask = <0x0>; 2401 dma-coherent; 2402 2403 status = "disabled"; 2404 }; 2405 2406 pcie@141e0000 { 2407 compatible = "nvidia,tegra234-pcie"; 2408 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2409 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2410 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2411 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2412 <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2413 reg-names = "appl", "config", "atu_dma", "dbi"; 2414 2415 #address-cells = <3>; 2416 #size-cells = <2>; 2417 device_type = "pci"; 2418 num-lanes = <8>; 2419 num-viewport = <8>; 2420 linux,pci-domain = <7>; 2421 2422 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2423 clock-names = "core"; 2424 2425 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2426 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2427 reset-names = "apb", "core"; 2428 2429 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2430 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2431 interrupt-names = "intr", "msi"; 2432 2433 #interrupt-cells = <1>; 2434 interrupt-map-mask = <0 0 0 0>; 2435 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2436 2437 nvidia,bpmp = <&bpmp 7>; 2438 2439 nvidia,aspm-cmrt-us = <60>; 2440 nvidia,aspm-pwr-on-t-us = <20>; 2441 nvidia,aspm-l0s-entrance-latency-us = <3>; 2442 2443 bus-range = <0x0 0xff>; 2444 2445 ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2446 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2447 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2448 2449 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2450 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2451 interconnect-names = "dma-mem", "write"; 2452 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2453 iommu-map-mask = <0x0>; 2454 dma-coherent; 2455 2456 status = "disabled"; 2457 }; 2458 2459 pcie-ep@141a0000 { 2460 compatible = "nvidia,tegra234-pcie-ep"; 2461 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2462 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2463 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2464 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2465 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2466 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2467 2468 num-lanes = <8>; 2469 2470 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2471 clock-names = "core"; 2472 2473 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2474 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2475 reset-names = "apb", "core"; 2476 2477 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2478 interrupt-names = "intr"; 2479 2480 nvidia,bpmp = <&bpmp 5>; 2481 2482 nvidia,enable-ext-refclk; 2483 nvidia,aspm-cmrt-us = <60>; 2484 nvidia,aspm-pwr-on-t-us = <20>; 2485 nvidia,aspm-l0s-entrance-latency-us = <3>; 2486 2487 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2488 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2489 interconnect-names = "dma-mem", "write"; 2490 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2491 iommu-map-mask = <0x0>; 2492 dma-coherent; 2493 2494 status = "disabled"; 2495 }; 2496 2497 pcie-ep@141c0000{ 2498 compatible = "nvidia,tegra234-pcie-ep"; 2499 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2500 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2501 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2502 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2503 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2504 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2505 2506 num-lanes = <4>; 2507 2508 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2509 clock-names = "core"; 2510 2511 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2512 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2513 reset-names = "apb", "core"; 2514 2515 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2516 interrupt-names = "intr"; 2517 2518 nvidia,bpmp = <&bpmp 6>; 2519 2520 nvidia,enable-ext-refclk; 2521 nvidia,aspm-cmrt-us = <60>; 2522 nvidia,aspm-pwr-on-t-us = <20>; 2523 nvidia,aspm-l0s-entrance-latency-us = <3>; 2524 2525 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2526 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2527 interconnect-names = "dma-mem", "write"; 2528 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2529 iommu-map-mask = <0x0>; 2530 dma-coherent; 2531 2532 status = "disabled"; 2533 }; 2534 2535 pcie-ep@141e0000{ 2536 compatible = "nvidia,tegra234-pcie-ep"; 2537 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2538 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2539 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2540 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2541 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2542 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2543 2544 num-lanes = <8>; 2545 2546 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2547 clock-names = "core"; 2548 2549 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2550 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2551 reset-names = "apb", "core"; 2552 2553 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2554 interrupt-names = "intr"; 2555 2556 nvidia,bpmp = <&bpmp 7>; 2557 2558 nvidia,enable-ext-refclk; 2559 nvidia,aspm-cmrt-us = <60>; 2560 nvidia,aspm-pwr-on-t-us = <20>; 2561 nvidia,aspm-l0s-entrance-latency-us = <3>; 2562 2563 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2564 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2565 interconnect-names = "dma-mem", "write"; 2566 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2567 iommu-map-mask = <0x0>; 2568 dma-coherent; 2569 2570 status = "disabled"; 2571 }; 2572 2573 pcie-ep@140e0000{ 2574 compatible = "nvidia,tegra234-pcie-ep"; 2575 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2576 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2577 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2578 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2579 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2580 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2581 2582 num-lanes = <4>; 2583 2584 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2585 clock-names = "core"; 2586 2587 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2588 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2589 reset-names = "apb", "core"; 2590 2591 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2592 interrupt-names = "intr"; 2593 2594 nvidia,bpmp = <&bpmp 10>; 2595 2596 nvidia,enable-ext-refclk; 2597 nvidia,aspm-cmrt-us = <60>; 2598 nvidia,aspm-pwr-on-t-us = <20>; 2599 nvidia,aspm-l0s-entrance-latency-us = <3>; 2600 2601 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2602 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2603 interconnect-names = "dma-mem", "write"; 2604 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2605 iommu-map-mask = <0x0>; 2606 dma-coherent; 2607 2608 status = "disabled"; 2609 }; 2610 2611 sram@40000000 { 2612 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2613 reg = <0x0 0x40000000 0x0 0x80000>; 2614 #address-cells = <1>; 2615 #size-cells = <1>; 2616 ranges = <0x0 0x0 0x40000000 0x80000>; 2617 no-memory-wc; 2618 2619 cpu_bpmp_tx: sram@70000 { 2620 reg = <0x70000 0x1000>; 2621 label = "cpu-bpmp-tx"; 2622 pool; 2623 }; 2624 2625 cpu_bpmp_rx: sram@71000 { 2626 reg = <0x71000 0x1000>; 2627 label = "cpu-bpmp-rx"; 2628 pool; 2629 }; 2630 }; 2631 2632 bpmp: bpmp { 2633 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2634 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2635 TEGRA_HSP_DB_MASTER_BPMP>; 2636 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2637 #clock-cells = <1>; 2638 #reset-cells = <1>; 2639 #power-domain-cells = <1>; 2640 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 2641 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 2642 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 2643 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 2644 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2645 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 2646 2647 bpmp_i2c: i2c { 2648 compatible = "nvidia,tegra186-bpmp-i2c"; 2649 nvidia,bpmp-bus-id = <5>; 2650 #address-cells = <1>; 2651 #size-cells = <0>; 2652 }; 2653 }; 2654 2655 cpus { 2656 #address-cells = <1>; 2657 #size-cells = <0>; 2658 2659 cpu0_0: cpu@0 { 2660 compatible = "arm,cortex-a78"; 2661 device_type = "cpu"; 2662 reg = <0x00000>; 2663 2664 enable-method = "psci"; 2665 2666 i-cache-size = <65536>; 2667 i-cache-line-size = <64>; 2668 i-cache-sets = <256>; 2669 d-cache-size = <65536>; 2670 d-cache-line-size = <64>; 2671 d-cache-sets = <256>; 2672 next-level-cache = <&l2c0_0>; 2673 }; 2674 2675 cpu0_1: cpu@100 { 2676 compatible = "arm,cortex-a78"; 2677 device_type = "cpu"; 2678 reg = <0x00100>; 2679 2680 enable-method = "psci"; 2681 2682 i-cache-size = <65536>; 2683 i-cache-line-size = <64>; 2684 i-cache-sets = <256>; 2685 d-cache-size = <65536>; 2686 d-cache-line-size = <64>; 2687 d-cache-sets = <256>; 2688 next-level-cache = <&l2c0_1>; 2689 }; 2690 2691 cpu0_2: cpu@200 { 2692 compatible = "arm,cortex-a78"; 2693 device_type = "cpu"; 2694 reg = <0x00200>; 2695 2696 enable-method = "psci"; 2697 2698 i-cache-size = <65536>; 2699 i-cache-line-size = <64>; 2700 i-cache-sets = <256>; 2701 d-cache-size = <65536>; 2702 d-cache-line-size = <64>; 2703 d-cache-sets = <256>; 2704 next-level-cache = <&l2c0_2>; 2705 }; 2706 2707 cpu0_3: cpu@300 { 2708 compatible = "arm,cortex-a78"; 2709 device_type = "cpu"; 2710 reg = <0x00300>; 2711 2712 enable-method = "psci"; 2713 2714 i-cache-size = <65536>; 2715 i-cache-line-size = <64>; 2716 i-cache-sets = <256>; 2717 d-cache-size = <65536>; 2718 d-cache-line-size = <64>; 2719 d-cache-sets = <256>; 2720 next-level-cache = <&l2c0_3>; 2721 }; 2722 2723 cpu1_0: cpu@10000 { 2724 compatible = "arm,cortex-a78"; 2725 device_type = "cpu"; 2726 reg = <0x10000>; 2727 2728 enable-method = "psci"; 2729 2730 i-cache-size = <65536>; 2731 i-cache-line-size = <64>; 2732 i-cache-sets = <256>; 2733 d-cache-size = <65536>; 2734 d-cache-line-size = <64>; 2735 d-cache-sets = <256>; 2736 next-level-cache = <&l2c1_0>; 2737 }; 2738 2739 cpu1_1: cpu@10100 { 2740 compatible = "arm,cortex-a78"; 2741 device_type = "cpu"; 2742 reg = <0x10100>; 2743 2744 enable-method = "psci"; 2745 2746 i-cache-size = <65536>; 2747 i-cache-line-size = <64>; 2748 i-cache-sets = <256>; 2749 d-cache-size = <65536>; 2750 d-cache-line-size = <64>; 2751 d-cache-sets = <256>; 2752 next-level-cache = <&l2c1_1>; 2753 }; 2754 2755 cpu1_2: cpu@10200 { 2756 compatible = "arm,cortex-a78"; 2757 device_type = "cpu"; 2758 reg = <0x10200>; 2759 2760 enable-method = "psci"; 2761 2762 i-cache-size = <65536>; 2763 i-cache-line-size = <64>; 2764 i-cache-sets = <256>; 2765 d-cache-size = <65536>; 2766 d-cache-line-size = <64>; 2767 d-cache-sets = <256>; 2768 next-level-cache = <&l2c1_2>; 2769 }; 2770 2771 cpu1_3: cpu@10300 { 2772 compatible = "arm,cortex-a78"; 2773 device_type = "cpu"; 2774 reg = <0x10300>; 2775 2776 enable-method = "psci"; 2777 2778 i-cache-size = <65536>; 2779 i-cache-line-size = <64>; 2780 i-cache-sets = <256>; 2781 d-cache-size = <65536>; 2782 d-cache-line-size = <64>; 2783 d-cache-sets = <256>; 2784 next-level-cache = <&l2c1_3>; 2785 }; 2786 2787 cpu2_0: cpu@20000 { 2788 compatible = "arm,cortex-a78"; 2789 device_type = "cpu"; 2790 reg = <0x20000>; 2791 2792 enable-method = "psci"; 2793 2794 i-cache-size = <65536>; 2795 i-cache-line-size = <64>; 2796 i-cache-sets = <256>; 2797 d-cache-size = <65536>; 2798 d-cache-line-size = <64>; 2799 d-cache-sets = <256>; 2800 next-level-cache = <&l2c2_0>; 2801 }; 2802 2803 cpu2_1: cpu@20100 { 2804 compatible = "arm,cortex-a78"; 2805 device_type = "cpu"; 2806 reg = <0x20100>; 2807 2808 enable-method = "psci"; 2809 2810 i-cache-size = <65536>; 2811 i-cache-line-size = <64>; 2812 i-cache-sets = <256>; 2813 d-cache-size = <65536>; 2814 d-cache-line-size = <64>; 2815 d-cache-sets = <256>; 2816 next-level-cache = <&l2c2_1>; 2817 }; 2818 2819 cpu2_2: cpu@20200 { 2820 compatible = "arm,cortex-a78"; 2821 device_type = "cpu"; 2822 reg = <0x20200>; 2823 2824 enable-method = "psci"; 2825 2826 i-cache-size = <65536>; 2827 i-cache-line-size = <64>; 2828 i-cache-sets = <256>; 2829 d-cache-size = <65536>; 2830 d-cache-line-size = <64>; 2831 d-cache-sets = <256>; 2832 next-level-cache = <&l2c2_2>; 2833 }; 2834 2835 cpu2_3: cpu@20300 { 2836 compatible = "arm,cortex-a78"; 2837 device_type = "cpu"; 2838 reg = <0x20300>; 2839 2840 enable-method = "psci"; 2841 2842 i-cache-size = <65536>; 2843 i-cache-line-size = <64>; 2844 i-cache-sets = <256>; 2845 d-cache-size = <65536>; 2846 d-cache-line-size = <64>; 2847 d-cache-sets = <256>; 2848 next-level-cache = <&l2c2_3>; 2849 }; 2850 2851 cpu-map { 2852 cluster0 { 2853 core0 { 2854 cpu = <&cpu0_0>; 2855 }; 2856 2857 core1 { 2858 cpu = <&cpu0_1>; 2859 }; 2860 2861 core2 { 2862 cpu = <&cpu0_2>; 2863 }; 2864 2865 core3 { 2866 cpu = <&cpu0_3>; 2867 }; 2868 }; 2869 2870 cluster1 { 2871 core0 { 2872 cpu = <&cpu1_0>; 2873 }; 2874 2875 core1 { 2876 cpu = <&cpu1_1>; 2877 }; 2878 2879 core2 { 2880 cpu = <&cpu1_2>; 2881 }; 2882 2883 core3 { 2884 cpu = <&cpu1_3>; 2885 }; 2886 }; 2887 2888 cluster2 { 2889 core0 { 2890 cpu = <&cpu2_0>; 2891 }; 2892 2893 core1 { 2894 cpu = <&cpu2_1>; 2895 }; 2896 2897 core2 { 2898 cpu = <&cpu2_2>; 2899 }; 2900 2901 core3 { 2902 cpu = <&cpu2_3>; 2903 }; 2904 }; 2905 }; 2906 2907 l2c0_0: l2-cache00 { 2908 cache-size = <262144>; 2909 cache-line-size = <64>; 2910 cache-sets = <512>; 2911 cache-unified; 2912 next-level-cache = <&l3c0>; 2913 }; 2914 2915 l2c0_1: l2-cache01 { 2916 cache-size = <262144>; 2917 cache-line-size = <64>; 2918 cache-sets = <512>; 2919 cache-unified; 2920 next-level-cache = <&l3c0>; 2921 }; 2922 2923 l2c0_2: l2-cache02 { 2924 cache-size = <262144>; 2925 cache-line-size = <64>; 2926 cache-sets = <512>; 2927 cache-unified; 2928 next-level-cache = <&l3c0>; 2929 }; 2930 2931 l2c0_3: l2-cache03 { 2932 cache-size = <262144>; 2933 cache-line-size = <64>; 2934 cache-sets = <512>; 2935 cache-unified; 2936 next-level-cache = <&l3c0>; 2937 }; 2938 2939 l2c1_0: l2-cache10 { 2940 cache-size = <262144>; 2941 cache-line-size = <64>; 2942 cache-sets = <512>; 2943 cache-unified; 2944 next-level-cache = <&l3c1>; 2945 }; 2946 2947 l2c1_1: l2-cache11 { 2948 cache-size = <262144>; 2949 cache-line-size = <64>; 2950 cache-sets = <512>; 2951 cache-unified; 2952 next-level-cache = <&l3c1>; 2953 }; 2954 2955 l2c1_2: l2-cache12 { 2956 cache-size = <262144>; 2957 cache-line-size = <64>; 2958 cache-sets = <512>; 2959 cache-unified; 2960 next-level-cache = <&l3c1>; 2961 }; 2962 2963 l2c1_3: l2-cache13 { 2964 cache-size = <262144>; 2965 cache-line-size = <64>; 2966 cache-sets = <512>; 2967 cache-unified; 2968 next-level-cache = <&l3c1>; 2969 }; 2970 2971 l2c2_0: l2-cache20 { 2972 cache-size = <262144>; 2973 cache-line-size = <64>; 2974 cache-sets = <512>; 2975 cache-unified; 2976 next-level-cache = <&l3c2>; 2977 }; 2978 2979 l2c2_1: l2-cache21 { 2980 cache-size = <262144>; 2981 cache-line-size = <64>; 2982 cache-sets = <512>; 2983 cache-unified; 2984 next-level-cache = <&l3c2>; 2985 }; 2986 2987 l2c2_2: l2-cache22 { 2988 cache-size = <262144>; 2989 cache-line-size = <64>; 2990 cache-sets = <512>; 2991 cache-unified; 2992 next-level-cache = <&l3c2>; 2993 }; 2994 2995 l2c2_3: l2-cache23 { 2996 cache-size = <262144>; 2997 cache-line-size = <64>; 2998 cache-sets = <512>; 2999 cache-unified; 3000 next-level-cache = <&l3c2>; 3001 }; 3002 3003 l3c0: l3-cache0 { 3004 cache-size = <2097152>; 3005 cache-line-size = <64>; 3006 cache-sets = <2048>; 3007 }; 3008 3009 l3c1: l3-cache1 { 3010 cache-size = <2097152>; 3011 cache-line-size = <64>; 3012 cache-sets = <2048>; 3013 }; 3014 3015 l3c2: l3-cache2 { 3016 cache-size = <2097152>; 3017 cache-line-size = <64>; 3018 cache-sets = <2048>; 3019 }; 3020 }; 3021 3022 pmu { 3023 compatible = "arm,cortex-a78-pmu"; 3024 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3025 status = "okay"; 3026 }; 3027 3028 psci { 3029 compatible = "arm,psci-1.0"; 3030 status = "okay"; 3031 method = "smc"; 3032 }; 3033 3034 tcu: serial { 3035 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3036 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3037 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3038 mbox-names = "rx", "tx"; 3039 status = "disabled"; 3040 }; 3041 3042 sound { 3043 status = "disabled"; 3044 3045 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3046 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3047 clock-names = "pll_a", "plla_out0"; 3048 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3049 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3050 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3051 assigned-clock-parents = <0>, 3052 <&bpmp TEGRA234_CLK_PLLA>, 3053 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3054 }; 3055 3056 timer { 3057 compatible = "arm,armv8-timer"; 3058 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3059 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3060 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3061 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3062 interrupt-parent = <&gic>; 3063 always-on; 3064 }; 3065}; 3066