1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra234-misc"; 27 reg = <0x0 0x00100000 0x0 0xf000>, 28 <0x0 0x0010f000 0x0 0x1000>; 29 status = "okay"; 30 }; 31 32 timer@2080000 { 33 compatible = "nvidia,tegra234-timer"; 34 reg = <0x0 0x02080000 0x0 0x00121000>; 35 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51 status = "okay"; 52 }; 53 54 gpio: gpio@2200000 { 55 compatible = "nvidia,tegra234-gpio"; 56 reg-names = "security", "gpio"; 57 reg = <0x0 0x02200000 0x0 0x10000>, 58 <0x0 0x02210000 0x0 0x10000>; 59 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 #gpio-cells = <2>; 110 gpio-controller; 111 }; 112 113 gpcdma: dma-controller@2600000 { 114 compatible = "nvidia,tegra234-gpcdma", 115 "nvidia,tegra186-gpcdma"; 116 reg = <0x0 0x2600000 0x0 0x210000>; 117 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 118 reset-names = "gpcdma"; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153 dma-channel-mask = <0xfffffffe>; 154 dma-coherent; 155 }; 156 157 aconnect@2900000 { 158 compatible = "nvidia,tegra234-aconnect", 159 "nvidia,tegra210-aconnect"; 160 clocks = <&bpmp TEGRA234_CLK_APE>, 161 <&bpmp TEGRA234_CLK_APB2APE>; 162 clock-names = "ape", "apb2ape"; 163 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164 status = "disabled"; 165 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 169 170 tegra_ahub: ahub@2900800 { 171 compatible = "nvidia,tegra234-ahub"; 172 reg = <0x0 0x02900800 0x0 0x800>; 173 clocks = <&bpmp TEGRA234_CLK_AHUB>; 174 clock-names = "ahub"; 175 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177 status = "disabled"; 178 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 182 183 tegra_i2s1: i2s@2901000 { 184 compatible = "nvidia,tegra234-i2s", 185 "nvidia,tegra210-i2s"; 186 reg = <0x0 0x2901000 0x0 0x100>; 187 clocks = <&bpmp TEGRA234_CLK_I2S1>, 188 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189 clock-names = "i2s", "sync_input"; 190 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192 assigned-clock-rates = <1536000>; 193 sound-name-prefix = "I2S1"; 194 status = "disabled"; 195 }; 196 197 tegra_i2s2: i2s@2901100 { 198 compatible = "nvidia,tegra234-i2s", 199 "nvidia,tegra210-i2s"; 200 reg = <0x0 0x2901100 0x0 0x100>; 201 clocks = <&bpmp TEGRA234_CLK_I2S2>, 202 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203 clock-names = "i2s", "sync_input"; 204 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206 assigned-clock-rates = <1536000>; 207 sound-name-prefix = "I2S2"; 208 status = "disabled"; 209 }; 210 211 tegra_i2s3: i2s@2901200 { 212 compatible = "nvidia,tegra234-i2s", 213 "nvidia,tegra210-i2s"; 214 reg = <0x0 0x2901200 0x0 0x100>; 215 clocks = <&bpmp TEGRA234_CLK_I2S3>, 216 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217 clock-names = "i2s", "sync_input"; 218 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220 assigned-clock-rates = <1536000>; 221 sound-name-prefix = "I2S3"; 222 status = "disabled"; 223 }; 224 225 tegra_i2s4: i2s@2901300 { 226 compatible = "nvidia,tegra234-i2s", 227 "nvidia,tegra210-i2s"; 228 reg = <0x0 0x2901300 0x0 0x100>; 229 clocks = <&bpmp TEGRA234_CLK_I2S4>, 230 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231 clock-names = "i2s", "sync_input"; 232 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234 assigned-clock-rates = <1536000>; 235 sound-name-prefix = "I2S4"; 236 status = "disabled"; 237 }; 238 239 tegra_i2s5: i2s@2901400 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901400 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S5>, 244 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S5"; 250 status = "disabled"; 251 }; 252 253 tegra_i2s6: i2s@2901500 { 254 compatible = "nvidia,tegra234-i2s", 255 "nvidia,tegra210-i2s"; 256 reg = <0x0 0x2901500 0x0 0x100>; 257 clocks = <&bpmp TEGRA234_CLK_I2S6>, 258 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S6"; 264 status = "disabled"; 265 }; 266 267 tegra_sfc1: sfc@2902000 { 268 compatible = "nvidia,tegra234-sfc", 269 "nvidia,tegra210-sfc"; 270 reg = <0x0 0x2902000 0x0 0x200>; 271 sound-name-prefix = "SFC1"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc2: sfc@2902200 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902200 0x0 0x200>; 279 sound-name-prefix = "SFC2"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc3: sfc@2902400 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902400 0x0 0x200>; 287 sound-name-prefix = "SFC3"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc4: sfc@2902600 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902600 0x0 0x200>; 295 sound-name-prefix = "SFC4"; 296 status = "disabled"; 297 }; 298 299 tegra_amx1: amx@2903000 { 300 compatible = "nvidia,tegra234-amx", 301 "nvidia,tegra194-amx"; 302 reg = <0x0 0x2903000 0x0 0x100>; 303 sound-name-prefix = "AMX1"; 304 status = "disabled"; 305 }; 306 307 tegra_amx2: amx@2903100 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903100 0x0 0x100>; 311 sound-name-prefix = "AMX2"; 312 status = "disabled"; 313 }; 314 315 tegra_amx3: amx@2903200 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903200 0x0 0x100>; 319 sound-name-prefix = "AMX3"; 320 status = "disabled"; 321 }; 322 323 tegra_amx4: amx@2903300 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903300 0x0 0x100>; 327 sound-name-prefix = "AMX4"; 328 status = "disabled"; 329 }; 330 331 tegra_adx1: adx@2903800 { 332 compatible = "nvidia,tegra234-adx", 333 "nvidia,tegra210-adx"; 334 reg = <0x0 0x2903800 0x0 0x100>; 335 sound-name-prefix = "ADX1"; 336 status = "disabled"; 337 }; 338 339 tegra_adx2: adx@2903900 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903900 0x0 0x100>; 343 sound-name-prefix = "ADX2"; 344 status = "disabled"; 345 }; 346 347 tegra_adx3: adx@2903a00 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903a00 0x0 0x100>; 351 sound-name-prefix = "ADX3"; 352 status = "disabled"; 353 }; 354 355 tegra_adx4: adx@2903b00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903b00 0x0 0x100>; 359 sound-name-prefix = "ADX4"; 360 status = "disabled"; 361 }; 362 363 364 tegra_dmic1: dmic@2904000 { 365 compatible = "nvidia,tegra234-dmic", 366 "nvidia,tegra210-dmic"; 367 reg = <0x0 0x2904000 0x0 0x100>; 368 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369 clock-names = "dmic"; 370 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372 assigned-clock-rates = <3072000>; 373 sound-name-prefix = "DMIC1"; 374 status = "disabled"; 375 }; 376 377 tegra_dmic2: dmic@2904100 { 378 compatible = "nvidia,tegra234-dmic", 379 "nvidia,tegra210-dmic"; 380 reg = <0x0 0x2904100 0x0 0x100>; 381 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382 clock-names = "dmic"; 383 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385 assigned-clock-rates = <3072000>; 386 sound-name-prefix = "DMIC2"; 387 status = "disabled"; 388 }; 389 390 tegra_dmic3: dmic@2904200 { 391 compatible = "nvidia,tegra234-dmic", 392 "nvidia,tegra210-dmic"; 393 reg = <0x0 0x2904200 0x0 0x100>; 394 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395 clock-names = "dmic"; 396 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <3072000>; 399 sound-name-prefix = "DMIC3"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic4: dmic@2904300 { 404 compatible = "nvidia,tegra234-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x0 0x2904300 0x0 0x100>; 407 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC4"; 413 status = "disabled"; 414 }; 415 416 tegra_dspk1: dspk@2905000 { 417 compatible = "nvidia,tegra234-dspk", 418 "nvidia,tegra186-dspk"; 419 reg = <0x0 0x2905000 0x0 0x100>; 420 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421 clock-names = "dspk"; 422 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <12288000>; 425 sound-name-prefix = "DSPK1"; 426 status = "disabled"; 427 }; 428 429 tegra_dspk2: dspk@2905100 { 430 compatible = "nvidia,tegra234-dspk", 431 "nvidia,tegra186-dspk"; 432 reg = <0x0 0x2905100 0x0 0x100>; 433 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434 clock-names = "dspk"; 435 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <12288000>; 438 sound-name-prefix = "DSPK2"; 439 status = "disabled"; 440 }; 441 442 tegra_ope1: processing-engine@2908000 { 443 compatible = "nvidia,tegra234-ope", 444 "nvidia,tegra210-ope"; 445 reg = <0x0 0x2908000 0x0 0x100>; 446 sound-name-prefix = "OPE1"; 447 status = "disabled"; 448 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 equalizer@2908100 { 454 compatible = "nvidia,tegra234-peq", 455 "nvidia,tegra210-peq"; 456 reg = <0x0 0x2908100 0x0 0x100>; 457 }; 458 459 dynamic-range-compressor@2908200 { 460 compatible = "nvidia,tegra234-mbdrc", 461 "nvidia,tegra210-mbdrc"; 462 reg = <0x0 0x2908200 0x0 0x200>; 463 }; 464 }; 465 466 tegra_mvc1: mvc@290a000 { 467 compatible = "nvidia,tegra234-mvc", 468 "nvidia,tegra210-mvc"; 469 reg = <0x0 0x290a000 0x0 0x200>; 470 sound-name-prefix = "MVC1"; 471 status = "disabled"; 472 }; 473 474 tegra_mvc2: mvc@290a200 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a200 0x0 0x200>; 478 sound-name-prefix = "MVC2"; 479 status = "disabled"; 480 }; 481 482 tegra_amixer: amixer@290bb00 { 483 compatible = "nvidia,tegra234-amixer", 484 "nvidia,tegra210-amixer"; 485 reg = <0x0 0x290bb00 0x0 0x800>; 486 sound-name-prefix = "MIXER1"; 487 status = "disabled"; 488 }; 489 490 tegra_admaif: admaif@290f000 { 491 compatible = "nvidia,tegra234-admaif", 492 "nvidia,tegra186-admaif"; 493 reg = <0x0 0x0290f000 0x0 0x1000>; 494 dmas = <&adma 1>, <&adma 1>, 495 <&adma 2>, <&adma 2>, 496 <&adma 3>, <&adma 3>, 497 <&adma 4>, <&adma 4>, 498 <&adma 5>, <&adma 5>, 499 <&adma 6>, <&adma 6>, 500 <&adma 7>, <&adma 7>, 501 <&adma 8>, <&adma 8>, 502 <&adma 9>, <&adma 9>, 503 <&adma 10>, <&adma 10>, 504 <&adma 11>, <&adma 11>, 505 <&adma 12>, <&adma 12>, 506 <&adma 13>, <&adma 13>, 507 <&adma 14>, <&adma 14>, 508 <&adma 15>, <&adma 15>, 509 <&adma 16>, <&adma 16>, 510 <&adma 17>, <&adma 17>, 511 <&adma 18>, <&adma 18>, 512 <&adma 19>, <&adma 19>, 513 <&adma 20>, <&adma 20>; 514 dma-names = "rx1", "tx1", 515 "rx2", "tx2", 516 "rx3", "tx3", 517 "rx4", "tx4", 518 "rx5", "tx5", 519 "rx6", "tx6", 520 "rx7", "tx7", 521 "rx8", "tx8", 522 "rx9", "tx9", 523 "rx10", "tx10", 524 "rx11", "tx11", 525 "rx12", "tx12", 526 "rx13", "tx13", 527 "rx14", "tx14", 528 "rx15", "tx15", 529 "rx16", "tx16", 530 "rx17", "tx17", 531 "rx18", "tx18", 532 "rx19", "tx19", 533 "rx20", "tx20"; 534 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536 interconnect-names = "dma-mem", "write"; 537 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538 status = "disabled"; 539 }; 540 541 tegra_asrc: asrc@2910000 { 542 compatible = "nvidia,tegra234-asrc", 543 "nvidia,tegra186-asrc"; 544 reg = <0x0 0x2910000 0x0 0x2000>; 545 sound-name-prefix = "ASRC1"; 546 status = "disabled"; 547 }; 548 }; 549 550 adma: dma-controller@2930000 { 551 compatible = "nvidia,tegra234-adma", 552 "nvidia,tegra186-adma"; 553 reg = <0x0 0x02930000 0x0 0x20000>; 554 interrupt-parent = <&agic>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587 #dma-cells = <1>; 588 clocks = <&bpmp TEGRA234_CLK_AHUB>; 589 clock-names = "d_audio"; 590 status = "disabled"; 591 }; 592 593 agic: interrupt-controller@2a40000 { 594 compatible = "nvidia,tegra234-agic", 595 "nvidia,tegra210-agic"; 596 #interrupt-cells = <3>; 597 interrupt-controller; 598 reg = <0x0 0x02a41000 0x0 0x1000>, 599 <0x0 0x02a42000 0x0 0x2000>; 600 interrupts = <GIC_SPI 145 601 (GIC_CPU_MASK_SIMPLE(4) | 602 IRQ_TYPE_LEVEL_HIGH)>; 603 clocks = <&bpmp TEGRA234_CLK_APE>; 604 clock-names = "clk"; 605 status = "disabled"; 606 }; 607 }; 608 609 mc: memory-controller@2c00000 { 610 compatible = "nvidia,tegra234-mc"; 611 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 612 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 613 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 614 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 615 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 616 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 617 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 618 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 619 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 620 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 621 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 622 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 623 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 624 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 625 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 626 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 627 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 628 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631 "ch11", "ch12", "ch13", "ch14", "ch15"; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 #interconnect-cells = <1>; 634 status = "okay"; 635 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 639 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 640 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641 642 /* 643 * Bit 39 of addresses passing through the memory 644 * controller selects the XBAR format used when memory 645 * is accessed. This is used to transparently access 646 * memory in the XBAR format used by the discrete GPU 647 * (bit 39 set) or Tegra (bit 39 clear). 648 * 649 * As a consequence, the operating system must ensure 650 * that bit 39 is never used implicitly, for example 651 * via an I/O virtual address mapping of an IOMMU. If 652 * devices require access to the XBAR switch, their 653 * drivers must set this bit explicitly. 654 * 655 * Limit the DMA range for memory clients to [38:0]. 656 */ 657 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658 659 emc: external-memory-controller@2c60000 { 660 compatible = "nvidia,tegra234-emc"; 661 reg = <0x0 0x02c60000 0x0 0x90000>, 662 <0x0 0x01780000 0x0 0x80000>; 663 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA234_CLK_EMC>; 665 clock-names = "emc"; 666 status = "okay"; 667 668 #interconnect-cells = <0>; 669 670 nvidia,bpmp = <&bpmp>; 671 }; 672 }; 673 674 uarta: serial@3100000 { 675 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 676 reg = <0x0 0x03100000 0x0 0x10000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&bpmp TEGRA234_CLK_UARTA>; 679 clock-names = "serial"; 680 resets = <&bpmp TEGRA234_RESET_UARTA>; 681 reset-names = "serial"; 682 status = "disabled"; 683 }; 684 685 gen1_i2c: i2c@3160000 { 686 compatible = "nvidia,tegra194-i2c"; 687 reg = <0x0 0x3160000 0x0 0x100>; 688 status = "disabled"; 689 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 clock-frequency = <400000>; 693 clocks = <&bpmp TEGRA234_CLK_I2C1 694 &bpmp TEGRA234_CLK_PLLP_OUT0>; 695 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 696 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 697 clock-names = "div-clk", "parent"; 698 resets = <&bpmp TEGRA234_RESET_I2C1>; 699 reset-names = "i2c"; 700 dmas = <&gpcdma 21>, <&gpcdma 21>; 701 dma-names = "rx", "tx"; 702 }; 703 704 cam_i2c: i2c@3180000 { 705 compatible = "nvidia,tegra194-i2c"; 706 reg = <0x0 0x3180000 0x0 0x100>; 707 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 status = "disabled"; 711 clock-frequency = <400000>; 712 clocks = <&bpmp TEGRA234_CLK_I2C3 713 &bpmp TEGRA234_CLK_PLLP_OUT0>; 714 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 715 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 716 clock-names = "div-clk", "parent"; 717 resets = <&bpmp TEGRA234_RESET_I2C3>; 718 reset-names = "i2c"; 719 dmas = <&gpcdma 23>, <&gpcdma 23>; 720 dma-names = "rx", "tx"; 721 }; 722 723 dp_aux_ch1_i2c: i2c@3190000 { 724 compatible = "nvidia,tegra194-i2c"; 725 reg = <0x0 0x3190000 0x0 0x100>; 726 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 status = "disabled"; 730 clock-frequency = <100000>; 731 clocks = <&bpmp TEGRA234_CLK_I2C4 732 &bpmp TEGRA234_CLK_PLLP_OUT0>; 733 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 734 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 735 clock-names = "div-clk", "parent"; 736 resets = <&bpmp TEGRA234_RESET_I2C4>; 737 reset-names = "i2c"; 738 dmas = <&gpcdma 26>, <&gpcdma 26>; 739 dma-names = "rx", "tx"; 740 }; 741 742 dp_aux_ch0_i2c: i2c@31b0000 { 743 compatible = "nvidia,tegra194-i2c"; 744 reg = <0x0 0x31b0000 0x0 0x100>; 745 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 status = "disabled"; 749 clock-frequency = <100000>; 750 clocks = <&bpmp TEGRA234_CLK_I2C6 751 &bpmp TEGRA234_CLK_PLLP_OUT0>; 752 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 753 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 754 clock-names = "div-clk", "parent"; 755 resets = <&bpmp TEGRA234_RESET_I2C6>; 756 reset-names = "i2c"; 757 dmas = <&gpcdma 30>, <&gpcdma 30>; 758 dma-names = "rx", "tx"; 759 }; 760 761 dp_aux_ch2_i2c: i2c@31c0000 { 762 compatible = "nvidia,tegra194-i2c"; 763 reg = <0x0 0x31c0000 0x0 0x100>; 764 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 status = "disabled"; 768 clock-frequency = <100000>; 769 clocks = <&bpmp TEGRA234_CLK_I2C7 770 &bpmp TEGRA234_CLK_PLLP_OUT0>; 771 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 772 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 773 clock-names = "div-clk", "parent"; 774 resets = <&bpmp TEGRA234_RESET_I2C7>; 775 reset-names = "i2c"; 776 dmas = <&gpcdma 27>, <&gpcdma 27>; 777 dma-names = "rx", "tx"; 778 }; 779 780 uarti: serial@31d0000 { 781 compatible = "arm,sbsa-uart"; 782 reg = <0x0 0x31d0000 0x0 0x10000>; 783 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 784 status = "disabled"; 785 }; 786 787 dp_aux_ch3_i2c: i2c@31e0000 { 788 compatible = "nvidia,tegra194-i2c"; 789 reg = <0x0 0x31e0000 0x0 0x100>; 790 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 status = "disabled"; 794 clock-frequency = <100000>; 795 clocks = <&bpmp TEGRA234_CLK_I2C9 796 &bpmp TEGRA234_CLK_PLLP_OUT0>; 797 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 798 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 799 clock-names = "div-clk", "parent"; 800 resets = <&bpmp TEGRA234_RESET_I2C9>; 801 reset-names = "i2c"; 802 dmas = <&gpcdma 31>, <&gpcdma 31>; 803 dma-names = "rx", "tx"; 804 }; 805 806 spi@3270000 { 807 compatible = "nvidia,tegra234-qspi"; 808 reg = <0x0 0x3270000 0x0 0x1000>; 809 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 813 <&bpmp TEGRA234_CLK_QSPI0_PM>; 814 clock-names = "qspi", "qspi_out"; 815 resets = <&bpmp TEGRA234_RESET_QSPI0>; 816 status = "disabled"; 817 }; 818 819 pwm1: pwm@3280000 { 820 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 821 reg = <0x0 0x3280000 0x0 0x10000>; 822 clocks = <&bpmp TEGRA234_CLK_PWM1>; 823 resets = <&bpmp TEGRA234_RESET_PWM1>; 824 reset-names = "pwm"; 825 status = "disabled"; 826 #pwm-cells = <2>; 827 }; 828 829 pwm2: pwm@3290000 { 830 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 831 reg = <0x0 0x3290000 0x0 0x10000>; 832 clocks = <&bpmp TEGRA234_CLK_PWM2>; 833 resets = <&bpmp TEGRA234_RESET_PWM2>; 834 reset-names = "pwm"; 835 status = "disabled"; 836 #pwm-cells = <2>; 837 }; 838 839 pwm3: pwm@32a0000 { 840 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 841 reg = <0x0 0x32a0000 0x0 0x10000>; 842 clocks = <&bpmp TEGRA234_CLK_PWM3>; 843 resets = <&bpmp TEGRA234_RESET_PWM3>; 844 reset-names = "pwm"; 845 status = "disabled"; 846 #pwm-cells = <2>; 847 }; 848 849 pwm5: pwm@32c0000 { 850 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 851 reg = <0x0 0x32c0000 0x0 0x10000>; 852 clocks = <&bpmp TEGRA234_CLK_PWM5>; 853 resets = <&bpmp TEGRA234_RESET_PWM5>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 pwm6: pwm@32d0000 { 860 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 861 reg = <0x0 0x32d0000 0x0 0x10000>; 862 clocks = <&bpmp TEGRA234_CLK_PWM6>; 863 resets = <&bpmp TEGRA234_RESET_PWM6>; 864 reset-names = "pwm"; 865 status = "disabled"; 866 #pwm-cells = <2>; 867 }; 868 869 pwm7: pwm@32e0000 { 870 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 871 reg = <0x0 0x32e0000 0x0 0x10000>; 872 clocks = <&bpmp TEGRA234_CLK_PWM7>; 873 resets = <&bpmp TEGRA234_RESET_PWM7>; 874 reset-names = "pwm"; 875 status = "disabled"; 876 #pwm-cells = <2>; 877 }; 878 879 pwm8: pwm@32f0000 { 880 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 881 reg = <0x0 0x32f0000 0x0 0x10000>; 882 clocks = <&bpmp TEGRA234_CLK_PWM8>; 883 resets = <&bpmp TEGRA234_RESET_PWM8>; 884 reset-names = "pwm"; 885 status = "disabled"; 886 #pwm-cells = <2>; 887 }; 888 889 spi@3300000 { 890 compatible = "nvidia,tegra234-qspi"; 891 reg = <0x0 0x3300000 0x0 0x1000>; 892 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 896 <&bpmp TEGRA234_CLK_QSPI1_PM>; 897 clock-names = "qspi", "qspi_out"; 898 resets = <&bpmp TEGRA234_RESET_QSPI1>; 899 status = "disabled"; 900 }; 901 902 mmc@3400000 { 903 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 904 reg = <0x0 0x03400000 0x0 0x20000>; 905 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 907 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 908 clock-names = "sdhci", "tmclk"; 909 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 910 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 911 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 912 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 913 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 914 reset-names = "sdhci"; 915 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 916 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 917 interconnect-names = "dma-mem", "write"; 918 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 919 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 920 pinctrl-0 = <&sdmmc1_3v3>; 921 pinctrl-1 = <&sdmmc1_1v8>; 922 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 923 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 924 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 925 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 926 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 927 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 928 nvidia,default-tap = <14>; 929 nvidia,default-trim = <0x8>; 930 sd-uhs-sdr25; 931 sd-uhs-sdr50; 932 sd-uhs-ddr50; 933 sd-uhs-sdr104; 934 status = "disabled"; 935 }; 936 937 mmc@3460000 { 938 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 939 reg = <0x0 0x03460000 0x0 0x20000>; 940 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 942 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 943 clock-names = "sdhci", "tmclk"; 944 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 945 <&bpmp TEGRA234_CLK_PLLC4>; 946 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 947 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 948 reset-names = "sdhci"; 949 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 950 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 951 interconnect-names = "dma-mem", "write"; 952 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 953 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 954 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 955 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 956 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 957 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 958 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 959 nvidia,default-tap = <0x8>; 960 nvidia,default-trim = <0x14>; 961 nvidia,dqs-trim = <40>; 962 supports-cqe; 963 status = "disabled"; 964 }; 965 966 hda@3510000 { 967 compatible = "nvidia,tegra234-hda"; 968 reg = <0x0 0x3510000 0x0 0x10000>; 969 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 971 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 972 clock-names = "hda", "hda2codec_2x"; 973 resets = <&bpmp TEGRA234_RESET_HDA>, 974 <&bpmp TEGRA234_RESET_HDACODEC>; 975 reset-names = "hda", "hda2codec_2x"; 976 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 977 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 978 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 979 interconnect-names = "dma-mem", "write"; 980 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 981 status = "disabled"; 982 }; 983 984 xusb_padctl: padctl@3520000 { 985 compatible = "nvidia,tegra234-xusb-padctl"; 986 reg = <0x0 0x03520000 0x0 0x20000>, 987 <0x0 0x03540000 0x0 0x10000>; 988 reg-names = "padctl", "ao"; 989 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 990 991 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 992 reset-names = "padctl"; 993 994 status = "disabled"; 995 996 pads { 997 usb2 { 998 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 999 clock-names = "trk"; 1000 1001 lanes { 1002 usb2-0 { 1003 nvidia,function = "xusb"; 1004 status = "disabled"; 1005 #phy-cells = <0>; 1006 }; 1007 1008 usb2-1 { 1009 nvidia,function = "xusb"; 1010 status = "disabled"; 1011 #phy-cells = <0>; 1012 }; 1013 1014 usb2-2 { 1015 nvidia,function = "xusb"; 1016 status = "disabled"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 usb2-3 { 1021 nvidia,function = "xusb"; 1022 status = "disabled"; 1023 #phy-cells = <0>; 1024 }; 1025 }; 1026 }; 1027 1028 usb3 { 1029 lanes { 1030 usb3-0 { 1031 nvidia,function = "xusb"; 1032 status = "disabled"; 1033 #phy-cells = <0>; 1034 }; 1035 1036 usb3-1 { 1037 nvidia,function = "xusb"; 1038 status = "disabled"; 1039 #phy-cells = <0>; 1040 }; 1041 1042 usb3-2 { 1043 nvidia,function = "xusb"; 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 1048 usb3-3 { 1049 nvidia,function = "xusb"; 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 }; 1054 }; 1055 }; 1056 1057 ports { 1058 usb2-0 { 1059 status = "disabled"; 1060 }; 1061 1062 usb2-1 { 1063 status = "disabled"; 1064 }; 1065 1066 usb2-2 { 1067 status = "disabled"; 1068 }; 1069 1070 usb2-3 { 1071 status = "disabled"; 1072 }; 1073 1074 usb3-0 { 1075 status = "disabled"; 1076 }; 1077 1078 usb3-1 { 1079 status = "disabled"; 1080 }; 1081 1082 usb3-2 { 1083 status = "disabled"; 1084 }; 1085 1086 usb3-3 { 1087 status = "disabled"; 1088 }; 1089 }; 1090 }; 1091 1092 usb@3550000 { 1093 compatible = "nvidia,tegra234-xudc"; 1094 reg = <0x0 0x03550000 0x0 0x8000>, 1095 <0x0 0x03558000 0x0 0x8000>; 1096 reg-names = "base", "fpci"; 1097 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1099 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1100 <&bpmp TEGRA234_CLK_XUSB_SS>, 1101 <&bpmp TEGRA234_CLK_XUSB_FS>; 1102 clock-names = "dev", "ss", "ss_src", "fs_src"; 1103 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1104 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1105 interconnect-names = "dma-mem", "write"; 1106 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1107 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1108 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1109 power-domain-names = "dev", "ss"; 1110 nvidia,xusb-padctl = <&xusb_padctl>; 1111 dma-coherent; 1112 status = "disabled"; 1113 }; 1114 1115 usb@3610000 { 1116 compatible = "nvidia,tegra234-xusb"; 1117 reg = <0x0 0x03610000 0x0 0x40000>, 1118 <0x0 0x03600000 0x0 0x10000>, 1119 <0x0 0x03650000 0x0 0x10000>; 1120 reg-names = "hcd", "fpci", "bar2"; 1121 1122 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1124 1125 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1126 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1127 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1128 <&bpmp TEGRA234_CLK_XUSB_SS>, 1129 <&bpmp TEGRA234_CLK_CLK_M>, 1130 <&bpmp TEGRA234_CLK_XUSB_FS>, 1131 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1132 <&bpmp TEGRA234_CLK_CLK_M>, 1133 <&bpmp TEGRA234_CLK_PLLE>; 1134 clock-names = "xusb_host", "xusb_falcon_src", 1135 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1136 "xusb_fs_src", "pll_u_480m", "clk_m", 1137 "pll_e"; 1138 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1139 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1140 interconnect-names = "dma-mem", "write"; 1141 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1142 1143 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1144 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1145 power-domain-names = "xusb_host", "xusb_ss"; 1146 1147 nvidia,xusb-padctl = <&xusb_padctl>; 1148 dma-coherent; 1149 status = "disabled"; 1150 }; 1151 1152 fuse@3810000 { 1153 compatible = "nvidia,tegra234-efuse"; 1154 reg = <0x0 0x03810000 0x0 0x10000>; 1155 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1156 clock-names = "fuse"; 1157 }; 1158 1159 hsp_top0: hsp@3c00000 { 1160 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1161 reg = <0x0 0x03c00000 0x0 0xa0000>; 1162 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1172 "shared3", "shared4", "shared5", "shared6", 1173 "shared7"; 1174 #mbox-cells = <2>; 1175 }; 1176 1177 p2u_hsio_0: phy@3e00000 { 1178 compatible = "nvidia,tegra234-p2u"; 1179 reg = <0x0 0x03e00000 0x0 0x10000>; 1180 reg-names = "ctl"; 1181 1182 #phy-cells = <0>; 1183 }; 1184 1185 p2u_hsio_1: phy@3e10000 { 1186 compatible = "nvidia,tegra234-p2u"; 1187 reg = <0x0 0x03e10000 0x0 0x10000>; 1188 reg-names = "ctl"; 1189 1190 #phy-cells = <0>; 1191 }; 1192 1193 p2u_hsio_2: phy@3e20000 { 1194 compatible = "nvidia,tegra234-p2u"; 1195 reg = <0x0 0x03e20000 0x0 0x10000>; 1196 reg-names = "ctl"; 1197 1198 #phy-cells = <0>; 1199 }; 1200 1201 p2u_hsio_3: phy@3e30000 { 1202 compatible = "nvidia,tegra234-p2u"; 1203 reg = <0x0 0x03e30000 0x0 0x10000>; 1204 reg-names = "ctl"; 1205 1206 #phy-cells = <0>; 1207 }; 1208 1209 p2u_hsio_4: phy@3e40000 { 1210 compatible = "nvidia,tegra234-p2u"; 1211 reg = <0x0 0x03e40000 0x0 0x10000>; 1212 reg-names = "ctl"; 1213 1214 #phy-cells = <0>; 1215 }; 1216 1217 p2u_hsio_5: phy@3e50000 { 1218 compatible = "nvidia,tegra234-p2u"; 1219 reg = <0x0 0x03e50000 0x0 0x10000>; 1220 reg-names = "ctl"; 1221 1222 #phy-cells = <0>; 1223 }; 1224 1225 p2u_hsio_6: phy@3e60000 { 1226 compatible = "nvidia,tegra234-p2u"; 1227 reg = <0x0 0x03e60000 0x0 0x10000>; 1228 reg-names = "ctl"; 1229 1230 #phy-cells = <0>; 1231 }; 1232 1233 p2u_hsio_7: phy@3e70000 { 1234 compatible = "nvidia,tegra234-p2u"; 1235 reg = <0x0 0x03e70000 0x0 0x10000>; 1236 reg-names = "ctl"; 1237 1238 #phy-cells = <0>; 1239 }; 1240 1241 p2u_nvhs_0: phy@3e90000 { 1242 compatible = "nvidia,tegra234-p2u"; 1243 reg = <0x0 0x03e90000 0x0 0x10000>; 1244 reg-names = "ctl"; 1245 1246 #phy-cells = <0>; 1247 }; 1248 1249 p2u_nvhs_1: phy@3ea0000 { 1250 compatible = "nvidia,tegra234-p2u"; 1251 reg = <0x0 0x03ea0000 0x0 0x10000>; 1252 reg-names = "ctl"; 1253 1254 #phy-cells = <0>; 1255 }; 1256 1257 p2u_nvhs_2: phy@3eb0000 { 1258 compatible = "nvidia,tegra234-p2u"; 1259 reg = <0x0 0x03eb0000 0x0 0x10000>; 1260 reg-names = "ctl"; 1261 1262 #phy-cells = <0>; 1263 }; 1264 1265 p2u_nvhs_3: phy@3ec0000 { 1266 compatible = "nvidia,tegra234-p2u"; 1267 reg = <0x0 0x03ec0000 0x0 0x10000>; 1268 reg-names = "ctl"; 1269 1270 #phy-cells = <0>; 1271 }; 1272 1273 p2u_nvhs_4: phy@3ed0000 { 1274 compatible = "nvidia,tegra234-p2u"; 1275 reg = <0x0 0x03ed0000 0x0 0x10000>; 1276 reg-names = "ctl"; 1277 1278 #phy-cells = <0>; 1279 }; 1280 1281 p2u_nvhs_5: phy@3ee0000 { 1282 compatible = "nvidia,tegra234-p2u"; 1283 reg = <0x0 0x03ee0000 0x0 0x10000>; 1284 reg-names = "ctl"; 1285 1286 #phy-cells = <0>; 1287 }; 1288 1289 p2u_nvhs_6: phy@3ef0000 { 1290 compatible = "nvidia,tegra234-p2u"; 1291 reg = <0x0 0x03ef0000 0x0 0x10000>; 1292 reg-names = "ctl"; 1293 1294 #phy-cells = <0>; 1295 }; 1296 1297 p2u_nvhs_7: phy@3f00000 { 1298 compatible = "nvidia,tegra234-p2u"; 1299 reg = <0x0 0x03f00000 0x0 0x10000>; 1300 reg-names = "ctl"; 1301 1302 #phy-cells = <0>; 1303 }; 1304 1305 p2u_gbe_0: phy@3f20000 { 1306 compatible = "nvidia,tegra234-p2u"; 1307 reg = <0x0 0x03f20000 0x0 0x10000>; 1308 reg-names = "ctl"; 1309 1310 #phy-cells = <0>; 1311 }; 1312 1313 p2u_gbe_1: phy@3f30000 { 1314 compatible = "nvidia,tegra234-p2u"; 1315 reg = <0x0 0x03f30000 0x0 0x10000>; 1316 reg-names = "ctl"; 1317 1318 #phy-cells = <0>; 1319 }; 1320 1321 p2u_gbe_2: phy@3f40000 { 1322 compatible = "nvidia,tegra234-p2u"; 1323 reg = <0x0 0x03f40000 0x0 0x10000>; 1324 reg-names = "ctl"; 1325 1326 #phy-cells = <0>; 1327 }; 1328 1329 p2u_gbe_3: phy@3f50000 { 1330 compatible = "nvidia,tegra234-p2u"; 1331 reg = <0x0 0x03f50000 0x0 0x10000>; 1332 reg-names = "ctl"; 1333 1334 #phy-cells = <0>; 1335 }; 1336 1337 p2u_gbe_4: phy@3f60000 { 1338 compatible = "nvidia,tegra234-p2u"; 1339 reg = <0x0 0x03f60000 0x0 0x10000>; 1340 reg-names = "ctl"; 1341 1342 #phy-cells = <0>; 1343 }; 1344 1345 p2u_gbe_5: phy@3f70000 { 1346 compatible = "nvidia,tegra234-p2u"; 1347 reg = <0x0 0x03f70000 0x0 0x10000>; 1348 reg-names = "ctl"; 1349 1350 #phy-cells = <0>; 1351 }; 1352 1353 p2u_gbe_6: phy@3f80000 { 1354 compatible = "nvidia,tegra234-p2u"; 1355 reg = <0x0 0x03f80000 0x0 0x10000>; 1356 reg-names = "ctl"; 1357 1358 #phy-cells = <0>; 1359 }; 1360 1361 p2u_gbe_7: phy@3f90000 { 1362 compatible = "nvidia,tegra234-p2u"; 1363 reg = <0x0 0x03f90000 0x0 0x10000>; 1364 reg-names = "ctl"; 1365 1366 #phy-cells = <0>; 1367 }; 1368 1369 ethernet@6800000 { 1370 compatible = "nvidia,tegra234-mgbe"; 1371 reg = <0x0 0x06800000 0x0 0x10000>, 1372 <0x0 0x06810000 0x0 0x10000>, 1373 <0x0 0x068a0000 0x0 0x10000>; 1374 reg-names = "hypervisor", "mac", "xpcs"; 1375 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1376 interrupt-names = "common"; 1377 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1378 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1379 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1380 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1381 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1382 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1383 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1384 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1385 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1386 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1387 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1388 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1389 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1390 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1391 "rx-pcs", "tx-pcs"; 1392 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1393 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1394 reset-names = "mac", "pcs"; 1395 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1396 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1397 interconnect-names = "dma-mem", "write"; 1398 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1399 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1400 status = "disabled"; 1401 }; 1402 1403 ethernet@6900000 { 1404 compatible = "nvidia,tegra234-mgbe"; 1405 reg = <0x0 0x06900000 0x0 0x10000>, 1406 <0x0 0x06910000 0x0 0x10000>, 1407 <0x0 0x069a0000 0x0 0x10000>; 1408 reg-names = "hypervisor", "mac", "xpcs"; 1409 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1410 interrupt-names = "common"; 1411 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1412 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1413 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1414 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1415 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1416 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1417 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1418 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1419 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1420 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1421 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1422 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1423 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1424 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1425 "rx-pcs", "tx-pcs"; 1426 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1427 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1428 reset-names = "mac", "pcs"; 1429 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1430 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1431 interconnect-names = "dma-mem", "write"; 1432 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1433 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1434 status = "disabled"; 1435 }; 1436 1437 ethernet@6a00000 { 1438 compatible = "nvidia,tegra234-mgbe"; 1439 reg = <0x0 0x06a00000 0x0 0x10000>, 1440 <0x0 0x06a10000 0x0 0x10000>, 1441 <0x0 0x06aa0000 0x0 0x10000>; 1442 reg-names = "hypervisor", "mac", "xpcs"; 1443 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1444 interrupt-names = "common"; 1445 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1446 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1447 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1448 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1449 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1450 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1451 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1452 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1453 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1454 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1455 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1456 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1457 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1458 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1459 "rx-pcs", "tx-pcs"; 1460 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1461 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1462 reset-names = "mac", "pcs"; 1463 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1464 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1465 interconnect-names = "dma-mem", "write"; 1466 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1467 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1468 status = "disabled"; 1469 }; 1470 1471 ethernet@6b00000 { 1472 compatible = "nvidia,tegra234-mgbe"; 1473 reg = <0x0 0x06b00000 0x0 0x10000>, 1474 <0x0 0x06b10000 0x0 0x10000>, 1475 <0x0 0x06ba0000 0x0 0x10000>; 1476 reg-names = "hypervisor", "mac", "xpcs"; 1477 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1478 interrupt-names = "common"; 1479 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1480 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1481 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1482 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1483 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1484 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1485 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1486 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1487 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1488 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1489 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1490 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1491 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1492 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1493 "rx-pcs", "tx-pcs"; 1494 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1495 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1496 reset-names = "mac", "pcs"; 1497 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1498 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1499 interconnect-names = "dma-mem", "write"; 1500 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1501 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1502 status = "disabled"; 1503 }; 1504 1505 smmu_niso1: iommu@8000000 { 1506 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1507 reg = <0x0 0x8000000 0x0 0x1000000>, 1508 <0x0 0x7000000 0x0 0x1000000>; 1509 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1639 stream-match-mask = <0x7f80>; 1640 #global-interrupts = <2>; 1641 #iommu-cells = <1>; 1642 1643 nvidia,memory-controller = <&mc>; 1644 status = "okay"; 1645 }; 1646 1647 sce-fabric@b600000 { 1648 compatible = "nvidia,tegra234-sce-fabric"; 1649 reg = <0x0 0xb600000 0x0 0x40000>; 1650 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1651 status = "okay"; 1652 }; 1653 1654 rce-fabric@be00000 { 1655 compatible = "nvidia,tegra234-rce-fabric"; 1656 reg = <0x0 0xbe00000 0x0 0x40000>; 1657 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1658 status = "okay"; 1659 }; 1660 1661 hsp_aon: hsp@c150000 { 1662 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1663 reg = <0x0 0x0c150000 0x0 0x90000>; 1664 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1668 /* 1669 * Shared interrupt 0 is routed only to AON/SPE, so 1670 * we only have 4 shared interrupts for the CCPLEX. 1671 */ 1672 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1673 #mbox-cells = <2>; 1674 }; 1675 1676 gen2_i2c: i2c@c240000 { 1677 compatible = "nvidia,tegra194-i2c"; 1678 reg = <0x0 0xc240000 0x0 0x100>; 1679 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1680 #address-cells = <1>; 1681 #size-cells = <0>; 1682 status = "disabled"; 1683 clock-frequency = <100000>; 1684 clocks = <&bpmp TEGRA234_CLK_I2C2 1685 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1686 clock-names = "div-clk", "parent"; 1687 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1688 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1689 resets = <&bpmp TEGRA234_RESET_I2C2>; 1690 reset-names = "i2c"; 1691 dmas = <&gpcdma 22>, <&gpcdma 22>; 1692 dma-names = "rx", "tx"; 1693 }; 1694 1695 gen8_i2c: i2c@c250000 { 1696 compatible = "nvidia,tegra194-i2c"; 1697 reg = <0x0 0xc250000 0x0 0x100>; 1698 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 status = "disabled"; 1702 clock-frequency = <400000>; 1703 clocks = <&bpmp TEGRA234_CLK_I2C8 1704 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1705 clock-names = "div-clk", "parent"; 1706 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1707 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1708 resets = <&bpmp TEGRA234_RESET_I2C8>; 1709 reset-names = "i2c"; 1710 dmas = <&gpcdma 0>, <&gpcdma 0>; 1711 dma-names = "rx", "tx"; 1712 }; 1713 1714 rtc@c2a0000 { 1715 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1716 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1717 interrupt-parent = <&pmc>; 1718 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1719 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1720 clock-names = "rtc"; 1721 status = "disabled"; 1722 }; 1723 1724 gpio_aon: gpio@c2f0000 { 1725 compatible = "nvidia,tegra234-gpio-aon"; 1726 reg-names = "security", "gpio"; 1727 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1728 <0x0 0x0c2f1000 0x0 0x1000>; 1729 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1733 #interrupt-cells = <2>; 1734 interrupt-controller; 1735 #gpio-cells = <2>; 1736 gpio-controller; 1737 }; 1738 1739 pwm4: pwm@c340000 { 1740 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1741 reg = <0x0 0xc340000 0x0 0x10000>; 1742 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1743 resets = <&bpmp TEGRA234_RESET_PWM4>; 1744 reset-names = "pwm"; 1745 status = "disabled"; 1746 #pwm-cells = <2>; 1747 }; 1748 1749 pmc: pmc@c360000 { 1750 compatible = "nvidia,tegra234-pmc"; 1751 reg = <0x0 0x0c360000 0x0 0x10000>, 1752 <0x0 0x0c370000 0x0 0x10000>, 1753 <0x0 0x0c380000 0x0 0x10000>, 1754 <0x0 0x0c390000 0x0 0x10000>, 1755 <0x0 0x0c3a0000 0x0 0x10000>; 1756 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1757 1758 #interrupt-cells = <2>; 1759 interrupt-controller; 1760 1761 sdmmc1_1v8: sdmmc1-1v8 { 1762 pins = "sdmmc1-hv"; 1763 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1764 }; 1765 1766 sdmmc1_3v3: sdmmc1-3v3 { 1767 pins = "sdmmc1-hv"; 1768 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1769 }; 1770 1771 sdmmc3_1v8: sdmmc3-1v8 { 1772 pins = "sdmmc3-hv"; 1773 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1774 }; 1775 1776 sdmmc3_3v3: sdmmc3-3v3 { 1777 pins = "sdmmc3-hv"; 1778 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1779 }; 1780 }; 1781 1782 aon-fabric@c600000 { 1783 compatible = "nvidia,tegra234-aon-fabric"; 1784 reg = <0x0 0xc600000 0x0 0x40000>; 1785 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1786 status = "okay"; 1787 }; 1788 1789 bpmp-fabric@d600000 { 1790 compatible = "nvidia,tegra234-bpmp-fabric"; 1791 reg = <0x0 0xd600000 0x0 0x40000>; 1792 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1793 status = "okay"; 1794 }; 1795 1796 dce-fabric@de00000 { 1797 compatible = "nvidia,tegra234-sce-fabric"; 1798 reg = <0x0 0xde00000 0x0 0x40000>; 1799 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1800 status = "okay"; 1801 }; 1802 1803 ccplex@e000000 { 1804 compatible = "nvidia,tegra234-ccplex-cluster"; 1805 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1806 nvidia,bpmp = <&bpmp>; 1807 status = "okay"; 1808 }; 1809 1810 gic: interrupt-controller@f400000 { 1811 compatible = "arm,gic-v3"; 1812 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1813 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1814 interrupt-parent = <&gic>; 1815 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1816 1817 #redistributor-regions = <1>; 1818 #interrupt-cells = <3>; 1819 interrupt-controller; 1820 }; 1821 1822 smmu_iso: iommu@10000000 { 1823 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1824 reg = <0x0 0x10000000 0x0 0x1000000>; 1825 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1954 stream-match-mask = <0x7f80>; 1955 #global-interrupts = <1>; 1956 #iommu-cells = <1>; 1957 1958 nvidia,memory-controller = <&mc>; 1959 status = "okay"; 1960 }; 1961 1962 smmu_niso0: iommu@12000000 { 1963 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1964 reg = <0x0 0x12000000 0x0 0x1000000>, 1965 <0x0 0x11000000 0x0 0x1000000>; 1966 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2096 stream-match-mask = <0x7f80>; 2097 #global-interrupts = <2>; 2098 #iommu-cells = <1>; 2099 2100 nvidia,memory-controller = <&mc>; 2101 status = "okay"; 2102 }; 2103 2104 cbb-fabric@13a00000 { 2105 compatible = "nvidia,tegra234-cbb-fabric"; 2106 reg = <0x0 0x13a00000 0x0 0x400000>; 2107 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2108 status = "okay"; 2109 }; 2110 2111 host1x@13e00000 { 2112 compatible = "nvidia,tegra234-host1x"; 2113 reg = <0x0 0x13e00000 0x0 0x10000>, 2114 <0x0 0x13e10000 0x0 0x10000>, 2115 <0x0 0x13e40000 0x0 0x10000>; 2116 reg-names = "common", "hypervisor", "vm"; 2117 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2126 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2127 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2128 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2129 clock-names = "host1x"; 2130 2131 #address-cells = <2>; 2132 #size-cells = <2>; 2133 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2134 2135 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2136 interconnect-names = "dma-mem"; 2137 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2138 dma-coherent; 2139 2140 /* Context isolation domains */ 2141 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2142 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2143 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2144 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2145 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2146 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2147 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2148 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2149 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2150 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2151 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2152 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2153 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2154 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2155 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2156 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2157 2158 vic@15340000 { 2159 compatible = "nvidia,tegra234-vic"; 2160 reg = <0x0 0x15340000 0x0 0x00040000>; 2161 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&bpmp TEGRA234_CLK_VIC>; 2163 clock-names = "vic"; 2164 resets = <&bpmp TEGRA234_RESET_VIC>; 2165 reset-names = "vic"; 2166 2167 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2168 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2169 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2170 interconnect-names = "dma-mem", "write"; 2171 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2172 dma-coherent; 2173 }; 2174 2175 nvdec@15480000 { 2176 compatible = "nvidia,tegra234-nvdec"; 2177 reg = <0x0 0x15480000 0x0 0x00040000>; 2178 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2179 <&bpmp TEGRA234_CLK_FUSE>, 2180 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2181 clock-names = "nvdec", "fuse", "tsec_pka"; 2182 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2183 reset-names = "nvdec"; 2184 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2185 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2186 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2187 interconnect-names = "dma-mem", "write"; 2188 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2189 dma-coherent; 2190 2191 nvidia,memory-controller = <&mc>; 2192 2193 /* 2194 * Placeholder values that firmware needs to update with the real 2195 * offsets parsed from the microcode headers. 2196 */ 2197 nvidia,bl-manifest-offset = <0>; 2198 nvidia,bl-data-offset = <0>; 2199 nvidia,bl-code-offset = <0>; 2200 nvidia,os-manifest-offset = <0>; 2201 nvidia,os-data-offset = <0>; 2202 nvidia,os-code-offset = <0>; 2203 2204 /* 2205 * Firmware needs to set this to "okay" once the above values have 2206 * been updated. 2207 */ 2208 status = "disabled"; 2209 }; 2210 }; 2211 2212 pcie@140a0000 { 2213 compatible = "nvidia,tegra234-pcie"; 2214 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2215 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2216 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2217 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2218 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2219 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2220 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2221 2222 #address-cells = <3>; 2223 #size-cells = <2>; 2224 device_type = "pci"; 2225 num-lanes = <4>; 2226 num-viewport = <8>; 2227 linux,pci-domain = <8>; 2228 2229 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2230 clock-names = "core"; 2231 2232 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2233 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2234 reset-names = "apb", "core"; 2235 2236 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2237 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2238 interrupt-names = "intr", "msi"; 2239 2240 #interrupt-cells = <1>; 2241 interrupt-map-mask = <0 0 0 0>; 2242 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2243 2244 nvidia,bpmp = <&bpmp 8>; 2245 2246 nvidia,aspm-cmrt-us = <60>; 2247 nvidia,aspm-pwr-on-t-us = <20>; 2248 nvidia,aspm-l0s-entrance-latency-us = <3>; 2249 2250 bus-range = <0x0 0xff>; 2251 2252 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2253 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2254 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2255 2256 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2257 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2258 interconnect-names = "dma-mem", "write"; 2259 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2260 iommu-map-mask = <0x0>; 2261 dma-coherent; 2262 2263 status = "disabled"; 2264 }; 2265 2266 pcie@140c0000 { 2267 compatible = "nvidia,tegra234-pcie"; 2268 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2269 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2270 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2271 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2272 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2273 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2274 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2275 2276 #address-cells = <3>; 2277 #size-cells = <2>; 2278 device_type = "pci"; 2279 num-lanes = <4>; 2280 num-viewport = <8>; 2281 linux,pci-domain = <9>; 2282 2283 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2284 clock-names = "core"; 2285 2286 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2287 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2288 reset-names = "apb", "core"; 2289 2290 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2291 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2292 interrupt-names = "intr", "msi"; 2293 2294 #interrupt-cells = <1>; 2295 interrupt-map-mask = <0 0 0 0>; 2296 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2297 2298 nvidia,bpmp = <&bpmp 9>; 2299 2300 nvidia,aspm-cmrt-us = <60>; 2301 nvidia,aspm-pwr-on-t-us = <20>; 2302 nvidia,aspm-l0s-entrance-latency-us = <3>; 2303 2304 bus-range = <0x0 0xff>; 2305 2306 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2307 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2308 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2309 2310 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2311 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2312 interconnect-names = "dma-mem", "write"; 2313 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2314 iommu-map-mask = <0x0>; 2315 dma-coherent; 2316 2317 status = "disabled"; 2318 }; 2319 2320 pcie@140e0000 { 2321 compatible = "nvidia,tegra234-pcie"; 2322 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2323 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2324 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2325 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2326 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2327 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2328 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2329 2330 #address-cells = <3>; 2331 #size-cells = <2>; 2332 device_type = "pci"; 2333 num-lanes = <4>; 2334 num-viewport = <8>; 2335 linux,pci-domain = <10>; 2336 2337 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2338 clock-names = "core"; 2339 2340 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2341 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2342 reset-names = "apb", "core"; 2343 2344 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2345 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2346 interrupt-names = "intr", "msi"; 2347 2348 #interrupt-cells = <1>; 2349 interrupt-map-mask = <0 0 0 0>; 2350 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2351 2352 nvidia,bpmp = <&bpmp 10>; 2353 2354 nvidia,aspm-cmrt-us = <60>; 2355 nvidia,aspm-pwr-on-t-us = <20>; 2356 nvidia,aspm-l0s-entrance-latency-us = <3>; 2357 2358 bus-range = <0x0 0xff>; 2359 2360 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2361 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2362 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2363 2364 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2365 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2366 interconnect-names = "dma-mem", "write"; 2367 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2368 iommu-map-mask = <0x0>; 2369 dma-coherent; 2370 2371 status = "disabled"; 2372 }; 2373 2374 pcie-ep@140e0000 { 2375 compatible = "nvidia,tegra234-pcie-ep"; 2376 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2377 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2378 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2379 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2380 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2381 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2382 2383 num-lanes = <4>; 2384 2385 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2386 clock-names = "core"; 2387 2388 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2389 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2390 reset-names = "apb", "core"; 2391 2392 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2393 interrupt-names = "intr"; 2394 2395 nvidia,bpmp = <&bpmp 10>; 2396 2397 nvidia,enable-ext-refclk; 2398 nvidia,aspm-cmrt-us = <60>; 2399 nvidia,aspm-pwr-on-t-us = <20>; 2400 nvidia,aspm-l0s-entrance-latency-us = <3>; 2401 2402 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2403 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2404 interconnect-names = "dma-mem", "write"; 2405 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2406 iommu-map-mask = <0x0>; 2407 dma-coherent; 2408 2409 status = "disabled"; 2410 }; 2411 2412 pcie@14100000 { 2413 compatible = "nvidia,tegra234-pcie"; 2414 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2415 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2416 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2417 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2418 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2419 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2420 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2421 2422 #address-cells = <3>; 2423 #size-cells = <2>; 2424 device_type = "pci"; 2425 num-lanes = <1>; 2426 num-viewport = <8>; 2427 linux,pci-domain = <1>; 2428 2429 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2430 clock-names = "core"; 2431 2432 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2433 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2434 reset-names = "apb", "core"; 2435 2436 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2437 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2438 interrupt-names = "intr", "msi"; 2439 2440 #interrupt-cells = <1>; 2441 interrupt-map-mask = <0 0 0 0>; 2442 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2443 2444 nvidia,bpmp = <&bpmp 1>; 2445 2446 nvidia,aspm-cmrt-us = <60>; 2447 nvidia,aspm-pwr-on-t-us = <20>; 2448 nvidia,aspm-l0s-entrance-latency-us = <3>; 2449 2450 bus-range = <0x0 0xff>; 2451 2452 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2453 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2454 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2455 2456 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2457 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2458 interconnect-names = "dma-mem", "write"; 2459 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2460 iommu-map-mask = <0x0>; 2461 dma-coherent; 2462 2463 status = "disabled"; 2464 }; 2465 2466 pcie@14120000 { 2467 compatible = "nvidia,tegra234-pcie"; 2468 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2469 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2470 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2471 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2472 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2473 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2474 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2475 2476 #address-cells = <3>; 2477 #size-cells = <2>; 2478 device_type = "pci"; 2479 num-lanes = <1>; 2480 num-viewport = <8>; 2481 linux,pci-domain = <2>; 2482 2483 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2484 clock-names = "core"; 2485 2486 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2487 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2488 reset-names = "apb", "core"; 2489 2490 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2491 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2492 interrupt-names = "intr", "msi"; 2493 2494 #interrupt-cells = <1>; 2495 interrupt-map-mask = <0 0 0 0>; 2496 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2497 2498 nvidia,bpmp = <&bpmp 2>; 2499 2500 nvidia,aspm-cmrt-us = <60>; 2501 nvidia,aspm-pwr-on-t-us = <20>; 2502 nvidia,aspm-l0s-entrance-latency-us = <3>; 2503 2504 bus-range = <0x0 0xff>; 2505 2506 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2507 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2508 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2509 2510 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2511 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2512 interconnect-names = "dma-mem", "write"; 2513 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2514 iommu-map-mask = <0x0>; 2515 dma-coherent; 2516 2517 status = "disabled"; 2518 }; 2519 2520 pcie@14140000 { 2521 compatible = "nvidia,tegra234-pcie"; 2522 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2523 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2524 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2525 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2526 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2527 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2528 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2529 2530 #address-cells = <3>; 2531 #size-cells = <2>; 2532 device_type = "pci"; 2533 num-lanes = <1>; 2534 num-viewport = <8>; 2535 linux,pci-domain = <3>; 2536 2537 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2538 clock-names = "core"; 2539 2540 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2541 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2542 reset-names = "apb", "core"; 2543 2544 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2545 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2546 interrupt-names = "intr", "msi"; 2547 2548 #interrupt-cells = <1>; 2549 interrupt-map-mask = <0 0 0 0>; 2550 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2551 2552 nvidia,bpmp = <&bpmp 3>; 2553 2554 nvidia,aspm-cmrt-us = <60>; 2555 nvidia,aspm-pwr-on-t-us = <20>; 2556 nvidia,aspm-l0s-entrance-latency-us = <3>; 2557 2558 bus-range = <0x0 0xff>; 2559 2560 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2561 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2562 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2563 2564 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2565 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2566 interconnect-names = "dma-mem", "write"; 2567 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2568 iommu-map-mask = <0x0>; 2569 dma-coherent; 2570 2571 status = "disabled"; 2572 }; 2573 2574 pcie@14160000 { 2575 compatible = "nvidia,tegra234-pcie"; 2576 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2577 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2578 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2579 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2580 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2581 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2582 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2583 2584 #address-cells = <3>; 2585 #size-cells = <2>; 2586 device_type = "pci"; 2587 num-lanes = <4>; 2588 num-viewport = <8>; 2589 linux,pci-domain = <4>; 2590 2591 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2592 clock-names = "core"; 2593 2594 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2595 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2596 reset-names = "apb", "core"; 2597 2598 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2599 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2600 interrupt-names = "intr", "msi"; 2601 2602 #interrupt-cells = <1>; 2603 interrupt-map-mask = <0 0 0 0>; 2604 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2605 2606 nvidia,bpmp = <&bpmp 4>; 2607 2608 nvidia,aspm-cmrt-us = <60>; 2609 nvidia,aspm-pwr-on-t-us = <20>; 2610 nvidia,aspm-l0s-entrance-latency-us = <3>; 2611 2612 bus-range = <0x0 0xff>; 2613 2614 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2615 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2616 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2617 2618 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2619 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2620 interconnect-names = "dma-mem", "write"; 2621 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2622 iommu-map-mask = <0x0>; 2623 dma-coherent; 2624 2625 status = "disabled"; 2626 }; 2627 2628 pcie@14180000 { 2629 compatible = "nvidia,tegra234-pcie"; 2630 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2631 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2632 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2633 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2634 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2635 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2636 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2637 2638 #address-cells = <3>; 2639 #size-cells = <2>; 2640 device_type = "pci"; 2641 num-lanes = <4>; 2642 num-viewport = <8>; 2643 linux,pci-domain = <0>; 2644 2645 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2646 clock-names = "core"; 2647 2648 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2649 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2650 reset-names = "apb", "core"; 2651 2652 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2653 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2654 interrupt-names = "intr", "msi"; 2655 2656 #interrupt-cells = <1>; 2657 interrupt-map-mask = <0 0 0 0>; 2658 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2659 2660 nvidia,bpmp = <&bpmp 0>; 2661 2662 nvidia,aspm-cmrt-us = <60>; 2663 nvidia,aspm-pwr-on-t-us = <20>; 2664 nvidia,aspm-l0s-entrance-latency-us = <3>; 2665 2666 bus-range = <0x0 0xff>; 2667 2668 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2669 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2670 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2671 2672 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2673 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2674 interconnect-names = "dma-mem", "write"; 2675 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2676 iommu-map-mask = <0x0>; 2677 dma-coherent; 2678 2679 status = "disabled"; 2680 }; 2681 2682 pcie@141a0000 { 2683 compatible = "nvidia,tegra234-pcie"; 2684 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2685 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2686 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2687 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2688 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2689 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2690 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2691 2692 #address-cells = <3>; 2693 #size-cells = <2>; 2694 device_type = "pci"; 2695 num-lanes = <8>; 2696 num-viewport = <8>; 2697 linux,pci-domain = <5>; 2698 2699 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2700 clock-names = "core"; 2701 2702 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2703 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2704 reset-names = "apb", "core"; 2705 2706 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2707 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2708 interrupt-names = "intr", "msi"; 2709 2710 #interrupt-cells = <1>; 2711 interrupt-map-mask = <0 0 0 0>; 2712 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2713 2714 nvidia,bpmp = <&bpmp 5>; 2715 2716 nvidia,aspm-cmrt-us = <60>; 2717 nvidia,aspm-pwr-on-t-us = <20>; 2718 nvidia,aspm-l0s-entrance-latency-us = <3>; 2719 2720 bus-range = <0x0 0xff>; 2721 2722 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2723 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2724 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2725 2726 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2727 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2728 interconnect-names = "dma-mem", "write"; 2729 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2730 iommu-map-mask = <0x0>; 2731 dma-coherent; 2732 2733 status = "disabled"; 2734 }; 2735 2736 pcie-ep@141a0000 { 2737 compatible = "nvidia,tegra234-pcie-ep"; 2738 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2739 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2740 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2741 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2742 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2743 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2744 2745 num-lanes = <8>; 2746 2747 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2748 clock-names = "core"; 2749 2750 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2751 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2752 reset-names = "apb", "core"; 2753 2754 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2755 interrupt-names = "intr"; 2756 2757 nvidia,bpmp = <&bpmp 5>; 2758 2759 nvidia,enable-ext-refclk; 2760 nvidia,aspm-cmrt-us = <60>; 2761 nvidia,aspm-pwr-on-t-us = <20>; 2762 nvidia,aspm-l0s-entrance-latency-us = <3>; 2763 2764 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2765 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2766 interconnect-names = "dma-mem", "write"; 2767 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2768 iommu-map-mask = <0x0>; 2769 dma-coherent; 2770 2771 status = "disabled"; 2772 }; 2773 2774 pcie@141c0000 { 2775 compatible = "nvidia,tegra234-pcie"; 2776 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2777 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2778 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2779 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2780 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2781 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2782 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2783 2784 #address-cells = <3>; 2785 #size-cells = <2>; 2786 device_type = "pci"; 2787 num-lanes = <4>; 2788 num-viewport = <8>; 2789 linux,pci-domain = <6>; 2790 2791 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2792 clock-names = "core"; 2793 2794 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2795 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2796 reset-names = "apb", "core"; 2797 2798 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2799 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2800 interrupt-names = "intr", "msi"; 2801 2802 #interrupt-cells = <1>; 2803 interrupt-map-mask = <0 0 0 0>; 2804 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2805 2806 nvidia,bpmp = <&bpmp 6>; 2807 2808 nvidia,aspm-cmrt-us = <60>; 2809 nvidia,aspm-pwr-on-t-us = <20>; 2810 nvidia,aspm-l0s-entrance-latency-us = <3>; 2811 2812 bus-range = <0x0 0xff>; 2813 2814 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2815 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2816 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2817 2818 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2819 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2820 interconnect-names = "dma-mem", "write"; 2821 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2822 iommu-map-mask = <0x0>; 2823 dma-coherent; 2824 2825 status = "disabled"; 2826 }; 2827 2828 pcie-ep@141c0000 { 2829 compatible = "nvidia,tegra234-pcie-ep"; 2830 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2831 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2832 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2833 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2834 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2835 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2836 2837 num-lanes = <4>; 2838 2839 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2840 clock-names = "core"; 2841 2842 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2843 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2844 reset-names = "apb", "core"; 2845 2846 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2847 interrupt-names = "intr"; 2848 2849 nvidia,bpmp = <&bpmp 6>; 2850 2851 nvidia,enable-ext-refclk; 2852 nvidia,aspm-cmrt-us = <60>; 2853 nvidia,aspm-pwr-on-t-us = <20>; 2854 nvidia,aspm-l0s-entrance-latency-us = <3>; 2855 2856 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2857 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2858 interconnect-names = "dma-mem", "write"; 2859 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2860 iommu-map-mask = <0x0>; 2861 dma-coherent; 2862 2863 status = "disabled"; 2864 }; 2865 2866 pcie@141e0000 { 2867 compatible = "nvidia,tegra234-pcie"; 2868 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2869 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2870 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2871 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2872 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2873 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2874 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2875 2876 #address-cells = <3>; 2877 #size-cells = <2>; 2878 device_type = "pci"; 2879 num-lanes = <8>; 2880 num-viewport = <8>; 2881 linux,pci-domain = <7>; 2882 2883 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2884 clock-names = "core"; 2885 2886 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2887 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2888 reset-names = "apb", "core"; 2889 2890 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2891 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2892 interrupt-names = "intr", "msi"; 2893 2894 #interrupt-cells = <1>; 2895 interrupt-map-mask = <0 0 0 0>; 2896 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2897 2898 nvidia,bpmp = <&bpmp 7>; 2899 2900 nvidia,aspm-cmrt-us = <60>; 2901 nvidia,aspm-pwr-on-t-us = <20>; 2902 nvidia,aspm-l0s-entrance-latency-us = <3>; 2903 2904 bus-range = <0x0 0xff>; 2905 2906 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2907 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2908 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2909 2910 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2911 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2912 interconnect-names = "dma-mem", "write"; 2913 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2914 iommu-map-mask = <0x0>; 2915 dma-coherent; 2916 2917 status = "disabled"; 2918 }; 2919 2920 pcie-ep@141e0000 { 2921 compatible = "nvidia,tegra234-pcie-ep"; 2922 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2923 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2924 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2925 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2926 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2927 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2928 2929 num-lanes = <8>; 2930 2931 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2932 clock-names = "core"; 2933 2934 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2935 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2936 reset-names = "apb", "core"; 2937 2938 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2939 interrupt-names = "intr"; 2940 2941 nvidia,bpmp = <&bpmp 7>; 2942 2943 nvidia,enable-ext-refclk; 2944 nvidia,aspm-cmrt-us = <60>; 2945 nvidia,aspm-pwr-on-t-us = <20>; 2946 nvidia,aspm-l0s-entrance-latency-us = <3>; 2947 2948 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2949 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2950 interconnect-names = "dma-mem", "write"; 2951 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2952 iommu-map-mask = <0x0>; 2953 dma-coherent; 2954 2955 status = "disabled"; 2956 }; 2957 }; 2958 2959 sram@40000000 { 2960 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2961 reg = <0x0 0x40000000 0x0 0x80000>; 2962 2963 #address-cells = <1>; 2964 #size-cells = <1>; 2965 ranges = <0x0 0x0 0x40000000 0x80000>; 2966 2967 no-memory-wc; 2968 2969 cpu_bpmp_tx: sram@70000 { 2970 reg = <0x70000 0x1000>; 2971 label = "cpu-bpmp-tx"; 2972 pool; 2973 }; 2974 2975 cpu_bpmp_rx: sram@71000 { 2976 reg = <0x71000 0x1000>; 2977 label = "cpu-bpmp-rx"; 2978 pool; 2979 }; 2980 }; 2981 2982 bpmp: bpmp { 2983 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2984 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2985 TEGRA_HSP_DB_MASTER_BPMP>; 2986 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2987 #clock-cells = <1>; 2988 #reset-cells = <1>; 2989 #power-domain-cells = <1>; 2990 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 2991 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 2992 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 2993 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 2994 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2995 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 2996 2997 bpmp_i2c: i2c { 2998 compatible = "nvidia,tegra186-bpmp-i2c"; 2999 nvidia,bpmp-bus-id = <5>; 3000 #address-cells = <1>; 3001 #size-cells = <0>; 3002 }; 3003 }; 3004 3005 cpus { 3006 #address-cells = <1>; 3007 #size-cells = <0>; 3008 3009 cpu0_0: cpu@0 { 3010 compatible = "arm,cortex-a78"; 3011 device_type = "cpu"; 3012 reg = <0x00000>; 3013 3014 enable-method = "psci"; 3015 3016 i-cache-size = <65536>; 3017 i-cache-line-size = <64>; 3018 i-cache-sets = <256>; 3019 d-cache-size = <65536>; 3020 d-cache-line-size = <64>; 3021 d-cache-sets = <256>; 3022 next-level-cache = <&l2c0_0>; 3023 }; 3024 3025 cpu0_1: cpu@100 { 3026 compatible = "arm,cortex-a78"; 3027 device_type = "cpu"; 3028 reg = <0x00100>; 3029 3030 enable-method = "psci"; 3031 3032 i-cache-size = <65536>; 3033 i-cache-line-size = <64>; 3034 i-cache-sets = <256>; 3035 d-cache-size = <65536>; 3036 d-cache-line-size = <64>; 3037 d-cache-sets = <256>; 3038 next-level-cache = <&l2c0_1>; 3039 }; 3040 3041 cpu0_2: cpu@200 { 3042 compatible = "arm,cortex-a78"; 3043 device_type = "cpu"; 3044 reg = <0x00200>; 3045 3046 enable-method = "psci"; 3047 3048 i-cache-size = <65536>; 3049 i-cache-line-size = <64>; 3050 i-cache-sets = <256>; 3051 d-cache-size = <65536>; 3052 d-cache-line-size = <64>; 3053 d-cache-sets = <256>; 3054 next-level-cache = <&l2c0_2>; 3055 }; 3056 3057 cpu0_3: cpu@300 { 3058 compatible = "arm,cortex-a78"; 3059 device_type = "cpu"; 3060 reg = <0x00300>; 3061 3062 enable-method = "psci"; 3063 3064 i-cache-size = <65536>; 3065 i-cache-line-size = <64>; 3066 i-cache-sets = <256>; 3067 d-cache-size = <65536>; 3068 d-cache-line-size = <64>; 3069 d-cache-sets = <256>; 3070 next-level-cache = <&l2c0_3>; 3071 }; 3072 3073 cpu1_0: cpu@10000 { 3074 compatible = "arm,cortex-a78"; 3075 device_type = "cpu"; 3076 reg = <0x10000>; 3077 3078 enable-method = "psci"; 3079 3080 i-cache-size = <65536>; 3081 i-cache-line-size = <64>; 3082 i-cache-sets = <256>; 3083 d-cache-size = <65536>; 3084 d-cache-line-size = <64>; 3085 d-cache-sets = <256>; 3086 next-level-cache = <&l2c1_0>; 3087 }; 3088 3089 cpu1_1: cpu@10100 { 3090 compatible = "arm,cortex-a78"; 3091 device_type = "cpu"; 3092 reg = <0x10100>; 3093 3094 enable-method = "psci"; 3095 3096 i-cache-size = <65536>; 3097 i-cache-line-size = <64>; 3098 i-cache-sets = <256>; 3099 d-cache-size = <65536>; 3100 d-cache-line-size = <64>; 3101 d-cache-sets = <256>; 3102 next-level-cache = <&l2c1_1>; 3103 }; 3104 3105 cpu1_2: cpu@10200 { 3106 compatible = "arm,cortex-a78"; 3107 device_type = "cpu"; 3108 reg = <0x10200>; 3109 3110 enable-method = "psci"; 3111 3112 i-cache-size = <65536>; 3113 i-cache-line-size = <64>; 3114 i-cache-sets = <256>; 3115 d-cache-size = <65536>; 3116 d-cache-line-size = <64>; 3117 d-cache-sets = <256>; 3118 next-level-cache = <&l2c1_2>; 3119 }; 3120 3121 cpu1_3: cpu@10300 { 3122 compatible = "arm,cortex-a78"; 3123 device_type = "cpu"; 3124 reg = <0x10300>; 3125 3126 enable-method = "psci"; 3127 3128 i-cache-size = <65536>; 3129 i-cache-line-size = <64>; 3130 i-cache-sets = <256>; 3131 d-cache-size = <65536>; 3132 d-cache-line-size = <64>; 3133 d-cache-sets = <256>; 3134 next-level-cache = <&l2c1_3>; 3135 }; 3136 3137 cpu2_0: cpu@20000 { 3138 compatible = "arm,cortex-a78"; 3139 device_type = "cpu"; 3140 reg = <0x20000>; 3141 3142 enable-method = "psci"; 3143 3144 i-cache-size = <65536>; 3145 i-cache-line-size = <64>; 3146 i-cache-sets = <256>; 3147 d-cache-size = <65536>; 3148 d-cache-line-size = <64>; 3149 d-cache-sets = <256>; 3150 next-level-cache = <&l2c2_0>; 3151 }; 3152 3153 cpu2_1: cpu@20100 { 3154 compatible = "arm,cortex-a78"; 3155 device_type = "cpu"; 3156 reg = <0x20100>; 3157 3158 enable-method = "psci"; 3159 3160 i-cache-size = <65536>; 3161 i-cache-line-size = <64>; 3162 i-cache-sets = <256>; 3163 d-cache-size = <65536>; 3164 d-cache-line-size = <64>; 3165 d-cache-sets = <256>; 3166 next-level-cache = <&l2c2_1>; 3167 }; 3168 3169 cpu2_2: cpu@20200 { 3170 compatible = "arm,cortex-a78"; 3171 device_type = "cpu"; 3172 reg = <0x20200>; 3173 3174 enable-method = "psci"; 3175 3176 i-cache-size = <65536>; 3177 i-cache-line-size = <64>; 3178 i-cache-sets = <256>; 3179 d-cache-size = <65536>; 3180 d-cache-line-size = <64>; 3181 d-cache-sets = <256>; 3182 next-level-cache = <&l2c2_2>; 3183 }; 3184 3185 cpu2_3: cpu@20300 { 3186 compatible = "arm,cortex-a78"; 3187 device_type = "cpu"; 3188 reg = <0x20300>; 3189 3190 enable-method = "psci"; 3191 3192 i-cache-size = <65536>; 3193 i-cache-line-size = <64>; 3194 i-cache-sets = <256>; 3195 d-cache-size = <65536>; 3196 d-cache-line-size = <64>; 3197 d-cache-sets = <256>; 3198 next-level-cache = <&l2c2_3>; 3199 }; 3200 3201 cpu-map { 3202 cluster0 { 3203 core0 { 3204 cpu = <&cpu0_0>; 3205 }; 3206 3207 core1 { 3208 cpu = <&cpu0_1>; 3209 }; 3210 3211 core2 { 3212 cpu = <&cpu0_2>; 3213 }; 3214 3215 core3 { 3216 cpu = <&cpu0_3>; 3217 }; 3218 }; 3219 3220 cluster1 { 3221 core0 { 3222 cpu = <&cpu1_0>; 3223 }; 3224 3225 core1 { 3226 cpu = <&cpu1_1>; 3227 }; 3228 3229 core2 { 3230 cpu = <&cpu1_2>; 3231 }; 3232 3233 core3 { 3234 cpu = <&cpu1_3>; 3235 }; 3236 }; 3237 3238 cluster2 { 3239 core0 { 3240 cpu = <&cpu2_0>; 3241 }; 3242 3243 core1 { 3244 cpu = <&cpu2_1>; 3245 }; 3246 3247 core2 { 3248 cpu = <&cpu2_2>; 3249 }; 3250 3251 core3 { 3252 cpu = <&cpu2_3>; 3253 }; 3254 }; 3255 }; 3256 3257 l2c0_0: l2-cache00 { 3258 compatible = "cache"; 3259 cache-size = <262144>; 3260 cache-line-size = <64>; 3261 cache-sets = <512>; 3262 cache-unified; 3263 cache-level = <2>; 3264 next-level-cache = <&l3c0>; 3265 }; 3266 3267 l2c0_1: l2-cache01 { 3268 compatible = "cache"; 3269 cache-size = <262144>; 3270 cache-line-size = <64>; 3271 cache-sets = <512>; 3272 cache-unified; 3273 cache-level = <2>; 3274 next-level-cache = <&l3c0>; 3275 }; 3276 3277 l2c0_2: l2-cache02 { 3278 compatible = "cache"; 3279 cache-size = <262144>; 3280 cache-line-size = <64>; 3281 cache-sets = <512>; 3282 cache-unified; 3283 cache-level = <2>; 3284 next-level-cache = <&l3c0>; 3285 }; 3286 3287 l2c0_3: l2-cache03 { 3288 compatible = "cache"; 3289 cache-size = <262144>; 3290 cache-line-size = <64>; 3291 cache-sets = <512>; 3292 cache-unified; 3293 cache-level = <2>; 3294 next-level-cache = <&l3c0>; 3295 }; 3296 3297 l2c1_0: l2-cache10 { 3298 compatible = "cache"; 3299 cache-size = <262144>; 3300 cache-line-size = <64>; 3301 cache-sets = <512>; 3302 cache-unified; 3303 cache-level = <2>; 3304 next-level-cache = <&l3c1>; 3305 }; 3306 3307 l2c1_1: l2-cache11 { 3308 compatible = "cache"; 3309 cache-size = <262144>; 3310 cache-line-size = <64>; 3311 cache-sets = <512>; 3312 cache-unified; 3313 cache-level = <2>; 3314 next-level-cache = <&l3c1>; 3315 }; 3316 3317 l2c1_2: l2-cache12 { 3318 compatible = "cache"; 3319 cache-size = <262144>; 3320 cache-line-size = <64>; 3321 cache-sets = <512>; 3322 cache-unified; 3323 cache-level = <2>; 3324 next-level-cache = <&l3c1>; 3325 }; 3326 3327 l2c1_3: l2-cache13 { 3328 compatible = "cache"; 3329 cache-size = <262144>; 3330 cache-line-size = <64>; 3331 cache-sets = <512>; 3332 cache-unified; 3333 cache-level = <2>; 3334 next-level-cache = <&l3c1>; 3335 }; 3336 3337 l2c2_0: l2-cache20 { 3338 compatible = "cache"; 3339 cache-size = <262144>; 3340 cache-line-size = <64>; 3341 cache-sets = <512>; 3342 cache-unified; 3343 cache-level = <2>; 3344 next-level-cache = <&l3c2>; 3345 }; 3346 3347 l2c2_1: l2-cache21 { 3348 compatible = "cache"; 3349 cache-size = <262144>; 3350 cache-line-size = <64>; 3351 cache-sets = <512>; 3352 cache-unified; 3353 cache-level = <2>; 3354 next-level-cache = <&l3c2>; 3355 }; 3356 3357 l2c2_2: l2-cache22 { 3358 compatible = "cache"; 3359 cache-size = <262144>; 3360 cache-line-size = <64>; 3361 cache-sets = <512>; 3362 cache-unified; 3363 cache-level = <2>; 3364 next-level-cache = <&l3c2>; 3365 }; 3366 3367 l2c2_3: l2-cache23 { 3368 compatible = "cache"; 3369 cache-size = <262144>; 3370 cache-line-size = <64>; 3371 cache-sets = <512>; 3372 cache-unified; 3373 cache-level = <2>; 3374 next-level-cache = <&l3c2>; 3375 }; 3376 3377 l3c0: l3-cache0 { 3378 compatible = "cache"; 3379 cache-unified; 3380 cache-size = <2097152>; 3381 cache-line-size = <64>; 3382 cache-sets = <2048>; 3383 cache-level = <3>; 3384 }; 3385 3386 l3c1: l3-cache1 { 3387 compatible = "cache"; 3388 cache-unified; 3389 cache-size = <2097152>; 3390 cache-line-size = <64>; 3391 cache-sets = <2048>; 3392 cache-level = <3>; 3393 }; 3394 3395 l3c2: l3-cache2 { 3396 compatible = "cache"; 3397 cache-unified; 3398 cache-size = <2097152>; 3399 cache-line-size = <64>; 3400 cache-sets = <2048>; 3401 cache-level = <3>; 3402 }; 3403 }; 3404 3405 pmu { 3406 compatible = "arm,cortex-a78-pmu"; 3407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3408 status = "okay"; 3409 }; 3410 3411 psci { 3412 compatible = "arm,psci-1.0"; 3413 status = "okay"; 3414 method = "smc"; 3415 }; 3416 3417 tcu: serial { 3418 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3419 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3420 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3421 mbox-names = "rx", "tx"; 3422 status = "disabled"; 3423 }; 3424 3425 sound { 3426 status = "disabled"; 3427 3428 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3429 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3430 clock-names = "pll_a", "plla_out0"; 3431 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3432 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3433 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3434 assigned-clock-parents = <0>, 3435 <&bpmp TEGRA234_CLK_PLLA>, 3436 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3437 }; 3438 3439 timer { 3440 compatible = "arm,armv8-timer"; 3441 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3442 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3443 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3444 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3445 interrupt-parent = <&gic>; 3446 always-on; 3447 }; 3448}; 3449