1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11#include <dt-bindings/thermal/tegra234-bpmp-thermal.h> 12 13/ { 14 compatible = "nvidia,tegra234"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 bus@0 { 20 compatible = "simple-bus"; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra234-misc"; 28 reg = <0x0 0x00100000 0x0 0xf000>, 29 <0x0 0x0010f000 0x0 0x1000>; 30 status = "okay"; 31 }; 32 33 timer@2080000 { 34 compatible = "nvidia,tegra234-timer"; 35 reg = <0x0 0x02080000 0x0 0x00121000>; 36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 52 status = "okay"; 53 }; 54 55 gpio: gpio@2200000 { 56 compatible = "nvidia,tegra234-gpio"; 57 reg-names = "security", "gpio"; 58 reg = <0x0 0x02200000 0x0 0x10000>, 59 <0x0 0x02210000 0x0 0x10000>; 60 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 108 #interrupt-cells = <2>; 109 interrupt-controller; 110 #gpio-cells = <2>; 111 gpio-controller; 112 gpio-ranges = <&pinmux 0 0 164>; 113 }; 114 115 pinmux: pinmux@2430000 { 116 compatible = "nvidia,tegra234-pinmux"; 117 reg = <0x0 0x2430000 0x0 0x19100>; 118 }; 119 120 gpcdma: dma-controller@2600000 { 121 compatible = "nvidia,tegra234-gpcdma", 122 "nvidia,tegra186-gpcdma"; 123 reg = <0x0 0x2600000 0x0 0x210000>; 124 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 125 reset-names = "gpcdma"; 126 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 158 #dma-cells = <1>; 159 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 160 dma-channel-mask = <0xfffffffe>; 161 dma-coherent; 162 }; 163 164 aconnect@2900000 { 165 compatible = "nvidia,tegra234-aconnect", 166 "nvidia,tegra210-aconnect"; 167 clocks = <&bpmp TEGRA234_CLK_APE>, 168 <&bpmp TEGRA234_CLK_APB2APE>; 169 clock-names = "ape", "apb2ape"; 170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 171 status = "disabled"; 172 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 176 177 tegra_ahub: ahub@2900800 { 178 compatible = "nvidia,tegra234-ahub"; 179 reg = <0x0 0x02900800 0x0 0x800>; 180 clocks = <&bpmp TEGRA234_CLK_AHUB>; 181 clock-names = "ahub"; 182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 184 status = "disabled"; 185 186 #address-cells = <2>; 187 #size-cells = <2>; 188 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 189 190 tegra_i2s1: i2s@2901000 { 191 compatible = "nvidia,tegra234-i2s", 192 "nvidia,tegra210-i2s"; 193 reg = <0x0 0x2901000 0x0 0x100>; 194 clocks = <&bpmp TEGRA234_CLK_I2S1>, 195 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 196 clock-names = "i2s", "sync_input"; 197 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 198 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 199 assigned-clock-rates = <1536000>; 200 sound-name-prefix = "I2S1"; 201 status = "disabled"; 202 }; 203 204 tegra_i2s2: i2s@2901100 { 205 compatible = "nvidia,tegra234-i2s", 206 "nvidia,tegra210-i2s"; 207 reg = <0x0 0x2901100 0x0 0x100>; 208 clocks = <&bpmp TEGRA234_CLK_I2S2>, 209 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 210 clock-names = "i2s", "sync_input"; 211 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 212 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 213 assigned-clock-rates = <1536000>; 214 sound-name-prefix = "I2S2"; 215 status = "disabled"; 216 }; 217 218 tegra_i2s3: i2s@2901200 { 219 compatible = "nvidia,tegra234-i2s", 220 "nvidia,tegra210-i2s"; 221 reg = <0x0 0x2901200 0x0 0x100>; 222 clocks = <&bpmp TEGRA234_CLK_I2S3>, 223 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 224 clock-names = "i2s", "sync_input"; 225 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 226 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 227 assigned-clock-rates = <1536000>; 228 sound-name-prefix = "I2S3"; 229 status = "disabled"; 230 }; 231 232 tegra_i2s4: i2s@2901300 { 233 compatible = "nvidia,tegra234-i2s", 234 "nvidia,tegra210-i2s"; 235 reg = <0x0 0x2901300 0x0 0x100>; 236 clocks = <&bpmp TEGRA234_CLK_I2S4>, 237 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 238 clock-names = "i2s", "sync_input"; 239 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 240 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 241 assigned-clock-rates = <1536000>; 242 sound-name-prefix = "I2S4"; 243 status = "disabled"; 244 }; 245 246 tegra_i2s5: i2s@2901400 { 247 compatible = "nvidia,tegra234-i2s", 248 "nvidia,tegra210-i2s"; 249 reg = <0x0 0x2901400 0x0 0x100>; 250 clocks = <&bpmp TEGRA234_CLK_I2S5>, 251 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 252 clock-names = "i2s", "sync_input"; 253 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 254 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 255 assigned-clock-rates = <1536000>; 256 sound-name-prefix = "I2S5"; 257 status = "disabled"; 258 }; 259 260 tegra_i2s6: i2s@2901500 { 261 compatible = "nvidia,tegra234-i2s", 262 "nvidia,tegra210-i2s"; 263 reg = <0x0 0x2901500 0x0 0x100>; 264 clocks = <&bpmp TEGRA234_CLK_I2S6>, 265 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 266 clock-names = "i2s", "sync_input"; 267 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 268 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 269 assigned-clock-rates = <1536000>; 270 sound-name-prefix = "I2S6"; 271 status = "disabled"; 272 }; 273 274 tegra_sfc1: sfc@2902000 { 275 compatible = "nvidia,tegra234-sfc", 276 "nvidia,tegra210-sfc"; 277 reg = <0x0 0x2902000 0x0 0x200>; 278 sound-name-prefix = "SFC1"; 279 status = "disabled"; 280 }; 281 282 tegra_sfc2: sfc@2902200 { 283 compatible = "nvidia,tegra234-sfc", 284 "nvidia,tegra210-sfc"; 285 reg = <0x0 0x2902200 0x0 0x200>; 286 sound-name-prefix = "SFC2"; 287 status = "disabled"; 288 }; 289 290 tegra_sfc3: sfc@2902400 { 291 compatible = "nvidia,tegra234-sfc", 292 "nvidia,tegra210-sfc"; 293 reg = <0x0 0x2902400 0x0 0x200>; 294 sound-name-prefix = "SFC3"; 295 status = "disabled"; 296 }; 297 298 tegra_sfc4: sfc@2902600 { 299 compatible = "nvidia,tegra234-sfc", 300 "nvidia,tegra210-sfc"; 301 reg = <0x0 0x2902600 0x0 0x200>; 302 sound-name-prefix = "SFC4"; 303 status = "disabled"; 304 }; 305 306 tegra_amx1: amx@2903000 { 307 compatible = "nvidia,tegra234-amx", 308 "nvidia,tegra194-amx"; 309 reg = <0x0 0x2903000 0x0 0x100>; 310 sound-name-prefix = "AMX1"; 311 status = "disabled"; 312 }; 313 314 tegra_amx2: amx@2903100 { 315 compatible = "nvidia,tegra234-amx", 316 "nvidia,tegra194-amx"; 317 reg = <0x0 0x2903100 0x0 0x100>; 318 sound-name-prefix = "AMX2"; 319 status = "disabled"; 320 }; 321 322 tegra_amx3: amx@2903200 { 323 compatible = "nvidia,tegra234-amx", 324 "nvidia,tegra194-amx"; 325 reg = <0x0 0x2903200 0x0 0x100>; 326 sound-name-prefix = "AMX3"; 327 status = "disabled"; 328 }; 329 330 tegra_amx4: amx@2903300 { 331 compatible = "nvidia,tegra234-amx", 332 "nvidia,tegra194-amx"; 333 reg = <0x0 0x2903300 0x0 0x100>; 334 sound-name-prefix = "AMX4"; 335 status = "disabled"; 336 }; 337 338 tegra_adx1: adx@2903800 { 339 compatible = "nvidia,tegra234-adx", 340 "nvidia,tegra210-adx"; 341 reg = <0x0 0x2903800 0x0 0x100>; 342 sound-name-prefix = "ADX1"; 343 status = "disabled"; 344 }; 345 346 tegra_adx2: adx@2903900 { 347 compatible = "nvidia,tegra234-adx", 348 "nvidia,tegra210-adx"; 349 reg = <0x0 0x2903900 0x0 0x100>; 350 sound-name-prefix = "ADX2"; 351 status = "disabled"; 352 }; 353 354 tegra_adx3: adx@2903a00 { 355 compatible = "nvidia,tegra234-adx", 356 "nvidia,tegra210-adx"; 357 reg = <0x0 0x2903a00 0x0 0x100>; 358 sound-name-prefix = "ADX3"; 359 status = "disabled"; 360 }; 361 362 tegra_adx4: adx@2903b00 { 363 compatible = "nvidia,tegra234-adx", 364 "nvidia,tegra210-adx"; 365 reg = <0x0 0x2903b00 0x0 0x100>; 366 sound-name-prefix = "ADX4"; 367 status = "disabled"; 368 }; 369 370 371 tegra_dmic1: dmic@2904000 { 372 compatible = "nvidia,tegra234-dmic", 373 "nvidia,tegra210-dmic"; 374 reg = <0x0 0x2904000 0x0 0x100>; 375 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 376 clock-names = "dmic"; 377 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 378 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 379 assigned-clock-rates = <3072000>; 380 sound-name-prefix = "DMIC1"; 381 status = "disabled"; 382 }; 383 384 tegra_dmic2: dmic@2904100 { 385 compatible = "nvidia,tegra234-dmic", 386 "nvidia,tegra210-dmic"; 387 reg = <0x0 0x2904100 0x0 0x100>; 388 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 389 clock-names = "dmic"; 390 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 391 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 392 assigned-clock-rates = <3072000>; 393 sound-name-prefix = "DMIC2"; 394 status = "disabled"; 395 }; 396 397 tegra_dmic3: dmic@2904200 { 398 compatible = "nvidia,tegra234-dmic", 399 "nvidia,tegra210-dmic"; 400 reg = <0x0 0x2904200 0x0 0x100>; 401 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 402 clock-names = "dmic"; 403 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 404 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 405 assigned-clock-rates = <3072000>; 406 sound-name-prefix = "DMIC3"; 407 status = "disabled"; 408 }; 409 410 tegra_dmic4: dmic@2904300 { 411 compatible = "nvidia,tegra234-dmic", 412 "nvidia,tegra210-dmic"; 413 reg = <0x0 0x2904300 0x0 0x100>; 414 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 415 clock-names = "dmic"; 416 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 417 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 418 assigned-clock-rates = <3072000>; 419 sound-name-prefix = "DMIC4"; 420 status = "disabled"; 421 }; 422 423 tegra_dspk1: dspk@2905000 { 424 compatible = "nvidia,tegra234-dspk", 425 "nvidia,tegra186-dspk"; 426 reg = <0x0 0x2905000 0x0 0x100>; 427 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 428 clock-names = "dspk"; 429 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 430 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 431 assigned-clock-rates = <12288000>; 432 sound-name-prefix = "DSPK1"; 433 status = "disabled"; 434 }; 435 436 tegra_dspk2: dspk@2905100 { 437 compatible = "nvidia,tegra234-dspk", 438 "nvidia,tegra186-dspk"; 439 reg = <0x0 0x2905100 0x0 0x100>; 440 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 441 clock-names = "dspk"; 442 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 443 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 444 assigned-clock-rates = <12288000>; 445 sound-name-prefix = "DSPK2"; 446 status = "disabled"; 447 }; 448 449 tegra_ope1: processing-engine@2908000 { 450 compatible = "nvidia,tegra234-ope", 451 "nvidia,tegra210-ope"; 452 reg = <0x0 0x2908000 0x0 0x100>; 453 sound-name-prefix = "OPE1"; 454 status = "disabled"; 455 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges; 459 460 equalizer@2908100 { 461 compatible = "nvidia,tegra234-peq", 462 "nvidia,tegra210-peq"; 463 reg = <0x0 0x2908100 0x0 0x100>; 464 }; 465 466 dynamic-range-compressor@2908200 { 467 compatible = "nvidia,tegra234-mbdrc", 468 "nvidia,tegra210-mbdrc"; 469 reg = <0x0 0x2908200 0x0 0x200>; 470 }; 471 }; 472 473 tegra_mvc1: mvc@290a000 { 474 compatible = "nvidia,tegra234-mvc", 475 "nvidia,tegra210-mvc"; 476 reg = <0x0 0x290a000 0x0 0x200>; 477 sound-name-prefix = "MVC1"; 478 status = "disabled"; 479 }; 480 481 tegra_mvc2: mvc@290a200 { 482 compatible = "nvidia,tegra234-mvc", 483 "nvidia,tegra210-mvc"; 484 reg = <0x0 0x290a200 0x0 0x200>; 485 sound-name-prefix = "MVC2"; 486 status = "disabled"; 487 }; 488 489 tegra_amixer: amixer@290bb00 { 490 compatible = "nvidia,tegra234-amixer", 491 "nvidia,tegra210-amixer"; 492 reg = <0x0 0x290bb00 0x0 0x800>; 493 sound-name-prefix = "MIXER1"; 494 status = "disabled"; 495 }; 496 497 tegra_admaif: admaif@290f000 { 498 compatible = "nvidia,tegra234-admaif", 499 "nvidia,tegra186-admaif"; 500 reg = <0x0 0x0290f000 0x0 0x1000>; 501 dmas = <&adma 1>, <&adma 1>, 502 <&adma 2>, <&adma 2>, 503 <&adma 3>, <&adma 3>, 504 <&adma 4>, <&adma 4>, 505 <&adma 5>, <&adma 5>, 506 <&adma 6>, <&adma 6>, 507 <&adma 7>, <&adma 7>, 508 <&adma 8>, <&adma 8>, 509 <&adma 9>, <&adma 9>, 510 <&adma 10>, <&adma 10>, 511 <&adma 11>, <&adma 11>, 512 <&adma 12>, <&adma 12>, 513 <&adma 13>, <&adma 13>, 514 <&adma 14>, <&adma 14>, 515 <&adma 15>, <&adma 15>, 516 <&adma 16>, <&adma 16>, 517 <&adma 17>, <&adma 17>, 518 <&adma 18>, <&adma 18>, 519 <&adma 19>, <&adma 19>, 520 <&adma 20>, <&adma 20>; 521 dma-names = "rx1", "tx1", 522 "rx2", "tx2", 523 "rx3", "tx3", 524 "rx4", "tx4", 525 "rx5", "tx5", 526 "rx6", "tx6", 527 "rx7", "tx7", 528 "rx8", "tx8", 529 "rx9", "tx9", 530 "rx10", "tx10", 531 "rx11", "tx11", 532 "rx12", "tx12", 533 "rx13", "tx13", 534 "rx14", "tx14", 535 "rx15", "tx15", 536 "rx16", "tx16", 537 "rx17", "tx17", 538 "rx18", "tx18", 539 "rx19", "tx19", 540 "rx20", "tx20"; 541 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 542 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 543 interconnect-names = "dma-mem", "write"; 544 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 545 status = "disabled"; 546 }; 547 548 tegra_asrc: asrc@2910000 { 549 compatible = "nvidia,tegra234-asrc", 550 "nvidia,tegra186-asrc"; 551 reg = <0x0 0x2910000 0x0 0x2000>; 552 sound-name-prefix = "ASRC1"; 553 status = "disabled"; 554 }; 555 }; 556 557 adma: dma-controller@2930000 { 558 compatible = "nvidia,tegra234-adma", 559 "nvidia,tegra186-adma"; 560 reg = <0x0 0x02930000 0x0 0x20000>; 561 interrupt-parent = <&agic>; 562 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 594 #dma-cells = <1>; 595 clocks = <&bpmp TEGRA234_CLK_AHUB>; 596 clock-names = "d_audio"; 597 status = "disabled"; 598 }; 599 600 agic: interrupt-controller@2a40000 { 601 compatible = "nvidia,tegra234-agic", 602 "nvidia,tegra210-agic"; 603 #interrupt-cells = <3>; 604 interrupt-controller; 605 reg = <0x0 0x02a41000 0x0 0x1000>, 606 <0x0 0x02a42000 0x0 0x2000>; 607 interrupts = <GIC_SPI 145 608 (GIC_CPU_MASK_SIMPLE(4) | 609 IRQ_TYPE_LEVEL_HIGH)>; 610 clocks = <&bpmp TEGRA234_CLK_APE>; 611 clock-names = "clk"; 612 status = "disabled"; 613 }; 614 }; 615 616 mc: memory-controller@2c00000 { 617 compatible = "nvidia,tegra234-mc"; 618 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 619 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 620 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 621 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 622 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 623 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 624 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 625 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 626 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 627 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 628 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 629 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 630 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 631 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 632 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 633 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 634 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 635 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 636 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 637 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 638 "ch11", "ch12", "ch13", "ch14", "ch15"; 639 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 640 #interconnect-cells = <1>; 641 status = "okay"; 642 643 #address-cells = <2>; 644 #size-cells = <2>; 645 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 646 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 647 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 648 649 /* 650 * Bit 39 of addresses passing through the memory 651 * controller selects the XBAR format used when memory 652 * is accessed. This is used to transparently access 653 * memory in the XBAR format used by the discrete GPU 654 * (bit 39 set) or Tegra (bit 39 clear). 655 * 656 * As a consequence, the operating system must ensure 657 * that bit 39 is never used implicitly, for example 658 * via an I/O virtual address mapping of an IOMMU. If 659 * devices require access to the XBAR switch, their 660 * drivers must set this bit explicitly. 661 * 662 * Limit the DMA range for memory clients to [38:0]. 663 */ 664 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 665 666 emc: external-memory-controller@2c60000 { 667 compatible = "nvidia,tegra234-emc"; 668 reg = <0x0 0x02c60000 0x0 0x90000>, 669 <0x0 0x01780000 0x0 0x80000>; 670 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&bpmp TEGRA234_CLK_EMC>; 672 clock-names = "emc"; 673 status = "okay"; 674 675 #interconnect-cells = <0>; 676 677 nvidia,bpmp = <&bpmp>; 678 }; 679 }; 680 681 uarta: serial@3100000 { 682 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 683 reg = <0x0 0x03100000 0x0 0x10000>; 684 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&bpmp TEGRA234_CLK_UARTA>; 686 resets = <&bpmp TEGRA234_RESET_UARTA>; 687 status = "disabled"; 688 }; 689 690 gen1_i2c: i2c@3160000 { 691 compatible = "nvidia,tegra194-i2c"; 692 reg = <0x0 0x3160000 0x0 0x100>; 693 status = "disabled"; 694 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 clock-frequency = <400000>; 698 clocks = <&bpmp TEGRA234_CLK_I2C1 699 &bpmp TEGRA234_CLK_PLLP_OUT0>; 700 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 701 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 702 clock-names = "div-clk", "parent"; 703 resets = <&bpmp TEGRA234_RESET_I2C1>; 704 reset-names = "i2c"; 705 dmas = <&gpcdma 21>, <&gpcdma 21>; 706 dma-names = "rx", "tx"; 707 }; 708 709 cam_i2c: i2c@3180000 { 710 compatible = "nvidia,tegra194-i2c"; 711 reg = <0x0 0x3180000 0x0 0x100>; 712 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 status = "disabled"; 716 clock-frequency = <400000>; 717 clocks = <&bpmp TEGRA234_CLK_I2C3 718 &bpmp TEGRA234_CLK_PLLP_OUT0>; 719 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 720 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 721 clock-names = "div-clk", "parent"; 722 resets = <&bpmp TEGRA234_RESET_I2C3>; 723 reset-names = "i2c"; 724 dmas = <&gpcdma 23>, <&gpcdma 23>; 725 dma-names = "rx", "tx"; 726 }; 727 728 dp_aux_ch1_i2c: i2c@3190000 { 729 compatible = "nvidia,tegra194-i2c"; 730 reg = <0x0 0x3190000 0x0 0x100>; 731 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 clock-frequency = <100000>; 736 clocks = <&bpmp TEGRA234_CLK_I2C4 737 &bpmp TEGRA234_CLK_PLLP_OUT0>; 738 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 739 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 740 clock-names = "div-clk", "parent"; 741 resets = <&bpmp TEGRA234_RESET_I2C4>; 742 reset-names = "i2c"; 743 dmas = <&gpcdma 26>, <&gpcdma 26>; 744 dma-names = "rx", "tx"; 745 }; 746 747 dp_aux_ch0_i2c: i2c@31b0000 { 748 compatible = "nvidia,tegra194-i2c"; 749 reg = <0x0 0x31b0000 0x0 0x100>; 750 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 status = "disabled"; 754 clock-frequency = <100000>; 755 clocks = <&bpmp TEGRA234_CLK_I2C6 756 &bpmp TEGRA234_CLK_PLLP_OUT0>; 757 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 758 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 759 clock-names = "div-clk", "parent"; 760 resets = <&bpmp TEGRA234_RESET_I2C6>; 761 reset-names = "i2c"; 762 dmas = <&gpcdma 30>, <&gpcdma 30>; 763 dma-names = "rx", "tx"; 764 }; 765 766 dp_aux_ch2_i2c: i2c@31c0000 { 767 compatible = "nvidia,tegra194-i2c"; 768 reg = <0x0 0x31c0000 0x0 0x100>; 769 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 status = "disabled"; 773 clock-frequency = <100000>; 774 clocks = <&bpmp TEGRA234_CLK_I2C7 775 &bpmp TEGRA234_CLK_PLLP_OUT0>; 776 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 777 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 778 clock-names = "div-clk", "parent"; 779 resets = <&bpmp TEGRA234_RESET_I2C7>; 780 reset-names = "i2c"; 781 dmas = <&gpcdma 27>, <&gpcdma 27>; 782 dma-names = "rx", "tx"; 783 }; 784 785 uarti: serial@31d0000 { 786 compatible = "arm,sbsa-uart"; 787 reg = <0x0 0x31d0000 0x0 0x10000>; 788 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 789 status = "disabled"; 790 }; 791 792 dp_aux_ch3_i2c: i2c@31e0000 { 793 compatible = "nvidia,tegra194-i2c"; 794 reg = <0x0 0x31e0000 0x0 0x100>; 795 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 status = "disabled"; 799 clock-frequency = <100000>; 800 clocks = <&bpmp TEGRA234_CLK_I2C9 801 &bpmp TEGRA234_CLK_PLLP_OUT0>; 802 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 803 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 804 clock-names = "div-clk", "parent"; 805 resets = <&bpmp TEGRA234_RESET_I2C9>; 806 reset-names = "i2c"; 807 dmas = <&gpcdma 31>, <&gpcdma 31>; 808 dma-names = "rx", "tx"; 809 }; 810 811 spi@3270000 { 812 compatible = "nvidia,tegra234-qspi"; 813 reg = <0x0 0x3270000 0x0 0x1000>; 814 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 818 <&bpmp TEGRA234_CLK_QSPI0_PM>; 819 clock-names = "qspi", "qspi_out"; 820 resets = <&bpmp TEGRA234_RESET_QSPI0>; 821 status = "disabled"; 822 }; 823 824 pwm1: pwm@3280000 { 825 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 826 reg = <0x0 0x3280000 0x0 0x10000>; 827 clocks = <&bpmp TEGRA234_CLK_PWM1>; 828 resets = <&bpmp TEGRA234_RESET_PWM1>; 829 reset-names = "pwm"; 830 status = "disabled"; 831 #pwm-cells = <2>; 832 }; 833 834 pwm2: pwm@3290000 { 835 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 836 reg = <0x0 0x3290000 0x0 0x10000>; 837 clocks = <&bpmp TEGRA234_CLK_PWM2>; 838 resets = <&bpmp TEGRA234_RESET_PWM2>; 839 reset-names = "pwm"; 840 status = "disabled"; 841 #pwm-cells = <2>; 842 }; 843 844 pwm3: pwm@32a0000 { 845 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 846 reg = <0x0 0x32a0000 0x0 0x10000>; 847 clocks = <&bpmp TEGRA234_CLK_PWM3>; 848 resets = <&bpmp TEGRA234_RESET_PWM3>; 849 reset-names = "pwm"; 850 status = "disabled"; 851 #pwm-cells = <2>; 852 }; 853 854 pwm5: pwm@32c0000 { 855 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 856 reg = <0x0 0x32c0000 0x0 0x10000>; 857 clocks = <&bpmp TEGRA234_CLK_PWM5>; 858 resets = <&bpmp TEGRA234_RESET_PWM5>; 859 reset-names = "pwm"; 860 status = "disabled"; 861 #pwm-cells = <2>; 862 }; 863 864 pwm6: pwm@32d0000 { 865 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 866 reg = <0x0 0x32d0000 0x0 0x10000>; 867 clocks = <&bpmp TEGRA234_CLK_PWM6>; 868 resets = <&bpmp TEGRA234_RESET_PWM6>; 869 reset-names = "pwm"; 870 status = "disabled"; 871 #pwm-cells = <2>; 872 }; 873 874 pwm7: pwm@32e0000 { 875 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 876 reg = <0x0 0x32e0000 0x0 0x10000>; 877 clocks = <&bpmp TEGRA234_CLK_PWM7>; 878 resets = <&bpmp TEGRA234_RESET_PWM7>; 879 reset-names = "pwm"; 880 status = "disabled"; 881 #pwm-cells = <2>; 882 }; 883 884 pwm8: pwm@32f0000 { 885 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 886 reg = <0x0 0x32f0000 0x0 0x10000>; 887 clocks = <&bpmp TEGRA234_CLK_PWM8>; 888 resets = <&bpmp TEGRA234_RESET_PWM8>; 889 reset-names = "pwm"; 890 status = "disabled"; 891 #pwm-cells = <2>; 892 }; 893 894 spi@3300000 { 895 compatible = "nvidia,tegra234-qspi"; 896 reg = <0x0 0x3300000 0x0 0x1000>; 897 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 901 <&bpmp TEGRA234_CLK_QSPI1_PM>; 902 clock-names = "qspi", "qspi_out"; 903 resets = <&bpmp TEGRA234_RESET_QSPI1>; 904 status = "disabled"; 905 }; 906 907 mmc@3400000 { 908 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 909 reg = <0x0 0x03400000 0x0 0x20000>; 910 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 912 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 913 clock-names = "sdhci", "tmclk"; 914 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 915 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 916 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 917 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 918 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 919 reset-names = "sdhci"; 920 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 921 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 922 interconnect-names = "dma-mem", "write"; 923 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 924 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 925 pinctrl-0 = <&sdmmc1_3v3>; 926 pinctrl-1 = <&sdmmc1_1v8>; 927 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 928 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 929 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 930 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 931 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 932 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 933 nvidia,default-tap = <14>; 934 nvidia,default-trim = <0x8>; 935 sd-uhs-sdr25; 936 sd-uhs-sdr50; 937 sd-uhs-ddr50; 938 sd-uhs-sdr104; 939 status = "disabled"; 940 }; 941 942 mmc@3460000 { 943 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 944 reg = <0x0 0x03460000 0x0 0x20000>; 945 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 947 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 948 clock-names = "sdhci", "tmclk"; 949 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 950 <&bpmp TEGRA234_CLK_PLLC4>; 951 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 952 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 953 reset-names = "sdhci"; 954 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 955 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 956 interconnect-names = "dma-mem", "write"; 957 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 958 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 959 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 960 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 961 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 962 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 963 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 964 nvidia,default-tap = <0x8>; 965 nvidia,default-trim = <0x14>; 966 nvidia,dqs-trim = <40>; 967 supports-cqe; 968 status = "disabled"; 969 }; 970 971 hda@3510000 { 972 compatible = "nvidia,tegra234-hda"; 973 reg = <0x0 0x3510000 0x0 0x10000>; 974 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 976 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 977 clock-names = "hda", "hda2codec_2x"; 978 resets = <&bpmp TEGRA234_RESET_HDA>, 979 <&bpmp TEGRA234_RESET_HDACODEC>; 980 reset-names = "hda", "hda2codec_2x"; 981 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 982 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 983 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 984 interconnect-names = "dma-mem", "write"; 985 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 986 status = "disabled"; 987 }; 988 989 xusb_padctl: padctl@3520000 { 990 compatible = "nvidia,tegra234-xusb-padctl"; 991 reg = <0x0 0x03520000 0x0 0x20000>, 992 <0x0 0x03540000 0x0 0x10000>; 993 reg-names = "padctl", "ao"; 994 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 995 996 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 997 reset-names = "padctl"; 998 999 status = "disabled"; 1000 1001 pads { 1002 usb2 { 1003 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 1004 clock-names = "trk"; 1005 1006 lanes { 1007 usb2-0 { 1008 nvidia,function = "xusb"; 1009 status = "disabled"; 1010 #phy-cells = <0>; 1011 }; 1012 1013 usb2-1 { 1014 nvidia,function = "xusb"; 1015 status = "disabled"; 1016 #phy-cells = <0>; 1017 }; 1018 1019 usb2-2 { 1020 nvidia,function = "xusb"; 1021 status = "disabled"; 1022 #phy-cells = <0>; 1023 }; 1024 1025 usb2-3 { 1026 nvidia,function = "xusb"; 1027 status = "disabled"; 1028 #phy-cells = <0>; 1029 }; 1030 }; 1031 }; 1032 1033 usb3 { 1034 lanes { 1035 usb3-0 { 1036 nvidia,function = "xusb"; 1037 status = "disabled"; 1038 #phy-cells = <0>; 1039 }; 1040 1041 usb3-1 { 1042 nvidia,function = "xusb"; 1043 status = "disabled"; 1044 #phy-cells = <0>; 1045 }; 1046 1047 usb3-2 { 1048 nvidia,function = "xusb"; 1049 status = "disabled"; 1050 #phy-cells = <0>; 1051 }; 1052 1053 usb3-3 { 1054 nvidia,function = "xusb"; 1055 status = "disabled"; 1056 #phy-cells = <0>; 1057 }; 1058 }; 1059 }; 1060 }; 1061 1062 ports { 1063 usb2-0 { 1064 status = "disabled"; 1065 }; 1066 1067 usb2-1 { 1068 status = "disabled"; 1069 }; 1070 1071 usb2-2 { 1072 status = "disabled"; 1073 }; 1074 1075 usb2-3 { 1076 status = "disabled"; 1077 }; 1078 1079 usb3-0 { 1080 status = "disabled"; 1081 }; 1082 1083 usb3-1 { 1084 status = "disabled"; 1085 }; 1086 1087 usb3-2 { 1088 status = "disabled"; 1089 }; 1090 1091 usb3-3 { 1092 status = "disabled"; 1093 }; 1094 }; 1095 }; 1096 1097 usb@3550000 { 1098 compatible = "nvidia,tegra234-xudc"; 1099 reg = <0x0 0x03550000 0x0 0x8000>, 1100 <0x0 0x03558000 0x0 0x8000>; 1101 reg-names = "base", "fpci"; 1102 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1104 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1105 <&bpmp TEGRA234_CLK_XUSB_SS>, 1106 <&bpmp TEGRA234_CLK_XUSB_FS>; 1107 clock-names = "dev", "ss", "ss_src", "fs_src"; 1108 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1109 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1110 interconnect-names = "dma-mem", "write"; 1111 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1112 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1113 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1114 power-domain-names = "dev", "ss"; 1115 nvidia,xusb-padctl = <&xusb_padctl>; 1116 dma-coherent; 1117 status = "disabled"; 1118 }; 1119 1120 usb@3610000 { 1121 compatible = "nvidia,tegra234-xusb"; 1122 reg = <0x0 0x03610000 0x0 0x40000>, 1123 <0x0 0x03600000 0x0 0x10000>, 1124 <0x0 0x03650000 0x0 0x10000>; 1125 reg-names = "hcd", "fpci", "bar2"; 1126 1127 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1129 1130 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1131 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1132 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1133 <&bpmp TEGRA234_CLK_XUSB_SS>, 1134 <&bpmp TEGRA234_CLK_CLK_M>, 1135 <&bpmp TEGRA234_CLK_XUSB_FS>, 1136 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1137 <&bpmp TEGRA234_CLK_CLK_M>, 1138 <&bpmp TEGRA234_CLK_PLLE>; 1139 clock-names = "xusb_host", "xusb_falcon_src", 1140 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1141 "xusb_fs_src", "pll_u_480m", "clk_m", 1142 "pll_e"; 1143 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1144 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1145 interconnect-names = "dma-mem", "write"; 1146 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1147 1148 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1149 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1150 power-domain-names = "xusb_host", "xusb_ss"; 1151 1152 nvidia,xusb-padctl = <&xusb_padctl>; 1153 dma-coherent; 1154 status = "disabled"; 1155 }; 1156 1157 fuse@3810000 { 1158 compatible = "nvidia,tegra234-efuse"; 1159 reg = <0x0 0x03810000 0x0 0x10000>; 1160 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1161 clock-names = "fuse"; 1162 }; 1163 1164 hte_lic: hardware-timestamp@3aa0000 { 1165 compatible = "nvidia,tegra234-gte-lic"; 1166 reg = <0x0 0x3aa0000 0x0 0x10000>; 1167 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1168 nvidia,int-threshold = <1>; 1169 #timestamp-cells = <1>; 1170 }; 1171 1172 hsp_top0: hsp@3c00000 { 1173 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1174 reg = <0x0 0x03c00000 0x0 0xa0000>; 1175 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1184 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1185 "shared3", "shared4", "shared5", "shared6", 1186 "shared7"; 1187 #mbox-cells = <2>; 1188 }; 1189 1190 p2u_hsio_0: phy@3e00000 { 1191 compatible = "nvidia,tegra234-p2u"; 1192 reg = <0x0 0x03e00000 0x0 0x10000>; 1193 reg-names = "ctl"; 1194 1195 #phy-cells = <0>; 1196 }; 1197 1198 p2u_hsio_1: phy@3e10000 { 1199 compatible = "nvidia,tegra234-p2u"; 1200 reg = <0x0 0x03e10000 0x0 0x10000>; 1201 reg-names = "ctl"; 1202 1203 #phy-cells = <0>; 1204 }; 1205 1206 p2u_hsio_2: phy@3e20000 { 1207 compatible = "nvidia,tegra234-p2u"; 1208 reg = <0x0 0x03e20000 0x0 0x10000>; 1209 reg-names = "ctl"; 1210 1211 #phy-cells = <0>; 1212 }; 1213 1214 p2u_hsio_3: phy@3e30000 { 1215 compatible = "nvidia,tegra234-p2u"; 1216 reg = <0x0 0x03e30000 0x0 0x10000>; 1217 reg-names = "ctl"; 1218 1219 #phy-cells = <0>; 1220 }; 1221 1222 p2u_hsio_4: phy@3e40000 { 1223 compatible = "nvidia,tegra234-p2u"; 1224 reg = <0x0 0x03e40000 0x0 0x10000>; 1225 reg-names = "ctl"; 1226 1227 #phy-cells = <0>; 1228 }; 1229 1230 p2u_hsio_5: phy@3e50000 { 1231 compatible = "nvidia,tegra234-p2u"; 1232 reg = <0x0 0x03e50000 0x0 0x10000>; 1233 reg-names = "ctl"; 1234 1235 #phy-cells = <0>; 1236 }; 1237 1238 p2u_hsio_6: phy@3e60000 { 1239 compatible = "nvidia,tegra234-p2u"; 1240 reg = <0x0 0x03e60000 0x0 0x10000>; 1241 reg-names = "ctl"; 1242 1243 #phy-cells = <0>; 1244 }; 1245 1246 p2u_hsio_7: phy@3e70000 { 1247 compatible = "nvidia,tegra234-p2u"; 1248 reg = <0x0 0x03e70000 0x0 0x10000>; 1249 reg-names = "ctl"; 1250 1251 #phy-cells = <0>; 1252 }; 1253 1254 p2u_nvhs_0: phy@3e90000 { 1255 compatible = "nvidia,tegra234-p2u"; 1256 reg = <0x0 0x03e90000 0x0 0x10000>; 1257 reg-names = "ctl"; 1258 1259 #phy-cells = <0>; 1260 }; 1261 1262 p2u_nvhs_1: phy@3ea0000 { 1263 compatible = "nvidia,tegra234-p2u"; 1264 reg = <0x0 0x03ea0000 0x0 0x10000>; 1265 reg-names = "ctl"; 1266 1267 #phy-cells = <0>; 1268 }; 1269 1270 p2u_nvhs_2: phy@3eb0000 { 1271 compatible = "nvidia,tegra234-p2u"; 1272 reg = <0x0 0x03eb0000 0x0 0x10000>; 1273 reg-names = "ctl"; 1274 1275 #phy-cells = <0>; 1276 }; 1277 1278 p2u_nvhs_3: phy@3ec0000 { 1279 compatible = "nvidia,tegra234-p2u"; 1280 reg = <0x0 0x03ec0000 0x0 0x10000>; 1281 reg-names = "ctl"; 1282 1283 #phy-cells = <0>; 1284 }; 1285 1286 p2u_nvhs_4: phy@3ed0000 { 1287 compatible = "nvidia,tegra234-p2u"; 1288 reg = <0x0 0x03ed0000 0x0 0x10000>; 1289 reg-names = "ctl"; 1290 1291 #phy-cells = <0>; 1292 }; 1293 1294 p2u_nvhs_5: phy@3ee0000 { 1295 compatible = "nvidia,tegra234-p2u"; 1296 reg = <0x0 0x03ee0000 0x0 0x10000>; 1297 reg-names = "ctl"; 1298 1299 #phy-cells = <0>; 1300 }; 1301 1302 p2u_nvhs_6: phy@3ef0000 { 1303 compatible = "nvidia,tegra234-p2u"; 1304 reg = <0x0 0x03ef0000 0x0 0x10000>; 1305 reg-names = "ctl"; 1306 1307 #phy-cells = <0>; 1308 }; 1309 1310 p2u_nvhs_7: phy@3f00000 { 1311 compatible = "nvidia,tegra234-p2u"; 1312 reg = <0x0 0x03f00000 0x0 0x10000>; 1313 reg-names = "ctl"; 1314 1315 #phy-cells = <0>; 1316 }; 1317 1318 p2u_gbe_0: phy@3f20000 { 1319 compatible = "nvidia,tegra234-p2u"; 1320 reg = <0x0 0x03f20000 0x0 0x10000>; 1321 reg-names = "ctl"; 1322 1323 #phy-cells = <0>; 1324 }; 1325 1326 p2u_gbe_1: phy@3f30000 { 1327 compatible = "nvidia,tegra234-p2u"; 1328 reg = <0x0 0x03f30000 0x0 0x10000>; 1329 reg-names = "ctl"; 1330 1331 #phy-cells = <0>; 1332 }; 1333 1334 p2u_gbe_2: phy@3f40000 { 1335 compatible = "nvidia,tegra234-p2u"; 1336 reg = <0x0 0x03f40000 0x0 0x10000>; 1337 reg-names = "ctl"; 1338 1339 #phy-cells = <0>; 1340 }; 1341 1342 p2u_gbe_3: phy@3f50000 { 1343 compatible = "nvidia,tegra234-p2u"; 1344 reg = <0x0 0x03f50000 0x0 0x10000>; 1345 reg-names = "ctl"; 1346 1347 #phy-cells = <0>; 1348 }; 1349 1350 p2u_gbe_4: phy@3f60000 { 1351 compatible = "nvidia,tegra234-p2u"; 1352 reg = <0x0 0x03f60000 0x0 0x10000>; 1353 reg-names = "ctl"; 1354 1355 #phy-cells = <0>; 1356 }; 1357 1358 p2u_gbe_5: phy@3f70000 { 1359 compatible = "nvidia,tegra234-p2u"; 1360 reg = <0x0 0x03f70000 0x0 0x10000>; 1361 reg-names = "ctl"; 1362 1363 #phy-cells = <0>; 1364 }; 1365 1366 p2u_gbe_6: phy@3f80000 { 1367 compatible = "nvidia,tegra234-p2u"; 1368 reg = <0x0 0x03f80000 0x0 0x10000>; 1369 reg-names = "ctl"; 1370 1371 #phy-cells = <0>; 1372 }; 1373 1374 p2u_gbe_7: phy@3f90000 { 1375 compatible = "nvidia,tegra234-p2u"; 1376 reg = <0x0 0x03f90000 0x0 0x10000>; 1377 reg-names = "ctl"; 1378 1379 #phy-cells = <0>; 1380 }; 1381 1382 ethernet@6800000 { 1383 compatible = "nvidia,tegra234-mgbe"; 1384 reg = <0x0 0x06800000 0x0 0x10000>, 1385 <0x0 0x06810000 0x0 0x10000>, 1386 <0x0 0x068a0000 0x0 0x10000>; 1387 reg-names = "hypervisor", "mac", "xpcs"; 1388 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1389 interrupt-names = "common"; 1390 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1391 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1392 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1393 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1394 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1395 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1396 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1397 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1398 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1399 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1400 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1401 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1402 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1403 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1404 "rx-pcs", "tx-pcs"; 1405 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1406 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1407 reset-names = "mac", "pcs"; 1408 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1409 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1410 interconnect-names = "dma-mem", "write"; 1411 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1412 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1413 status = "disabled"; 1414 }; 1415 1416 ethernet@6900000 { 1417 compatible = "nvidia,tegra234-mgbe"; 1418 reg = <0x0 0x06900000 0x0 0x10000>, 1419 <0x0 0x06910000 0x0 0x10000>, 1420 <0x0 0x069a0000 0x0 0x10000>; 1421 reg-names = "hypervisor", "mac", "xpcs"; 1422 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1423 interrupt-names = "common"; 1424 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1425 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1426 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1427 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1428 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1429 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1430 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1431 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1432 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1433 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1434 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1435 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1436 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1437 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1438 "rx-pcs", "tx-pcs"; 1439 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1440 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1441 reset-names = "mac", "pcs"; 1442 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1443 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1444 interconnect-names = "dma-mem", "write"; 1445 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1446 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1447 status = "disabled"; 1448 }; 1449 1450 ethernet@6a00000 { 1451 compatible = "nvidia,tegra234-mgbe"; 1452 reg = <0x0 0x06a00000 0x0 0x10000>, 1453 <0x0 0x06a10000 0x0 0x10000>, 1454 <0x0 0x06aa0000 0x0 0x10000>; 1455 reg-names = "hypervisor", "mac", "xpcs"; 1456 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1457 interrupt-names = "common"; 1458 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1459 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1460 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1461 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1462 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1463 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1464 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1465 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1466 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1467 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1468 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1469 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1470 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1471 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1472 "rx-pcs", "tx-pcs"; 1473 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1474 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1475 reset-names = "mac", "pcs"; 1476 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1477 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1478 interconnect-names = "dma-mem", "write"; 1479 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1480 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1481 status = "disabled"; 1482 }; 1483 1484 ethernet@6b00000 { 1485 compatible = "nvidia,tegra234-mgbe"; 1486 reg = <0x0 0x06b00000 0x0 0x10000>, 1487 <0x0 0x06b10000 0x0 0x10000>, 1488 <0x0 0x06ba0000 0x0 0x10000>; 1489 reg-names = "hypervisor", "mac", "xpcs"; 1490 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1491 interrupt-names = "common"; 1492 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1493 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1494 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1495 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1496 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1497 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1498 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1499 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1500 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1501 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1502 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1503 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1504 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1505 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1506 "rx-pcs", "tx-pcs"; 1507 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1508 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1509 reset-names = "mac", "pcs"; 1510 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1511 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1512 interconnect-names = "dma-mem", "write"; 1513 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1514 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1515 status = "disabled"; 1516 }; 1517 1518 smmu_niso1: iommu@8000000 { 1519 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1520 reg = <0x0 0x8000000 0x0 0x1000000>, 1521 <0x0 0x7000000 0x0 0x1000000>; 1522 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1652 stream-match-mask = <0x7f80>; 1653 #global-interrupts = <2>; 1654 #iommu-cells = <1>; 1655 1656 nvidia,memory-controller = <&mc>; 1657 status = "okay"; 1658 }; 1659 1660 sce-fabric@b600000 { 1661 compatible = "nvidia,tegra234-sce-fabric"; 1662 reg = <0x0 0xb600000 0x0 0x40000>; 1663 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1664 status = "okay"; 1665 }; 1666 1667 rce-fabric@be00000 { 1668 compatible = "nvidia,tegra234-rce-fabric"; 1669 reg = <0x0 0xbe00000 0x0 0x40000>; 1670 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1671 status = "okay"; 1672 }; 1673 1674 hsp_aon: hsp@c150000 { 1675 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1676 reg = <0x0 0x0c150000 0x0 0x90000>; 1677 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1681 /* 1682 * Shared interrupt 0 is routed only to AON/SPE, so 1683 * we only have 4 shared interrupts for the CCPLEX. 1684 */ 1685 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1686 #mbox-cells = <2>; 1687 }; 1688 1689 hte_aon: hardware-timestamp@c1e0000 { 1690 compatible = "nvidia,tegra234-gte-aon"; 1691 reg = <0x0 0xc1e0000 0x0 0x10000>; 1692 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1693 nvidia,int-threshold = <1>; 1694 nvidia,gpio-controller = <&gpio_aon>; 1695 #timestamp-cells = <1>; 1696 }; 1697 1698 gen2_i2c: i2c@c240000 { 1699 compatible = "nvidia,tegra194-i2c"; 1700 reg = <0x0 0xc240000 0x0 0x100>; 1701 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 status = "disabled"; 1705 clock-frequency = <100000>; 1706 clocks = <&bpmp TEGRA234_CLK_I2C2 1707 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1708 clock-names = "div-clk", "parent"; 1709 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1710 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1711 resets = <&bpmp TEGRA234_RESET_I2C2>; 1712 reset-names = "i2c"; 1713 dmas = <&gpcdma 22>, <&gpcdma 22>; 1714 dma-names = "rx", "tx"; 1715 }; 1716 1717 gen8_i2c: i2c@c250000 { 1718 compatible = "nvidia,tegra194-i2c"; 1719 reg = <0x0 0xc250000 0x0 0x100>; 1720 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 status = "disabled"; 1724 clock-frequency = <400000>; 1725 clocks = <&bpmp TEGRA234_CLK_I2C8 1726 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1727 clock-names = "div-clk", "parent"; 1728 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1729 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1730 resets = <&bpmp TEGRA234_RESET_I2C8>; 1731 reset-names = "i2c"; 1732 dmas = <&gpcdma 0>, <&gpcdma 0>; 1733 dma-names = "rx", "tx"; 1734 }; 1735 1736 rtc@c2a0000 { 1737 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1738 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1739 interrupt-parent = <&pmc>; 1740 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1741 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1742 clock-names = "rtc"; 1743 status = "disabled"; 1744 }; 1745 1746 gpio_aon: gpio@c2f0000 { 1747 compatible = "nvidia,tegra234-gpio-aon"; 1748 reg-names = "security", "gpio"; 1749 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1750 <0x0 0x0c2f1000 0x0 0x1000>; 1751 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1755 #interrupt-cells = <2>; 1756 interrupt-controller; 1757 #gpio-cells = <2>; 1758 gpio-controller; 1759 gpio-ranges = <&pinmux_aon 0 0 32>; 1760 }; 1761 1762 pinmux_aon: pinmux@c300000 { 1763 compatible = "nvidia,tegra234-pinmux-aon"; 1764 reg = <0x0 0xc300000 0x0 0x4000>; 1765 }; 1766 1767 pwm4: pwm@c340000 { 1768 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1769 reg = <0x0 0xc340000 0x0 0x10000>; 1770 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1771 resets = <&bpmp TEGRA234_RESET_PWM4>; 1772 reset-names = "pwm"; 1773 status = "disabled"; 1774 #pwm-cells = <2>; 1775 }; 1776 1777 pmc: pmc@c360000 { 1778 compatible = "nvidia,tegra234-pmc"; 1779 reg = <0x0 0x0c360000 0x0 0x10000>, 1780 <0x0 0x0c370000 0x0 0x10000>, 1781 <0x0 0x0c380000 0x0 0x10000>, 1782 <0x0 0x0c390000 0x0 0x10000>, 1783 <0x0 0x0c3a0000 0x0 0x10000>; 1784 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1785 1786 #interrupt-cells = <2>; 1787 interrupt-controller; 1788 1789 sdmmc1_1v8: sdmmc1-1v8 { 1790 pins = "sdmmc1-hv"; 1791 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1792 }; 1793 1794 sdmmc1_3v3: sdmmc1-3v3 { 1795 pins = "sdmmc1-hv"; 1796 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1797 }; 1798 1799 sdmmc3_1v8: sdmmc3-1v8 { 1800 pins = "sdmmc3-hv"; 1801 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1802 }; 1803 1804 sdmmc3_3v3: sdmmc3-3v3 { 1805 pins = "sdmmc3-hv"; 1806 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1807 }; 1808 }; 1809 1810 aon-fabric@c600000 { 1811 compatible = "nvidia,tegra234-aon-fabric"; 1812 reg = <0x0 0xc600000 0x0 0x40000>; 1813 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1814 status = "okay"; 1815 }; 1816 1817 bpmp-fabric@d600000 { 1818 compatible = "nvidia,tegra234-bpmp-fabric"; 1819 reg = <0x0 0xd600000 0x0 0x40000>; 1820 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1821 status = "okay"; 1822 }; 1823 1824 dce-fabric@de00000 { 1825 compatible = "nvidia,tegra234-sce-fabric"; 1826 reg = <0x0 0xde00000 0x0 0x40000>; 1827 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1828 status = "okay"; 1829 }; 1830 1831 ccplex@e000000 { 1832 compatible = "nvidia,tegra234-ccplex-cluster"; 1833 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1834 nvidia,bpmp = <&bpmp>; 1835 status = "okay"; 1836 }; 1837 1838 gic: interrupt-controller@f400000 { 1839 compatible = "arm,gic-v3"; 1840 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1841 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1842 interrupt-parent = <&gic>; 1843 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1844 1845 #redistributor-regions = <1>; 1846 #interrupt-cells = <3>; 1847 interrupt-controller; 1848 }; 1849 1850 smmu_iso: iommu@10000000 { 1851 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1852 reg = <0x0 0x10000000 0x0 0x1000000>; 1853 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1982 stream-match-mask = <0x7f80>; 1983 #global-interrupts = <1>; 1984 #iommu-cells = <1>; 1985 1986 nvidia,memory-controller = <&mc>; 1987 status = "okay"; 1988 }; 1989 1990 smmu_niso0: iommu@12000000 { 1991 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1992 reg = <0x0 0x12000000 0x0 0x1000000>, 1993 <0x0 0x11000000 0x0 0x1000000>; 1994 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2124 stream-match-mask = <0x7f80>; 2125 #global-interrupts = <2>; 2126 #iommu-cells = <1>; 2127 2128 nvidia,memory-controller = <&mc>; 2129 status = "okay"; 2130 }; 2131 2132 cbb-fabric@13a00000 { 2133 compatible = "nvidia,tegra234-cbb-fabric"; 2134 reg = <0x0 0x13a00000 0x0 0x400000>; 2135 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2136 status = "okay"; 2137 }; 2138 2139 host1x@13e00000 { 2140 compatible = "nvidia,tegra234-host1x"; 2141 reg = <0x0 0x13e00000 0x0 0x10000>, 2142 <0x0 0x13e10000 0x0 0x10000>, 2143 <0x0 0x13e40000 0x0 0x10000>; 2144 reg-names = "common", "hypervisor", "vm"; 2145 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2154 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2155 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2156 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2157 clock-names = "host1x"; 2158 2159 #address-cells = <2>; 2160 #size-cells = <2>; 2161 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2162 2163 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2164 interconnect-names = "dma-mem"; 2165 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2166 dma-coherent; 2167 2168 /* Context isolation domains */ 2169 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2170 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2171 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2172 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2173 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2174 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2175 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2176 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2177 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2178 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2179 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2180 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2181 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2182 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2183 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2184 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2185 2186 vic@15340000 { 2187 compatible = "nvidia,tegra234-vic"; 2188 reg = <0x0 0x15340000 0x0 0x00040000>; 2189 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2190 clocks = <&bpmp TEGRA234_CLK_VIC>; 2191 clock-names = "vic"; 2192 resets = <&bpmp TEGRA234_RESET_VIC>; 2193 reset-names = "vic"; 2194 2195 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2196 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2197 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2198 interconnect-names = "dma-mem", "write"; 2199 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2200 dma-coherent; 2201 }; 2202 2203 nvdec@15480000 { 2204 compatible = "nvidia,tegra234-nvdec"; 2205 reg = <0x0 0x15480000 0x0 0x00040000>; 2206 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2207 <&bpmp TEGRA234_CLK_FUSE>, 2208 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2209 clock-names = "nvdec", "fuse", "tsec_pka"; 2210 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2211 reset-names = "nvdec"; 2212 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2213 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2214 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2215 interconnect-names = "dma-mem", "write"; 2216 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2217 dma-coherent; 2218 2219 nvidia,memory-controller = <&mc>; 2220 2221 /* 2222 * Placeholder values that firmware needs to update with the real 2223 * offsets parsed from the microcode headers. 2224 */ 2225 nvidia,bl-manifest-offset = <0>; 2226 nvidia,bl-data-offset = <0>; 2227 nvidia,bl-code-offset = <0>; 2228 nvidia,os-manifest-offset = <0>; 2229 nvidia,os-data-offset = <0>; 2230 nvidia,os-code-offset = <0>; 2231 2232 /* 2233 * Firmware needs to set this to "okay" once the above values have 2234 * been updated. 2235 */ 2236 status = "disabled"; 2237 }; 2238 }; 2239 2240 pcie@140a0000 { 2241 compatible = "nvidia,tegra234-pcie"; 2242 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2243 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2244 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2245 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2246 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2247 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2248 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2249 2250 #address-cells = <3>; 2251 #size-cells = <2>; 2252 device_type = "pci"; 2253 num-lanes = <4>; 2254 num-viewport = <8>; 2255 linux,pci-domain = <8>; 2256 2257 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2258 clock-names = "core"; 2259 2260 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2261 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2262 reset-names = "apb", "core"; 2263 2264 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2265 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2266 interrupt-names = "intr", "msi"; 2267 2268 #interrupt-cells = <1>; 2269 interrupt-map-mask = <0 0 0 0>; 2270 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2271 2272 nvidia,bpmp = <&bpmp 8>; 2273 2274 nvidia,aspm-cmrt-us = <60>; 2275 nvidia,aspm-pwr-on-t-us = <20>; 2276 nvidia,aspm-l0s-entrance-latency-us = <3>; 2277 2278 bus-range = <0x0 0xff>; 2279 2280 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2281 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2282 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2283 2284 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2285 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2286 interconnect-names = "dma-mem", "write"; 2287 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2288 iommu-map-mask = <0x0>; 2289 dma-coherent; 2290 2291 status = "disabled"; 2292 }; 2293 2294 pcie@140c0000 { 2295 compatible = "nvidia,tegra234-pcie"; 2296 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2297 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2298 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2299 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2300 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2301 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2302 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2303 2304 #address-cells = <3>; 2305 #size-cells = <2>; 2306 device_type = "pci"; 2307 num-lanes = <4>; 2308 num-viewport = <8>; 2309 linux,pci-domain = <9>; 2310 2311 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2312 clock-names = "core"; 2313 2314 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2315 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2316 reset-names = "apb", "core"; 2317 2318 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2319 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2320 interrupt-names = "intr", "msi"; 2321 2322 #interrupt-cells = <1>; 2323 interrupt-map-mask = <0 0 0 0>; 2324 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2325 2326 nvidia,bpmp = <&bpmp 9>; 2327 2328 nvidia,aspm-cmrt-us = <60>; 2329 nvidia,aspm-pwr-on-t-us = <20>; 2330 nvidia,aspm-l0s-entrance-latency-us = <3>; 2331 2332 bus-range = <0x0 0xff>; 2333 2334 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2335 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2336 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2337 2338 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2339 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2340 interconnect-names = "dma-mem", "write"; 2341 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2342 iommu-map-mask = <0x0>; 2343 dma-coherent; 2344 2345 status = "disabled"; 2346 }; 2347 2348 pcie@140e0000 { 2349 compatible = "nvidia,tegra234-pcie"; 2350 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2351 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2352 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2353 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2354 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2355 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2356 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2357 2358 #address-cells = <3>; 2359 #size-cells = <2>; 2360 device_type = "pci"; 2361 num-lanes = <4>; 2362 num-viewport = <8>; 2363 linux,pci-domain = <10>; 2364 2365 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2366 clock-names = "core"; 2367 2368 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2369 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2370 reset-names = "apb", "core"; 2371 2372 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2373 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2374 interrupt-names = "intr", "msi"; 2375 2376 #interrupt-cells = <1>; 2377 interrupt-map-mask = <0 0 0 0>; 2378 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2379 2380 nvidia,bpmp = <&bpmp 10>; 2381 2382 nvidia,aspm-cmrt-us = <60>; 2383 nvidia,aspm-pwr-on-t-us = <20>; 2384 nvidia,aspm-l0s-entrance-latency-us = <3>; 2385 2386 bus-range = <0x0 0xff>; 2387 2388 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2389 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2390 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2391 2392 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2393 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2394 interconnect-names = "dma-mem", "write"; 2395 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2396 iommu-map-mask = <0x0>; 2397 dma-coherent; 2398 2399 status = "disabled"; 2400 }; 2401 2402 pcie-ep@140e0000 { 2403 compatible = "nvidia,tegra234-pcie-ep"; 2404 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2405 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2406 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2407 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2408 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2409 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2410 2411 num-lanes = <4>; 2412 2413 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2414 clock-names = "core"; 2415 2416 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2417 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2418 reset-names = "apb", "core"; 2419 2420 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2421 interrupt-names = "intr"; 2422 2423 nvidia,bpmp = <&bpmp 10>; 2424 2425 nvidia,enable-ext-refclk; 2426 nvidia,aspm-cmrt-us = <60>; 2427 nvidia,aspm-pwr-on-t-us = <20>; 2428 nvidia,aspm-l0s-entrance-latency-us = <3>; 2429 2430 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2431 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2432 interconnect-names = "dma-mem", "write"; 2433 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2434 iommu-map-mask = <0x0>; 2435 dma-coherent; 2436 2437 status = "disabled"; 2438 }; 2439 2440 pcie@14100000 { 2441 compatible = "nvidia,tegra234-pcie"; 2442 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2443 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2444 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2445 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2446 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2447 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2448 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2449 2450 #address-cells = <3>; 2451 #size-cells = <2>; 2452 device_type = "pci"; 2453 num-lanes = <1>; 2454 num-viewport = <8>; 2455 linux,pci-domain = <1>; 2456 2457 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2458 clock-names = "core"; 2459 2460 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2461 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2462 reset-names = "apb", "core"; 2463 2464 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2465 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2466 interrupt-names = "intr", "msi"; 2467 2468 #interrupt-cells = <1>; 2469 interrupt-map-mask = <0 0 0 0>; 2470 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2471 2472 nvidia,bpmp = <&bpmp 1>; 2473 2474 nvidia,aspm-cmrt-us = <60>; 2475 nvidia,aspm-pwr-on-t-us = <20>; 2476 nvidia,aspm-l0s-entrance-latency-us = <3>; 2477 2478 bus-range = <0x0 0xff>; 2479 2480 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2481 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2482 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2483 2484 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2485 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2486 interconnect-names = "dma-mem", "write"; 2487 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2488 iommu-map-mask = <0x0>; 2489 dma-coherent; 2490 2491 status = "disabled"; 2492 }; 2493 2494 pcie@14120000 { 2495 compatible = "nvidia,tegra234-pcie"; 2496 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2497 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2498 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2499 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2500 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2501 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2502 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2503 2504 #address-cells = <3>; 2505 #size-cells = <2>; 2506 device_type = "pci"; 2507 num-lanes = <1>; 2508 num-viewport = <8>; 2509 linux,pci-domain = <2>; 2510 2511 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2512 clock-names = "core"; 2513 2514 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2515 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2516 reset-names = "apb", "core"; 2517 2518 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2519 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2520 interrupt-names = "intr", "msi"; 2521 2522 #interrupt-cells = <1>; 2523 interrupt-map-mask = <0 0 0 0>; 2524 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2525 2526 nvidia,bpmp = <&bpmp 2>; 2527 2528 nvidia,aspm-cmrt-us = <60>; 2529 nvidia,aspm-pwr-on-t-us = <20>; 2530 nvidia,aspm-l0s-entrance-latency-us = <3>; 2531 2532 bus-range = <0x0 0xff>; 2533 2534 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2535 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2536 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2537 2538 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2539 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2540 interconnect-names = "dma-mem", "write"; 2541 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2542 iommu-map-mask = <0x0>; 2543 dma-coherent; 2544 2545 status = "disabled"; 2546 }; 2547 2548 pcie@14140000 { 2549 compatible = "nvidia,tegra234-pcie"; 2550 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2551 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2552 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2553 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2554 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2555 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2556 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2557 2558 #address-cells = <3>; 2559 #size-cells = <2>; 2560 device_type = "pci"; 2561 num-lanes = <1>; 2562 num-viewport = <8>; 2563 linux,pci-domain = <3>; 2564 2565 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2566 clock-names = "core"; 2567 2568 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2569 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2570 reset-names = "apb", "core"; 2571 2572 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2573 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2574 interrupt-names = "intr", "msi"; 2575 2576 #interrupt-cells = <1>; 2577 interrupt-map-mask = <0 0 0 0>; 2578 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2579 2580 nvidia,bpmp = <&bpmp 3>; 2581 2582 nvidia,aspm-cmrt-us = <60>; 2583 nvidia,aspm-pwr-on-t-us = <20>; 2584 nvidia,aspm-l0s-entrance-latency-us = <3>; 2585 2586 bus-range = <0x0 0xff>; 2587 2588 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2589 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2590 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2591 2592 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2593 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2594 interconnect-names = "dma-mem", "write"; 2595 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2596 iommu-map-mask = <0x0>; 2597 dma-coherent; 2598 2599 status = "disabled"; 2600 }; 2601 2602 pcie@14160000 { 2603 compatible = "nvidia,tegra234-pcie"; 2604 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2605 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2606 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2607 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2608 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2609 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2610 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2611 2612 #address-cells = <3>; 2613 #size-cells = <2>; 2614 device_type = "pci"; 2615 num-lanes = <4>; 2616 num-viewport = <8>; 2617 linux,pci-domain = <4>; 2618 2619 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2620 clock-names = "core"; 2621 2622 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2623 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2624 reset-names = "apb", "core"; 2625 2626 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2627 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2628 interrupt-names = "intr", "msi"; 2629 2630 #interrupt-cells = <1>; 2631 interrupt-map-mask = <0 0 0 0>; 2632 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2633 2634 nvidia,bpmp = <&bpmp 4>; 2635 2636 nvidia,aspm-cmrt-us = <60>; 2637 nvidia,aspm-pwr-on-t-us = <20>; 2638 nvidia,aspm-l0s-entrance-latency-us = <3>; 2639 2640 bus-range = <0x0 0xff>; 2641 2642 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2643 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2644 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2645 2646 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2647 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2648 interconnect-names = "dma-mem", "write"; 2649 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2650 iommu-map-mask = <0x0>; 2651 dma-coherent; 2652 2653 status = "disabled"; 2654 }; 2655 2656 pcie@14180000 { 2657 compatible = "nvidia,tegra234-pcie"; 2658 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2659 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2660 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2661 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2662 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2663 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2664 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2665 2666 #address-cells = <3>; 2667 #size-cells = <2>; 2668 device_type = "pci"; 2669 num-lanes = <4>; 2670 num-viewport = <8>; 2671 linux,pci-domain = <0>; 2672 2673 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2674 clock-names = "core"; 2675 2676 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2677 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2678 reset-names = "apb", "core"; 2679 2680 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2681 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2682 interrupt-names = "intr", "msi"; 2683 2684 #interrupt-cells = <1>; 2685 interrupt-map-mask = <0 0 0 0>; 2686 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2687 2688 nvidia,bpmp = <&bpmp 0>; 2689 2690 nvidia,aspm-cmrt-us = <60>; 2691 nvidia,aspm-pwr-on-t-us = <20>; 2692 nvidia,aspm-l0s-entrance-latency-us = <3>; 2693 2694 bus-range = <0x0 0xff>; 2695 2696 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2697 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2698 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2699 2700 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2701 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2702 interconnect-names = "dma-mem", "write"; 2703 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2704 iommu-map-mask = <0x0>; 2705 dma-coherent; 2706 2707 status = "disabled"; 2708 }; 2709 2710 pcie@141a0000 { 2711 compatible = "nvidia,tegra234-pcie"; 2712 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2713 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2714 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2715 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2716 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2717 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2718 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2719 2720 #address-cells = <3>; 2721 #size-cells = <2>; 2722 device_type = "pci"; 2723 num-lanes = <8>; 2724 num-viewport = <8>; 2725 linux,pci-domain = <5>; 2726 2727 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2728 clock-names = "core"; 2729 2730 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2731 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2732 reset-names = "apb", "core"; 2733 2734 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2735 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2736 interrupt-names = "intr", "msi"; 2737 2738 #interrupt-cells = <1>; 2739 interrupt-map-mask = <0 0 0 0>; 2740 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2741 2742 nvidia,bpmp = <&bpmp 5>; 2743 2744 nvidia,aspm-cmrt-us = <60>; 2745 nvidia,aspm-pwr-on-t-us = <20>; 2746 nvidia,aspm-l0s-entrance-latency-us = <3>; 2747 2748 bus-range = <0x0 0xff>; 2749 2750 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2751 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2752 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2753 2754 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2755 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2756 interconnect-names = "dma-mem", "write"; 2757 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2758 iommu-map-mask = <0x0>; 2759 dma-coherent; 2760 2761 status = "disabled"; 2762 }; 2763 2764 pcie-ep@141a0000 { 2765 compatible = "nvidia,tegra234-pcie-ep"; 2766 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2767 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2768 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2769 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2770 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2771 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2772 2773 num-lanes = <8>; 2774 2775 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2776 clock-names = "core"; 2777 2778 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2779 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2780 reset-names = "apb", "core"; 2781 2782 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2783 interrupt-names = "intr"; 2784 2785 nvidia,bpmp = <&bpmp 5>; 2786 2787 nvidia,enable-ext-refclk; 2788 nvidia,aspm-cmrt-us = <60>; 2789 nvidia,aspm-pwr-on-t-us = <20>; 2790 nvidia,aspm-l0s-entrance-latency-us = <3>; 2791 2792 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2793 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2794 interconnect-names = "dma-mem", "write"; 2795 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2796 iommu-map-mask = <0x0>; 2797 dma-coherent; 2798 2799 status = "disabled"; 2800 }; 2801 2802 pcie@141c0000 { 2803 compatible = "nvidia,tegra234-pcie"; 2804 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2805 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2806 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2807 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2808 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2809 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2810 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2811 2812 #address-cells = <3>; 2813 #size-cells = <2>; 2814 device_type = "pci"; 2815 num-lanes = <4>; 2816 num-viewport = <8>; 2817 linux,pci-domain = <6>; 2818 2819 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2820 clock-names = "core"; 2821 2822 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2823 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2824 reset-names = "apb", "core"; 2825 2826 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2827 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2828 interrupt-names = "intr", "msi"; 2829 2830 #interrupt-cells = <1>; 2831 interrupt-map-mask = <0 0 0 0>; 2832 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2833 2834 nvidia,bpmp = <&bpmp 6>; 2835 2836 nvidia,aspm-cmrt-us = <60>; 2837 nvidia,aspm-pwr-on-t-us = <20>; 2838 nvidia,aspm-l0s-entrance-latency-us = <3>; 2839 2840 bus-range = <0x0 0xff>; 2841 2842 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2843 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2844 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2845 2846 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2847 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2848 interconnect-names = "dma-mem", "write"; 2849 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2850 iommu-map-mask = <0x0>; 2851 dma-coherent; 2852 2853 status = "disabled"; 2854 }; 2855 2856 pcie-ep@141c0000 { 2857 compatible = "nvidia,tegra234-pcie-ep"; 2858 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2859 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2860 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2861 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2862 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2863 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2864 2865 num-lanes = <4>; 2866 2867 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2868 clock-names = "core"; 2869 2870 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2871 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2872 reset-names = "apb", "core"; 2873 2874 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2875 interrupt-names = "intr"; 2876 2877 nvidia,bpmp = <&bpmp 6>; 2878 2879 nvidia,enable-ext-refclk; 2880 nvidia,aspm-cmrt-us = <60>; 2881 nvidia,aspm-pwr-on-t-us = <20>; 2882 nvidia,aspm-l0s-entrance-latency-us = <3>; 2883 2884 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2885 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2886 interconnect-names = "dma-mem", "write"; 2887 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2888 iommu-map-mask = <0x0>; 2889 dma-coherent; 2890 2891 status = "disabled"; 2892 }; 2893 2894 pcie@141e0000 { 2895 compatible = "nvidia,tegra234-pcie"; 2896 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2897 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2898 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2899 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2900 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2901 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2902 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2903 2904 #address-cells = <3>; 2905 #size-cells = <2>; 2906 device_type = "pci"; 2907 num-lanes = <8>; 2908 num-viewport = <8>; 2909 linux,pci-domain = <7>; 2910 2911 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2912 clock-names = "core"; 2913 2914 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2915 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2916 reset-names = "apb", "core"; 2917 2918 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2919 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2920 interrupt-names = "intr", "msi"; 2921 2922 #interrupt-cells = <1>; 2923 interrupt-map-mask = <0 0 0 0>; 2924 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2925 2926 nvidia,bpmp = <&bpmp 7>; 2927 2928 nvidia,aspm-cmrt-us = <60>; 2929 nvidia,aspm-pwr-on-t-us = <20>; 2930 nvidia,aspm-l0s-entrance-latency-us = <3>; 2931 2932 bus-range = <0x0 0xff>; 2933 2934 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2935 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2936 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2937 2938 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2939 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2940 interconnect-names = "dma-mem", "write"; 2941 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2942 iommu-map-mask = <0x0>; 2943 dma-coherent; 2944 2945 status = "disabled"; 2946 }; 2947 2948 pcie-ep@141e0000 { 2949 compatible = "nvidia,tegra234-pcie-ep"; 2950 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2951 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2952 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2953 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2954 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2955 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2956 2957 num-lanes = <8>; 2958 2959 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2960 clock-names = "core"; 2961 2962 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2963 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2964 reset-names = "apb", "core"; 2965 2966 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2967 interrupt-names = "intr"; 2968 2969 nvidia,bpmp = <&bpmp 7>; 2970 2971 nvidia,enable-ext-refclk; 2972 nvidia,aspm-cmrt-us = <60>; 2973 nvidia,aspm-pwr-on-t-us = <20>; 2974 nvidia,aspm-l0s-entrance-latency-us = <3>; 2975 2976 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2977 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2978 interconnect-names = "dma-mem", "write"; 2979 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2980 iommu-map-mask = <0x0>; 2981 dma-coherent; 2982 2983 status = "disabled"; 2984 }; 2985 }; 2986 2987 sram@40000000 { 2988 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2989 reg = <0x0 0x40000000 0x0 0x80000>; 2990 2991 #address-cells = <1>; 2992 #size-cells = <1>; 2993 ranges = <0x0 0x0 0x40000000 0x80000>; 2994 2995 no-memory-wc; 2996 2997 cpu_bpmp_tx: sram@70000 { 2998 reg = <0x70000 0x1000>; 2999 label = "cpu-bpmp-tx"; 3000 pool; 3001 }; 3002 3003 cpu_bpmp_rx: sram@71000 { 3004 reg = <0x71000 0x1000>; 3005 label = "cpu-bpmp-rx"; 3006 pool; 3007 }; 3008 }; 3009 3010 bpmp: bpmp { 3011 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 3012 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 3013 TEGRA_HSP_DB_MASTER_BPMP>; 3014 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 3015 #clock-cells = <1>; 3016 #reset-cells = <1>; 3017 #power-domain-cells = <1>; 3018 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 3019 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 3020 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 3021 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 3022 interconnect-names = "read", "write", "dma-mem", "dma-write"; 3023 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 3024 3025 bpmp_i2c: i2c { 3026 compatible = "nvidia,tegra186-bpmp-i2c"; 3027 nvidia,bpmp-bus-id = <5>; 3028 #address-cells = <1>; 3029 #size-cells = <0>; 3030 }; 3031 3032 bpmp_thermal: thermal { 3033 compatible = "nvidia,tegra186-bpmp-thermal"; 3034 #thermal-sensor-cells = <1>; 3035 }; 3036 }; 3037 3038 cpus { 3039 #address-cells = <1>; 3040 #size-cells = <0>; 3041 3042 cpu0_0: cpu@0 { 3043 compatible = "arm,cortex-a78"; 3044 device_type = "cpu"; 3045 reg = <0x00000>; 3046 3047 enable-method = "psci"; 3048 3049 operating-points-v2 = <&cl0_opp_tbl>; 3050 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3051 3052 i-cache-size = <65536>; 3053 i-cache-line-size = <64>; 3054 i-cache-sets = <256>; 3055 d-cache-size = <65536>; 3056 d-cache-line-size = <64>; 3057 d-cache-sets = <256>; 3058 next-level-cache = <&l2c0_0>; 3059 }; 3060 3061 cpu0_1: cpu@100 { 3062 compatible = "arm,cortex-a78"; 3063 device_type = "cpu"; 3064 reg = <0x00100>; 3065 3066 enable-method = "psci"; 3067 3068 operating-points-v2 = <&cl0_opp_tbl>; 3069 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3070 3071 i-cache-size = <65536>; 3072 i-cache-line-size = <64>; 3073 i-cache-sets = <256>; 3074 d-cache-size = <65536>; 3075 d-cache-line-size = <64>; 3076 d-cache-sets = <256>; 3077 next-level-cache = <&l2c0_1>; 3078 }; 3079 3080 cpu0_2: cpu@200 { 3081 compatible = "arm,cortex-a78"; 3082 device_type = "cpu"; 3083 reg = <0x00200>; 3084 3085 enable-method = "psci"; 3086 3087 operating-points-v2 = <&cl0_opp_tbl>; 3088 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3089 3090 i-cache-size = <65536>; 3091 i-cache-line-size = <64>; 3092 i-cache-sets = <256>; 3093 d-cache-size = <65536>; 3094 d-cache-line-size = <64>; 3095 d-cache-sets = <256>; 3096 next-level-cache = <&l2c0_2>; 3097 }; 3098 3099 cpu0_3: cpu@300 { 3100 compatible = "arm,cortex-a78"; 3101 device_type = "cpu"; 3102 reg = <0x00300>; 3103 3104 enable-method = "psci"; 3105 3106 operating-points-v2 = <&cl0_opp_tbl>; 3107 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3108 3109 i-cache-size = <65536>; 3110 i-cache-line-size = <64>; 3111 i-cache-sets = <256>; 3112 d-cache-size = <65536>; 3113 d-cache-line-size = <64>; 3114 d-cache-sets = <256>; 3115 next-level-cache = <&l2c0_3>; 3116 }; 3117 3118 cpu1_0: cpu@10000 { 3119 compatible = "arm,cortex-a78"; 3120 device_type = "cpu"; 3121 reg = <0x10000>; 3122 3123 enable-method = "psci"; 3124 3125 operating-points-v2 = <&cl1_opp_tbl>; 3126 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3127 3128 i-cache-size = <65536>; 3129 i-cache-line-size = <64>; 3130 i-cache-sets = <256>; 3131 d-cache-size = <65536>; 3132 d-cache-line-size = <64>; 3133 d-cache-sets = <256>; 3134 next-level-cache = <&l2c1_0>; 3135 }; 3136 3137 cpu1_1: cpu@10100 { 3138 compatible = "arm,cortex-a78"; 3139 device_type = "cpu"; 3140 reg = <0x10100>; 3141 3142 enable-method = "psci"; 3143 3144 operating-points-v2 = <&cl1_opp_tbl>; 3145 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3146 3147 i-cache-size = <65536>; 3148 i-cache-line-size = <64>; 3149 i-cache-sets = <256>; 3150 d-cache-size = <65536>; 3151 d-cache-line-size = <64>; 3152 d-cache-sets = <256>; 3153 next-level-cache = <&l2c1_1>; 3154 }; 3155 3156 cpu1_2: cpu@10200 { 3157 compatible = "arm,cortex-a78"; 3158 device_type = "cpu"; 3159 reg = <0x10200>; 3160 3161 enable-method = "psci"; 3162 3163 operating-points-v2 = <&cl1_opp_tbl>; 3164 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3165 3166 i-cache-size = <65536>; 3167 i-cache-line-size = <64>; 3168 i-cache-sets = <256>; 3169 d-cache-size = <65536>; 3170 d-cache-line-size = <64>; 3171 d-cache-sets = <256>; 3172 next-level-cache = <&l2c1_2>; 3173 }; 3174 3175 cpu1_3: cpu@10300 { 3176 compatible = "arm,cortex-a78"; 3177 device_type = "cpu"; 3178 reg = <0x10300>; 3179 3180 enable-method = "psci"; 3181 3182 operating-points-v2 = <&cl1_opp_tbl>; 3183 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3184 3185 i-cache-size = <65536>; 3186 i-cache-line-size = <64>; 3187 i-cache-sets = <256>; 3188 d-cache-size = <65536>; 3189 d-cache-line-size = <64>; 3190 d-cache-sets = <256>; 3191 next-level-cache = <&l2c1_3>; 3192 }; 3193 3194 cpu2_0: cpu@20000 { 3195 compatible = "arm,cortex-a78"; 3196 device_type = "cpu"; 3197 reg = <0x20000>; 3198 3199 enable-method = "psci"; 3200 3201 operating-points-v2 = <&cl2_opp_tbl>; 3202 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3203 3204 i-cache-size = <65536>; 3205 i-cache-line-size = <64>; 3206 i-cache-sets = <256>; 3207 d-cache-size = <65536>; 3208 d-cache-line-size = <64>; 3209 d-cache-sets = <256>; 3210 next-level-cache = <&l2c2_0>; 3211 }; 3212 3213 cpu2_1: cpu@20100 { 3214 compatible = "arm,cortex-a78"; 3215 device_type = "cpu"; 3216 reg = <0x20100>; 3217 3218 enable-method = "psci"; 3219 3220 operating-points-v2 = <&cl2_opp_tbl>; 3221 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3222 3223 i-cache-size = <65536>; 3224 i-cache-line-size = <64>; 3225 i-cache-sets = <256>; 3226 d-cache-size = <65536>; 3227 d-cache-line-size = <64>; 3228 d-cache-sets = <256>; 3229 next-level-cache = <&l2c2_1>; 3230 }; 3231 3232 cpu2_2: cpu@20200 { 3233 compatible = "arm,cortex-a78"; 3234 device_type = "cpu"; 3235 reg = <0x20200>; 3236 3237 enable-method = "psci"; 3238 3239 operating-points-v2 = <&cl2_opp_tbl>; 3240 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3241 3242 i-cache-size = <65536>; 3243 i-cache-line-size = <64>; 3244 i-cache-sets = <256>; 3245 d-cache-size = <65536>; 3246 d-cache-line-size = <64>; 3247 d-cache-sets = <256>; 3248 next-level-cache = <&l2c2_2>; 3249 }; 3250 3251 cpu2_3: cpu@20300 { 3252 compatible = "arm,cortex-a78"; 3253 device_type = "cpu"; 3254 reg = <0x20300>; 3255 3256 enable-method = "psci"; 3257 3258 operating-points-v2 = <&cl2_opp_tbl>; 3259 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3260 3261 i-cache-size = <65536>; 3262 i-cache-line-size = <64>; 3263 i-cache-sets = <256>; 3264 d-cache-size = <65536>; 3265 d-cache-line-size = <64>; 3266 d-cache-sets = <256>; 3267 next-level-cache = <&l2c2_3>; 3268 }; 3269 3270 cpu-map { 3271 cluster0 { 3272 core0 { 3273 cpu = <&cpu0_0>; 3274 }; 3275 3276 core1 { 3277 cpu = <&cpu0_1>; 3278 }; 3279 3280 core2 { 3281 cpu = <&cpu0_2>; 3282 }; 3283 3284 core3 { 3285 cpu = <&cpu0_3>; 3286 }; 3287 }; 3288 3289 cluster1 { 3290 core0 { 3291 cpu = <&cpu1_0>; 3292 }; 3293 3294 core1 { 3295 cpu = <&cpu1_1>; 3296 }; 3297 3298 core2 { 3299 cpu = <&cpu1_2>; 3300 }; 3301 3302 core3 { 3303 cpu = <&cpu1_3>; 3304 }; 3305 }; 3306 3307 cluster2 { 3308 core0 { 3309 cpu = <&cpu2_0>; 3310 }; 3311 3312 core1 { 3313 cpu = <&cpu2_1>; 3314 }; 3315 3316 core2 { 3317 cpu = <&cpu2_2>; 3318 }; 3319 3320 core3 { 3321 cpu = <&cpu2_3>; 3322 }; 3323 }; 3324 }; 3325 3326 l2c0_0: l2-cache00 { 3327 compatible = "cache"; 3328 cache-size = <262144>; 3329 cache-line-size = <64>; 3330 cache-sets = <512>; 3331 cache-unified; 3332 cache-level = <2>; 3333 next-level-cache = <&l3c0>; 3334 }; 3335 3336 l2c0_1: l2-cache01 { 3337 compatible = "cache"; 3338 cache-size = <262144>; 3339 cache-line-size = <64>; 3340 cache-sets = <512>; 3341 cache-unified; 3342 cache-level = <2>; 3343 next-level-cache = <&l3c0>; 3344 }; 3345 3346 l2c0_2: l2-cache02 { 3347 compatible = "cache"; 3348 cache-size = <262144>; 3349 cache-line-size = <64>; 3350 cache-sets = <512>; 3351 cache-unified; 3352 cache-level = <2>; 3353 next-level-cache = <&l3c0>; 3354 }; 3355 3356 l2c0_3: l2-cache03 { 3357 compatible = "cache"; 3358 cache-size = <262144>; 3359 cache-line-size = <64>; 3360 cache-sets = <512>; 3361 cache-unified; 3362 cache-level = <2>; 3363 next-level-cache = <&l3c0>; 3364 }; 3365 3366 l2c1_0: l2-cache10 { 3367 compatible = "cache"; 3368 cache-size = <262144>; 3369 cache-line-size = <64>; 3370 cache-sets = <512>; 3371 cache-unified; 3372 cache-level = <2>; 3373 next-level-cache = <&l3c1>; 3374 }; 3375 3376 l2c1_1: l2-cache11 { 3377 compatible = "cache"; 3378 cache-size = <262144>; 3379 cache-line-size = <64>; 3380 cache-sets = <512>; 3381 cache-unified; 3382 cache-level = <2>; 3383 next-level-cache = <&l3c1>; 3384 }; 3385 3386 l2c1_2: l2-cache12 { 3387 compatible = "cache"; 3388 cache-size = <262144>; 3389 cache-line-size = <64>; 3390 cache-sets = <512>; 3391 cache-unified; 3392 cache-level = <2>; 3393 next-level-cache = <&l3c1>; 3394 }; 3395 3396 l2c1_3: l2-cache13 { 3397 compatible = "cache"; 3398 cache-size = <262144>; 3399 cache-line-size = <64>; 3400 cache-sets = <512>; 3401 cache-unified; 3402 cache-level = <2>; 3403 next-level-cache = <&l3c1>; 3404 }; 3405 3406 l2c2_0: l2-cache20 { 3407 compatible = "cache"; 3408 cache-size = <262144>; 3409 cache-line-size = <64>; 3410 cache-sets = <512>; 3411 cache-unified; 3412 cache-level = <2>; 3413 next-level-cache = <&l3c2>; 3414 }; 3415 3416 l2c2_1: l2-cache21 { 3417 compatible = "cache"; 3418 cache-size = <262144>; 3419 cache-line-size = <64>; 3420 cache-sets = <512>; 3421 cache-unified; 3422 cache-level = <2>; 3423 next-level-cache = <&l3c2>; 3424 }; 3425 3426 l2c2_2: l2-cache22 { 3427 compatible = "cache"; 3428 cache-size = <262144>; 3429 cache-line-size = <64>; 3430 cache-sets = <512>; 3431 cache-unified; 3432 cache-level = <2>; 3433 next-level-cache = <&l3c2>; 3434 }; 3435 3436 l2c2_3: l2-cache23 { 3437 compatible = "cache"; 3438 cache-size = <262144>; 3439 cache-line-size = <64>; 3440 cache-sets = <512>; 3441 cache-unified; 3442 cache-level = <2>; 3443 next-level-cache = <&l3c2>; 3444 }; 3445 3446 l3c0: l3-cache0 { 3447 compatible = "cache"; 3448 cache-unified; 3449 cache-size = <2097152>; 3450 cache-line-size = <64>; 3451 cache-sets = <2048>; 3452 cache-level = <3>; 3453 }; 3454 3455 l3c1: l3-cache1 { 3456 compatible = "cache"; 3457 cache-unified; 3458 cache-size = <2097152>; 3459 cache-line-size = <64>; 3460 cache-sets = <2048>; 3461 cache-level = <3>; 3462 }; 3463 3464 l3c2: l3-cache2 { 3465 compatible = "cache"; 3466 cache-unified; 3467 cache-size = <2097152>; 3468 cache-line-size = <64>; 3469 cache-sets = <2048>; 3470 cache-level = <3>; 3471 }; 3472 }; 3473 3474 dsu-pmu0 { 3475 compatible = "arm,dsu-pmu"; 3476 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 3477 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 3478 }; 3479 3480 dsu-pmu1 { 3481 compatible = "arm,dsu-pmu"; 3482 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 3483 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 3484 }; 3485 3486 dsu-pmu2 { 3487 compatible = "arm,dsu-pmu"; 3488 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 3489 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 3490 }; 3491 3492 pmu { 3493 compatible = "arm,cortex-a78-pmu"; 3494 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3495 status = "okay"; 3496 }; 3497 3498 psci { 3499 compatible = "arm,psci-1.0"; 3500 status = "okay"; 3501 method = "smc"; 3502 }; 3503 3504 tcu: serial { 3505 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3506 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3507 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3508 mbox-names = "rx", "tx"; 3509 status = "disabled"; 3510 }; 3511 3512 sound { 3513 status = "disabled"; 3514 3515 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3516 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3517 clock-names = "pll_a", "plla_out0"; 3518 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3519 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3520 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3521 assigned-clock-parents = <0>, 3522 <&bpmp TEGRA234_CLK_PLLA>, 3523 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3524 }; 3525 3526 thermal-zones { 3527 cpu-thermal { 3528 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; 3529 status = "disabled"; 3530 }; 3531 3532 gpu-thermal { 3533 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; 3534 status = "disabled"; 3535 }; 3536 3537 cv0-thermal { 3538 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; 3539 status = "disabled"; 3540 }; 3541 3542 cv1-thermal { 3543 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; 3544 status = "disabled"; 3545 }; 3546 3547 cv2-thermal { 3548 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; 3549 status = "disabled"; 3550 }; 3551 3552 soc0-thermal { 3553 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; 3554 status = "disabled"; 3555 }; 3556 3557 soc1-thermal { 3558 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; 3559 status = "disabled"; 3560 }; 3561 3562 soc2-thermal { 3563 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; 3564 status = "disabled"; 3565 }; 3566 3567 tj-thermal { 3568 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; 3569 status = "disabled"; 3570 }; 3571 }; 3572 3573 timer { 3574 compatible = "arm,armv8-timer"; 3575 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3576 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3577 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3578 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3579 interrupt-parent = <&gic>; 3580 always-on; 3581 }; 3582 3583 cl0_opp_tbl: opp-table-cluster0 { 3584 compatible = "operating-points-v2"; 3585 opp-shared; 3586 3587 cl0_ch1_opp1: opp-115200000 { 3588 opp-hz = /bits/ 64 <115200000>; 3589 opp-peak-kBps = <816000>; 3590 }; 3591 3592 cl0_ch1_opp2: opp-268800000 { 3593 opp-hz = /bits/ 64 <268800000>; 3594 opp-peak-kBps = <816000>; 3595 }; 3596 3597 cl0_ch1_opp3: opp-422400000 { 3598 opp-hz = /bits/ 64 <422400000>; 3599 opp-peak-kBps = <816000>; 3600 }; 3601 3602 cl0_ch1_opp4: opp-576000000 { 3603 opp-hz = /bits/ 64 <576000000>; 3604 opp-peak-kBps = <816000>; 3605 }; 3606 3607 cl0_ch1_opp5: opp-729600000 { 3608 opp-hz = /bits/ 64 <729600000>; 3609 opp-peak-kBps = <816000>; 3610 }; 3611 3612 cl0_ch1_opp6: opp-883200000 { 3613 opp-hz = /bits/ 64 <883200000>; 3614 opp-peak-kBps = <816000>; 3615 }; 3616 3617 cl0_ch1_opp7: opp-1036800000 { 3618 opp-hz = /bits/ 64 <1036800000>; 3619 opp-peak-kBps = <816000>; 3620 }; 3621 3622 cl0_ch1_opp8: opp-1190400000 { 3623 opp-hz = /bits/ 64 <1190400000>; 3624 opp-peak-kBps = <816000>; 3625 }; 3626 3627 cl0_ch1_opp9: opp-1344000000 { 3628 opp-hz = /bits/ 64 <1344000000>; 3629 opp-peak-kBps = <1632000>; 3630 }; 3631 3632 cl0_ch1_opp10: opp-1497600000 { 3633 opp-hz = /bits/ 64 <1497600000>; 3634 opp-peak-kBps = <1632000>; 3635 }; 3636 3637 cl0_ch1_opp11: opp-1651200000 { 3638 opp-hz = /bits/ 64 <1651200000>; 3639 opp-peak-kBps = <2660000>; 3640 }; 3641 3642 cl0_ch1_opp12: opp-1804800000 { 3643 opp-hz = /bits/ 64 <1804800000>; 3644 opp-peak-kBps = <2660000>; 3645 }; 3646 3647 cl0_ch1_opp13: opp-1958400000 { 3648 opp-hz = /bits/ 64 <1958400000>; 3649 opp-peak-kBps = <3200000>; 3650 }; 3651 3652 cl0_ch1_opp14: opp-2112000000 { 3653 opp-hz = /bits/ 64 <2112000000>; 3654 opp-peak-kBps = <6400000>; 3655 }; 3656 3657 cl0_ch1_opp15: opp-2201600000 { 3658 opp-hz = /bits/ 64 <2201600000>; 3659 opp-peak-kBps = <6400000>; 3660 }; 3661 }; 3662 3663 cl1_opp_tbl: opp-table-cluster1 { 3664 compatible = "operating-points-v2"; 3665 opp-shared; 3666 3667 cl1_ch1_opp1: opp-115200000 { 3668 opp-hz = /bits/ 64 <115200000>; 3669 opp-peak-kBps = <816000>; 3670 }; 3671 3672 cl1_ch1_opp2: opp-268800000 { 3673 opp-hz = /bits/ 64 <268800000>; 3674 opp-peak-kBps = <816000>; 3675 }; 3676 3677 cl1_ch1_opp3: opp-422400000 { 3678 opp-hz = /bits/ 64 <422400000>; 3679 opp-peak-kBps = <816000>; 3680 }; 3681 3682 cl1_ch1_opp4: opp-576000000 { 3683 opp-hz = /bits/ 64 <576000000>; 3684 opp-peak-kBps = <816000>; 3685 }; 3686 3687 cl1_ch1_opp5: opp-729600000 { 3688 opp-hz = /bits/ 64 <729600000>; 3689 opp-peak-kBps = <816000>; 3690 }; 3691 3692 cl1_ch1_opp6: opp-883200000 { 3693 opp-hz = /bits/ 64 <883200000>; 3694 opp-peak-kBps = <816000>; 3695 }; 3696 3697 cl1_ch1_opp7: opp-1036800000 { 3698 opp-hz = /bits/ 64 <1036800000>; 3699 opp-peak-kBps = <816000>; 3700 }; 3701 3702 cl1_ch1_opp8: opp-1190400000 { 3703 opp-hz = /bits/ 64 <1190400000>; 3704 opp-peak-kBps = <816000>; 3705 }; 3706 3707 cl1_ch1_opp9: opp-1344000000 { 3708 opp-hz = /bits/ 64 <1344000000>; 3709 opp-peak-kBps = <1632000>; 3710 }; 3711 3712 cl1_ch1_opp10: opp-1497600000 { 3713 opp-hz = /bits/ 64 <1497600000>; 3714 opp-peak-kBps = <1632000>; 3715 }; 3716 3717 cl1_ch1_opp11: opp-1651200000 { 3718 opp-hz = /bits/ 64 <1651200000>; 3719 opp-peak-kBps = <2660000>; 3720 }; 3721 3722 cl1_ch1_opp12: opp-1804800000 { 3723 opp-hz = /bits/ 64 <1804800000>; 3724 opp-peak-kBps = <2660000>; 3725 }; 3726 3727 cl1_ch1_opp13: opp-1958400000 { 3728 opp-hz = /bits/ 64 <1958400000>; 3729 opp-peak-kBps = <3200000>; 3730 }; 3731 3732 cl1_ch1_opp14: opp-2112000000 { 3733 opp-hz = /bits/ 64 <2112000000>; 3734 opp-peak-kBps = <6400000>; 3735 }; 3736 3737 cl1_ch1_opp15: opp-2201600000 { 3738 opp-hz = /bits/ 64 <2201600000>; 3739 opp-peak-kBps = <6400000>; 3740 }; 3741 }; 3742 3743 cl2_opp_tbl: opp-table-cluster2 { 3744 compatible = "operating-points-v2"; 3745 opp-shared; 3746 3747 cl2_ch1_opp1: opp-115200000 { 3748 opp-hz = /bits/ 64 <115200000>; 3749 opp-peak-kBps = <816000>; 3750 }; 3751 3752 cl2_ch1_opp2: opp-268800000 { 3753 opp-hz = /bits/ 64 <268800000>; 3754 opp-peak-kBps = <816000>; 3755 }; 3756 3757 cl2_ch1_opp3: opp-422400000 { 3758 opp-hz = /bits/ 64 <422400000>; 3759 opp-peak-kBps = <816000>; 3760 }; 3761 3762 cl2_ch1_opp4: opp-576000000 { 3763 opp-hz = /bits/ 64 <576000000>; 3764 opp-peak-kBps = <816000>; 3765 }; 3766 3767 cl2_ch1_opp5: opp-729600000 { 3768 opp-hz = /bits/ 64 <729600000>; 3769 opp-peak-kBps = <816000>; 3770 }; 3771 3772 cl2_ch1_opp6: opp-883200000 { 3773 opp-hz = /bits/ 64 <883200000>; 3774 opp-peak-kBps = <816000>; 3775 }; 3776 3777 cl2_ch1_opp7: opp-1036800000 { 3778 opp-hz = /bits/ 64 <1036800000>; 3779 opp-peak-kBps = <816000>; 3780 }; 3781 3782 cl2_ch1_opp8: opp-1190400000 { 3783 opp-hz = /bits/ 64 <1190400000>; 3784 opp-peak-kBps = <816000>; 3785 }; 3786 3787 cl2_ch1_opp9: opp-1344000000 { 3788 opp-hz = /bits/ 64 <1344000000>; 3789 opp-peak-kBps = <1632000>; 3790 }; 3791 3792 cl2_ch1_opp10: opp-1497600000 { 3793 opp-hz = /bits/ 64 <1497600000>; 3794 opp-peak-kBps = <1632000>; 3795 }; 3796 3797 cl2_ch1_opp11: opp-1651200000 { 3798 opp-hz = /bits/ 64 <1651200000>; 3799 opp-peak-kBps = <2660000>; 3800 }; 3801 3802 cl2_ch1_opp12: opp-1804800000 { 3803 opp-hz = /bits/ 64 <1804800000>; 3804 opp-peak-kBps = <2660000>; 3805 }; 3806 3807 cl2_ch1_opp13: opp-1958400000 { 3808 opp-hz = /bits/ 64 <1958400000>; 3809 opp-peak-kBps = <3200000>; 3810 }; 3811 3812 cl2_ch1_opp14: opp-2112000000 { 3813 opp-hz = /bits/ 64 <2112000000>; 3814 opp-peak-kBps = <6400000>; 3815 }; 3816 3817 cl2_ch1_opp15: opp-2201600000 { 3818 opp-hz = /bits/ 64 <2201600000>; 3819 opp-peak-kBps = <6400000>; 3820 }; 3821 }; 3822}; 3823