1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97 reset-names = "host1x", "mc"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 186 clock-names = "tsec"; 187 resets = <&tegra_car 83>; 188 reset-names = "tsec"; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 status = "disabled"; 257 }; 258 259 dsib: dsi@54400000 { 260 compatible = "nvidia,tegra210-dsi"; 261 reg = <0x0 0x54400000 0x0 0x00040000>; 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263 <&tegra_car TEGRA210_CLK_DSIBLP>, 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265 clock-names = "dsi", "lp", "parent"; 266 resets = <&tegra_car 82>; 267 reset-names = "dsi"; 268 power-domains = <&pd_sor>; 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270 271 status = "disabled"; 272 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 nvdec@54480000 { 278 compatible = "nvidia,tegra210-nvdec"; 279 reg = <0x0 0x54480000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 nvenc@544c0000 { 284 compatible = "nvidia,tegra210-nvenc"; 285 reg = <0x0 0x544c0000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 tsec@54500000 { 290 compatible = "nvidia,tegra210-tsec"; 291 reg = <0x0 0x54500000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 294 clock-names = "tsec"; 295 resets = <&tegra_car 206>; 296 reset-names = "tsec"; 297 status = "disabled"; 298 }; 299 300 sor0: sor@54540000 { 301 compatible = "nvidia,tegra210-sor"; 302 reg = <0x0 0x54540000 0x0 0x00040000>; 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307 <&tegra_car TEGRA210_CLK_PLL_DP>, 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309 clock-names = "sor", "out", "parent", "dp", "safe"; 310 resets = <&tegra_car 182>; 311 reset-names = "sor"; 312 pinctrl-0 = <&state_dpaux_aux>; 313 pinctrl-1 = <&state_dpaux_i2c>; 314 pinctrl-2 = <&state_dpaux_off>; 315 pinctrl-names = "aux", "i2c", "off"; 316 power-domains = <&pd_sor>; 317 status = "disabled"; 318 }; 319 320 sor1: sor@54580000 { 321 compatible = "nvidia,tegra210-sor1"; 322 reg = <0x0 0x54580000 0x0 0x00040000>; 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327 <&tegra_car TEGRA210_CLK_PLL_DP>, 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 329 clock-names = "sor", "out", "parent", "dp", "safe"; 330 resets = <&tegra_car 183>; 331 reset-names = "sor"; 332 pinctrl-0 = <&state_dpaux1_aux>; 333 pinctrl-1 = <&state_dpaux1_i2c>; 334 pinctrl-2 = <&state_dpaux1_off>; 335 pinctrl-names = "aux", "i2c", "off"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 }; 339 340 dpaux: dpaux@545c0000 { 341 compatible = "nvidia,tegra210-dpaux"; 342 reg = <0x0 0x545c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345 <&tegra_car TEGRA210_CLK_PLL_DP>; 346 clock-names = "dpaux", "parent"; 347 resets = <&tegra_car 181>; 348 reset-names = "dpaux"; 349 power-domains = <&pd_sor>; 350 status = "disabled"; 351 352 state_dpaux_aux: pinmux-aux { 353 groups = "dpaux-io"; 354 function = "aux"; 355 }; 356 357 state_dpaux_i2c: pinmux-i2c { 358 groups = "dpaux-io"; 359 function = "i2c"; 360 }; 361 362 state_dpaux_off: pinmux-off { 363 groups = "dpaux-io"; 364 function = "off"; 365 }; 366 367 i2c-bus { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 }; 372 373 isp@54600000 { 374 compatible = "nvidia,tegra210-isp"; 375 reg = <0x0 0x54600000 0x0 0x00040000>; 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 378 resets = <&tegra_car 23>; 379 reset-names = "isp"; 380 status = "disabled"; 381 }; 382 383 isp@54680000 { 384 compatible = "nvidia,tegra210-isp"; 385 reg = <0x0 0x54680000 0x0 0x00040000>; 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 388 resets = <&tegra_car 3>; 389 reset-names = "isp"; 390 status = "disabled"; 391 }; 392 393 i2c@546c0000 { 394 compatible = "nvidia,tegra210-i2c-vi"; 395 reg = <0x0 0x546c0000 0x0 0x00040000>; 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398 <&tegra_car TEGRA210_CLK_I2CSLOW>; 399 clock-names = "div-clk", "slow"; 400 resets = <&tegra_car 208>; 401 reset-names = "i2c"; 402 power-domains = <&pd_venc>; 403 status = "disabled"; 404 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 }; 409 410 gic: interrupt-controller@50041000 { 411 compatible = "arm,gic-400"; 412 #interrupt-cells = <3>; 413 interrupt-controller; 414 reg = <0x0 0x50041000 0x0 0x1000>, 415 <0x0 0x50042000 0x0 0x2000>, 416 <0x0 0x50044000 0x0 0x2000>, 417 <0x0 0x50046000 0x0 0x2000>; 418 interrupts = <GIC_PPI 9 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420 interrupt-parent = <&gic>; 421 }; 422 423 gpu@57000000 { 424 compatible = "nvidia,gm20b"; 425 reg = <0x0 0x57000000 0x0 0x01000000>, 426 <0x0 0x58000000 0x0 0x01000000>; 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "stall", "nonstall"; 430 clocks = <&tegra_car TEGRA210_CLK_GPU>, 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 433 clock-names = "gpu", "pwr", "ref"; 434 resets = <&tegra_car 184>; 435 reset-names = "gpu"; 436 437 iommus = <&mc TEGRA_SWGROUP_GPU>; 438 439 status = "disabled"; 440 }; 441 442 lic: interrupt-controller@60004000 { 443 compatible = "nvidia,tegra210-ictlr"; 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450 interrupt-controller; 451 #interrupt-cells = <3>; 452 interrupt-parent = <&gic>; 453 }; 454 455 timer@60005000 { 456 compatible = "nvidia,tegra210-timer"; 457 reg = <0x0 0x60005000 0x0 0x400>; 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473 clock-names = "timer"; 474 }; 475 476 tegra_car: clock@60006000 { 477 compatible = "nvidia,tegra210-car"; 478 reg = <0x0 0x60006000 0x0 0x1000>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 481 }; 482 483 flow-controller@60007000 { 484 compatible = "nvidia,tegra210-flowctrl"; 485 reg = <0x0 0x60007000 0x0 0x1000>; 486 }; 487 488 gpio: gpio@6000d000 { 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490 reg = <0x0 0x6000d000 0x0 0x1000>; 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499 #gpio-cells = <2>; 500 gpio-controller; 501 #interrupt-cells = <2>; 502 interrupt-controller; 503 }; 504 505 apbdma: dma@60020000 { 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507 reg = <0x0 0x60020000 0x0 0x1400>; 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541 clock-names = "dma"; 542 resets = <&tegra_car 34>; 543 reset-names = "dma"; 544 #dma-cells = <1>; 545 }; 546 547 apbmisc@70000800 { 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551 }; 552 553 pinmux: pinmux@700008d4 { 554 compatible = "nvidia,tegra210-pinmux"; 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 558 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 559 sdmmc1 { 560 nvidia,pins = "drive_sdmmc1"; 561 nvidia,pull-down-strength = <0x4>; 562 nvidia,pull-up-strength = <0x3>; 563 }; 564 }; 565 566 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 567 sdmmc1 { 568 nvidia,pins = "drive_sdmmc1"; 569 nvidia,pull-down-strength = <0x8>; 570 nvidia,pull-up-strength = <0x8>; 571 }; 572 }; 573 574 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 575 sdmmc2 { 576 nvidia,pins = "drive_sdmmc2"; 577 nvidia,pull-down-strength = <0x10>; 578 nvidia,pull-up-strength = <0x10>; 579 }; 580 }; 581 582 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 583 sdmmc3 { 584 nvidia,pins = "drive_sdmmc3"; 585 nvidia,pull-down-strength = <0x4>; 586 nvidia,pull-up-strength = <0x3>; 587 }; 588 }; 589 590 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 591 sdmmc3 { 592 nvidia,pins = "drive_sdmmc3"; 593 nvidia,pull-down-strength = <0x8>; 594 nvidia,pull-up-strength = <0x8>; 595 }; 596 }; 597 598 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 599 sdmmc4 { 600 nvidia,pins = "drive_sdmmc4"; 601 nvidia,pull-down-strength = <0x10>; 602 nvidia,pull-up-strength = <0x10>; 603 }; 604 }; 605 }; 606 607 /* 608 * There are two serial driver i.e. 8250 based simple serial 609 * driver and APB DMA based serial driver for higher baudrate 610 * and performance. To enable the 8250 based driver, the compatible 611 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 612 * the APB DMA based serial driver, the compatible is 613 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 614 */ 615 uarta: serial@70006000 { 616 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 617 reg = <0x0 0x70006000 0x0 0x40>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 621 clock-names = "serial"; 622 resets = <&tegra_car 6>; 623 reset-names = "serial"; 624 dmas = <&apbdma 8>, <&apbdma 8>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 uartb: serial@70006040 { 630 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 631 reg = <0x0 0x70006040 0x0 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 635 clock-names = "serial"; 636 resets = <&tegra_car 7>; 637 reset-names = "serial"; 638 dmas = <&apbdma 9>, <&apbdma 9>; 639 dma-names = "rx", "tx"; 640 status = "disabled"; 641 }; 642 643 uartc: serial@70006200 { 644 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 645 reg = <0x0 0x70006200 0x0 0x40>; 646 reg-shift = <2>; 647 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 649 clock-names = "serial"; 650 resets = <&tegra_car 55>; 651 reset-names = "serial"; 652 dmas = <&apbdma 10>, <&apbdma 10>; 653 dma-names = "rx", "tx"; 654 status = "disabled"; 655 }; 656 657 uartd: serial@70006300 { 658 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 659 reg = <0x0 0x70006300 0x0 0x40>; 660 reg-shift = <2>; 661 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 663 clock-names = "serial"; 664 resets = <&tegra_car 65>; 665 reset-names = "serial"; 666 dmas = <&apbdma 19>, <&apbdma 19>; 667 dma-names = "rx", "tx"; 668 status = "disabled"; 669 }; 670 671 pwm: pwm@7000a000 { 672 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 673 reg = <0x0 0x7000a000 0x0 0x100>; 674 #pwm-cells = <2>; 675 clocks = <&tegra_car TEGRA210_CLK_PWM>; 676 resets = <&tegra_car 17>; 677 reset-names = "pwm"; 678 status = "disabled"; 679 }; 680 681 i2c@7000c000 { 682 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 683 reg = <0x0 0x7000c000 0x0 0x100>; 684 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 688 clock-names = "div-clk"; 689 resets = <&tegra_car 12>; 690 reset-names = "i2c"; 691 dmas = <&apbdma 21>, <&apbdma 21>; 692 dma-names = "rx", "tx"; 693 status = "disabled"; 694 }; 695 696 i2c@7000c400 { 697 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 698 reg = <0x0 0x7000c400 0x0 0x100>; 699 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 703 clock-names = "div-clk"; 704 resets = <&tegra_car 54>; 705 reset-names = "i2c"; 706 dmas = <&apbdma 22>, <&apbdma 22>; 707 dma-names = "rx", "tx"; 708 status = "disabled"; 709 }; 710 711 i2c@7000c500 { 712 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 713 reg = <0x0 0x7000c500 0x0 0x100>; 714 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 718 clock-names = "div-clk"; 719 resets = <&tegra_car 67>; 720 reset-names = "i2c"; 721 dmas = <&apbdma 23>, <&apbdma 23>; 722 dma-names = "rx", "tx"; 723 status = "disabled"; 724 }; 725 726 i2c@7000c700 { 727 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 728 reg = <0x0 0x7000c700 0x0 0x100>; 729 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 733 clock-names = "div-clk"; 734 resets = <&tegra_car 103>; 735 reset-names = "i2c"; 736 dmas = <&apbdma 26>, <&apbdma 26>; 737 dma-names = "rx", "tx"; 738 pinctrl-0 = <&state_dpaux1_i2c>; 739 pinctrl-1 = <&state_dpaux1_off>; 740 pinctrl-names = "default", "idle"; 741 status = "disabled"; 742 }; 743 744 i2c@7000d000 { 745 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 746 reg = <0x0 0x7000d000 0x0 0x100>; 747 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 751 clock-names = "div-clk"; 752 resets = <&tegra_car 47>; 753 reset-names = "i2c"; 754 dmas = <&apbdma 24>, <&apbdma 24>; 755 dma-names = "rx", "tx"; 756 status = "disabled"; 757 }; 758 759 i2c@7000d100 { 760 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 761 reg = <0x0 0x7000d100 0x0 0x100>; 762 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 766 clock-names = "div-clk"; 767 resets = <&tegra_car 166>; 768 reset-names = "i2c"; 769 dmas = <&apbdma 30>, <&apbdma 30>; 770 dma-names = "rx", "tx"; 771 pinctrl-0 = <&state_dpaux_i2c>; 772 pinctrl-1 = <&state_dpaux_off>; 773 pinctrl-names = "default", "idle"; 774 status = "disabled"; 775 }; 776 777 spi@7000d400 { 778 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 779 reg = <0x0 0x7000d400 0x0 0x200>; 780 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 784 clock-names = "spi"; 785 resets = <&tegra_car 41>; 786 reset-names = "spi"; 787 dmas = <&apbdma 15>, <&apbdma 15>; 788 dma-names = "rx", "tx"; 789 status = "disabled"; 790 }; 791 792 spi@7000d600 { 793 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 794 reg = <0x0 0x7000d600 0x0 0x200>; 795 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 799 clock-names = "spi"; 800 resets = <&tegra_car 44>; 801 reset-names = "spi"; 802 dmas = <&apbdma 16>, <&apbdma 16>; 803 dma-names = "rx", "tx"; 804 status = "disabled"; 805 }; 806 807 spi@7000d800 { 808 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 809 reg = <0x0 0x7000d800 0x0 0x200>; 810 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 814 clock-names = "spi"; 815 resets = <&tegra_car 46>; 816 reset-names = "spi"; 817 dmas = <&apbdma 17>, <&apbdma 17>; 818 dma-names = "rx", "tx"; 819 status = "disabled"; 820 }; 821 822 spi@7000da00 { 823 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 824 reg = <0x0 0x7000da00 0x0 0x200>; 825 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 829 clock-names = "spi"; 830 resets = <&tegra_car 68>; 831 reset-names = "spi"; 832 dmas = <&apbdma 18>, <&apbdma 18>; 833 dma-names = "rx", "tx"; 834 status = "disabled"; 835 }; 836 837 rtc@7000e000 { 838 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 839 reg = <0x0 0x7000e000 0x0 0x100>; 840 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-parent = <&tegra_pmc>; 842 clocks = <&tegra_car TEGRA210_CLK_RTC>; 843 clock-names = "rtc"; 844 }; 845 846 tegra_pmc: pmc@7000e400 { 847 compatible = "nvidia,tegra210-pmc"; 848 reg = <0x0 0x7000e400 0x0 0x400>; 849 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 850 clock-names = "pclk", "clk32k_in"; 851 #clock-cells = <1>; 852 #interrupt-cells = <2>; 853 interrupt-controller; 854 855 pinmux { 856 pex_dpd_disable: pex-dpd-disable { 857 pins = "pex-bias", "pex-clk1", "pex-clk2"; 858 low-power-disable; 859 }; 860 861 pex_dpd_enable: pex-dpd-enable { 862 pins = "pex-bias", "pex-clk1", "pex-clk2"; 863 low-power-enable; 864 }; 865 866 sdmmc1_1v8: sdmmc1-1v8 { 867 pins = "sdmmc1"; 868 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 869 }; 870 871 sdmmc1_3v3: sdmmc1-3v3 { 872 pins = "sdmmc1"; 873 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 874 }; 875 876 sdmmc3_1v8: sdmmc3-1v8 { 877 pins = "sdmmc3"; 878 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 879 }; 880 881 sdmmc3_3v3: sdmmc3-3v3 { 882 pins = "sdmmc3"; 883 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 884 }; 885 }; 886 887 powergates { 888 pd_audio: aud { 889 clocks = <&tegra_car TEGRA210_CLK_APE>, 890 <&tegra_car TEGRA210_CLK_APB2APE>; 891 resets = <&tegra_car 198>; 892 #power-domain-cells = <0>; 893 }; 894 895 pd_sor: sor { 896 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 897 <&tegra_car TEGRA210_CLK_SOR1>, 898 <&tegra_car TEGRA210_CLK_CILAB>, 899 <&tegra_car TEGRA210_CLK_CILCD>, 900 <&tegra_car TEGRA210_CLK_CILE>, 901 <&tegra_car TEGRA210_CLK_DSIA>, 902 <&tegra_car TEGRA210_CLK_DSIB>, 903 <&tegra_car TEGRA210_CLK_DPAUX>, 904 <&tegra_car TEGRA210_CLK_DPAUX1>, 905 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 906 resets = <&tegra_car TEGRA210_CLK_SOR0>, 907 <&tegra_car TEGRA210_CLK_SOR1>, 908 <&tegra_car TEGRA210_CLK_DSIA>, 909 <&tegra_car TEGRA210_CLK_DSIB>, 910 <&tegra_car TEGRA210_CLK_DPAUX>, 911 <&tegra_car TEGRA210_CLK_DPAUX1>, 912 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 913 #power-domain-cells = <0>; 914 }; 915 916 pd_venc: venc { 917 clocks = <&tegra_car TEGRA210_CLK_VI>, 918 <&tegra_car TEGRA210_CLK_CSI>; 919 resets = <&mc TEGRA210_MC_RESET_VI>, 920 <&tegra_car 20>, 921 <&tegra_car 52>; 922 #power-domain-cells = <0>; 923 }; 924 925 pd_vic: vic { 926 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 927 clock-names = "vic"; 928 resets = <&tegra_car 178>; 929 reset-names = "vic"; 930 #power-domain-cells = <0>; 931 }; 932 933 pd_xusbss: xusba { 934 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 935 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 936 #power-domain-cells = <0>; 937 }; 938 939 pd_xusbdev: xusbb { 940 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 941 resets = <&tegra_car 95>; 942 #power-domain-cells = <0>; 943 }; 944 945 pd_xusbhost: xusbc { 946 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 947 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 948 #power-domain-cells = <0>; 949 }; 950 }; 951 }; 952 953 fuse@7000f800 { 954 compatible = "nvidia,tegra210-efuse"; 955 reg = <0x0 0x7000f800 0x0 0x400>; 956 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 957 clock-names = "fuse"; 958 resets = <&tegra_car 39>; 959 reset-names = "fuse"; 960 }; 961 962 mc: memory-controller@70019000 { 963 compatible = "nvidia,tegra210-mc"; 964 reg = <0x0 0x70019000 0x0 0x1000>; 965 clocks = <&tegra_car TEGRA210_CLK_MC>; 966 clock-names = "mc"; 967 968 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 969 970 #iommu-cells = <1>; 971 #reset-cells = <1>; 972 }; 973 974 emc: external-memory-controller@7001b000 { 975 compatible = "nvidia,tegra210-emc"; 976 reg = <0x0 0x7001b000 0x0 0x1000>, 977 <0x0 0x7001e000 0x0 0x1000>, 978 <0x0 0x7001f000 0x0 0x1000>; 979 clocks = <&tegra_car TEGRA210_CLK_EMC>; 980 clock-names = "emc"; 981 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 982 nvidia,memory-controller = <&mc>; 983 #cooling-cells = <2>; 984 }; 985 986 sata@70020000 { 987 compatible = "nvidia,tegra210-ahci"; 988 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 989 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 990 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 991 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&tegra_car TEGRA210_CLK_SATA>, 993 <&tegra_car TEGRA210_CLK_SATA_OOB>; 994 clock-names = "sata", "sata-oob"; 995 resets = <&tegra_car 124>, 996 <&tegra_car 129>, 997 <&tegra_car 123>; 998 reset-names = "sata", "sata-cold", "sata-oob"; 999 status = "disabled"; 1000 }; 1001 1002 hda@70030000 { 1003 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 1004 reg = <0x0 0x70030000 0x0 0x10000>; 1005 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1007 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1008 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1009 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1010 resets = <&tegra_car 125>, /* hda */ 1011 <&tegra_car 128>, /* hda2hdmi */ 1012 <&tegra_car 111>; /* hda2codec_2x */ 1013 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1014 power-domains = <&pd_sor>; 1015 status = "disabled"; 1016 }; 1017 1018 usb@70090000 { 1019 compatible = "nvidia,tegra210-xusb"; 1020 reg = <0x0 0x70090000 0x0 0x8000>, 1021 <0x0 0x70098000 0x0 0x1000>, 1022 <0x0 0x70099000 0x0 0x1000>; 1023 reg-names = "hcd", "fpci", "ipfs"; 1024 1025 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1027 1028 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1029 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1030 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1031 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1032 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1033 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1034 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1035 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1036 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1037 <&tegra_car TEGRA210_CLK_CLK_M>, 1038 <&tegra_car TEGRA210_CLK_PLL_E>; 1039 clock-names = "xusb_host", "xusb_host_src", 1040 "xusb_falcon_src", "xusb_ss", 1041 "xusb_ss_div2", "xusb_ss_src", 1042 "xusb_hs_src", "xusb_fs_src", 1043 "pll_u_480m", "clk_m", "pll_e"; 1044 resets = <&tegra_car 89>, <&tegra_car 156>, 1045 <&tegra_car 143>; 1046 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1047 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1048 power-domain-names = "xusb_host", "xusb_ss"; 1049 1050 nvidia,xusb-padctl = <&padctl>; 1051 1052 status = "disabled"; 1053 }; 1054 1055 padctl: padctl@7009f000 { 1056 compatible = "nvidia,tegra210-xusb-padctl"; 1057 reg = <0x0 0x7009f000 0x0 0x1000>; 1058 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1059 resets = <&tegra_car 142>; 1060 reset-names = "padctl"; 1061 nvidia,pmc = <&tegra_pmc>; 1062 1063 status = "disabled"; 1064 1065 pads { 1066 usb2 { 1067 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1068 clock-names = "trk"; 1069 status = "disabled"; 1070 1071 lanes { 1072 usb2-0 { 1073 status = "disabled"; 1074 #phy-cells = <0>; 1075 }; 1076 1077 usb2-1 { 1078 status = "disabled"; 1079 #phy-cells = <0>; 1080 }; 1081 1082 usb2-2 { 1083 status = "disabled"; 1084 #phy-cells = <0>; 1085 }; 1086 1087 usb2-3 { 1088 status = "disabled"; 1089 #phy-cells = <0>; 1090 }; 1091 }; 1092 }; 1093 1094 hsic { 1095 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1096 clock-names = "trk"; 1097 status = "disabled"; 1098 1099 lanes { 1100 hsic-0 { 1101 status = "disabled"; 1102 #phy-cells = <0>; 1103 }; 1104 1105 hsic-1 { 1106 status = "disabled"; 1107 #phy-cells = <0>; 1108 }; 1109 }; 1110 }; 1111 1112 pcie { 1113 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1114 clock-names = "pll"; 1115 resets = <&tegra_car 205>; 1116 reset-names = "phy"; 1117 status = "disabled"; 1118 1119 lanes { 1120 pcie-0 { 1121 status = "disabled"; 1122 #phy-cells = <0>; 1123 }; 1124 1125 pcie-1 { 1126 status = "disabled"; 1127 #phy-cells = <0>; 1128 }; 1129 1130 pcie-2 { 1131 status = "disabled"; 1132 #phy-cells = <0>; 1133 }; 1134 1135 pcie-3 { 1136 status = "disabled"; 1137 #phy-cells = <0>; 1138 }; 1139 1140 pcie-4 { 1141 status = "disabled"; 1142 #phy-cells = <0>; 1143 }; 1144 1145 pcie-5 { 1146 status = "disabled"; 1147 #phy-cells = <0>; 1148 }; 1149 1150 pcie-6 { 1151 status = "disabled"; 1152 #phy-cells = <0>; 1153 }; 1154 }; 1155 }; 1156 1157 sata { 1158 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1159 clock-names = "pll"; 1160 resets = <&tegra_car 204>; 1161 reset-names = "phy"; 1162 status = "disabled"; 1163 1164 lanes { 1165 sata-0 { 1166 status = "disabled"; 1167 #phy-cells = <0>; 1168 }; 1169 }; 1170 }; 1171 }; 1172 1173 ports { 1174 usb2-0 { 1175 status = "disabled"; 1176 }; 1177 1178 usb2-1 { 1179 status = "disabled"; 1180 }; 1181 1182 usb2-2 { 1183 status = "disabled"; 1184 }; 1185 1186 usb2-3 { 1187 status = "disabled"; 1188 }; 1189 1190 hsic-0 { 1191 status = "disabled"; 1192 }; 1193 1194 usb3-0 { 1195 status = "disabled"; 1196 }; 1197 1198 usb3-1 { 1199 status = "disabled"; 1200 }; 1201 1202 usb3-2 { 1203 status = "disabled"; 1204 }; 1205 1206 usb3-3 { 1207 status = "disabled"; 1208 }; 1209 }; 1210 }; 1211 1212 mmc@700b0000 { 1213 compatible = "nvidia,tegra210-sdhci"; 1214 reg = <0x0 0x700b0000 0x0 0x200>; 1215 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1217 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1218 clock-names = "sdhci", "tmclk"; 1219 resets = <&tegra_car 14>; 1220 reset-names = "sdhci"; 1221 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1222 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1223 pinctrl-0 = <&sdmmc1_3v3>; 1224 pinctrl-1 = <&sdmmc1_1v8>; 1225 pinctrl-2 = <&sdmmc1_3v3_drv>; 1226 pinctrl-3 = <&sdmmc1_1v8_drv>; 1227 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1228 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1229 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1230 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1231 nvidia,default-tap = <0x2>; 1232 nvidia,default-trim = <0x4>; 1233 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1234 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1235 <&tegra_car TEGRA210_CLK_PLL_C4>; 1236 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1237 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1238 status = "disabled"; 1239 }; 1240 1241 mmc@700b0200 { 1242 compatible = "nvidia,tegra210-sdhci"; 1243 reg = <0x0 0x700b0200 0x0 0x200>; 1244 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1246 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1247 clock-names = "sdhci", "tmclk"; 1248 resets = <&tegra_car 9>; 1249 reset-names = "sdhci"; 1250 pinctrl-names = "sdmmc-1v8-drv"; 1251 pinctrl-0 = <&sdmmc2_1v8_drv>; 1252 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1253 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1254 nvidia,default-tap = <0x8>; 1255 nvidia,default-trim = <0x0>; 1256 status = "disabled"; 1257 }; 1258 1259 mmc@700b0400 { 1260 compatible = "nvidia,tegra210-sdhci"; 1261 reg = <0x0 0x700b0400 0x0 0x200>; 1262 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1264 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1265 clock-names = "sdhci", "tmclk"; 1266 resets = <&tegra_car 69>; 1267 reset-names = "sdhci"; 1268 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1269 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1270 pinctrl-0 = <&sdmmc3_3v3>; 1271 pinctrl-1 = <&sdmmc3_1v8>; 1272 pinctrl-2 = <&sdmmc3_3v3_drv>; 1273 pinctrl-3 = <&sdmmc3_1v8_drv>; 1274 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1275 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1276 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1277 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1278 nvidia,default-tap = <0x3>; 1279 nvidia,default-trim = <0x3>; 1280 status = "disabled"; 1281 }; 1282 1283 mmc@700b0600 { 1284 compatible = "nvidia,tegra210-sdhci"; 1285 reg = <0x0 0x700b0600 0x0 0x200>; 1286 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1288 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1289 clock-names = "sdhci", "tmclk"; 1290 resets = <&tegra_car 15>; 1291 reset-names = "sdhci"; 1292 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1293 pinctrl-0 = <&sdmmc4_1v8_drv>; 1294 pinctrl-1 = <&sdmmc4_1v8_drv>; 1295 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1296 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1297 nvidia,default-tap = <0x8>; 1298 nvidia,default-trim = <0x0>; 1299 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1300 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1301 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1302 nvidia,dqs-trim = <40>; 1303 mmc-hs400-1_8v; 1304 status = "disabled"; 1305 }; 1306 1307 usb@700d0000 { 1308 compatible = "nvidia,tegra210-xudc"; 1309 reg = <0x0 0x700d0000 0x0 0x8000>, 1310 <0x0 0x700d8000 0x0 0x1000>, 1311 <0x0 0x700d9000 0x0 0x1000>; 1312 reg-names = "base", "fpci", "ipfs"; 1313 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1315 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1316 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1317 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1318 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1319 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1320 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1321 power-domain-names = "dev", "ss"; 1322 nvidia,xusb-padctl = <&padctl>; 1323 status = "disabled"; 1324 }; 1325 1326 soctherm: thermal-sensor@700e2000 { 1327 compatible = "nvidia,tegra210-soctherm"; 1328 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1329 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1330 reg-names = "soctherm-reg", "car-reg"; 1331 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1333 interrupt-names = "thermal", "edp"; 1334 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1335 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1336 clock-names = "tsensor", "soctherm"; 1337 resets = <&tegra_car 78>; 1338 reset-names = "soctherm"; 1339 #thermal-sensor-cells = <1>; 1340 1341 throttle-cfgs { 1342 throttle_heavy: heavy { 1343 nvidia,priority = <100>; 1344 nvidia,cpu-throt-percent = <85>; 1345 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1346 1347 #cooling-cells = <2>; 1348 }; 1349 }; 1350 }; 1351 1352 mipi: mipi@700e3000 { 1353 compatible = "nvidia,tegra210-mipi"; 1354 reg = <0x0 0x700e3000 0x0 0x100>; 1355 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1356 clock-names = "mipi-cal"; 1357 power-domains = <&pd_sor>; 1358 #nvidia,mipi-calibrate-cells = <1>; 1359 }; 1360 1361 dfll: clock@70110000 { 1362 compatible = "nvidia,tegra210-dfll"; 1363 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1364 <0 0x70110000 0 0x100>, /* I2C output control */ 1365 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1366 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1367 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1368 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1369 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1370 <&tegra_car TEGRA210_CLK_I2C5>; 1371 clock-names = "soc", "ref", "i2c"; 1372 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1373 <&tegra_car 155>; 1374 reset-names = "dvco", "dfll"; 1375 #clock-cells = <0>; 1376 clock-output-names = "dfllCPU_out"; 1377 status = "disabled"; 1378 }; 1379 1380 aconnect@702c0000 { 1381 compatible = "nvidia,tegra210-aconnect"; 1382 clocks = <&tegra_car TEGRA210_CLK_APE>, 1383 <&tegra_car TEGRA210_CLK_APB2APE>; 1384 clock-names = "ape", "apb2ape"; 1385 power-domains = <&pd_audio>; 1386 #address-cells = <1>; 1387 #size-cells = <1>; 1388 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1389 status = "disabled"; 1390 1391 tegra_ahub: ahub@702d0800 { 1392 compatible = "nvidia,tegra210-ahub"; 1393 reg = <0x702d0800 0x800>; 1394 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1395 clock-names = "ahub"; 1396 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1397 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1398 #address-cells = <1>; 1399 #size-cells = <1>; 1400 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1401 status = "disabled"; 1402 1403 tegra_admaif: admaif@702d0000 { 1404 compatible = "nvidia,tegra210-admaif"; 1405 reg = <0x702d0000 0x800>; 1406 dmas = <&adma 1>, <&adma 1>, 1407 <&adma 2>, <&adma 2>, 1408 <&adma 3>, <&adma 3>, 1409 <&adma 4>, <&adma 4>, 1410 <&adma 5>, <&adma 5>, 1411 <&adma 6>, <&adma 6>, 1412 <&adma 7>, <&adma 7>, 1413 <&adma 8>, <&adma 8>, 1414 <&adma 9>, <&adma 9>, 1415 <&adma 10>, <&adma 10>; 1416 dma-names = "rx1", "tx1", 1417 "rx2", "tx2", 1418 "rx3", "tx3", 1419 "rx4", "tx4", 1420 "rx5", "tx5", 1421 "rx6", "tx6", 1422 "rx7", "tx7", 1423 "rx8", "tx8", 1424 "rx9", "tx9", 1425 "rx10", "tx10"; 1426 status = "disabled"; 1427 1428 ports { 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 1432 admaif1_port: port@0 { 1433 reg = <0>; 1434 1435 admaif1_ep: endpoint { 1436 remote-endpoint = <&xbar_admaif1_ep>; 1437 }; 1438 }; 1439 1440 admaif2_port: port@1 { 1441 reg = <1>; 1442 1443 admaif2_ep: endpoint { 1444 remote-endpoint = <&xbar_admaif2_ep>; 1445 }; 1446 }; 1447 1448 admaif3_port: port@2 { 1449 reg = <2>; 1450 1451 admaif3_ep: endpoint { 1452 remote-endpoint = <&xbar_admaif3_ep>; 1453 }; 1454 }; 1455 1456 admaif4_port: port@3 { 1457 reg = <3>; 1458 1459 admaif4_ep: endpoint { 1460 remote-endpoint = <&xbar_admaif4_ep>; 1461 }; 1462 }; 1463 1464 admaif5_port: port@4 { 1465 reg = <4>; 1466 1467 admaif5_ep: endpoint { 1468 remote-endpoint = <&xbar_admaif5_ep>; 1469 }; 1470 }; 1471 1472 admaif6_port: port@5 { 1473 reg = <5>; 1474 1475 admaif6_ep: endpoint { 1476 remote-endpoint = <&xbar_admaif6_ep>; 1477 }; 1478 }; 1479 1480 admaif7_port: port@6 { 1481 reg = <6>; 1482 1483 admaif7_ep: endpoint { 1484 remote-endpoint = <&xbar_admaif7_ep>; 1485 }; 1486 }; 1487 1488 admaif8_port: port@7 { 1489 reg = <7>; 1490 1491 admaif8_ep: endpoint { 1492 remote-endpoint = <&xbar_admaif8_ep>; 1493 }; 1494 }; 1495 1496 admaif9_port: port@8 { 1497 reg = <8>; 1498 1499 admaif9_ep: endpoint { 1500 remote-endpoint = <&xbar_admaif9_ep>; 1501 }; 1502 }; 1503 1504 admaif10_port: port@9 { 1505 reg = <9>; 1506 1507 admaif10_ep: endpoint { 1508 remote-endpoint = <&xbar_admaif10_ep>; 1509 }; 1510 }; 1511 }; 1512 }; 1513 1514 tegra_i2s1: i2s@702d1000 { 1515 compatible = "nvidia,tegra210-i2s"; 1516 reg = <0x702d1000 0x100>; 1517 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1518 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1519 clock-names = "i2s", "sync_input"; 1520 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1521 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1522 assigned-clock-rates = <1536000>; 1523 sound-name-prefix = "I2S1"; 1524 status = "disabled"; 1525 }; 1526 1527 tegra_i2s2: i2s@702d1100 { 1528 compatible = "nvidia,tegra210-i2s"; 1529 reg = <0x702d1100 0x100>; 1530 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1531 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1532 clock-names = "i2s", "sync_input"; 1533 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1534 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1535 assigned-clock-rates = <1536000>; 1536 sound-name-prefix = "I2S2"; 1537 status = "disabled"; 1538 }; 1539 1540 tegra_i2s3: i2s@702d1200 { 1541 compatible = "nvidia,tegra210-i2s"; 1542 reg = <0x702d1200 0x100>; 1543 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1544 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1545 clock-names = "i2s", "sync_input"; 1546 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1547 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1548 assigned-clock-rates = <1536000>; 1549 sound-name-prefix = "I2S3"; 1550 status = "disabled"; 1551 }; 1552 1553 tegra_i2s4: i2s@702d1300 { 1554 compatible = "nvidia,tegra210-i2s"; 1555 reg = <0x702d1300 0x100>; 1556 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1557 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1558 clock-names = "i2s", "sync_input"; 1559 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1560 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1561 assigned-clock-rates = <1536000>; 1562 sound-name-prefix = "I2S4"; 1563 status = "disabled"; 1564 }; 1565 1566 tegra_i2s5: i2s@702d1400 { 1567 compatible = "nvidia,tegra210-i2s"; 1568 reg = <0x702d1400 0x100>; 1569 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1570 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1571 clock-names = "i2s", "sync_input"; 1572 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1573 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1574 assigned-clock-rates = <1536000>; 1575 sound-name-prefix = "I2S5"; 1576 status = "disabled"; 1577 }; 1578 1579 tegra_sfc1: sfc@702d2000 { 1580 compatible = "nvidia,tegra210-sfc"; 1581 reg = <0x702d2000 0x200>; 1582 sound-name-prefix = "SFC1"; 1583 status = "disabled"; 1584 }; 1585 1586 tegra_sfc2: sfc@702d2200 { 1587 compatible = "nvidia,tegra210-sfc"; 1588 reg = <0x702d2200 0x200>; 1589 sound-name-prefix = "SFC2"; 1590 status = "disabled"; 1591 }; 1592 1593 tegra_sfc3: sfc@702d2400 { 1594 compatible = "nvidia,tegra210-sfc"; 1595 reg = <0x702d2400 0x200>; 1596 sound-name-prefix = "SFC3"; 1597 status = "disabled"; 1598 }; 1599 1600 tegra_sfc4: sfc@702d2600 { 1601 compatible = "nvidia,tegra210-sfc"; 1602 reg = <0x702d2600 0x200>; 1603 sound-name-prefix = "SFC4"; 1604 status = "disabled"; 1605 }; 1606 1607 tegra_amx1: amx@702d3000 { 1608 compatible = "nvidia,tegra210-amx"; 1609 reg = <0x702d3000 0x100>; 1610 sound-name-prefix = "AMX1"; 1611 status = "disabled"; 1612 }; 1613 1614 tegra_amx2: amx@702d3100 { 1615 compatible = "nvidia,tegra210-amx"; 1616 reg = <0x702d3100 0x100>; 1617 sound-name-prefix = "AMX2"; 1618 status = "disabled"; 1619 }; 1620 1621 tegra_adx1: adx@702d3800 { 1622 compatible = "nvidia,tegra210-adx"; 1623 reg = <0x702d3800 0x100>; 1624 sound-name-prefix = "ADX1"; 1625 status = "disabled"; 1626 }; 1627 1628 tegra_adx2: adx@702d3900 { 1629 compatible = "nvidia,tegra210-adx"; 1630 reg = <0x702d3900 0x100>; 1631 sound-name-prefix = "ADX2"; 1632 status = "disabled"; 1633 }; 1634 1635 tegra_dmic1: dmic@702d4000 { 1636 compatible = "nvidia,tegra210-dmic"; 1637 reg = <0x702d4000 0x100>; 1638 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1639 clock-names = "dmic"; 1640 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1641 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1642 assigned-clock-rates = <3072000>; 1643 sound-name-prefix = "DMIC1"; 1644 status = "disabled"; 1645 }; 1646 1647 tegra_dmic2: dmic@702d4100 { 1648 compatible = "nvidia,tegra210-dmic"; 1649 reg = <0x702d4100 0x100>; 1650 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1651 clock-names = "dmic"; 1652 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1653 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1654 assigned-clock-rates = <3072000>; 1655 sound-name-prefix = "DMIC2"; 1656 status = "disabled"; 1657 }; 1658 1659 tegra_dmic3: dmic@702d4200 { 1660 compatible = "nvidia,tegra210-dmic"; 1661 reg = <0x702d4200 0x100>; 1662 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1663 clock-names = "dmic"; 1664 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1665 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1666 assigned-clock-rates = <3072000>; 1667 sound-name-prefix = "DMIC3"; 1668 status = "disabled"; 1669 }; 1670 1671 tegra_ope1: processing-engine@702d8000 { 1672 compatible = "nvidia,tegra210-ope"; 1673 reg = <0x702d8000 0x100>; 1674 #address-cells = <1>; 1675 #size-cells = <1>; 1676 ranges; 1677 sound-name-prefix = "OPE1"; 1678 status = "disabled"; 1679 1680 equalizer@702d8100 { 1681 compatible = "nvidia,tegra210-peq"; 1682 reg = <0x702d8100 0x100>; 1683 }; 1684 1685 dynamic-range-compressor@702d8200 { 1686 compatible = "nvidia,tegra210-mbdrc"; 1687 reg = <0x702d8200 0x200>; 1688 }; 1689 }; 1690 1691 tegra_ope2: processing-engine@702d8400 { 1692 compatible = "nvidia,tegra210-ope"; 1693 reg = <0x702d8400 0x100>; 1694 #address-cells = <1>; 1695 #size-cells = <1>; 1696 ranges; 1697 sound-name-prefix = "OPE2"; 1698 status = "disabled"; 1699 1700 equalizer@702d8500 { 1701 compatible = "nvidia,tegra210-peq"; 1702 reg = <0x702d8500 0x100>; 1703 }; 1704 1705 dynamic-range-compressor@702d8600 { 1706 compatible = "nvidia,tegra210-mbdrc"; 1707 reg = <0x702d8600 0x200>; 1708 }; 1709 }; 1710 1711 tegra_mvc1: mvc@702da000 { 1712 compatible = "nvidia,tegra210-mvc"; 1713 reg = <0x702da000 0x200>; 1714 sound-name-prefix = "MVC1"; 1715 status = "disabled"; 1716 }; 1717 1718 tegra_mvc2: mvc@702da200 { 1719 compatible = "nvidia,tegra210-mvc"; 1720 reg = <0x702da200 0x200>; 1721 sound-name-prefix = "MVC2"; 1722 status = "disabled"; 1723 }; 1724 1725 tegra_amixer: amixer@702dbb00 { 1726 compatible = "nvidia,tegra210-amixer"; 1727 reg = <0x702dbb00 0x800>; 1728 sound-name-prefix = "MIXER1"; 1729 status = "disabled"; 1730 }; 1731 1732 ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 port@0 { 1737 reg = <0x0>; 1738 1739 xbar_admaif1_ep: endpoint { 1740 remote-endpoint = <&admaif1_ep>; 1741 }; 1742 }; 1743 1744 port@1 { 1745 reg = <0x1>; 1746 1747 xbar_admaif2_ep: endpoint { 1748 remote-endpoint = <&admaif2_ep>; 1749 }; 1750 }; 1751 1752 port@2 { 1753 reg = <0x2>; 1754 1755 xbar_admaif3_ep: endpoint { 1756 remote-endpoint = <&admaif3_ep>; 1757 }; 1758 }; 1759 1760 port@3 { 1761 reg = <0x3>; 1762 1763 xbar_admaif4_ep: endpoint { 1764 remote-endpoint = <&admaif4_ep>; 1765 }; 1766 }; 1767 1768 port@4 { 1769 reg = <0x4>; 1770 xbar_admaif5_ep: endpoint { 1771 remote-endpoint = <&admaif5_ep>; 1772 }; 1773 }; 1774 port@5 { 1775 reg = <0x5>; 1776 1777 xbar_admaif6_ep: endpoint { 1778 remote-endpoint = <&admaif6_ep>; 1779 }; 1780 }; 1781 1782 port@6 { 1783 reg = <0x6>; 1784 1785 xbar_admaif7_ep: endpoint { 1786 remote-endpoint = <&admaif7_ep>; 1787 }; 1788 }; 1789 1790 port@7 { 1791 reg = <0x7>; 1792 1793 xbar_admaif8_ep: endpoint { 1794 remote-endpoint = <&admaif8_ep>; 1795 }; 1796 }; 1797 1798 port@8 { 1799 reg = <0x8>; 1800 1801 xbar_admaif9_ep: endpoint { 1802 remote-endpoint = <&admaif9_ep>; 1803 }; 1804 }; 1805 1806 port@9 { 1807 reg = <0x9>; 1808 1809 xbar_admaif10_ep: endpoint { 1810 remote-endpoint = <&admaif10_ep>; 1811 }; 1812 }; 1813 }; 1814 }; 1815 1816 adma: dma-controller@702e2000 { 1817 compatible = "nvidia,tegra210-adma"; 1818 reg = <0x702e2000 0x2000>; 1819 interrupt-parent = <&agic>; 1820 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1842 #dma-cells = <1>; 1843 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1844 clock-names = "d_audio"; 1845 status = "disabled"; 1846 }; 1847 1848 agic: interrupt-controller@702f9000 { 1849 compatible = "nvidia,tegra210-agic"; 1850 #interrupt-cells = <3>; 1851 interrupt-controller; 1852 reg = <0x702f9000 0x1000>, 1853 <0x702fa000 0x2000>; 1854 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1855 clocks = <&tegra_car TEGRA210_CLK_APE>; 1856 clock-names = "clk"; 1857 status = "disabled"; 1858 }; 1859 }; 1860 1861 spi@70410000 { 1862 compatible = "nvidia,tegra210-qspi"; 1863 reg = <0x0 0x70410000 0x0 0x1000>; 1864 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1868 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1869 clock-names = "qspi", "qspi_out"; 1870 resets = <&tegra_car 211>; 1871 dmas = <&apbdma 5>, <&apbdma 5>; 1872 dma-names = "rx", "tx"; 1873 status = "disabled"; 1874 }; 1875 1876 usb@7d000000 { 1877 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1878 reg = <0x0 0x7d000000 0x0 0x4000>; 1879 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1880 phy_type = "utmi"; 1881 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1882 clock-names = "usb"; 1883 resets = <&tegra_car 22>; 1884 reset-names = "usb"; 1885 nvidia,phy = <&phy1>; 1886 status = "disabled"; 1887 }; 1888 1889 phy1: usb-phy@7d000000 { 1890 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1891 reg = <0x0 0x7d000000 0x0 0x4000>, 1892 <0x0 0x7d000000 0x0 0x4000>; 1893 phy_type = "utmi"; 1894 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1895 <&tegra_car TEGRA210_CLK_PLL_U>, 1896 <&tegra_car TEGRA210_CLK_USBD>; 1897 clock-names = "reg", "pll_u", "utmi-pads"; 1898 resets = <&tegra_car 22>, <&tegra_car 22>; 1899 reset-names = "usb", "utmi-pads"; 1900 nvidia,hssync-start-delay = <0>; 1901 nvidia,idle-wait-delay = <17>; 1902 nvidia,elastic-limit = <16>; 1903 nvidia,term-range-adj = <6>; 1904 nvidia,xcvr-setup = <9>; 1905 nvidia,xcvr-lsfslew = <0>; 1906 nvidia,xcvr-lsrslew = <3>; 1907 nvidia,hssquelch-level = <2>; 1908 nvidia,hsdiscon-level = <5>; 1909 nvidia,xcvr-hsslew = <12>; 1910 nvidia,has-utmi-pad-registers; 1911 status = "disabled"; 1912 }; 1913 1914 usb@7d004000 { 1915 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1916 reg = <0x0 0x7d004000 0x0 0x4000>; 1917 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1918 phy_type = "utmi"; 1919 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1920 clock-names = "usb"; 1921 resets = <&tegra_car 58>; 1922 reset-names = "usb"; 1923 nvidia,phy = <&phy2>; 1924 status = "disabled"; 1925 }; 1926 1927 phy2: usb-phy@7d004000 { 1928 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1929 reg = <0x0 0x7d004000 0x0 0x4000>, 1930 <0x0 0x7d000000 0x0 0x4000>; 1931 phy_type = "utmi"; 1932 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1933 <&tegra_car TEGRA210_CLK_PLL_U>, 1934 <&tegra_car TEGRA210_CLK_USBD>; 1935 clock-names = "reg", "pll_u", "utmi-pads"; 1936 resets = <&tegra_car 58>, <&tegra_car 22>; 1937 reset-names = "usb", "utmi-pads"; 1938 nvidia,hssync-start-delay = <0>; 1939 nvidia,idle-wait-delay = <17>; 1940 nvidia,elastic-limit = <16>; 1941 nvidia,term-range-adj = <6>; 1942 nvidia,xcvr-setup = <9>; 1943 nvidia,xcvr-lsfslew = <0>; 1944 nvidia,xcvr-lsrslew = <3>; 1945 nvidia,hssquelch-level = <2>; 1946 nvidia,hsdiscon-level = <5>; 1947 nvidia,xcvr-hsslew = <12>; 1948 status = "disabled"; 1949 }; 1950 1951 cpus { 1952 #address-cells = <1>; 1953 #size-cells = <0>; 1954 1955 cpu@0 { 1956 device_type = "cpu"; 1957 compatible = "arm,cortex-a57"; 1958 reg = <0>; 1959 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1960 <&tegra_car TEGRA210_CLK_PLL_X>, 1961 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1962 <&dfll>; 1963 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1964 clock-latency = <300000>; 1965 cpu-idle-states = <&CPU_SLEEP>; 1966 next-level-cache = <&L2>; 1967 }; 1968 1969 cpu@1 { 1970 device_type = "cpu"; 1971 compatible = "arm,cortex-a57"; 1972 reg = <1>; 1973 cpu-idle-states = <&CPU_SLEEP>; 1974 next-level-cache = <&L2>; 1975 }; 1976 1977 cpu@2 { 1978 device_type = "cpu"; 1979 compatible = "arm,cortex-a57"; 1980 reg = <2>; 1981 cpu-idle-states = <&CPU_SLEEP>; 1982 next-level-cache = <&L2>; 1983 }; 1984 1985 cpu@3 { 1986 device_type = "cpu"; 1987 compatible = "arm,cortex-a57"; 1988 reg = <3>; 1989 cpu-idle-states = <&CPU_SLEEP>; 1990 next-level-cache = <&L2>; 1991 }; 1992 1993 idle-states { 1994 entry-method = "psci"; 1995 1996 CPU_SLEEP: cpu-sleep { 1997 compatible = "arm,idle-state"; 1998 arm,psci-suspend-param = <0x40000007>; 1999 entry-latency-us = <100>; 2000 exit-latency-us = <30>; 2001 min-residency-us = <1000>; 2002 wakeup-latency-us = <130>; 2003 idle-state-name = "cpu-sleep"; 2004 status = "disabled"; 2005 }; 2006 }; 2007 2008 L2: l2-cache { 2009 compatible = "cache"; 2010 cache-level = <2>; 2011 }; 2012 }; 2013 2014 pmu { 2015 compatible = "arm,armv8-pmuv3"; 2016 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2020 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2021 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2022 }; 2023 2024 sound { 2025 status = "disabled"; 2026 2027 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2028 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2029 clock-names = "pll_a", "plla_out0"; 2030 2031 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2032 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2033 <&tegra_car TEGRA210_CLK_EXTERN1>; 2034 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2035 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2036 }; 2037 2038 thermal-zones { 2039 cpu-thermal { 2040 polling-delay-passive = <1000>; 2041 polling-delay = <0>; 2042 2043 thermal-sensors = 2044 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2045 2046 trips { 2047 cpu-shutdown-trip { 2048 temperature = <102500>; 2049 hysteresis = <0>; 2050 type = "critical"; 2051 }; 2052 2053 cpu_throttle_trip: throttle-trip { 2054 temperature = <98500>; 2055 hysteresis = <1000>; 2056 type = "hot"; 2057 }; 2058 }; 2059 2060 cooling-maps { 2061 map0 { 2062 trip = <&cpu_throttle_trip>; 2063 cooling-device = <&throttle_heavy 1 1>; 2064 }; 2065 }; 2066 }; 2067 2068 mem-thermal { 2069 polling-delay-passive = <0>; 2070 polling-delay = <0>; 2071 2072 thermal-sensors = 2073 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2074 2075 trips { 2076 dram_nominal: mem-nominal-trip { 2077 temperature = <50000>; 2078 hysteresis = <1000>; 2079 type = "passive"; 2080 }; 2081 2082 dram_throttle: mem-throttle-trip { 2083 temperature = <70000>; 2084 hysteresis = <1000>; 2085 type = "active"; 2086 }; 2087 2088 mem-hot-trip { 2089 temperature = <100000>; 2090 hysteresis = <1000>; 2091 type = "hot"; 2092 }; 2093 2094 mem-shutdown-trip { 2095 temperature = <103000>; 2096 hysteresis = <0>; 2097 type = "critical"; 2098 }; 2099 }; 2100 2101 cooling-maps { 2102 dram-passive { 2103 cooling-device = <&emc 0 0>; 2104 trip = <&dram_nominal>; 2105 }; 2106 2107 dram-active { 2108 cooling-device = <&emc 1 1>; 2109 trip = <&dram_throttle>; 2110 }; 2111 }; 2112 }; 2113 2114 gpu-thermal { 2115 polling-delay-passive = <1000>; 2116 polling-delay = <0>; 2117 2118 thermal-sensors = 2119 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2120 2121 trips { 2122 gpu-shutdown-trip { 2123 temperature = <103000>; 2124 hysteresis = <0>; 2125 type = "critical"; 2126 }; 2127 2128 gpu_throttle_trip: throttle-trip { 2129 temperature = <100000>; 2130 hysteresis = <1000>; 2131 type = "hot"; 2132 }; 2133 }; 2134 2135 cooling-maps { 2136 map0 { 2137 trip = <&gpu_throttle_trip>; 2138 cooling-device = <&throttle_heavy 1 1>; 2139 }; 2140 }; 2141 }; 2142 2143 pllx-thermal { 2144 polling-delay-passive = <0>; 2145 polling-delay = <0>; 2146 2147 thermal-sensors = 2148 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2149 2150 trips { 2151 pllx-shutdown-trip { 2152 temperature = <103000>; 2153 hysteresis = <0>; 2154 type = "critical"; 2155 }; 2156 2157 pllx-throttle-trip { 2158 temperature = <100000>; 2159 hysteresis = <1000>; 2160 type = "hot"; 2161 }; 2162 }; 2163 2164 cooling-maps { 2165 /* 2166 * There are currently no cooling maps, 2167 * because there are no cooling devices. 2168 */ 2169 }; 2170 }; 2171 }; 2172 2173 timer { 2174 compatible = "arm,armv8-timer"; 2175 interrupts = <GIC_PPI 13 2176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2177 <GIC_PPI 14 2178 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2179 <GIC_PPI 11 2180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2181 <GIC_PPI 10 2182 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2183 interrupt-parent = <&gic>; 2184 arm,no-tick-in-suspend; 2185 }; 2186}; 2187