1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/thermal/tegra124-soctherm.h> 7 8/ { 9 compatible = "nvidia,tegra210"; 10 interrupt-parent = <&lic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 host1x@50000000 { 15 compatible = "nvidia,tegra210-host1x", "simple-bus"; 16 reg = <0x0 0x50000000 0x0 0x00034000>; 17 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 18 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 19 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 20 clock-names = "host1x"; 21 resets = <&tegra_car 28>; 22 reset-names = "host1x"; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 28 29 dpaux1: dpaux@54040000 { 30 compatible = "nvidia,tegra210-dpaux"; 31 reg = <0x0 0x54040000 0x0 0x00040000>; 32 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 33 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 34 <&tegra_car TEGRA210_CLK_PLL_DP>; 35 clock-names = "dpaux", "parent"; 36 resets = <&tegra_car 207>; 37 reset-names = "dpaux"; 38 power-domains = <&pd_sor>; 39 status = "disabled"; 40 41 state_dpaux1_aux: pinmux-aux { 42 groups = "dpaux-io"; 43 function = "aux"; 44 }; 45 46 state_dpaux1_i2c: pinmux-i2c { 47 groups = "dpaux-io"; 48 function = "i2c"; 49 }; 50 51 state_dpaux1_off: pinmux-off { 52 groups = "dpaux-io"; 53 function = "off"; 54 }; 55 56 i2c-bus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 }; 60 }; 61 62 vi@54080000 { 63 compatible = "nvidia,tegra210-vi"; 64 reg = <0x0 0x54080000 0x0 0x00040000>; 65 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 66 status = "disabled"; 67 }; 68 69 tsec@54100000 { 70 compatible = "nvidia,tegra210-tsec"; 71 reg = <0x0 0x54100000 0x0 0x00040000>; 72 }; 73 74 dc@54200000 { 75 compatible = "nvidia,tegra210-dc"; 76 reg = <0x0 0x54200000 0x0 0x00040000>; 77 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 79 <&tegra_car TEGRA210_CLK_PLL_P>; 80 clock-names = "dc", "parent"; 81 resets = <&tegra_car 27>; 82 reset-names = "dc"; 83 84 iommus = <&mc TEGRA_SWGROUP_DC>; 85 86 nvidia,head = <0>; 87 }; 88 89 dc@54240000 { 90 compatible = "nvidia,tegra210-dc"; 91 reg = <0x0 0x54240000 0x0 0x00040000>; 92 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 93 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 94 <&tegra_car TEGRA210_CLK_PLL_P>; 95 clock-names = "dc", "parent"; 96 resets = <&tegra_car 26>; 97 reset-names = "dc"; 98 99 iommus = <&mc TEGRA_SWGROUP_DCB>; 100 101 nvidia,head = <1>; 102 }; 103 104 dsi@54300000 { 105 compatible = "nvidia,tegra210-dsi"; 106 reg = <0x0 0x54300000 0x0 0x00040000>; 107 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 108 <&tegra_car TEGRA210_CLK_DSIALP>, 109 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 110 clock-names = "dsi", "lp", "parent"; 111 resets = <&tegra_car 48>; 112 reset-names = "dsi"; 113 power-domains = <&pd_sor>; 114 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 115 116 status = "disabled"; 117 118 #address-cells = <1>; 119 #size-cells = <0>; 120 }; 121 122 vic@54340000 { 123 compatible = "nvidia,tegra210-vic"; 124 reg = <0x0 0x54340000 0x0 0x00040000>; 125 status = "disabled"; 126 }; 127 128 nvjpg@54380000 { 129 compatible = "nvidia,tegra210-nvjpg"; 130 reg = <0x0 0x54380000 0x0 0x00040000>; 131 status = "disabled"; 132 }; 133 134 dsi@54400000 { 135 compatible = "nvidia,tegra210-dsi"; 136 reg = <0x0 0x54400000 0x0 0x00040000>; 137 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 138 <&tegra_car TEGRA210_CLK_DSIBLP>, 139 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 140 clock-names = "dsi", "lp", "parent"; 141 resets = <&tegra_car 82>; 142 reset-names = "dsi"; 143 power-domains = <&pd_sor>; 144 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 145 146 status = "disabled"; 147 148 #address-cells = <1>; 149 #size-cells = <0>; 150 }; 151 152 nvdec@54480000 { 153 compatible = "nvidia,tegra210-nvdec"; 154 reg = <0x0 0x54480000 0x0 0x00040000>; 155 status = "disabled"; 156 }; 157 158 nvenc@544c0000 { 159 compatible = "nvidia,tegra210-nvenc"; 160 reg = <0x0 0x544c0000 0x0 0x00040000>; 161 status = "disabled"; 162 }; 163 164 tsec@54500000 { 165 compatible = "nvidia,tegra210-tsec"; 166 reg = <0x0 0x54500000 0x0 0x00040000>; 167 status = "disabled"; 168 }; 169 170 sor@54540000 { 171 compatible = "nvidia,tegra210-sor"; 172 reg = <0x0 0x54540000 0x0 0x00040000>; 173 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 175 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 176 <&tegra_car TEGRA210_CLK_PLL_DP>, 177 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 178 clock-names = "sor", "parent", "dp", "safe"; 179 resets = <&tegra_car 182>; 180 reset-names = "sor"; 181 pinctrl-0 = <&state_dpaux_aux>; 182 pinctrl-1 = <&state_dpaux_i2c>; 183 pinctrl-2 = <&state_dpaux_off>; 184 pinctrl-names = "aux", "i2c", "off"; 185 power-domains = <&pd_sor>; 186 status = "disabled"; 187 }; 188 189 sor@54580000 { 190 compatible = "nvidia,tegra210-sor1"; 191 reg = <0x0 0x54580000 0x0 0x00040000>; 192 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 194 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 195 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 196 <&tegra_car TEGRA210_CLK_PLL_DP>, 197 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 198 clock-names = "sor", "source", "parent", "dp", "safe"; 199 resets = <&tegra_car 183>; 200 reset-names = "sor"; 201 pinctrl-0 = <&state_dpaux1_aux>; 202 pinctrl-1 = <&state_dpaux1_i2c>; 203 pinctrl-2 = <&state_dpaux1_off>; 204 pinctrl-names = "aux", "i2c", "off"; 205 power-domains = <&pd_sor>; 206 status = "disabled"; 207 }; 208 209 dpaux: dpaux@545c0000 { 210 compatible = "nvidia,tegra124-dpaux"; 211 reg = <0x0 0x545c0000 0x0 0x00040000>; 212 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 214 <&tegra_car TEGRA210_CLK_PLL_DP>; 215 clock-names = "dpaux", "parent"; 216 resets = <&tegra_car 181>; 217 reset-names = "dpaux"; 218 power-domains = <&pd_sor>; 219 status = "disabled"; 220 221 state_dpaux_aux: pinmux-aux { 222 groups = "dpaux-io"; 223 function = "aux"; 224 }; 225 226 state_dpaux_i2c: pinmux-i2c { 227 groups = "dpaux-io"; 228 function = "i2c"; 229 }; 230 231 state_dpaux_off: pinmux-off { 232 groups = "dpaux-io"; 233 function = "off"; 234 }; 235 236 i2c-bus { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 }; 240 }; 241 242 isp@54600000 { 243 compatible = "nvidia,tegra210-isp"; 244 reg = <0x0 0x54600000 0x0 0x00040000>; 245 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 246 status = "disabled"; 247 }; 248 249 isp@54680000 { 250 compatible = "nvidia,tegra210-isp"; 251 reg = <0x0 0x54680000 0x0 0x00040000>; 252 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 253 status = "disabled"; 254 }; 255 256 i2c@546c0000 { 257 compatible = "nvidia,tegra210-i2c-vi"; 258 reg = <0x0 0x546c0000 0x0 0x00040000>; 259 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 260 status = "disabled"; 261 }; 262 }; 263 264 gic: interrupt-controller@50041000 { 265 compatible = "arm,gic-400"; 266 #interrupt-cells = <3>; 267 interrupt-controller; 268 reg = <0x0 0x50041000 0x0 0x1000>, 269 <0x0 0x50042000 0x0 0x2000>, 270 <0x0 0x50044000 0x0 0x2000>, 271 <0x0 0x50046000 0x0 0x2000>; 272 interrupts = <GIC_PPI 9 273 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 274 interrupt-parent = <&gic>; 275 }; 276 277 gpu@57000000 { 278 compatible = "nvidia,gm20b"; 279 reg = <0x0 0x57000000 0x0 0x01000000>, 280 <0x0 0x58000000 0x0 0x01000000>; 281 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "stall", "nonstall"; 284 clocks = <&tegra_car TEGRA210_CLK_GPU>, 285 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 286 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 287 clock-names = "gpu", "pwr", "ref"; 288 resets = <&tegra_car 184>; 289 reset-names = "gpu"; 290 291 iommus = <&mc TEGRA_SWGROUP_GPU>; 292 293 status = "disabled"; 294 }; 295 296 lic: interrupt-controller@60004000 { 297 compatible = "nvidia,tegra210-ictlr"; 298 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 299 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 300 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 301 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 302 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 303 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 304 interrupt-controller; 305 #interrupt-cells = <3>; 306 interrupt-parent = <&gic>; 307 }; 308 309 timer@60005000 { 310 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 311 reg = <0x0 0x60005000 0x0 0x400>; 312 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 319 clock-names = "timer"; 320 }; 321 322 tegra_car: clock@60006000 { 323 compatible = "nvidia,tegra210-car"; 324 reg = <0x0 0x60006000 0x0 0x1000>; 325 #clock-cells = <1>; 326 #reset-cells = <1>; 327 }; 328 329 flow-controller@60007000 { 330 compatible = "nvidia,tegra210-flowctrl"; 331 reg = <0x0 0x60007000 0x0 0x1000>; 332 }; 333 334 gpio: gpio@6000d000 { 335 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 336 reg = <0x0 0x6000d000 0x0 0x1000>; 337 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 345 #gpio-cells = <2>; 346 gpio-controller; 347 #interrupt-cells = <2>; 348 interrupt-controller; 349 }; 350 351 apbdma: dma@60020000 { 352 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 353 reg = <0x0 0x60020000 0x0 0x1400>; 354 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 387 clock-names = "dma"; 388 resets = <&tegra_car 34>; 389 reset-names = "dma"; 390 #dma-cells = <1>; 391 }; 392 393 apbmisc@70000800 { 394 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 395 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 396 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 397 }; 398 399 pinmux: pinmux@700008d4 { 400 compatible = "nvidia,tegra210-pinmux"; 401 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 402 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 403 }; 404 405 /* 406 * There are two serial driver i.e. 8250 based simple serial 407 * driver and APB DMA based serial driver for higher baudrate 408 * and performance. To enable the 8250 based driver, the compatible 409 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 410 * the APB DMA based serial driver, the compatible is 411 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 412 */ 413 uarta: serial@70006000 { 414 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 415 reg = <0x0 0x70006000 0x0 0x40>; 416 reg-shift = <2>; 417 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 419 clock-names = "serial"; 420 resets = <&tegra_car 6>; 421 reset-names = "serial"; 422 dmas = <&apbdma 8>, <&apbdma 8>; 423 dma-names = "rx", "tx"; 424 status = "disabled"; 425 }; 426 427 uartb: serial@70006040 { 428 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 429 reg = <0x0 0x70006040 0x0 0x40>; 430 reg-shift = <2>; 431 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 433 clock-names = "serial"; 434 resets = <&tegra_car 7>; 435 reset-names = "serial"; 436 dmas = <&apbdma 9>, <&apbdma 9>; 437 dma-names = "rx", "tx"; 438 status = "disabled"; 439 }; 440 441 uartc: serial@70006200 { 442 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 443 reg = <0x0 0x70006200 0x0 0x40>; 444 reg-shift = <2>; 445 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 447 clock-names = "serial"; 448 resets = <&tegra_car 55>; 449 reset-names = "serial"; 450 dmas = <&apbdma 10>, <&apbdma 10>; 451 dma-names = "rx", "tx"; 452 status = "disabled"; 453 }; 454 455 uartd: serial@70006300 { 456 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 457 reg = <0x0 0x70006300 0x0 0x40>; 458 reg-shift = <2>; 459 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 461 clock-names = "serial"; 462 resets = <&tegra_car 65>; 463 reset-names = "serial"; 464 dmas = <&apbdma 19>, <&apbdma 19>; 465 dma-names = "rx", "tx"; 466 status = "disabled"; 467 }; 468 469 pwm: pwm@7000a000 { 470 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 471 reg = <0x0 0x7000a000 0x0 0x100>; 472 #pwm-cells = <2>; 473 clocks = <&tegra_car TEGRA210_CLK_PWM>; 474 clock-names = "pwm"; 475 resets = <&tegra_car 17>; 476 reset-names = "pwm"; 477 status = "disabled"; 478 }; 479 480 i2c@7000c000 { 481 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 482 reg = <0x0 0x7000c000 0x0 0x100>; 483 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 487 clock-names = "div-clk"; 488 resets = <&tegra_car 12>; 489 reset-names = "i2c"; 490 dmas = <&apbdma 21>, <&apbdma 21>; 491 dma-names = "rx", "tx"; 492 status = "disabled"; 493 }; 494 495 i2c@7000c400 { 496 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 497 reg = <0x0 0x7000c400 0x0 0x100>; 498 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 502 clock-names = "div-clk"; 503 resets = <&tegra_car 54>; 504 reset-names = "i2c"; 505 dmas = <&apbdma 22>, <&apbdma 22>; 506 dma-names = "rx", "tx"; 507 status = "disabled"; 508 }; 509 510 i2c@7000c500 { 511 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 512 reg = <0x0 0x7000c500 0x0 0x100>; 513 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 517 clock-names = "div-clk"; 518 resets = <&tegra_car 67>; 519 reset-names = "i2c"; 520 dmas = <&apbdma 23>, <&apbdma 23>; 521 dma-names = "rx", "tx"; 522 status = "disabled"; 523 }; 524 525 i2c@7000c700 { 526 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 527 reg = <0x0 0x7000c700 0x0 0x100>; 528 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 532 clock-names = "div-clk"; 533 resets = <&tegra_car 103>; 534 reset-names = "i2c"; 535 dmas = <&apbdma 26>, <&apbdma 26>; 536 dma-names = "rx", "tx"; 537 pinctrl-0 = <&state_dpaux1_i2c>; 538 pinctrl-1 = <&state_dpaux1_off>; 539 pinctrl-names = "default", "idle"; 540 status = "disabled"; 541 }; 542 543 i2c@7000d000 { 544 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 545 reg = <0x0 0x7000d000 0x0 0x100>; 546 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 550 clock-names = "div-clk"; 551 resets = <&tegra_car 47>; 552 reset-names = "i2c"; 553 dmas = <&apbdma 24>, <&apbdma 24>; 554 dma-names = "rx", "tx"; 555 status = "disabled"; 556 }; 557 558 i2c@7000d100 { 559 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 560 reg = <0x0 0x7000d100 0x0 0x100>; 561 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 565 clock-names = "div-clk"; 566 resets = <&tegra_car 166>; 567 reset-names = "i2c"; 568 dmas = <&apbdma 30>, <&apbdma 30>; 569 dma-names = "rx", "tx"; 570 pinctrl-0 = <&state_dpaux_i2c>; 571 pinctrl-1 = <&state_dpaux_off>; 572 pinctrl-names = "default", "idle"; 573 status = "disabled"; 574 }; 575 576 spi@7000d400 { 577 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 578 reg = <0x0 0x7000d400 0x0 0x200>; 579 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 583 clock-names = "spi"; 584 resets = <&tegra_car 41>; 585 reset-names = "spi"; 586 dmas = <&apbdma 15>, <&apbdma 15>; 587 dma-names = "rx", "tx"; 588 status = "disabled"; 589 }; 590 591 spi@7000d600 { 592 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 593 reg = <0x0 0x7000d600 0x0 0x200>; 594 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 598 clock-names = "spi"; 599 resets = <&tegra_car 44>; 600 reset-names = "spi"; 601 dmas = <&apbdma 16>, <&apbdma 16>; 602 dma-names = "rx", "tx"; 603 status = "disabled"; 604 }; 605 606 spi@7000d800 { 607 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 608 reg = <0x0 0x7000d800 0x0 0x200>; 609 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 613 clock-names = "spi"; 614 resets = <&tegra_car 46>; 615 reset-names = "spi"; 616 dmas = <&apbdma 17>, <&apbdma 17>; 617 dma-names = "rx", "tx"; 618 status = "disabled"; 619 }; 620 621 spi@7000da00 { 622 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 623 reg = <0x0 0x7000da00 0x0 0x200>; 624 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 628 clock-names = "spi"; 629 resets = <&tegra_car 68>; 630 reset-names = "spi"; 631 dmas = <&apbdma 18>, <&apbdma 18>; 632 dma-names = "rx", "tx"; 633 status = "disabled"; 634 }; 635 636 rtc@7000e000 { 637 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 638 reg = <0x0 0x7000e000 0x0 0x100>; 639 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&tegra_car TEGRA210_CLK_RTC>; 641 clock-names = "rtc"; 642 }; 643 644 pmc: pmc@7000e400 { 645 compatible = "nvidia,tegra210-pmc"; 646 reg = <0x0 0x7000e400 0x0 0x400>; 647 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 648 clock-names = "pclk", "clk32k_in"; 649 650 powergates { 651 pd_audio: aud { 652 clocks = <&tegra_car TEGRA210_CLK_APE>, 653 <&tegra_car TEGRA210_CLK_APB2APE>; 654 resets = <&tegra_car 198>; 655 #power-domain-cells = <0>; 656 }; 657 658 pd_sor: sor { 659 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 660 <&tegra_car TEGRA210_CLK_SOR1>, 661 <&tegra_car TEGRA210_CLK_CSI>, 662 <&tegra_car TEGRA210_CLK_DSIA>, 663 <&tegra_car TEGRA210_CLK_DSIB>, 664 <&tegra_car TEGRA210_CLK_DPAUX>, 665 <&tegra_car TEGRA210_CLK_DPAUX1>, 666 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 667 resets = <&tegra_car TEGRA210_CLK_SOR0>, 668 <&tegra_car TEGRA210_CLK_SOR1>, 669 <&tegra_car TEGRA210_CLK_CSI>, 670 <&tegra_car TEGRA210_CLK_DSIA>, 671 <&tegra_car TEGRA210_CLK_DSIB>, 672 <&tegra_car TEGRA210_CLK_DPAUX>, 673 <&tegra_car TEGRA210_CLK_DPAUX1>, 674 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 675 #power-domain-cells = <0>; 676 }; 677 678 pd_xusbss: xusba { 679 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 680 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 681 #power-domain-cells = <0>; 682 }; 683 684 pd_xusbdev: xusbb { 685 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 686 resets = <&tegra_car 95>; 687 #power-domain-cells = <0>; 688 }; 689 690 pd_xusbhost: xusbc { 691 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 692 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 693 #power-domain-cells = <0>; 694 }; 695 }; 696 }; 697 698 fuse@7000f800 { 699 compatible = "nvidia,tegra210-efuse"; 700 reg = <0x0 0x7000f800 0x0 0x400>; 701 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 702 clock-names = "fuse"; 703 resets = <&tegra_car 39>; 704 reset-names = "fuse"; 705 }; 706 707 mc: memory-controller@70019000 { 708 compatible = "nvidia,tegra210-mc"; 709 reg = <0x0 0x70019000 0x0 0x1000>; 710 clocks = <&tegra_car TEGRA210_CLK_MC>; 711 clock-names = "mc"; 712 713 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 714 715 #iommu-cells = <1>; 716 }; 717 718 hda@70030000 { 719 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 720 reg = <0x0 0x70030000 0x0 0x10000>; 721 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&tegra_car TEGRA210_CLK_HDA>, 723 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 724 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 725 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 726 resets = <&tegra_car 125>, /* hda */ 727 <&tegra_car 128>, /* hda2hdmi */ 728 <&tegra_car 111>; /* hda2codec_2x */ 729 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 730 status = "disabled"; 731 }; 732 733 usb@70090000 { 734 compatible = "nvidia,tegra210-xusb"; 735 reg = <0x0 0x70090000 0x0 0x8000>, 736 <0x0 0x70098000 0x0 0x1000>, 737 <0x0 0x70099000 0x0 0x1000>; 738 reg-names = "hcd", "fpci", "ipfs"; 739 740 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 742 743 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 744 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 745 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 746 <&tegra_car TEGRA210_CLK_XUSB_SS>, 747 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 748 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 749 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 750 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 751 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 752 <&tegra_car TEGRA210_CLK_CLK_M>, 753 <&tegra_car TEGRA210_CLK_PLL_E>; 754 clock-names = "xusb_host", "xusb_host_src", 755 "xusb_falcon_src", "xusb_ss", 756 "xusb_ss_div2", "xusb_ss_src", 757 "xusb_hs_src", "xusb_fs_src", 758 "pll_u_480m", "clk_m", "pll_e"; 759 resets = <&tegra_car 89>, <&tegra_car 156>, 760 <&tegra_car 143>; 761 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 762 763 nvidia,xusb-padctl = <&padctl>; 764 765 status = "disabled"; 766 }; 767 768 padctl: padctl@7009f000 { 769 compatible = "nvidia,tegra210-xusb-padctl"; 770 reg = <0x0 0x7009f000 0x0 0x1000>; 771 resets = <&tegra_car 142>; 772 reset-names = "padctl"; 773 774 status = "disabled"; 775 776 pads { 777 usb2 { 778 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 779 clock-names = "trk"; 780 status = "disabled"; 781 782 lanes { 783 usb2-0 { 784 status = "disabled"; 785 #phy-cells = <0>; 786 }; 787 788 usb2-1 { 789 status = "disabled"; 790 #phy-cells = <0>; 791 }; 792 793 usb2-2 { 794 status = "disabled"; 795 #phy-cells = <0>; 796 }; 797 798 usb2-3 { 799 status = "disabled"; 800 #phy-cells = <0>; 801 }; 802 }; 803 }; 804 805 hsic { 806 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 807 clock-names = "trk"; 808 status = "disabled"; 809 810 lanes { 811 hsic-0 { 812 status = "disabled"; 813 #phy-cells = <0>; 814 }; 815 816 hsic-1 { 817 status = "disabled"; 818 #phy-cells = <0>; 819 }; 820 }; 821 }; 822 823 pcie { 824 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 825 clock-names = "pll"; 826 resets = <&tegra_car 205>; 827 reset-names = "phy"; 828 status = "disabled"; 829 830 lanes { 831 pcie-0 { 832 status = "disabled"; 833 #phy-cells = <0>; 834 }; 835 836 pcie-1 { 837 status = "disabled"; 838 #phy-cells = <0>; 839 }; 840 841 pcie-2 { 842 status = "disabled"; 843 #phy-cells = <0>; 844 }; 845 846 pcie-3 { 847 status = "disabled"; 848 #phy-cells = <0>; 849 }; 850 851 pcie-4 { 852 status = "disabled"; 853 #phy-cells = <0>; 854 }; 855 856 pcie-5 { 857 status = "disabled"; 858 #phy-cells = <0>; 859 }; 860 861 pcie-6 { 862 status = "disabled"; 863 #phy-cells = <0>; 864 }; 865 }; 866 }; 867 868 sata { 869 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 870 clock-names = "pll"; 871 resets = <&tegra_car 204>; 872 reset-names = "phy"; 873 status = "disabled"; 874 875 lanes { 876 sata-0 { 877 status = "disabled"; 878 #phy-cells = <0>; 879 }; 880 }; 881 }; 882 }; 883 884 ports { 885 usb2-0 { 886 status = "disabled"; 887 }; 888 889 usb2-1 { 890 status = "disabled"; 891 }; 892 893 usb2-2 { 894 status = "disabled"; 895 }; 896 897 usb2-3 { 898 status = "disabled"; 899 }; 900 901 hsic-0 { 902 status = "disabled"; 903 }; 904 905 usb3-0 { 906 status = "disabled"; 907 }; 908 909 usb3-1 { 910 status = "disabled"; 911 }; 912 913 usb3-2 { 914 status = "disabled"; 915 }; 916 917 usb3-3 { 918 status = "disabled"; 919 }; 920 }; 921 }; 922 923 sdhci@700b0000 { 924 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 925 reg = <0x0 0x700b0000 0x0 0x200>; 926 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 928 clock-names = "sdhci"; 929 resets = <&tegra_car 14>; 930 reset-names = "sdhci"; 931 status = "disabled"; 932 }; 933 934 sdhci@700b0200 { 935 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 936 reg = <0x0 0x700b0200 0x0 0x200>; 937 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 939 clock-names = "sdhci"; 940 resets = <&tegra_car 9>; 941 reset-names = "sdhci"; 942 status = "disabled"; 943 }; 944 945 sdhci@700b0400 { 946 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 947 reg = <0x0 0x700b0400 0x0 0x200>; 948 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 950 clock-names = "sdhci"; 951 resets = <&tegra_car 69>; 952 reset-names = "sdhci"; 953 status = "disabled"; 954 }; 955 956 sdhci@700b0600 { 957 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 958 reg = <0x0 0x700b0600 0x0 0x200>; 959 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 961 clock-names = "sdhci"; 962 resets = <&tegra_car 15>; 963 reset-names = "sdhci"; 964 status = "disabled"; 965 }; 966 967 mipi: mipi@700e3000 { 968 compatible = "nvidia,tegra210-mipi"; 969 reg = <0x0 0x700e3000 0x0 0x100>; 970 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 971 clock-names = "mipi-cal"; 972 power-domains = <&pd_sor>; 973 #nvidia,mipi-calibrate-cells = <1>; 974 }; 975 976 aconnect@702c0000 { 977 compatible = "nvidia,tegra210-aconnect"; 978 clocks = <&tegra_car TEGRA210_CLK_APE>, 979 <&tegra_car TEGRA210_CLK_APB2APE>; 980 clock-names = "ape", "apb2ape"; 981 power-domains = <&pd_audio>; 982 #address-cells = <1>; 983 #size-cells = <1>; 984 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 985 status = "disabled"; 986 987 adma: dma@702e2000 { 988 compatible = "nvidia,tegra210-adma"; 989 reg = <0x702e2000 0x2000>; 990 interrupt-parent = <&agic>; 991 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1013 #dma-cells = <1>; 1014 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1015 clock-names = "d_audio"; 1016 status = "disabled"; 1017 }; 1018 1019 agic: agic@702f9000 { 1020 compatible = "nvidia,tegra210-agic"; 1021 #interrupt-cells = <3>; 1022 interrupt-controller; 1023 reg = <0x702f9000 0x2000>, 1024 <0x702fa000 0x2000>; 1025 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1026 clocks = <&tegra_car TEGRA210_CLK_APE>; 1027 clock-names = "clk"; 1028 status = "disabled"; 1029 }; 1030 }; 1031 1032 spi@70410000 { 1033 compatible = "nvidia,tegra210-qspi"; 1034 reg = <0x0 0x70410000 0x0 0x1000>; 1035 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1039 clock-names = "qspi"; 1040 resets = <&tegra_car 211>; 1041 reset-names = "qspi"; 1042 dmas = <&apbdma 5>, <&apbdma 5>; 1043 dma-names = "rx", "tx"; 1044 status = "disabled"; 1045 }; 1046 1047 usb@7d000000 { 1048 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1049 reg = <0x0 0x7d000000 0x0 0x4000>; 1050 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1051 phy_type = "utmi"; 1052 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1053 clock-names = "usb"; 1054 resets = <&tegra_car 22>; 1055 reset-names = "usb"; 1056 nvidia,phy = <&phy1>; 1057 status = "disabled"; 1058 }; 1059 1060 phy1: usb-phy@7d000000 { 1061 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1062 reg = <0x0 0x7d000000 0x0 0x4000>, 1063 <0x0 0x7d000000 0x0 0x4000>; 1064 phy_type = "utmi"; 1065 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1066 <&tegra_car TEGRA210_CLK_PLL_U>, 1067 <&tegra_car TEGRA210_CLK_USBD>; 1068 clock-names = "reg", "pll_u", "utmi-pads"; 1069 resets = <&tegra_car 22>, <&tegra_car 22>; 1070 reset-names = "usb", "utmi-pads"; 1071 nvidia,hssync-start-delay = <0>; 1072 nvidia,idle-wait-delay = <17>; 1073 nvidia,elastic-limit = <16>; 1074 nvidia,term-range-adj = <6>; 1075 nvidia,xcvr-setup = <9>; 1076 nvidia,xcvr-lsfslew = <0>; 1077 nvidia,xcvr-lsrslew = <3>; 1078 nvidia,hssquelch-level = <2>; 1079 nvidia,hsdiscon-level = <5>; 1080 nvidia,xcvr-hsslew = <12>; 1081 nvidia,has-utmi-pad-registers; 1082 status = "disabled"; 1083 }; 1084 1085 usb@7d004000 { 1086 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1087 reg = <0x0 0x7d004000 0x0 0x4000>; 1088 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1089 phy_type = "utmi"; 1090 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1091 clock-names = "usb"; 1092 resets = <&tegra_car 58>; 1093 reset-names = "usb"; 1094 nvidia,phy = <&phy2>; 1095 status = "disabled"; 1096 }; 1097 1098 phy2: usb-phy@7d004000 { 1099 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1100 reg = <0x0 0x7d004000 0x0 0x4000>, 1101 <0x0 0x7d000000 0x0 0x4000>; 1102 phy_type = "utmi"; 1103 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1104 <&tegra_car TEGRA210_CLK_PLL_U>, 1105 <&tegra_car TEGRA210_CLK_USBD>; 1106 clock-names = "reg", "pll_u", "utmi-pads"; 1107 resets = <&tegra_car 58>, <&tegra_car 22>; 1108 reset-names = "usb", "utmi-pads"; 1109 nvidia,hssync-start-delay = <0>; 1110 nvidia,idle-wait-delay = <17>; 1111 nvidia,elastic-limit = <16>; 1112 nvidia,term-range-adj = <6>; 1113 nvidia,xcvr-setup = <9>; 1114 nvidia,xcvr-lsfslew = <0>; 1115 nvidia,xcvr-lsrslew = <3>; 1116 nvidia,hssquelch-level = <2>; 1117 nvidia,hsdiscon-level = <5>; 1118 nvidia,xcvr-hsslew = <12>; 1119 status = "disabled"; 1120 }; 1121 1122 cpus { 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 1126 cpu@0 { 1127 device_type = "cpu"; 1128 compatible = "arm,cortex-a57"; 1129 reg = <0>; 1130 }; 1131 1132 cpu@1 { 1133 device_type = "cpu"; 1134 compatible = "arm,cortex-a57"; 1135 reg = <1>; 1136 }; 1137 1138 cpu@2 { 1139 device_type = "cpu"; 1140 compatible = "arm,cortex-a57"; 1141 reg = <2>; 1142 }; 1143 1144 cpu@3 { 1145 device_type = "cpu"; 1146 compatible = "arm,cortex-a57"; 1147 reg = <3>; 1148 }; 1149 }; 1150 1151 timer { 1152 compatible = "arm,armv8-timer"; 1153 interrupts = <GIC_PPI 13 1154 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1155 <GIC_PPI 14 1156 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1157 <GIC_PPI 11 1158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1159 <GIC_PPI 10 1160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1161 interrupt-parent = <&gic>; 1162 }; 1163 1164 soctherm: thermal-sensor@700e2000 { 1165 compatible = "nvidia,tegra210-soctherm"; 1166 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1167 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1168 reg-names = "soctherm-reg", "car-reg"; 1169 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1171 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1172 clock-names = "tsensor", "soctherm"; 1173 resets = <&tegra_car 78>; 1174 reset-names = "soctherm"; 1175 #thermal-sensor-cells = <1>; 1176 1177 throttle-cfgs { 1178 throttle_heavy: heavy { 1179 nvidia,priority = <100>; 1180 nvidia,cpu-throt-percent = <85>; 1181 1182 #cooling-cells = <2>; 1183 }; 1184 }; 1185 }; 1186 1187 thermal-zones { 1188 cpu { 1189 polling-delay-passive = <1000>; 1190 polling-delay = <0>; 1191 1192 thermal-sensors = 1193 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1194 1195 trips { 1196 cpu-shutdown-trip { 1197 temperature = <102500>; 1198 hysteresis = <0>; 1199 type = "critical"; 1200 }; 1201 1202 cpu_throttle_trip: throttle-trip { 1203 temperature = <98500>; 1204 hysteresis = <1000>; 1205 type = "hot"; 1206 }; 1207 }; 1208 1209 cooling-maps { 1210 map0 { 1211 trip = <&cpu_throttle_trip>; 1212 cooling-device = <&throttle_heavy 1 1>; 1213 }; 1214 }; 1215 }; 1216 mem { 1217 polling-delay-passive = <0>; 1218 polling-delay = <0>; 1219 1220 thermal-sensors = 1221 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1222 1223 trips { 1224 mem-shutdown-trip { 1225 temperature = <103000>; 1226 hysteresis = <0>; 1227 type = "critical"; 1228 }; 1229 }; 1230 1231 cooling-maps { 1232 /* 1233 * There are currently no cooling maps, 1234 * because there are no cooling devices. 1235 */ 1236 }; 1237 }; 1238 gpu { 1239 polling-delay-passive = <1000>; 1240 polling-delay = <0>; 1241 1242 thermal-sensors = 1243 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1244 1245 trips { 1246 gpu-shutdown-trip { 1247 temperature = <103000>; 1248 hysteresis = <0>; 1249 type = "critical"; 1250 }; 1251 1252 gpu_throttle_trip: throttle-trip { 1253 temperature = <100000>; 1254 hysteresis = <1000>; 1255 type = "hot"; 1256 }; 1257 }; 1258 1259 cooling-maps { 1260 map0 { 1261 trip = <&gpu_throttle_trip>; 1262 cooling-device = <&throttle_heavy 1 1>; 1263 }; 1264 }; 1265 }; 1266 pllx { 1267 polling-delay-passive = <0>; 1268 polling-delay = <0>; 1269 1270 thermal-sensors = 1271 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1272 1273 trips { 1274 pllx-shutdown-trip { 1275 temperature = <103000>; 1276 hysteresis = <0>; 1277 type = "critical"; 1278 }; 1279 }; 1280 1281 cooling-maps { 1282 /* 1283 * There are currently no cooling maps, 1284 * because there are no cooling devices. 1285 */ 1286 }; 1287 }; 1288 }; 1289}; 1290