1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 }; 185 186 dc@54200000 { 187 compatible = "nvidia,tegra210-dc"; 188 reg = <0x0 0x54200000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191 clock-names = "dc"; 192 resets = <&tegra_car 27>; 193 reset-names = "dc"; 194 195 iommus = <&mc TEGRA_SWGROUP_DC>; 196 197 nvidia,head = <0>; 198 }; 199 200 dc@54240000 { 201 compatible = "nvidia,tegra210-dc"; 202 reg = <0x0 0x54240000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 205 clock-names = "dc"; 206 resets = <&tegra_car 26>; 207 reset-names = "dc"; 208 209 iommus = <&mc TEGRA_SWGROUP_DCB>; 210 211 nvidia,head = <1>; 212 }; 213 214 dsi@54300000 { 215 compatible = "nvidia,tegra210-dsi"; 216 reg = <0x0 0x54300000 0x0 0x00040000>; 217 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 218 <&tegra_car TEGRA210_CLK_DSIALP>, 219 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 220 clock-names = "dsi", "lp", "parent"; 221 resets = <&tegra_car 48>; 222 reset-names = "dsi"; 223 power-domains = <&pd_sor>; 224 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 225 226 status = "disabled"; 227 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 vic@54340000 { 233 compatible = "nvidia,tegra210-vic"; 234 reg = <0x0 0x54340000 0x0 0x00040000>; 235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 237 clock-names = "vic"; 238 resets = <&tegra_car 178>; 239 reset-names = "vic"; 240 241 iommus = <&mc TEGRA_SWGROUP_VIC>; 242 power-domains = <&pd_vic>; 243 }; 244 245 nvjpg@54380000 { 246 compatible = "nvidia,tegra210-nvjpg"; 247 reg = <0x0 0x54380000 0x0 0x00040000>; 248 status = "disabled"; 249 }; 250 251 dsi@54400000 { 252 compatible = "nvidia,tegra210-dsi"; 253 reg = <0x0 0x54400000 0x0 0x00040000>; 254 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 255 <&tegra_car TEGRA210_CLK_DSIBLP>, 256 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 257 clock-names = "dsi", "lp", "parent"; 258 resets = <&tegra_car 82>; 259 reset-names = "dsi"; 260 power-domains = <&pd_sor>; 261 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 262 263 status = "disabled"; 264 265 #address-cells = <1>; 266 #size-cells = <0>; 267 }; 268 269 nvdec@54480000 { 270 compatible = "nvidia,tegra210-nvdec"; 271 reg = <0x0 0x54480000 0x0 0x00040000>; 272 status = "disabled"; 273 }; 274 275 nvenc@544c0000 { 276 compatible = "nvidia,tegra210-nvenc"; 277 reg = <0x0 0x544c0000 0x0 0x00040000>; 278 status = "disabled"; 279 }; 280 281 tsec@54500000 { 282 compatible = "nvidia,tegra210-tsec"; 283 reg = <0x0 0x54500000 0x0 0x00040000>; 284 status = "disabled"; 285 }; 286 287 sor@54540000 { 288 compatible = "nvidia,tegra210-sor"; 289 reg = <0x0 0x54540000 0x0 0x00040000>; 290 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 292 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 293 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 294 <&tegra_car TEGRA210_CLK_PLL_DP>, 295 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 296 clock-names = "sor", "out", "parent", "dp", "safe"; 297 resets = <&tegra_car 182>; 298 reset-names = "sor"; 299 pinctrl-0 = <&state_dpaux_aux>; 300 pinctrl-1 = <&state_dpaux_i2c>; 301 pinctrl-2 = <&state_dpaux_off>; 302 pinctrl-names = "aux", "i2c", "off"; 303 power-domains = <&pd_sor>; 304 status = "disabled"; 305 }; 306 307 sor@54580000 { 308 compatible = "nvidia,tegra210-sor1"; 309 reg = <0x0 0x54580000 0x0 0x00040000>; 310 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 312 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 313 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 314 <&tegra_car TEGRA210_CLK_PLL_DP>, 315 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 316 clock-names = "sor", "out", "parent", "dp", "safe"; 317 resets = <&tegra_car 183>; 318 reset-names = "sor"; 319 pinctrl-0 = <&state_dpaux1_aux>; 320 pinctrl-1 = <&state_dpaux1_i2c>; 321 pinctrl-2 = <&state_dpaux1_off>; 322 pinctrl-names = "aux", "i2c", "off"; 323 power-domains = <&pd_sor>; 324 status = "disabled"; 325 }; 326 327 dpaux: dpaux@545c0000 { 328 compatible = "nvidia,tegra210-dpaux"; 329 reg = <0x0 0x545c0000 0x0 0x00040000>; 330 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 332 <&tegra_car TEGRA210_CLK_PLL_DP>; 333 clock-names = "dpaux", "parent"; 334 resets = <&tegra_car 181>; 335 reset-names = "dpaux"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 339 state_dpaux_aux: pinmux-aux { 340 groups = "dpaux-io"; 341 function = "aux"; 342 }; 343 344 state_dpaux_i2c: pinmux-i2c { 345 groups = "dpaux-io"; 346 function = "i2c"; 347 }; 348 349 state_dpaux_off: pinmux-off { 350 groups = "dpaux-io"; 351 function = "off"; 352 }; 353 354 i2c-bus { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 }; 358 }; 359 360 isp@54600000 { 361 compatible = "nvidia,tegra210-isp"; 362 reg = <0x0 0x54600000 0x0 0x00040000>; 363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 365 resets = <&tegra_car 23>; 366 reset-names = "isp"; 367 status = "disabled"; 368 }; 369 370 isp@54680000 { 371 compatible = "nvidia,tegra210-isp"; 372 reg = <0x0 0x54680000 0x0 0x00040000>; 373 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 375 resets = <&tegra_car 3>; 376 reset-names = "isp"; 377 status = "disabled"; 378 }; 379 380 i2c@546c0000 { 381 compatible = "nvidia,tegra210-i2c-vi"; 382 reg = <0x0 0x546c0000 0x0 0x00040000>; 383 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 385 <&tegra_car TEGRA210_CLK_I2CSLOW>; 386 clock-names = "div-clk", "slow"; 387 resets = <&tegra_car 208>; 388 reset-names = "i2c"; 389 power-domains = <&pd_venc>; 390 status = "disabled"; 391 392 #address-cells = <1>; 393 #size-cells = <0>; 394 }; 395 }; 396 397 gic: interrupt-controller@50041000 { 398 compatible = "arm,gic-400"; 399 #interrupt-cells = <3>; 400 interrupt-controller; 401 reg = <0x0 0x50041000 0x0 0x1000>, 402 <0x0 0x50042000 0x0 0x2000>, 403 <0x0 0x50044000 0x0 0x2000>, 404 <0x0 0x50046000 0x0 0x2000>; 405 interrupts = <GIC_PPI 9 406 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 407 interrupt-parent = <&gic>; 408 }; 409 410 gpu@57000000 { 411 compatible = "nvidia,gm20b"; 412 reg = <0x0 0x57000000 0x0 0x01000000>, 413 <0x0 0x58000000 0x0 0x01000000>; 414 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "stall", "nonstall"; 417 clocks = <&tegra_car TEGRA210_CLK_GPU>, 418 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 419 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 420 clock-names = "gpu", "pwr", "ref"; 421 resets = <&tegra_car 184>; 422 reset-names = "gpu"; 423 424 iommus = <&mc TEGRA_SWGROUP_GPU>; 425 426 status = "disabled"; 427 }; 428 429 lic: interrupt-controller@60004000 { 430 compatible = "nvidia,tegra210-ictlr"; 431 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 432 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 433 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 434 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 435 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 436 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 437 interrupt-controller; 438 #interrupt-cells = <3>; 439 interrupt-parent = <&gic>; 440 }; 441 442 timer@60005000 { 443 compatible = "nvidia,tegra210-timer"; 444 reg = <0x0 0x60005000 0x0 0x400>; 445 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 460 clock-names = "timer"; 461 }; 462 463 tegra_car: clock@60006000 { 464 compatible = "nvidia,tegra210-car"; 465 reg = <0x0 0x60006000 0x0 0x1000>; 466 #clock-cells = <1>; 467 #reset-cells = <1>; 468 }; 469 470 flow-controller@60007000 { 471 compatible = "nvidia,tegra210-flowctrl"; 472 reg = <0x0 0x60007000 0x0 0x1000>; 473 }; 474 475 gpio: gpio@6000d000 { 476 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 477 reg = <0x0 0x6000d000 0x0 0x1000>; 478 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 486 #gpio-cells = <2>; 487 gpio-controller; 488 #interrupt-cells = <2>; 489 interrupt-controller; 490 }; 491 492 apbdma: dma@60020000 { 493 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 494 reg = <0x0 0x60020000 0x0 0x1400>; 495 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 528 clock-names = "dma"; 529 resets = <&tegra_car 34>; 530 reset-names = "dma"; 531 #dma-cells = <1>; 532 }; 533 534 apbmisc@70000800 { 535 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 536 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 537 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 538 }; 539 540 pinmux: pinmux@700008d4 { 541 compatible = "nvidia,tegra210-pinmux"; 542 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 543 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 544 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 545 sdmmc1 { 546 nvidia,pins = "drive_sdmmc1"; 547 nvidia,pull-down-strength = <0x8>; 548 nvidia,pull-up-strength = <0x8>; 549 }; 550 }; 551 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 552 sdmmc1 { 553 nvidia,pins = "drive_sdmmc1"; 554 nvidia,pull-down-strength = <0x4>; 555 nvidia,pull-up-strength = <0x3>; 556 }; 557 }; 558 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 559 sdmmc2 { 560 nvidia,pins = "drive_sdmmc2"; 561 nvidia,pull-down-strength = <0x10>; 562 nvidia,pull-up-strength = <0x10>; 563 }; 564 }; 565 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 566 sdmmc3 { 567 nvidia,pins = "drive_sdmmc3"; 568 nvidia,pull-down-strength = <0x8>; 569 nvidia,pull-up-strength = <0x8>; 570 }; 571 }; 572 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 573 sdmmc3 { 574 nvidia,pins = "drive_sdmmc3"; 575 nvidia,pull-down-strength = <0x4>; 576 nvidia,pull-up-strength = <0x3>; 577 }; 578 }; 579 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 580 sdmmc4 { 581 nvidia,pins = "drive_sdmmc4"; 582 nvidia,pull-down-strength = <0x10>; 583 nvidia,pull-up-strength = <0x10>; 584 }; 585 }; 586 }; 587 588 /* 589 * There are two serial driver i.e. 8250 based simple serial 590 * driver and APB DMA based serial driver for higher baudrate 591 * and performance. To enable the 8250 based driver, the compatible 592 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 593 * the APB DMA based serial driver, the compatible is 594 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 595 */ 596 uarta: serial@70006000 { 597 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 598 reg = <0x0 0x70006000 0x0 0x40>; 599 reg-shift = <2>; 600 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 602 clock-names = "serial"; 603 resets = <&tegra_car 6>; 604 reset-names = "serial"; 605 dmas = <&apbdma 8>, <&apbdma 8>; 606 dma-names = "rx", "tx"; 607 status = "disabled"; 608 }; 609 610 uartb: serial@70006040 { 611 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 612 reg = <0x0 0x70006040 0x0 0x40>; 613 reg-shift = <2>; 614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 616 clock-names = "serial"; 617 resets = <&tegra_car 7>; 618 reset-names = "serial"; 619 dmas = <&apbdma 9>, <&apbdma 9>; 620 dma-names = "rx", "tx"; 621 status = "disabled"; 622 }; 623 624 uartc: serial@70006200 { 625 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 626 reg = <0x0 0x70006200 0x0 0x40>; 627 reg-shift = <2>; 628 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 630 clock-names = "serial"; 631 resets = <&tegra_car 55>; 632 reset-names = "serial"; 633 dmas = <&apbdma 10>, <&apbdma 10>; 634 dma-names = "rx", "tx"; 635 status = "disabled"; 636 }; 637 638 uartd: serial@70006300 { 639 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 640 reg = <0x0 0x70006300 0x0 0x40>; 641 reg-shift = <2>; 642 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 644 clock-names = "serial"; 645 resets = <&tegra_car 65>; 646 reset-names = "serial"; 647 dmas = <&apbdma 19>, <&apbdma 19>; 648 dma-names = "rx", "tx"; 649 status = "disabled"; 650 }; 651 652 pwm: pwm@7000a000 { 653 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 654 reg = <0x0 0x7000a000 0x0 0x100>; 655 #pwm-cells = <2>; 656 clocks = <&tegra_car TEGRA210_CLK_PWM>; 657 clock-names = "pwm"; 658 resets = <&tegra_car 17>; 659 reset-names = "pwm"; 660 status = "disabled"; 661 }; 662 663 i2c@7000c000 { 664 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 665 reg = <0x0 0x7000c000 0x0 0x100>; 666 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 670 clock-names = "div-clk"; 671 resets = <&tegra_car 12>; 672 reset-names = "i2c"; 673 dmas = <&apbdma 21>, <&apbdma 21>; 674 dma-names = "rx", "tx"; 675 status = "disabled"; 676 }; 677 678 i2c@7000c400 { 679 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 680 reg = <0x0 0x7000c400 0x0 0x100>; 681 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 685 clock-names = "div-clk"; 686 resets = <&tegra_car 54>; 687 reset-names = "i2c"; 688 dmas = <&apbdma 22>, <&apbdma 22>; 689 dma-names = "rx", "tx"; 690 status = "disabled"; 691 }; 692 693 i2c@7000c500 { 694 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 695 reg = <0x0 0x7000c500 0x0 0x100>; 696 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 700 clock-names = "div-clk"; 701 resets = <&tegra_car 67>; 702 reset-names = "i2c"; 703 dmas = <&apbdma 23>, <&apbdma 23>; 704 dma-names = "rx", "tx"; 705 status = "disabled"; 706 }; 707 708 i2c@7000c700 { 709 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 710 reg = <0x0 0x7000c700 0x0 0x100>; 711 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 715 clock-names = "div-clk"; 716 resets = <&tegra_car 103>; 717 reset-names = "i2c"; 718 dmas = <&apbdma 26>, <&apbdma 26>; 719 dma-names = "rx", "tx"; 720 pinctrl-0 = <&state_dpaux1_i2c>; 721 pinctrl-1 = <&state_dpaux1_off>; 722 pinctrl-names = "default", "idle"; 723 status = "disabled"; 724 }; 725 726 i2c@7000d000 { 727 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 728 reg = <0x0 0x7000d000 0x0 0x100>; 729 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 733 clock-names = "div-clk"; 734 resets = <&tegra_car 47>; 735 reset-names = "i2c"; 736 dmas = <&apbdma 24>, <&apbdma 24>; 737 dma-names = "rx", "tx"; 738 status = "disabled"; 739 }; 740 741 i2c@7000d100 { 742 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 743 reg = <0x0 0x7000d100 0x0 0x100>; 744 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 748 clock-names = "div-clk"; 749 resets = <&tegra_car 166>; 750 reset-names = "i2c"; 751 dmas = <&apbdma 30>, <&apbdma 30>; 752 dma-names = "rx", "tx"; 753 pinctrl-0 = <&state_dpaux_i2c>; 754 pinctrl-1 = <&state_dpaux_off>; 755 pinctrl-names = "default", "idle"; 756 status = "disabled"; 757 }; 758 759 spi@7000d400 { 760 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 761 reg = <0x0 0x7000d400 0x0 0x200>; 762 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 766 clock-names = "spi"; 767 resets = <&tegra_car 41>; 768 reset-names = "spi"; 769 dmas = <&apbdma 15>, <&apbdma 15>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 spi@7000d600 { 775 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 776 reg = <0x0 0x7000d600 0x0 0x200>; 777 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 781 clock-names = "spi"; 782 resets = <&tegra_car 44>; 783 reset-names = "spi"; 784 dmas = <&apbdma 16>, <&apbdma 16>; 785 dma-names = "rx", "tx"; 786 status = "disabled"; 787 }; 788 789 spi@7000d800 { 790 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 791 reg = <0x0 0x7000d800 0x0 0x200>; 792 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 796 clock-names = "spi"; 797 resets = <&tegra_car 46>; 798 reset-names = "spi"; 799 dmas = <&apbdma 17>, <&apbdma 17>; 800 dma-names = "rx", "tx"; 801 status = "disabled"; 802 }; 803 804 spi@7000da00 { 805 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 806 reg = <0x0 0x7000da00 0x0 0x200>; 807 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 811 clock-names = "spi"; 812 resets = <&tegra_car 68>; 813 reset-names = "spi"; 814 dmas = <&apbdma 18>, <&apbdma 18>; 815 dma-names = "rx", "tx"; 816 status = "disabled"; 817 }; 818 819 rtc@7000e000 { 820 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 821 reg = <0x0 0x7000e000 0x0 0x100>; 822 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 823 interrupt-parent = <&tegra_pmc>; 824 clocks = <&tegra_car TEGRA210_CLK_RTC>; 825 clock-names = "rtc"; 826 }; 827 828 tegra_pmc: pmc@7000e400 { 829 compatible = "nvidia,tegra210-pmc"; 830 reg = <0x0 0x7000e400 0x0 0x400>; 831 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 832 clock-names = "pclk", "clk32k_in"; 833 #clock-cells = <1>; 834 #interrupt-cells = <2>; 835 interrupt-controller; 836 837 powergates { 838 pd_audio: aud { 839 clocks = <&tegra_car TEGRA210_CLK_APE>, 840 <&tegra_car TEGRA210_CLK_APB2APE>; 841 resets = <&tegra_car 198>; 842 #power-domain-cells = <0>; 843 }; 844 845 pd_sor: sor { 846 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 847 <&tegra_car TEGRA210_CLK_SOR1>, 848 <&tegra_car TEGRA210_CLK_CILAB>, 849 <&tegra_car TEGRA210_CLK_CILCD>, 850 <&tegra_car TEGRA210_CLK_CILE>, 851 <&tegra_car TEGRA210_CLK_DSIA>, 852 <&tegra_car TEGRA210_CLK_DSIB>, 853 <&tegra_car TEGRA210_CLK_DPAUX>, 854 <&tegra_car TEGRA210_CLK_DPAUX1>, 855 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 856 resets = <&tegra_car TEGRA210_CLK_SOR0>, 857 <&tegra_car TEGRA210_CLK_SOR1>, 858 <&tegra_car TEGRA210_CLK_DSIA>, 859 <&tegra_car TEGRA210_CLK_DSIB>, 860 <&tegra_car TEGRA210_CLK_DPAUX>, 861 <&tegra_car TEGRA210_CLK_DPAUX1>, 862 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 863 #power-domain-cells = <0>; 864 }; 865 866 pd_xusbss: xusba { 867 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 868 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 869 #power-domain-cells = <0>; 870 }; 871 872 pd_xusbdev: xusbb { 873 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 874 resets = <&tegra_car 95>; 875 #power-domain-cells = <0>; 876 }; 877 878 pd_xusbhost: xusbc { 879 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 880 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 881 #power-domain-cells = <0>; 882 }; 883 884 pd_vic: vic { 885 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 886 clock-names = "vic"; 887 resets = <&tegra_car 178>; 888 reset-names = "vic"; 889 #power-domain-cells = <0>; 890 }; 891 892 pd_venc: venc { 893 clocks = <&tegra_car TEGRA210_CLK_VI>, 894 <&tegra_car TEGRA210_CLK_CSI>; 895 resets = <&mc TEGRA210_MC_RESET_VI>, 896 <&tegra_car 20>, 897 <&tegra_car 52>; 898 #power-domain-cells = <0>; 899 }; 900 }; 901 902 sdmmc1_3v3: sdmmc1-3v3 { 903 pins = "sdmmc1"; 904 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 905 }; 906 907 sdmmc1_1v8: sdmmc1-1v8 { 908 pins = "sdmmc1"; 909 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 910 }; 911 912 sdmmc3_3v3: sdmmc3-3v3 { 913 pins = "sdmmc3"; 914 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 915 }; 916 917 sdmmc3_1v8: sdmmc3-1v8 { 918 pins = "sdmmc3"; 919 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 920 }; 921 922 pex_dpd_disable: pex_en { 923 pex-dpd-disable { 924 pins = "pex-bias", "pex-clk1", "pex-clk2"; 925 low-power-disable; 926 }; 927 }; 928 929 pex_dpd_enable: pex_dis { 930 pex-dpd-enable { 931 pins = "pex-bias", "pex-clk1", "pex-clk2"; 932 low-power-enable; 933 }; 934 }; 935 }; 936 937 fuse@7000f800 { 938 compatible = "nvidia,tegra210-efuse"; 939 reg = <0x0 0x7000f800 0x0 0x400>; 940 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 941 clock-names = "fuse"; 942 resets = <&tegra_car 39>; 943 reset-names = "fuse"; 944 }; 945 946 mc: memory-controller@70019000 { 947 compatible = "nvidia,tegra210-mc"; 948 reg = <0x0 0x70019000 0x0 0x1000>; 949 clocks = <&tegra_car TEGRA210_CLK_MC>; 950 clock-names = "mc"; 951 952 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 953 954 #iommu-cells = <1>; 955 #reset-cells = <1>; 956 }; 957 958 emc: external-memory-controller@7001b000 { 959 compatible = "nvidia,tegra210-emc"; 960 reg = <0x0 0x7001b000 0x0 0x1000>, 961 <0x0 0x7001e000 0x0 0x1000>, 962 <0x0 0x7001f000 0x0 0x1000>; 963 clocks = <&tegra_car TEGRA210_CLK_EMC>; 964 clock-names = "emc"; 965 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 966 nvidia,memory-controller = <&mc>; 967 #cooling-cells = <2>; 968 }; 969 970 sata@70020000 { 971 compatible = "nvidia,tegra210-ahci"; 972 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 973 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 974 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 975 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&tegra_car TEGRA210_CLK_SATA>, 977 <&tegra_car TEGRA210_CLK_SATA_OOB>; 978 clock-names = "sata", "sata-oob"; 979 resets = <&tegra_car 124>, 980 <&tegra_car 123>, 981 <&tegra_car 129>; 982 reset-names = "sata", "sata-oob", "sata-cold"; 983 status = "disabled"; 984 }; 985 986 hda@70030000 { 987 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 988 reg = <0x0 0x70030000 0x0 0x10000>; 989 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&tegra_car TEGRA210_CLK_HDA>, 991 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 992 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 993 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 994 resets = <&tegra_car 125>, /* hda */ 995 <&tegra_car 128>, /* hda2hdmi */ 996 <&tegra_car 111>; /* hda2codec_2x */ 997 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 998 status = "disabled"; 999 }; 1000 1001 usb@70090000 { 1002 compatible = "nvidia,tegra210-xusb"; 1003 reg = <0x0 0x70090000 0x0 0x8000>, 1004 <0x0 0x70098000 0x0 0x1000>, 1005 <0x0 0x70099000 0x0 0x1000>; 1006 reg-names = "hcd", "fpci", "ipfs"; 1007 1008 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1010 1011 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1012 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1013 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1014 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1015 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1016 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1017 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1018 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1019 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1020 <&tegra_car TEGRA210_CLK_CLK_M>, 1021 <&tegra_car TEGRA210_CLK_PLL_E>; 1022 clock-names = "xusb_host", "xusb_host_src", 1023 "xusb_falcon_src", "xusb_ss", 1024 "xusb_ss_src", "xusb_ss_div2", 1025 "xusb_hs_src", "xusb_fs_src", 1026 "pll_u_480m", "clk_m", "pll_e"; 1027 resets = <&tegra_car 89>, <&tegra_car 156>, 1028 <&tegra_car 143>; 1029 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1030 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1031 power-domain-names = "xusb_host", "xusb_ss"; 1032 1033 nvidia,xusb-padctl = <&padctl>; 1034 1035 status = "disabled"; 1036 }; 1037 1038 padctl: padctl@7009f000 { 1039 compatible = "nvidia,tegra210-xusb-padctl"; 1040 reg = <0x0 0x7009f000 0x0 0x1000>; 1041 resets = <&tegra_car 142>; 1042 reset-names = "padctl"; 1043 1044 status = "disabled"; 1045 1046 pads { 1047 usb2 { 1048 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1049 clock-names = "trk"; 1050 status = "disabled"; 1051 1052 lanes { 1053 usb2-0 { 1054 status = "disabled"; 1055 #phy-cells = <0>; 1056 }; 1057 1058 usb2-1 { 1059 status = "disabled"; 1060 #phy-cells = <0>; 1061 }; 1062 1063 usb2-2 { 1064 status = "disabled"; 1065 #phy-cells = <0>; 1066 }; 1067 1068 usb2-3 { 1069 status = "disabled"; 1070 #phy-cells = <0>; 1071 }; 1072 }; 1073 }; 1074 1075 hsic { 1076 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1077 clock-names = "trk"; 1078 status = "disabled"; 1079 1080 lanes { 1081 hsic-0 { 1082 status = "disabled"; 1083 #phy-cells = <0>; 1084 }; 1085 1086 hsic-1 { 1087 status = "disabled"; 1088 #phy-cells = <0>; 1089 }; 1090 }; 1091 }; 1092 1093 pcie { 1094 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1095 clock-names = "pll"; 1096 resets = <&tegra_car 205>; 1097 reset-names = "phy"; 1098 status = "disabled"; 1099 1100 lanes { 1101 pcie-0 { 1102 status = "disabled"; 1103 #phy-cells = <0>; 1104 }; 1105 1106 pcie-1 { 1107 status = "disabled"; 1108 #phy-cells = <0>; 1109 }; 1110 1111 pcie-2 { 1112 status = "disabled"; 1113 #phy-cells = <0>; 1114 }; 1115 1116 pcie-3 { 1117 status = "disabled"; 1118 #phy-cells = <0>; 1119 }; 1120 1121 pcie-4 { 1122 status = "disabled"; 1123 #phy-cells = <0>; 1124 }; 1125 1126 pcie-5 { 1127 status = "disabled"; 1128 #phy-cells = <0>; 1129 }; 1130 1131 pcie-6 { 1132 status = "disabled"; 1133 #phy-cells = <0>; 1134 }; 1135 }; 1136 }; 1137 1138 sata { 1139 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1140 clock-names = "pll"; 1141 resets = <&tegra_car 204>; 1142 reset-names = "phy"; 1143 status = "disabled"; 1144 1145 lanes { 1146 sata-0 { 1147 status = "disabled"; 1148 #phy-cells = <0>; 1149 }; 1150 }; 1151 }; 1152 }; 1153 1154 ports { 1155 usb2-0 { 1156 status = "disabled"; 1157 }; 1158 1159 usb2-1 { 1160 status = "disabled"; 1161 }; 1162 1163 usb2-2 { 1164 status = "disabled"; 1165 }; 1166 1167 usb2-3 { 1168 status = "disabled"; 1169 }; 1170 1171 hsic-0 { 1172 status = "disabled"; 1173 }; 1174 1175 usb3-0 { 1176 status = "disabled"; 1177 }; 1178 1179 usb3-1 { 1180 status = "disabled"; 1181 }; 1182 1183 usb3-2 { 1184 status = "disabled"; 1185 }; 1186 1187 usb3-3 { 1188 status = "disabled"; 1189 }; 1190 }; 1191 }; 1192 1193 mmc@700b0000 { 1194 compatible = "nvidia,tegra210-sdhci"; 1195 reg = <0x0 0x700b0000 0x0 0x200>; 1196 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1197 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1198 clock-names = "sdhci"; 1199 resets = <&tegra_car 14>; 1200 reset-names = "sdhci"; 1201 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1202 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1203 pinctrl-0 = <&sdmmc1_3v3>; 1204 pinctrl-1 = <&sdmmc1_1v8>; 1205 pinctrl-2 = <&sdmmc1_3v3_drv>; 1206 pinctrl-3 = <&sdmmc1_1v8_drv>; 1207 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1208 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1209 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1210 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1211 nvidia,default-tap = <0x2>; 1212 nvidia,default-trim = <0x4>; 1213 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1214 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1215 <&tegra_car TEGRA210_CLK_PLL_C4>; 1216 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1217 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1218 status = "disabled"; 1219 }; 1220 1221 mmc@700b0200 { 1222 compatible = "nvidia,tegra210-sdhci"; 1223 reg = <0x0 0x700b0200 0x0 0x200>; 1224 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1226 clock-names = "sdhci"; 1227 resets = <&tegra_car 9>; 1228 reset-names = "sdhci"; 1229 pinctrl-names = "sdmmc-1v8-drv"; 1230 pinctrl-0 = <&sdmmc2_1v8_drv>; 1231 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1232 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1233 nvidia,default-tap = <0x8>; 1234 nvidia,default-trim = <0x0>; 1235 status = "disabled"; 1236 }; 1237 1238 mmc@700b0400 { 1239 compatible = "nvidia,tegra210-sdhci"; 1240 reg = <0x0 0x700b0400 0x0 0x200>; 1241 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1243 clock-names = "sdhci"; 1244 resets = <&tegra_car 69>; 1245 reset-names = "sdhci"; 1246 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1247 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1248 pinctrl-0 = <&sdmmc3_3v3>; 1249 pinctrl-1 = <&sdmmc3_1v8>; 1250 pinctrl-2 = <&sdmmc3_3v3_drv>; 1251 pinctrl-3 = <&sdmmc3_1v8_drv>; 1252 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1253 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1254 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1255 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1256 nvidia,default-tap = <0x3>; 1257 nvidia,default-trim = <0x3>; 1258 status = "disabled"; 1259 }; 1260 1261 mmc@700b0600 { 1262 compatible = "nvidia,tegra210-sdhci"; 1263 reg = <0x0 0x700b0600 0x0 0x200>; 1264 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1266 clock-names = "sdhci"; 1267 resets = <&tegra_car 15>; 1268 reset-names = "sdhci"; 1269 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1270 pinctrl-0 = <&sdmmc4_1v8_drv>; 1271 pinctrl-1 = <&sdmmc4_1v8_drv>; 1272 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1273 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1274 nvidia,default-tap = <0x8>; 1275 nvidia,default-trim = <0x0>; 1276 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1277 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1278 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1279 nvidia,dqs-trim = <40>; 1280 mmc-hs400-1_8v; 1281 status = "disabled"; 1282 }; 1283 1284 usb@700d0000 { 1285 compatible = "nvidia,tegra210-xudc"; 1286 reg = <0x0 0x700d0000 0x0 0x8000>, 1287 <0x0 0x700d8000 0x0 0x1000>, 1288 <0x0 0x700d9000 0x0 0x1000>; 1289 reg-names = "base", "fpci", "ipfs"; 1290 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1292 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1293 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1294 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1295 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1296 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1297 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1298 power-domain-names = "dev", "ss"; 1299 nvidia,xusb-padctl = <&padctl>; 1300 status = "disabled"; 1301 }; 1302 1303 mipi: mipi@700e3000 { 1304 compatible = "nvidia,tegra210-mipi"; 1305 reg = <0x0 0x700e3000 0x0 0x100>; 1306 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1307 clock-names = "mipi-cal"; 1308 power-domains = <&pd_sor>; 1309 #nvidia,mipi-calibrate-cells = <1>; 1310 }; 1311 1312 dfll: clock@70110000 { 1313 compatible = "nvidia,tegra210-dfll"; 1314 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1315 <0 0x70110000 0 0x100>, /* I2C output control */ 1316 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1317 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1318 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1319 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1320 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1321 <&tegra_car TEGRA210_CLK_I2C5>; 1322 clock-names = "soc", "ref", "i2c"; 1323 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1324 reset-names = "dvco"; 1325 #clock-cells = <0>; 1326 clock-output-names = "dfllCPU_out"; 1327 status = "disabled"; 1328 }; 1329 1330 aconnect@702c0000 { 1331 compatible = "nvidia,tegra210-aconnect"; 1332 clocks = <&tegra_car TEGRA210_CLK_APE>, 1333 <&tegra_car TEGRA210_CLK_APB2APE>; 1334 clock-names = "ape", "apb2ape"; 1335 power-domains = <&pd_audio>; 1336 #address-cells = <1>; 1337 #size-cells = <1>; 1338 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1339 status = "disabled"; 1340 1341 adma: dma@702e2000 { 1342 compatible = "nvidia,tegra210-adma"; 1343 reg = <0x702e2000 0x2000>; 1344 interrupt-parent = <&agic>; 1345 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1367 #dma-cells = <1>; 1368 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1369 clock-names = "d_audio"; 1370 status = "disabled"; 1371 }; 1372 1373 agic: interrupt-controller@702f9000 { 1374 compatible = "nvidia,tegra210-agic"; 1375 #interrupt-cells = <3>; 1376 interrupt-controller; 1377 reg = <0x702f9000 0x1000>, 1378 <0x702fa000 0x2000>; 1379 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1380 clocks = <&tegra_car TEGRA210_CLK_APE>; 1381 clock-names = "clk"; 1382 status = "disabled"; 1383 }; 1384 }; 1385 1386 spi@70410000 { 1387 compatible = "nvidia,tegra210-qspi"; 1388 reg = <0x0 0x70410000 0x0 0x1000>; 1389 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1393 clock-names = "qspi"; 1394 resets = <&tegra_car 211>; 1395 reset-names = "qspi"; 1396 dmas = <&apbdma 5>, <&apbdma 5>; 1397 dma-names = "rx", "tx"; 1398 status = "disabled"; 1399 }; 1400 1401 usb@7d000000 { 1402 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1403 reg = <0x0 0x7d000000 0x0 0x4000>; 1404 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1405 phy_type = "utmi"; 1406 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1407 clock-names = "usb"; 1408 resets = <&tegra_car 22>; 1409 reset-names = "usb"; 1410 nvidia,phy = <&phy1>; 1411 status = "disabled"; 1412 }; 1413 1414 phy1: usb-phy@7d000000 { 1415 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1416 reg = <0x0 0x7d000000 0x0 0x4000>, 1417 <0x0 0x7d000000 0x0 0x4000>; 1418 phy_type = "utmi"; 1419 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1420 <&tegra_car TEGRA210_CLK_PLL_U>, 1421 <&tegra_car TEGRA210_CLK_USBD>; 1422 clock-names = "reg", "pll_u", "utmi-pads"; 1423 resets = <&tegra_car 22>, <&tegra_car 22>; 1424 reset-names = "usb", "utmi-pads"; 1425 nvidia,hssync-start-delay = <0>; 1426 nvidia,idle-wait-delay = <17>; 1427 nvidia,elastic-limit = <16>; 1428 nvidia,term-range-adj = <6>; 1429 nvidia,xcvr-setup = <9>; 1430 nvidia,xcvr-lsfslew = <0>; 1431 nvidia,xcvr-lsrslew = <3>; 1432 nvidia,hssquelch-level = <2>; 1433 nvidia,hsdiscon-level = <5>; 1434 nvidia,xcvr-hsslew = <12>; 1435 nvidia,has-utmi-pad-registers; 1436 status = "disabled"; 1437 }; 1438 1439 usb@7d004000 { 1440 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1441 reg = <0x0 0x7d004000 0x0 0x4000>; 1442 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1443 phy_type = "utmi"; 1444 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1445 clock-names = "usb"; 1446 resets = <&tegra_car 58>; 1447 reset-names = "usb"; 1448 nvidia,phy = <&phy2>; 1449 status = "disabled"; 1450 }; 1451 1452 phy2: usb-phy@7d004000 { 1453 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1454 reg = <0x0 0x7d004000 0x0 0x4000>, 1455 <0x0 0x7d000000 0x0 0x4000>; 1456 phy_type = "utmi"; 1457 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1458 <&tegra_car TEGRA210_CLK_PLL_U>, 1459 <&tegra_car TEGRA210_CLK_USBD>; 1460 clock-names = "reg", "pll_u", "utmi-pads"; 1461 resets = <&tegra_car 58>, <&tegra_car 22>; 1462 reset-names = "usb", "utmi-pads"; 1463 nvidia,hssync-start-delay = <0>; 1464 nvidia,idle-wait-delay = <17>; 1465 nvidia,elastic-limit = <16>; 1466 nvidia,term-range-adj = <6>; 1467 nvidia,xcvr-setup = <9>; 1468 nvidia,xcvr-lsfslew = <0>; 1469 nvidia,xcvr-lsrslew = <3>; 1470 nvidia,hssquelch-level = <2>; 1471 nvidia,hsdiscon-level = <5>; 1472 nvidia,xcvr-hsslew = <12>; 1473 status = "disabled"; 1474 }; 1475 1476 cpus { 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 1480 cpu@0 { 1481 device_type = "cpu"; 1482 compatible = "arm,cortex-a57"; 1483 reg = <0>; 1484 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1485 <&tegra_car TEGRA210_CLK_PLL_X>, 1486 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1487 <&dfll>; 1488 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1489 clock-latency = <300000>; 1490 cpu-idle-states = <&CPU_SLEEP>; 1491 next-level-cache = <&L2>; 1492 }; 1493 1494 cpu@1 { 1495 device_type = "cpu"; 1496 compatible = "arm,cortex-a57"; 1497 reg = <1>; 1498 cpu-idle-states = <&CPU_SLEEP>; 1499 next-level-cache = <&L2>; 1500 }; 1501 1502 cpu@2 { 1503 device_type = "cpu"; 1504 compatible = "arm,cortex-a57"; 1505 reg = <2>; 1506 cpu-idle-states = <&CPU_SLEEP>; 1507 next-level-cache = <&L2>; 1508 }; 1509 1510 cpu@3 { 1511 device_type = "cpu"; 1512 compatible = "arm,cortex-a57"; 1513 reg = <3>; 1514 cpu-idle-states = <&CPU_SLEEP>; 1515 next-level-cache = <&L2>; 1516 }; 1517 1518 idle-states { 1519 entry-method = "psci"; 1520 1521 CPU_SLEEP: cpu-sleep { 1522 compatible = "arm,idle-state"; 1523 arm,psci-suspend-param = <0x40000007>; 1524 entry-latency-us = <100>; 1525 exit-latency-us = <30>; 1526 min-residency-us = <1000>; 1527 wakeup-latency-us = <130>; 1528 idle-state-name = "cpu-sleep"; 1529 status = "disabled"; 1530 }; 1531 }; 1532 1533 L2: l2-cache { 1534 compatible = "cache"; 1535 }; 1536 }; 1537 1538 pmu { 1539 compatible = "arm,armv8-pmuv3"; 1540 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1544 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1545 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1546 }; 1547 1548 timer { 1549 compatible = "arm,armv8-timer"; 1550 interrupts = <GIC_PPI 13 1551 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1552 <GIC_PPI 14 1553 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1554 <GIC_PPI 11 1555 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1556 <GIC_PPI 10 1557 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1558 interrupt-parent = <&gic>; 1559 arm,no-tick-in-suspend; 1560 }; 1561 1562 soctherm: thermal-sensor@700e2000 { 1563 compatible = "nvidia,tegra210-soctherm"; 1564 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1565 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1566 reg-names = "soctherm-reg", "car-reg"; 1567 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1569 interrupt-names = "thermal", "edp"; 1570 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1571 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1572 clock-names = "tsensor", "soctherm"; 1573 resets = <&tegra_car 78>; 1574 reset-names = "soctherm"; 1575 #thermal-sensor-cells = <1>; 1576 1577 throttle-cfgs { 1578 throttle_heavy: heavy { 1579 nvidia,priority = <100>; 1580 nvidia,cpu-throt-percent = <85>; 1581 1582 #cooling-cells = <2>; 1583 }; 1584 }; 1585 }; 1586 1587 thermal-zones { 1588 cpu { 1589 polling-delay-passive = <1000>; 1590 polling-delay = <0>; 1591 1592 thermal-sensors = 1593 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1594 1595 trips { 1596 cpu-shutdown-trip { 1597 temperature = <102500>; 1598 hysteresis = <0>; 1599 type = "critical"; 1600 }; 1601 1602 cpu_throttle_trip: throttle-trip { 1603 temperature = <98500>; 1604 hysteresis = <1000>; 1605 type = "hot"; 1606 }; 1607 }; 1608 1609 cooling-maps { 1610 map0 { 1611 trip = <&cpu_throttle_trip>; 1612 cooling-device = <&throttle_heavy 1 1>; 1613 }; 1614 }; 1615 }; 1616 1617 mem { 1618 polling-delay-passive = <0>; 1619 polling-delay = <0>; 1620 1621 thermal-sensors = 1622 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1623 1624 trips { 1625 dram_nominal: mem-nominal-trip { 1626 temperature = <50000>; 1627 hysteresis = <1000>; 1628 type = "passive"; 1629 }; 1630 1631 dram_throttle: mem-throttle-trip { 1632 temperature = <70000>; 1633 hysteresis = <1000>; 1634 type = "active"; 1635 }; 1636 1637 mem-shutdown-trip { 1638 temperature = <103000>; 1639 hysteresis = <0>; 1640 type = "critical"; 1641 }; 1642 }; 1643 1644 cooling-maps { 1645 dram-passive { 1646 cooling-device = <&emc 0 0>; 1647 trip = <&dram_nominal>; 1648 }; 1649 1650 dram-active { 1651 cooling-device = <&emc 1 1>; 1652 trip = <&dram_throttle>; 1653 }; 1654 }; 1655 }; 1656 1657 gpu { 1658 polling-delay-passive = <1000>; 1659 polling-delay = <0>; 1660 1661 thermal-sensors = 1662 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1663 1664 trips { 1665 gpu-shutdown-trip { 1666 temperature = <103000>; 1667 hysteresis = <0>; 1668 type = "critical"; 1669 }; 1670 1671 gpu_throttle_trip: throttle-trip { 1672 temperature = <100000>; 1673 hysteresis = <1000>; 1674 type = "hot"; 1675 }; 1676 }; 1677 1678 cooling-maps { 1679 map0 { 1680 trip = <&gpu_throttle_trip>; 1681 cooling-device = <&throttle_heavy 1 1>; 1682 }; 1683 }; 1684 }; 1685 1686 pllx { 1687 polling-delay-passive = <0>; 1688 polling-delay = <0>; 1689 1690 thermal-sensors = 1691 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1692 1693 trips { 1694 pllx-shutdown-trip { 1695 temperature = <103000>; 1696 hysteresis = <0>; 1697 type = "critical"; 1698 }; 1699 }; 1700 1701 cooling-maps { 1702 /* 1703 * There are currently no cooling maps, 1704 * because there are no cooling devices. 1705 */ 1706 }; 1707 }; 1708 }; 1709}; 1710