1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/gpio-keys.h> 5#include <dt-bindings/input/linux-event-codes.h> 6#include <dt-bindings/mfd/max77620.h> 7 8#include "tegra210.dtsi" 9 10/ { 11 model = "NVIDIA Jetson Nano Developer Kit"; 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 13 14 aliases { 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; 16 rtc0 = "/i2c@7000d000/pmic@3c"; 17 rtc1 = "/rtc@7000e000"; 18 serial0 = &uarta; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x0 0x80000000 0x1 0x0>; 28 }; 29 30 pcie@1003000 { 31 status = "okay"; 32 33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 34 hvddio-pex-supply = <&vdd_1v8>; 35 dvddio-pex-supply = <&vdd_pex_1v05>; 36 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 37 hvdd-pex-pll-e-supply = <&vdd_1v8>; 38 vddio-pex-ctl-supply = <&vdd_1v8>; 39 40 pci@1,0 { 41 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 42 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 43 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, 44 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 45 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 46 nvidia,num-lanes = <4>; 47 status = "okay"; 48 }; 49 50 pci@2,0 { 51 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 52 phy-names = "pcie-0"; 53 status = "okay"; 54 55 ethernet@0,0 { 56 reg = <0x000000 0 0 0 0>; 57 local-mac-address = [ 00 00 00 00 00 00 ]; 58 }; 59 }; 60 }; 61 62 host1x@50000000 { 63 dpaux@54040000 { 64 status = "okay"; 65 }; 66 67 vi@54080000 { 68 status = "okay"; 69 70 avdd-dsi-csi-supply = <&vdd_sys_1v2>; 71 72 csi@838 { 73 status = "okay"; 74 }; 75 }; 76 77 sor@54540000 { 78 status = "okay"; 79 80 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; 81 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 82 83 nvidia,xbar-cfg = <2 1 0 3 4>; 84 nvidia,dpaux = <&dpaux>; 85 }; 86 87 sor@54580000 { 88 status = "okay"; 89 90 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 91 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 92 hdmi-supply = <&vdd_hdmi>; 93 94 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 95 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 96 GPIO_ACTIVE_LOW>; 97 nvidia,xbar-cfg = <0 1 2 3 4>; 98 }; 99 100 dpaux@545c0000 { 101 status = "okay"; 102 }; 103 104 i2c@546c0000 { 105 status = "okay"; 106 }; 107 }; 108 109 gpu@57000000 { 110 vdd-supply = <&vdd_gpu>; 111 status = "okay"; 112 }; 113 114 pinmux@700008d4 { 115 dvfs_pwm_active_state: dvfs_pwm_active { 116 dvfs_pwm_pbb1 { 117 nvidia,pins = "dvfs_pwm_pbb1"; 118 nvidia,tristate = <TEGRA_PIN_DISABLE>; 119 }; 120 }; 121 122 dvfs_pwm_inactive_state: dvfs_pwm_inactive { 123 dvfs_pwm_pbb1 { 124 nvidia,pins = "dvfs_pwm_pbb1"; 125 nvidia,tristate = <TEGRA_PIN_ENABLE>; 126 }; 127 }; 128 }; 129 130 /* debug port */ 131 serial@70006000 { 132 status = "okay"; 133 }; 134 135 pwm@7000a000 { 136 status = "okay"; 137 }; 138 139 i2c@7000c500 { 140 status = "okay"; 141 clock-frequency = <100000>; 142 143 eeprom@50 { 144 compatible = "atmel,24c02"; 145 reg = <0x50>; 146 147 label = "module"; 148 vcc-supply = <&vdd_1v8>; 149 address-width = <8>; 150 pagesize = <8>; 151 size = <256>; 152 read-only; 153 }; 154 155 eeprom@57 { 156 compatible = "atmel,24c02"; 157 reg = <0x57>; 158 159 label = "system"; 160 vcc-supply = <&vdd_1v8>; 161 address-width = <8>; 162 pagesize = <8>; 163 size = <256>; 164 read-only; 165 }; 166 }; 167 168 hdmi_ddc: i2c@7000c700 { 169 status = "okay"; 170 clock-frequency = <100000>; 171 }; 172 173 i2c@7000d000 { 174 status = "okay"; 175 clock-frequency = <400000>; 176 177 pmic: pmic@3c { 178 compatible = "maxim,max77620"; 179 reg = <0x3c>; 180 interrupt-parent = <&tegra_pmc>; 181 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 182 183 #interrupt-cells = <2>; 184 interrupt-controller; 185 186 #gpio-cells = <2>; 187 gpio-controller; 188 189 pinctrl-names = "default"; 190 pinctrl-0 = <&max77620_default>; 191 192 max77620_default: pinmux { 193 gpio0 { 194 pins = "gpio0"; 195 function = "gpio"; 196 }; 197 198 gpio1 { 199 pins = "gpio1"; 200 function = "fps-out"; 201 drive-push-pull = <1>; 202 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 203 maxim,active-fps-power-up-slot = <0>; 204 maxim,active-fps-power-down-slot = <7>; 205 }; 206 207 gpio2 { 208 pins = "gpio2"; 209 function = "fps-out"; 210 drive-open-drain = <1>; 211 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 212 maxim,active-fps-power-up-slot = <0>; 213 maxim,active-fps-power-down-slot = <7>; 214 }; 215 216 gpio3 { 217 pins = "gpio3"; 218 function = "fps-out"; 219 drive-open-drain = <1>; 220 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 221 maxim,active-fps-power-up-slot = <4>; 222 maxim,active-fps-power-down-slot = <3>; 223 }; 224 225 gpio4 { 226 pins = "gpio4"; 227 function = "32k-out1"; 228 }; 229 230 gpio5_6_7 { 231 pins = "gpio5", "gpio6", "gpio7"; 232 function = "gpio"; 233 drive-push-pull = <1>; 234 }; 235 }; 236 237 fps { 238 fps0 { 239 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 240 maxim,suspend-fps-time-period-us = <5120>; 241 }; 242 243 fps1 { 244 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 245 maxim,suspend-fps-time-period-us = <5120>; 246 }; 247 248 fps2 { 249 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 250 }; 251 }; 252 253 regulators { 254 in-ldo0-1-supply = <&vdd_pre>; 255 in-ldo2-supply = <&vdd_3v3_sys>; 256 in-ldo3-5-supply = <&vdd_1v8>; 257 in-ldo4-6-supply = <&vdd_5v0_sys>; 258 in-ldo7-8-supply = <&vdd_pre>; 259 in-sd0-supply = <&vdd_5v0_sys>; 260 in-sd1-supply = <&vdd_5v0_sys>; 261 in-sd2-supply = <&vdd_5v0_sys>; 262 in-sd3-supply = <&vdd_5v0_sys>; 263 264 vdd_soc: sd0 { 265 regulator-name = "VDD_SOC"; 266 regulator-min-microvolt = <1000000>; 267 regulator-max-microvolt = <1170000>; 268 regulator-enable-ramp-delay = <146>; 269 regulator-disable-ramp-delay = <4080>; 270 regulator-ramp-delay = <27500>; 271 regulator-ramp-delay-scale = <300>; 272 regulator-always-on; 273 regulator-boot-on; 274 275 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 276 maxim,active-fps-power-up-slot = <1>; 277 maxim,active-fps-power-down-slot = <6>; 278 }; 279 280 vdd_ddr: sd1 { 281 regulator-name = "VDD_DDR_1V1_PMIC"; 282 regulator-min-microvolt = <1150000>; 283 regulator-max-microvolt = <1150000>; 284 regulator-enable-ramp-delay = <176>; 285 regulator-disable-ramp-delay = <145800>; 286 regulator-ramp-delay = <27500>; 287 regulator-ramp-delay-scale = <300>; 288 regulator-always-on; 289 regulator-boot-on; 290 291 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 292 maxim,active-fps-power-up-slot = <5>; 293 maxim,active-fps-power-down-slot = <2>; 294 }; 295 296 vdd_pre: sd2 { 297 regulator-name = "VDD_PRE_REG_1V35"; 298 regulator-min-microvolt = <1350000>; 299 regulator-max-microvolt = <1350000>; 300 regulator-enable-ramp-delay = <176>; 301 regulator-disable-ramp-delay = <32000>; 302 regulator-ramp-delay = <27500>; 303 regulator-ramp-delay-scale = <350>; 304 regulator-always-on; 305 regulator-boot-on; 306 307 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 308 maxim,active-fps-power-up-slot = <2>; 309 maxim,active-fps-power-down-slot = <5>; 310 }; 311 312 vdd_1v8: sd3 { 313 regulator-name = "VDD_1V8"; 314 regulator-min-microvolt = <1800000>; 315 regulator-max-microvolt = <1800000>; 316 regulator-enable-ramp-delay = <242>; 317 regulator-disable-ramp-delay = <118000>; 318 regulator-ramp-delay = <27500>; 319 regulator-ramp-delay-scale = <360>; 320 regulator-always-on; 321 regulator-boot-on; 322 323 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 324 maxim,active-fps-power-up-slot = <3>; 325 maxim,active-fps-power-down-slot = <4>; 326 }; 327 328 vdd_sys_1v2: ldo0 { 329 regulator-name = "AVDD_SYS_1V2"; 330 regulator-min-microvolt = <1200000>; 331 regulator-max-microvolt = <1200000>; 332 regulator-enable-ramp-delay = <26>; 333 regulator-disable-ramp-delay = <626>; 334 regulator-ramp-delay = <100000>; 335 regulator-ramp-delay-scale = <200>; 336 regulator-always-on; 337 regulator-boot-on; 338 339 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 340 maxim,active-fps-power-up-slot = <0>; 341 maxim,active-fps-power-down-slot = <7>; 342 }; 343 344 vdd_pex_1v05: ldo1 { 345 regulator-name = "VDD_PEX_1V05"; 346 regulator-min-microvolt = <1050000>; 347 regulator-max-microvolt = <1050000>; 348 regulator-enable-ramp-delay = <22>; 349 regulator-disable-ramp-delay = <650>; 350 regulator-ramp-delay = <100000>; 351 regulator-ramp-delay-scale = <200>; 352 353 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 354 maxim,active-fps-power-up-slot = <0>; 355 maxim,active-fps-power-down-slot = <7>; 356 }; 357 358 vddio_sdmmc: ldo2 { 359 regulator-name = "VDDIO_SDMMC"; 360 regulator-min-microvolt = <1800000>; 361 regulator-max-microvolt = <3300000>; 362 regulator-enable-ramp-delay = <62>; 363 regulator-disable-ramp-delay = <650>; 364 regulator-ramp-delay = <100000>; 365 regulator-ramp-delay-scale = <200>; 366 367 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 368 maxim,active-fps-power-up-slot = <0>; 369 maxim,active-fps-power-down-slot = <7>; 370 }; 371 372 ldo3 { 373 status = "disabled"; 374 }; 375 376 vdd_rtc: ldo4 { 377 regulator-name = "VDD_RTC"; 378 regulator-min-microvolt = <850000>; 379 regulator-max-microvolt = <1100000>; 380 regulator-enable-ramp-delay = <22>; 381 regulator-disable-ramp-delay = <610>; 382 regulator-ramp-delay = <100000>; 383 regulator-ramp-delay-scale = <200>; 384 regulator-disable-active-discharge; 385 regulator-always-on; 386 regulator-boot-on; 387 388 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 389 maxim,active-fps-power-up-slot = <1>; 390 maxim,active-fps-power-down-slot = <6>; 391 }; 392 393 ldo5 { 394 status = "disabled"; 395 }; 396 397 ldo6 { 398 status = "disabled"; 399 }; 400 401 avdd_1v05_pll: ldo7 { 402 regulator-name = "AVDD_1V05_PLL"; 403 regulator-min-microvolt = <1050000>; 404 regulator-max-microvolt = <1050000>; 405 regulator-enable-ramp-delay = <24>; 406 regulator-disable-ramp-delay = <2768>; 407 regulator-ramp-delay = <100000>; 408 regulator-ramp-delay-scale = <200>; 409 410 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 411 maxim,active-fps-power-up-slot = <3>; 412 maxim,active-fps-power-down-slot = <4>; 413 }; 414 415 avdd_1v05: ldo8 { 416 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 417 regulator-min-microvolt = <1050000>; 418 regulator-max-microvolt = <1050000>; 419 regulator-enable-ramp-delay = <22>; 420 regulator-disable-ramp-delay = <1160>; 421 regulator-ramp-delay = <100000>; 422 regulator-ramp-delay-scale = <200>; 423 424 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 425 maxim,active-fps-power-up-slot = <6>; 426 maxim,active-fps-power-down-slot = <1>; 427 }; 428 }; 429 }; 430 }; 431 432 pmc@7000e400 { 433 nvidia,invert-interrupt; 434 nvidia,suspend-mode = <0>; 435 nvidia,cpu-pwr-good-time = <0>; 436 nvidia,cpu-pwr-off-time = <0>; 437 nvidia,core-pwr-good-time = <4587 3876>; 438 nvidia,core-pwr-off-time = <39065>; 439 nvidia,core-power-req-active-high; 440 nvidia,sys-clock-req-active-high; 441 }; 442 443 hda@70030000 { 444 nvidia,model = "NVIDIA Jetson Nano HDA"; 445 446 status = "okay"; 447 }; 448 449 usb@70090000 { 450 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 451 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 452 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 453 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; 454 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 455 456 avdd-usb-supply = <&vdd_3v3_sys>; 457 dvddio-pex-supply = <&vdd_pex_1v05>; 458 hvddio-pex-supply = <&vdd_1v8>; 459 /* these really belong to the XUSB pad controller */ 460 avdd-pll-utmip-supply = <&vdd_1v8>; 461 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 462 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; 463 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; 464 465 status = "okay"; 466 }; 467 468 padctl@7009f000 { 469 status = "okay"; 470 471 avdd-pll-utmip-supply = <&vdd_1v8>; 472 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 473 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 474 hvdd-pex-pll-e-supply = <&vdd_1v8>; 475 476 pads { 477 usb2 { 478 status = "okay"; 479 480 lanes { 481 micro_b: usb2-0 { 482 nvidia,function = "xusb"; 483 status = "okay"; 484 }; 485 486 usb2-1 { 487 nvidia,function = "xusb"; 488 status = "okay"; 489 }; 490 491 usb2-2 { 492 nvidia,function = "xusb"; 493 status = "okay"; 494 }; 495 }; 496 }; 497 498 pcie { 499 status = "okay"; 500 501 lanes { 502 pcie-0 { 503 nvidia,function = "pcie-x1"; 504 status = "okay"; 505 }; 506 507 pcie-1 { 508 nvidia,function = "pcie-x4"; 509 status = "okay"; 510 }; 511 512 pcie-2 { 513 nvidia,function = "pcie-x4"; 514 status = "okay"; 515 }; 516 517 pcie-3 { 518 nvidia,function = "pcie-x4"; 519 status = "okay"; 520 }; 521 522 pcie-4 { 523 nvidia,function = "pcie-x4"; 524 status = "okay"; 525 }; 526 527 pcie-5 { 528 nvidia,function = "usb3-ss"; 529 status = "okay"; 530 }; 531 532 pcie-6 { 533 nvidia,function = "usb3-ss"; 534 status = "okay"; 535 }; 536 }; 537 }; 538 }; 539 540 ports { 541 usb2-0 { 542 status = "okay"; 543 mode = "peripheral"; 544 usb-role-switch; 545 546 vbus-supply = <&vdd_5v0_usb>; 547 548 connector { 549 compatible = "gpio-usb-b-connector", 550 "usb-b-connector"; 551 label = "micro-USB"; 552 type = "micro"; 553 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) 554 GPIO_ACTIVE_LOW>; 555 }; 556 }; 557 558 usb2-1 { 559 status = "okay"; 560 mode = "host"; 561 }; 562 563 usb2-2 { 564 status = "okay"; 565 mode = "host"; 566 }; 567 568 usb3-0 { 569 status = "okay"; 570 nvidia,usb2-companion = <1>; 571 vbus-supply = <&vdd_hub_3v3>; 572 }; 573 }; 574 }; 575 576 mmc@700b0000 { 577 status = "okay"; 578 bus-width = <4>; 579 580 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 581 disable-wp; 582 583 vqmmc-supply = <&vddio_sdmmc>; 584 vmmc-supply = <&vdd_3v3_sd>; 585 }; 586 587 mmc@700b0400 { 588 status = "okay"; 589 bus-width = <4>; 590 591 vqmmc-supply = <&vdd_1v8>; 592 vmmc-supply = <&vdd_3v3_sys>; 593 594 non-removable; 595 cap-sdio-irq; 596 keep-power-in-suspend; 597 wakeup-source; 598 }; 599 600 usb@700d0000 { 601 status = "okay"; 602 phys = <µ_b>; 603 phy-names = "usb2-0"; 604 avddio-usb-supply = <&vdd_3v3_sys>; 605 hvdd-usb-supply = <&vdd_1v8>; 606 }; 607 608 clock@70110000 { 609 status = "okay"; 610 611 nvidia,cf = <6>; 612 nvidia,ci = <0>; 613 nvidia,cg = <2>; 614 nvidia,droop-ctrl = <0x00000f00>; 615 nvidia,force-mode = <1>; 616 nvidia,sample-rate = <25000>; 617 618 nvidia,pwm-min-microvolts = <708000>; 619 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 620 nvidia,pwm-to-pmic; 621 nvidia,pwm-tristate-microvolts = <1000000>; 622 nvidia,pwm-voltage-step-microvolts = <19200>; 623 624 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 625 pinctrl-0 = <&dvfs_pwm_active_state>; 626 pinctrl-1 = <&dvfs_pwm_inactive_state>; 627 }; 628 629 aconnect@702c0000 { 630 status = "okay"; 631 632 dma-controller@702e2000 { 633 status = "okay"; 634 }; 635 636 interrupt-controller@702f9000 { 637 status = "okay"; 638 }; 639 640 ahub@702d0800 { 641 status = "okay"; 642 643 admaif@702d0000 { 644 status = "okay"; 645 }; 646 647 i2s@702d1200 { 648 status = "okay"; 649 650 ports { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 654 port@0 { 655 reg = <0>; 656 657 i2s3_cif_ep: endpoint { 658 remote-endpoint = <&xbar_i2s3_ep>; 659 }; 660 }; 661 662 i2s3_port: port@1 { 663 reg = <1>; 664 665 i2s3_dap_ep: endpoint { 666 dai-format = "i2s"; 667 /* Placeholder for external Codec */ 668 }; 669 }; 670 }; 671 }; 672 673 i2s@702d1300 { 674 status = "okay"; 675 676 ports { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 680 port@0 { 681 reg = <0>; 682 683 i2s4_cif_ep: endpoint { 684 remote-endpoint = <&xbar_i2s4_ep>; 685 }; 686 }; 687 688 i2s4_port: port@1 { 689 reg = <1>; 690 691 i2s4_dap_ep: endpoint@0 { 692 dai-format = "i2s"; 693 /* Placeholder for external Codec */ 694 }; 695 }; 696 }; 697 }; 698 699 dmic@702d4000 { 700 status = "okay"; 701 702 ports { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 706 port@0 { 707 reg = <0>; 708 709 dmic1_cif_ep: endpoint@0 { 710 remote-endpoint = <&xbar_dmic1_ep>; 711 }; 712 }; 713 714 dmic1_port: port@1 { 715 reg = <1>; 716 717 dmic1_dap_ep: endpoint@0 { 718 /* Placeholder for external Codec */ 719 }; 720 }; 721 }; 722 }; 723 724 dmic@702d4100 { 725 status = "okay"; 726 727 ports { 728 #address-cells = <1>; 729 #size-cells = <0>; 730 731 port@0 { 732 reg = <0>; 733 734 dmic2_cif_ep: endpoint@0 { 735 remote-endpoint = <&xbar_dmic2_ep>; 736 }; 737 }; 738 739 dmic2_port: port@1 { 740 reg = <1>; 741 742 dmic2_dap_ep: endpoint@0 { 743 /* Placeholder for external Codec */ 744 }; 745 }; 746 }; 747 }; 748 749 sfc@702d2000 { 750 status = "okay"; 751 752 ports { 753 #address-cells = <1>; 754 #size-cells = <0>; 755 756 port@0 { 757 reg = <0>; 758 759 sfc1_cif_in_ep: endpoint { 760 remote-endpoint = <&xbar_sfc1_in_ep>; 761 }; 762 }; 763 764 sfc1_out_port: port@1 { 765 reg = <1>; 766 767 sfc1_cif_out_ep: endpoint { 768 remote-endpoint = <&xbar_sfc1_out_ep>; 769 }; 770 }; 771 }; 772 }; 773 774 sfc@702d2200 { 775 status = "okay"; 776 777 ports { 778 #address-cells = <1>; 779 #size-cells = <0>; 780 781 port@0 { 782 reg = <0>; 783 784 sfc2_cif_in_ep: endpoint { 785 remote-endpoint = <&xbar_sfc2_in_ep>; 786 }; 787 }; 788 789 sfc2_out_port: port@1 { 790 reg = <1>; 791 792 sfc2_cif_out_ep: endpoint { 793 remote-endpoint = <&xbar_sfc2_out_ep>; 794 }; 795 }; 796 }; 797 }; 798 799 sfc@702d2400 { 800 status = "okay"; 801 802 ports { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 806 port@0 { 807 reg = <0>; 808 809 sfc3_cif_in_ep: endpoint { 810 remote-endpoint = <&xbar_sfc3_in_ep>; 811 }; 812 }; 813 814 sfc3_out_port: port@1 { 815 reg = <1>; 816 817 sfc3_cif_out_ep: endpoint { 818 remote-endpoint = <&xbar_sfc3_out_ep>; 819 }; 820 }; 821 }; 822 }; 823 824 sfc@702d2600 { 825 status = "okay"; 826 827 ports { 828 #address-cells = <1>; 829 #size-cells = <0>; 830 831 port@0 { 832 reg = <0>; 833 834 sfc4_cif_in_ep: endpoint { 835 remote-endpoint = <&xbar_sfc4_in_ep>; 836 }; 837 }; 838 839 sfc4_out_port: port@1 { 840 reg = <1>; 841 842 sfc4_cif_out_ep: endpoint { 843 remote-endpoint = <&xbar_sfc4_out_ep>; 844 }; 845 }; 846 }; 847 }; 848 849 mvc@702da000 { 850 status = "okay"; 851 852 ports { 853 #address-cells = <1>; 854 #size-cells = <0>; 855 856 port@0 { 857 reg = <0>; 858 859 mvc1_cif_in_ep: endpoint { 860 remote-endpoint = <&xbar_mvc1_in_ep>; 861 }; 862 }; 863 864 mvc1_out_port: port@1 { 865 reg = <1>; 866 867 mvc1_cif_out_ep: endpoint { 868 remote-endpoint = <&xbar_mvc1_out_ep>; 869 }; 870 }; 871 }; 872 }; 873 874 mvc@702da200 { 875 status = "okay"; 876 877 ports { 878 #address-cells = <1>; 879 #size-cells = <0>; 880 881 port@0 { 882 reg = <0>; 883 884 mvc2_cif_in_ep: endpoint { 885 remote-endpoint = <&xbar_mvc2_in_ep>; 886 }; 887 }; 888 889 mvc2_out_port: port@1 { 890 reg = <1>; 891 892 mvc2_cif_out_ep: endpoint { 893 remote-endpoint = <&xbar_mvc2_out_ep>; 894 }; 895 }; 896 }; 897 }; 898 899 amx@702d3000 { 900 status = "okay"; 901 902 ports { 903 #address-cells = <1>; 904 #size-cells = <0>; 905 906 port@0 { 907 reg = <0>; 908 909 amx1_in1_ep: endpoint { 910 remote-endpoint = <&xbar_amx1_in1_ep>; 911 }; 912 }; 913 914 port@1 { 915 reg = <1>; 916 917 amx1_in2_ep: endpoint { 918 remote-endpoint = <&xbar_amx1_in2_ep>; 919 }; 920 }; 921 922 port@2 { 923 reg = <2>; 924 925 amx1_in3_ep: endpoint { 926 remote-endpoint = <&xbar_amx1_in3_ep>; 927 }; 928 }; 929 930 port@3 { 931 reg = <3>; 932 933 amx1_in4_ep: endpoint { 934 remote-endpoint = <&xbar_amx1_in4_ep>; 935 }; 936 }; 937 938 amx1_out_port: port@4 { 939 reg = <4>; 940 941 amx1_out_ep: endpoint { 942 remote-endpoint = <&xbar_amx1_out_ep>; 943 }; 944 }; 945 }; 946 }; 947 948 amx@702d3100 { 949 status = "okay"; 950 951 ports { 952 #address-cells = <1>; 953 #size-cells = <0>; 954 955 port@0 { 956 reg = <0>; 957 958 amx2_in1_ep: endpoint { 959 remote-endpoint = <&xbar_amx2_in1_ep>; 960 }; 961 }; 962 963 port@1 { 964 reg = <1>; 965 966 amx2_in2_ep: endpoint { 967 remote-endpoint = <&xbar_amx2_in2_ep>; 968 }; 969 }; 970 971 amx2_in3_port: port@2 { 972 reg = <2>; 973 974 amx2_in3_ep: endpoint { 975 remote-endpoint = <&xbar_amx2_in3_ep>; 976 }; 977 }; 978 979 amx2_in4_port: port@3 { 980 reg = <3>; 981 982 amx2_in4_ep: endpoint { 983 remote-endpoint = <&xbar_amx2_in4_ep>; 984 }; 985 }; 986 987 amx2_out_port: port@4 { 988 reg = <4>; 989 990 amx2_out_ep: endpoint { 991 remote-endpoint = <&xbar_amx2_out_ep>; 992 }; 993 }; 994 }; 995 }; 996 997 adx@702d3800 { 998 status = "okay"; 999 1000 ports { 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 1004 port@0 { 1005 reg = <0>; 1006 1007 adx1_in_ep: endpoint { 1008 remote-endpoint = <&xbar_adx1_in_ep>; 1009 }; 1010 }; 1011 1012 adx1_out1_port: port@1 { 1013 reg = <1>; 1014 1015 adx1_out1_ep: endpoint { 1016 remote-endpoint = <&xbar_adx1_out1_ep>; 1017 }; 1018 }; 1019 1020 adx1_out2_port: port@2 { 1021 reg = <2>; 1022 1023 adx1_out2_ep: endpoint { 1024 remote-endpoint = <&xbar_adx1_out2_ep>; 1025 }; 1026 }; 1027 1028 adx1_out3_port: port@3 { 1029 reg = <3>; 1030 1031 adx1_out3_ep: endpoint { 1032 remote-endpoint = <&xbar_adx1_out3_ep>; 1033 }; 1034 }; 1035 1036 adx1_out4_port: port@4 { 1037 reg = <4>; 1038 1039 adx1_out4_ep: endpoint { 1040 remote-endpoint = <&xbar_adx1_out4_ep>; 1041 }; 1042 }; 1043 }; 1044 }; 1045 1046 adx@702d3900 { 1047 status = "okay"; 1048 1049 ports { 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 1053 port@0 { 1054 reg = <0>; 1055 1056 adx2_in_ep: endpoint { 1057 remote-endpoint = <&xbar_adx2_in_ep>; 1058 }; 1059 }; 1060 1061 adx2_out1_port: port@1 { 1062 reg = <1>; 1063 1064 adx2_out1_ep: endpoint { 1065 remote-endpoint = <&xbar_adx2_out1_ep>; 1066 }; 1067 }; 1068 1069 adx2_out2_port: port@2 { 1070 reg = <2>; 1071 1072 adx2_out2_ep: endpoint { 1073 remote-endpoint = <&xbar_adx2_out2_ep>; 1074 }; 1075 }; 1076 1077 adx2_out3_port: port@3 { 1078 reg = <3>; 1079 1080 adx2_out3_ep: endpoint { 1081 remote-endpoint = <&xbar_adx2_out3_ep>; 1082 }; 1083 }; 1084 1085 adx2_out4_port: port@4 { 1086 reg = <4>; 1087 1088 adx2_out4_ep: endpoint { 1089 remote-endpoint = <&xbar_adx2_out4_ep>; 1090 }; 1091 }; 1092 }; 1093 }; 1094 1095 amixer@702dbb00 { 1096 status = "okay"; 1097 1098 ports { 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 1102 port@0 { 1103 reg = <0x0>; 1104 1105 mixer_in1_ep: endpoint { 1106 remote-endpoint = <&xbar_mixer_in1_ep>; 1107 }; 1108 }; 1109 1110 port@1 { 1111 reg = <0x1>; 1112 1113 mixer_in2_ep: endpoint { 1114 remote-endpoint = <&xbar_mixer_in2_ep>; 1115 }; 1116 }; 1117 1118 port@2 { 1119 reg = <0x2>; 1120 1121 mixer_in3_ep: endpoint { 1122 remote-endpoint = <&xbar_mixer_in3_ep>; 1123 }; 1124 }; 1125 1126 port@3 { 1127 reg = <0x3>; 1128 1129 mixer_in4_ep: endpoint { 1130 remote-endpoint = <&xbar_mixer_in4_ep>; 1131 }; 1132 }; 1133 1134 port@4 { 1135 reg = <0x4>; 1136 1137 mixer_in5_ep: endpoint { 1138 remote-endpoint = <&xbar_mixer_in5_ep>; 1139 }; 1140 }; 1141 1142 port@5 { 1143 reg = <0x5>; 1144 1145 mixer_in6_ep: endpoint { 1146 remote-endpoint = <&xbar_mixer_in6_ep>; 1147 }; 1148 }; 1149 1150 port@6 { 1151 reg = <0x6>; 1152 1153 mixer_in7_ep: endpoint { 1154 remote-endpoint = <&xbar_mixer_in7_ep>; 1155 }; 1156 }; 1157 1158 port@7 { 1159 reg = <0x7>; 1160 1161 mixer_in8_ep: endpoint { 1162 remote-endpoint = <&xbar_mixer_in8_ep>; 1163 }; 1164 }; 1165 1166 port@8 { 1167 reg = <0x8>; 1168 1169 mixer_in9_ep: endpoint { 1170 remote-endpoint = <&xbar_mixer_in9_ep>; 1171 }; 1172 }; 1173 1174 port@9 { 1175 reg = <0x9>; 1176 1177 mixer_in10_ep: endpoint { 1178 remote-endpoint = <&xbar_mixer_in10_ep>; 1179 }; 1180 }; 1181 1182 mixer_out1_port: port@a { 1183 reg = <0xa>; 1184 1185 mixer_out1_ep: endpoint { 1186 remote-endpoint = <&xbar_mixer_out1_ep>; 1187 }; 1188 }; 1189 1190 mixer_out2_port: port@b { 1191 reg = <0xb>; 1192 1193 mixer_out2_ep: endpoint { 1194 remote-endpoint = <&xbar_mixer_out2_ep>; 1195 }; 1196 }; 1197 1198 mixer_out3_port: port@c { 1199 reg = <0xc>; 1200 1201 mixer_out3_ep: endpoint { 1202 remote-endpoint = <&xbar_mixer_out3_ep>; 1203 }; 1204 }; 1205 1206 mixer_out4_port: port@d { 1207 reg = <0xd>; 1208 1209 mixer_out4_ep: endpoint { 1210 remote-endpoint = <&xbar_mixer_out4_ep>; 1211 }; 1212 }; 1213 1214 mixer_out5_port: port@e { 1215 reg = <0xe>; 1216 1217 mixer_out5_ep: endpoint { 1218 remote-endpoint = <&xbar_mixer_out5_ep>; 1219 }; 1220 }; 1221 }; 1222 }; 1223 1224 ports { 1225 xbar_i2s3_port: port@c { 1226 reg = <0xc>; 1227 1228 xbar_i2s3_ep: endpoint { 1229 remote-endpoint = <&i2s3_cif_ep>; 1230 }; 1231 }; 1232 1233 xbar_i2s4_port: port@d { 1234 reg = <0xd>; 1235 1236 xbar_i2s4_ep: endpoint { 1237 remote-endpoint = <&i2s4_cif_ep>; 1238 }; 1239 }; 1240 1241 xbar_dmic1_port: port@f { 1242 reg = <0xf>; 1243 1244 xbar_dmic1_ep: endpoint { 1245 remote-endpoint = <&dmic1_cif_ep>; 1246 }; 1247 }; 1248 1249 xbar_dmic2_port: port@10 { 1250 reg = <0x10>; 1251 1252 xbar_dmic2_ep: endpoint { 1253 remote-endpoint = <&dmic2_cif_ep>; 1254 }; 1255 }; 1256 1257 xbar_sfc1_in_port: port@12 { 1258 reg = <0x12>; 1259 1260 xbar_sfc1_in_ep: endpoint { 1261 remote-endpoint = <&sfc1_cif_in_ep>; 1262 }; 1263 }; 1264 1265 port@13 { 1266 reg = <0x13>; 1267 1268 xbar_sfc1_out_ep: endpoint { 1269 remote-endpoint = <&sfc1_cif_out_ep>; 1270 }; 1271 }; 1272 1273 xbar_sfc2_in_port: port@14 { 1274 reg = <0x14>; 1275 1276 xbar_sfc2_in_ep: endpoint { 1277 remote-endpoint = <&sfc2_cif_in_ep>; 1278 }; 1279 }; 1280 1281 port@15 { 1282 reg = <0x15>; 1283 1284 xbar_sfc2_out_ep: endpoint { 1285 remote-endpoint = <&sfc2_cif_out_ep>; 1286 }; 1287 }; 1288 1289 xbar_sfc3_in_port: port@16 { 1290 reg = <0x16>; 1291 1292 xbar_sfc3_in_ep: endpoint { 1293 remote-endpoint = <&sfc3_cif_in_ep>; 1294 }; 1295 }; 1296 1297 port@17 { 1298 reg = <0x17>; 1299 1300 xbar_sfc3_out_ep: endpoint { 1301 remote-endpoint = <&sfc3_cif_out_ep>; 1302 }; 1303 }; 1304 1305 xbar_sfc4_in_port: port@18 { 1306 reg = <0x18>; 1307 1308 xbar_sfc4_in_ep: endpoint { 1309 remote-endpoint = <&sfc4_cif_in_ep>; 1310 }; 1311 }; 1312 1313 port@19 { 1314 reg = <0x19>; 1315 1316 xbar_sfc4_out_ep: endpoint { 1317 remote-endpoint = <&sfc4_cif_out_ep>; 1318 }; 1319 }; 1320 1321 xbar_mvc1_in_port: port@1a { 1322 reg = <0x1a>; 1323 1324 xbar_mvc1_in_ep: endpoint { 1325 remote-endpoint = <&mvc1_cif_in_ep>; 1326 }; 1327 }; 1328 1329 port@1b { 1330 reg = <0x1b>; 1331 1332 xbar_mvc1_out_ep: endpoint { 1333 remote-endpoint = <&mvc1_cif_out_ep>; 1334 }; 1335 }; 1336 1337 xbar_mvc2_in_port: port@1c { 1338 reg = <0x1c>; 1339 1340 xbar_mvc2_in_ep: endpoint { 1341 remote-endpoint = <&mvc2_cif_in_ep>; 1342 }; 1343 }; 1344 1345 port@1d { 1346 reg = <0x1d>; 1347 1348 xbar_mvc2_out_ep: endpoint { 1349 remote-endpoint = <&mvc2_cif_out_ep>; 1350 }; 1351 }; 1352 1353 xbar_amx1_in1_port: port@1e { 1354 reg = <0x1e>; 1355 1356 xbar_amx1_in1_ep: endpoint { 1357 remote-endpoint = <&amx1_in1_ep>; 1358 }; 1359 }; 1360 1361 xbar_amx1_in2_port: port@1f { 1362 reg = <0x1f>; 1363 1364 xbar_amx1_in2_ep: endpoint { 1365 remote-endpoint = <&amx1_in2_ep>; 1366 }; 1367 }; 1368 1369 xbar_amx1_in3_port: port@20 { 1370 reg = <0x20>; 1371 1372 xbar_amx1_in3_ep: endpoint { 1373 remote-endpoint = <&amx1_in3_ep>; 1374 }; 1375 }; 1376 1377 xbar_amx1_in4_port: port@21 { 1378 reg = <0x21>; 1379 1380 xbar_amx1_in4_ep: endpoint { 1381 remote-endpoint = <&amx1_in4_ep>; 1382 }; 1383 }; 1384 1385 port@22 { 1386 reg = <0x22>; 1387 1388 xbar_amx1_out_ep: endpoint { 1389 remote-endpoint = <&amx1_out_ep>; 1390 }; 1391 }; 1392 1393 xbar_amx2_in1_port: port@23 { 1394 reg = <0x23>; 1395 1396 xbar_amx2_in1_ep: endpoint { 1397 remote-endpoint = <&amx2_in1_ep>; 1398 }; 1399 }; 1400 1401 xbar_amx2_in2_port: port@24 { 1402 reg = <0x24>; 1403 1404 xbar_amx2_in2_ep: endpoint { 1405 remote-endpoint = <&amx2_in2_ep>; 1406 }; 1407 }; 1408 1409 xbar_amx2_in3_port: port@25 { 1410 reg = <0x25>; 1411 1412 xbar_amx2_in3_ep: endpoint { 1413 remote-endpoint = <&amx2_in3_ep>; 1414 }; 1415 }; 1416 1417 xbar_amx2_in4_port: port@26 { 1418 reg = <0x26>; 1419 1420 xbar_amx2_in4_ep: endpoint { 1421 remote-endpoint = <&amx2_in4_ep>; 1422 }; 1423 }; 1424 1425 port@27 { 1426 reg = <0x27>; 1427 1428 xbar_amx2_out_ep: endpoint { 1429 remote-endpoint = <&amx2_out_ep>; 1430 }; 1431 }; 1432 1433 xbar_adx1_in_port: port@28 { 1434 reg = <0x28>; 1435 1436 xbar_adx1_in_ep: endpoint { 1437 remote-endpoint = <&adx1_in_ep>; 1438 }; 1439 }; 1440 1441 port@29 { 1442 reg = <0x29>; 1443 1444 xbar_adx1_out1_ep: endpoint { 1445 remote-endpoint = <&adx1_out1_ep>; 1446 }; 1447 }; 1448 1449 port@2a { 1450 reg = <0x2a>; 1451 1452 xbar_adx1_out2_ep: endpoint { 1453 remote-endpoint = <&adx1_out2_ep>; 1454 }; 1455 }; 1456 1457 port@2b { 1458 reg = <0x2b>; 1459 1460 xbar_adx1_out3_ep: endpoint { 1461 remote-endpoint = <&adx1_out3_ep>; 1462 }; 1463 }; 1464 1465 port@2c { 1466 reg = <0x2c>; 1467 1468 xbar_adx1_out4_ep: endpoint { 1469 remote-endpoint = <&adx1_out4_ep>; 1470 }; 1471 }; 1472 1473 xbar_adx2_in_port: port@2d { 1474 reg = <0x2d>; 1475 1476 xbar_adx2_in_ep: endpoint { 1477 remote-endpoint = <&adx2_in_ep>; 1478 }; 1479 }; 1480 1481 port@2e { 1482 reg = <0x2e>; 1483 1484 xbar_adx2_out1_ep: endpoint { 1485 remote-endpoint = <&adx2_out1_ep>; 1486 }; 1487 }; 1488 1489 port@2f { 1490 reg = <0x2f>; 1491 1492 xbar_adx2_out2_ep: endpoint { 1493 remote-endpoint = <&adx2_out2_ep>; 1494 }; 1495 }; 1496 1497 port@30 { 1498 reg = <0x30>; 1499 1500 xbar_adx2_out3_ep: endpoint { 1501 remote-endpoint = <&adx2_out3_ep>; 1502 }; 1503 }; 1504 1505 port@31 { 1506 reg = <0x31>; 1507 1508 xbar_adx2_out4_ep: endpoint { 1509 remote-endpoint = <&adx2_out4_ep>; 1510 }; 1511 }; 1512 1513 xbar_mixer_in1_port: port@32 { 1514 reg = <0x32>; 1515 1516 xbar_mixer_in1_ep: endpoint { 1517 remote-endpoint = <&mixer_in1_ep>; 1518 }; 1519 }; 1520 1521 xbar_mixer_in2_port: port@33 { 1522 reg = <0x33>; 1523 1524 xbar_mixer_in2_ep: endpoint { 1525 remote-endpoint = <&mixer_in2_ep>; 1526 }; 1527 }; 1528 1529 xbar_mixer_in3_port: port@34 { 1530 reg = <0x34>; 1531 1532 xbar_mixer_in3_ep: endpoint { 1533 remote-endpoint = <&mixer_in3_ep>; 1534 }; 1535 }; 1536 1537 xbar_mixer_in4_port: port@35 { 1538 reg = <0x35>; 1539 1540 xbar_mixer_in4_ep: endpoint { 1541 remote-endpoint = <&mixer_in4_ep>; 1542 }; 1543 }; 1544 1545 xbar_mixer_in5_port: port@36 { 1546 reg = <0x36>; 1547 1548 xbar_mixer_in5_ep: endpoint { 1549 remote-endpoint = <&mixer_in5_ep>; 1550 }; 1551 }; 1552 1553 xbar_mixer_in6_port: port@37 { 1554 reg = <0x37>; 1555 1556 xbar_mixer_in6_ep: endpoint { 1557 remote-endpoint = <&mixer_in6_ep>; 1558 }; 1559 }; 1560 1561 xbar_mixer_in7_port: port@38 { 1562 reg = <0x38>; 1563 1564 xbar_mixer_in7_ep: endpoint { 1565 remote-endpoint = <&mixer_in7_ep>; 1566 }; 1567 }; 1568 1569 xbar_mixer_in8_port: port@39 { 1570 reg = <0x39>; 1571 1572 xbar_mixer_in8_ep: endpoint { 1573 remote-endpoint = <&mixer_in8_ep>; 1574 }; 1575 }; 1576 1577 xbar_mixer_in9_port: port@3a { 1578 reg = <0x3a>; 1579 1580 xbar_mixer_in9_ep: endpoint { 1581 remote-endpoint = <&mixer_in9_ep>; 1582 }; 1583 }; 1584 1585 xbar_mixer_in10_port: port@3b { 1586 reg = <0x3b>; 1587 1588 xbar_mixer_in10_ep: endpoint { 1589 remote-endpoint = <&mixer_in10_ep>; 1590 }; 1591 }; 1592 1593 port@3c { 1594 reg = <0x3c>; 1595 1596 xbar_mixer_out1_ep: endpoint { 1597 remote-endpoint = <&mixer_out1_ep>; 1598 }; 1599 }; 1600 1601 port@3d { 1602 reg = <0x3d>; 1603 1604 xbar_mixer_out2_ep: endpoint { 1605 remote-endpoint = <&mixer_out2_ep>; 1606 }; 1607 }; 1608 1609 port@3e { 1610 reg = <0x3e>; 1611 1612 xbar_mixer_out3_ep: endpoint { 1613 remote-endpoint = <&mixer_out3_ep>; 1614 }; 1615 }; 1616 1617 port@3f { 1618 reg = <0x3f>; 1619 1620 xbar_mixer_out4_ep: endpoint { 1621 remote-endpoint = <&mixer_out4_ep>; 1622 }; 1623 }; 1624 1625 port@40 { 1626 reg = <0x40>; 1627 1628 xbar_mixer_out5_ep: endpoint { 1629 remote-endpoint = <&mixer_out5_ep>; 1630 }; 1631 }; 1632 }; 1633 }; 1634 }; 1635 1636 spi@70410000 { 1637 status = "okay"; 1638 1639 flash@0 { 1640 compatible = "spi-nor"; 1641 reg = <0>; 1642 spi-max-frequency = <104000000>; 1643 spi-tx-bus-width = <2>; 1644 spi-rx-bus-width = <2>; 1645 }; 1646 }; 1647 1648 clk32k_in: clock@0 { 1649 compatible = "fixed-clock"; 1650 clock-frequency = <32768>; 1651 #clock-cells = <0>; 1652 }; 1653 1654 cpus { 1655 cpu@0 { 1656 enable-method = "psci"; 1657 }; 1658 1659 cpu@1 { 1660 enable-method = "psci"; 1661 }; 1662 1663 cpu@2 { 1664 enable-method = "psci"; 1665 }; 1666 1667 cpu@3 { 1668 enable-method = "psci"; 1669 }; 1670 1671 idle-states { 1672 cpu-sleep { 1673 status = "okay"; 1674 }; 1675 }; 1676 }; 1677 1678 fan: fan { 1679 compatible = "pwm-fan"; 1680 pwms = <&pwm 3 45334>; 1681 1682 cooling-levels = <0 64 128 255>; 1683 #cooling-cells = <2>; 1684 }; 1685 1686 thermal-zones { 1687 cpu { 1688 trips { 1689 cpu_trip_critical: critical { 1690 temperature = <96500>; 1691 hysteresis = <0>; 1692 type = "critical"; 1693 }; 1694 1695 cpu_trip_hot: hot { 1696 temperature = <70000>; 1697 hysteresis = <2000>; 1698 type = "hot"; 1699 }; 1700 1701 cpu_trip_active: active { 1702 temperature = <50000>; 1703 hysteresis = <2000>; 1704 type = "active"; 1705 }; 1706 1707 cpu_trip_passive: passive { 1708 temperature = <30000>; 1709 hysteresis = <2000>; 1710 type = "passive"; 1711 }; 1712 }; 1713 1714 cooling-maps { 1715 cpu-critical { 1716 cooling-device = <&fan 3 3>; 1717 trip = <&cpu_trip_critical>; 1718 }; 1719 1720 cpu-hot { 1721 cooling-device = <&fan 2 2>; 1722 trip = <&cpu_trip_hot>; 1723 }; 1724 1725 cpu-active { 1726 cooling-device = <&fan 1 1>; 1727 trip = <&cpu_trip_active>; 1728 }; 1729 1730 cpu-passive { 1731 cooling-device = <&fan 0 0>; 1732 trip = <&cpu_trip_passive>; 1733 }; 1734 }; 1735 }; 1736 }; 1737 1738 gpio-keys { 1739 compatible = "gpio-keys"; 1740 1741 power { 1742 label = "Power"; 1743 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1744 linux,input-type = <EV_KEY>; 1745 linux,code = <KEY_POWER>; 1746 debounce-interval = <30>; 1747 wakeup-event-action = <EV_ACT_ASSERTED>; 1748 wakeup-source; 1749 }; 1750 1751 force-recovery { 1752 label = "Force Recovery"; 1753 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 1754 linux,input-type = <EV_KEY>; 1755 linux,code = <BTN_1>; 1756 debounce-interval = <30>; 1757 }; 1758 }; 1759 1760 psci { 1761 compatible = "arm,psci-1.0"; 1762 method = "smc"; 1763 }; 1764 1765 vdd_5v0_sys: regulator@0 { 1766 compatible = "regulator-fixed"; 1767 1768 regulator-name = "VDD_5V0_SYS"; 1769 regulator-min-microvolt = <5000000>; 1770 regulator-max-microvolt = <5000000>; 1771 regulator-always-on; 1772 regulator-boot-on; 1773 }; 1774 1775 vdd_3v3_sys: regulator@1 { 1776 compatible = "regulator-fixed"; 1777 1778 regulator-name = "VDD_3V3_SYS"; 1779 regulator-min-microvolt = <3300000>; 1780 regulator-max-microvolt = <3300000>; 1781 regulator-enable-ramp-delay = <240>; 1782 regulator-disable-ramp-delay = <11340>; 1783 regulator-always-on; 1784 regulator-boot-on; 1785 1786 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1787 enable-active-high; 1788 1789 vin-supply = <&vdd_5v0_sys>; 1790 }; 1791 1792 vdd_3v3_sd: regulator@2 { 1793 compatible = "regulator-fixed"; 1794 1795 regulator-name = "VDD_3V3_SD"; 1796 regulator-min-microvolt = <3300000>; 1797 regulator-max-microvolt = <3300000>; 1798 1799 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 1800 enable-active-high; 1801 1802 vin-supply = <&vdd_3v3_sys>; 1803 }; 1804 1805 vdd_hdmi: regulator@3 { 1806 compatible = "regulator-fixed"; 1807 1808 regulator-name = "VDD_HDMI_5V0"; 1809 regulator-min-microvolt = <5000000>; 1810 regulator-max-microvolt = <5000000>; 1811 1812 vin-supply = <&vdd_5v0_sys>; 1813 }; 1814 1815 vdd_hub_3v3: regulator@4 { 1816 compatible = "regulator-fixed"; 1817 1818 regulator-name = "VDD_HUB_3V3"; 1819 regulator-min-microvolt = <3300000>; 1820 regulator-max-microvolt = <3300000>; 1821 1822 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; 1823 enable-active-high; 1824 1825 vin-supply = <&vdd_5v0_sys>; 1826 }; 1827 1828 vdd_cpu: regulator@5 { 1829 compatible = "regulator-fixed"; 1830 1831 regulator-name = "VDD_CPU"; 1832 regulator-min-microvolt = <5000000>; 1833 regulator-max-microvolt = <5000000>; 1834 regulator-always-on; 1835 regulator-boot-on; 1836 1837 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; 1838 enable-active-high; 1839 1840 vin-supply = <&vdd_5v0_sys>; 1841 }; 1842 1843 vdd_gpu: regulator@6 { 1844 compatible = "pwm-regulator"; 1845 pwms = <&pwm 1 8000>; 1846 1847 regulator-name = "VDD_GPU"; 1848 regulator-min-microvolt = <710000>; 1849 regulator-max-microvolt = <1320000>; 1850 regulator-ramp-delay = <80>; 1851 regulator-enable-ramp-delay = <2000>; 1852 regulator-settling-time-us = <160>; 1853 1854 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 1855 vin-supply = <&vdd_5v0_sys>; 1856 }; 1857 1858 avdd_io_edp_1v05: regulator@7 { 1859 compatible = "regulator-fixed"; 1860 1861 regulator-name = "AVDD_IO_EDP_1V05"; 1862 regulator-min-microvolt = <1050000>; 1863 regulator-max-microvolt = <1050000>; 1864 1865 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 1866 enable-active-high; 1867 1868 vin-supply = <&avdd_1v05_pll>; 1869 }; 1870 1871 vdd_5v0_usb: regulator@8 { 1872 compatible = "regulator-fixed"; 1873 1874 regulator-name = "VDD_5V_USB"; 1875 regulator-min-microvolt = <50000000>; 1876 regulator-max-microvolt = <50000000>; 1877 1878 vin-supply = <&vdd_5v0_sys>; 1879 }; 1880 1881 sound { 1882 compatible = "nvidia,tegra210-audio-graph-card"; 1883 status = "okay"; 1884 1885 dais = /* FE */ 1886 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1887 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1888 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1889 <&admaif10_port>, 1890 /* Router */ 1891 <&xbar_i2s3_port>, <&xbar_i2s4_port>, 1892 <&xbar_dmic1_port>, <&xbar_dmic2_port>, 1893 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1894 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1895 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1896 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1897 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1898 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1899 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1900 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1901 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1902 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1903 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1904 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1905 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1906 /* HW accelerators */ 1907 <&sfc1_out_port>, <&sfc2_out_port>, 1908 <&sfc3_out_port>, <&sfc4_out_port>, 1909 <&mvc1_out_port>, <&mvc2_out_port>, 1910 <&amx1_out_port>, <&amx2_out_port>, 1911 <&adx1_out1_port>, <&adx1_out2_port>, 1912 <&adx1_out3_port>, <&adx1_out4_port>, 1913 <&adx2_out1_port>, <&adx2_out2_port>, 1914 <&adx2_out3_port>, <&adx2_out4_port>, 1915 <&mixer_out1_port>, <&mixer_out2_port>, 1916 <&mixer_out3_port>, <&mixer_out4_port>, 1917 <&mixer_out5_port>, 1918 /* I/O DAP Ports */ 1919 <&i2s3_port>, <&i2s4_port>, 1920 <&dmic1_port>, <&dmic2_port>; 1921 1922 label = "NVIDIA Jetson Nano APE"; 1923 }; 1924}; 1925