1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/mfd/max77620.h>
3
4#include "tegra210.dtsi"
5
6/ {
7	model = "NVIDIA Jetson TX1";
8	compatible = "nvidia,p2180", "nvidia,tegra210";
9
10	aliases {
11		rtc0 = "/i2c@7000d000/pmic@3c";
12		rtc1 = "/rtc@7000e000";
13		serial0 = &uarta;
14	};
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	memory {
21		device_type = "memory";
22		reg = <0x0 0x80000000 0x1 0x0>;
23	};
24
25	gpu@57000000 {
26		vdd-supply = <&vdd_gpu>;
27	};
28
29	/* debug port */
30	serial@70006000 {
31		status = "okay";
32	};
33
34	i2c@7000d000 {
35		status = "okay";
36		clock-frequency = <400000>;
37
38		pmic: pmic@3c {
39			compatible = "maxim,max77620";
40			reg = <0x3c>;
41			interrupt-parent = <&tegra_pmc>;
42			interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
43
44			#interrupt-cells = <2>;
45			interrupt-controller;
46
47			#gpio-cells = <2>;
48			gpio-controller;
49
50			pinctrl-names = "default";
51			pinctrl-0 = <&max77620_default>;
52
53			max77620_default: pinmux {
54				gpio0 {
55					pins = "gpio0";
56					function = "gpio";
57				};
58
59				gpio1 {
60					pins = "gpio1";
61					function = "fps-out";
62					drive-push-pull = <1>;
63					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
64					maxim,active-fps-power-up-slot = <7>;
65					maxim,active-fps-power-down-slot = <0>;
66				};
67
68				gpio2_3 {
69					pins = "gpio2", "gpio3";
70					function = "fps-out";
71					drive-open-drain = <1>;
72					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
73				};
74
75				gpio4 {
76					pins = "gpio4";
77					function = "32k-out1";
78				};
79
80				gpio5_6_7 {
81					pins = "gpio5", "gpio6", "gpio7";
82					function = "gpio";
83					drive-push-pull = <1>;
84				};
85			};
86
87			fps {
88				fps0 {
89					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
90					maxim,suspend-fps-time-period-us = <1280>;
91				};
92
93				fps1 {
94					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
95					maxim,suspend-fps-time-period-us = <1280>;
96				};
97
98				fps2 {
99					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
100				};
101			};
102
103			regulators {
104				in-ldo0-1-supply = <&vdd_pre>;
105				in-ldo7-8-supply = <&vdd_pre>;
106				in-sd3-supply = <&vdd_5v0_sys>;
107
108				vdd_soc: sd0 {
109					regulator-name = "VDD_SOC";
110					regulator-min-microvolt = <600000>;
111					regulator-max-microvolt = <1400000>;
112					regulator-always-on;
113					regulator-boot-on;
114
115					regulator-enable-ramp-delay = <146>;
116					regulator-ramp-delay = <27500>;
117
118					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
119				};
120
121				vdd_ddr: sd1 {
122					regulator-name = "VDD_DDR_1V1_PMIC";
123					regulator-always-on;
124					regulator-boot-on;
125
126					regulator-enable-ramp-delay = <130>;
127					regulator-ramp-delay = <27500>;
128
129					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
130				};
131
132				vdd_pre: sd2 {
133					regulator-name = "VDD_PRE_REG_1V35";
134					regulator-min-microvolt = <1350000>;
135					regulator-max-microvolt = <1350000>;
136
137					regulator-enable-ramp-delay = <176>;
138					regulator-ramp-delay = <27500>;
139
140					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
141				};
142
143				vdd_1v8: sd3 {
144					regulator-name = "VDD_1V8";
145					regulator-min-microvolt = <1800000>;
146					regulator-max-microvolt = <1800000>;
147					regulator-always-on;
148					regulator-boot-on;
149
150					regulator-enable-ramp-delay = <242>;
151					regulator-ramp-delay = <27500>;
152
153					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
154				};
155
156				vdd_sys_1v2: ldo0 {
157					regulator-name = "AVDD_SYS_1V2";
158					regulator-min-microvolt = <1200000>;
159					regulator-max-microvolt = <1200000>;
160					regulator-always-on;
161					regulator-boot-on;
162
163					regulator-enable-ramp-delay = <26>;
164					regulator-ramp-delay = <100000>;
165
166					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
167				};
168
169				vdd_pex_1v05: ldo1 {
170					regulator-name = "VDD_PEX_1V05";
171					regulator-min-microvolt = <1050000>;
172					regulator-max-microvolt = <1050000>;
173
174					regulator-enable-ramp-delay = <22>;
175					regulator-ramp-delay = <100000>;
176
177					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
178				};
179
180				vddio_sdmmc: ldo2 {
181					regulator-name = "VDDIO_SDMMC";
182					regulator-min-microvolt = <1800000>;
183					regulator-max-microvolt = <3300000>;
184					regulator-always-on;
185					regulator-boot-on;
186
187					regulator-enable-ramp-delay = <62>;
188					regulator-ramp-delay = <100000>;
189
190					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
191				};
192
193				vdd_cam_hv: ldo3 {
194					regulator-name = "VDD_CAM_HV";
195					regulator-min-microvolt = <2800000>;
196					regulator-max-microvolt = <2800000>;
197
198					regulator-enable-ramp-delay = <50>;
199					regulator-ramp-delay = <100000>;
200
201					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
202				};
203
204				vdd_rtc: ldo4 {
205					regulator-name = "VDD_RTC";
206					regulator-min-microvolt = <850000>;
207					regulator-max-microvolt = <850000>;
208					regulator-always-on;
209					regulator-boot-on;
210
211					regulator-enable-ramp-delay = <22>;
212					regulator-ramp-delay = <100000>;
213
214					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
215				};
216
217				vdd_ts_hv: ldo5 {
218					regulator-name = "VDD_TS_HV";
219					regulator-min-microvolt = <3300000>;
220					regulator-max-microvolt = <3300000>;
221
222					regulator-enable-ramp-delay = <62>;
223					regulator-ramp-delay = <100000>;
224
225					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
226				};
227
228				vdd_ts: ldo6 {
229					regulator-name = "VDD_TS_1V8";
230					regulator-min-microvolt = <1800000>;
231					regulator-max-microvolt = <1800000>;
232
233					regulator-enable-ramp-delay = <36>;
234					regulator-ramp-delay = <100000>;
235
236					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
237					maxim,active-fps-power-up-slot = <7>;
238					maxim,active-fps-power-down-slot = <0>;
239				};
240
241				avdd_1v05_pll: ldo7 {
242					regulator-name = "AVDD_1V05_PLL";
243					regulator-min-microvolt = <1050000>;
244					regulator-max-microvolt = <1050000>;
245					regulator-always-on;
246					regulator-boot-on;
247
248					regulator-enable-ramp-delay = <24>;
249					regulator-ramp-delay = <100000>;
250
251					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
252				};
253
254				avdd_1v05: ldo8 {
255					regulator-name = "AVDD_SATA_HDMI_DP_1V05";
256					regulator-min-microvolt = <1050000>;
257					regulator-max-microvolt = <1050000>;
258
259					regulator-enable-ramp-delay = <22>;
260					regulator-ramp-delay = <100000>;
261
262					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
263				};
264			};
265		};
266	};
267
268	i2c@7000c500 {
269		status = "okay";
270
271		/* module ID EEPROM */
272		eeprom@50 {
273			compatible = "atmel,24c02";
274			reg = <0x50>;
275
276			vcc-supply = <&vdd_1v8>;
277			address-bits = <8>;
278			page-size = <8>;
279			size = <256>;
280			read-only;
281		};
282	};
283
284	pmc@7000e400 {
285		nvidia,invert-interrupt;
286		nvidia,suspend-mode = <0>;
287		nvidia,cpu-pwr-good-time = <0>;
288		nvidia,cpu-pwr-off-time = <0>;
289		nvidia,core-pwr-good-time = <4587 3876>;
290		nvidia,core-pwr-off-time = <39065>;
291		nvidia,core-power-req-active-high;
292		nvidia,sys-clock-req-active-high;
293	};
294
295	/* eMMC */
296	sdhci@700b0600 {
297		status = "okay";
298		bus-width = <8>;
299		non-removable;
300		vqmmc-supply = <&vdd_1v8>;
301	};
302
303	clocks {
304		compatible = "simple-bus";
305		#address-cells = <1>;
306		#size-cells = <0>;
307
308		clk32k_in: clock@0 {
309			compatible = "fixed-clock";
310			reg = <0>;
311			#clock-cells = <0>;
312			clock-frequency = <32768>;
313		};
314	};
315
316	cpus {
317		cpu@0 {
318			enable-method = "psci";
319		};
320
321		cpu@1 {
322			enable-method = "psci";
323		};
324
325		cpu@2 {
326			enable-method = "psci";
327		};
328
329		cpu@3 {
330			enable-method = "psci";
331		};
332
333		idle-states {
334			cpu-sleep {
335				status = "okay";
336			};
337		};
338	};
339
340	psci {
341		compatible = "arm,psci-0.2";
342		method = "smc";
343	};
344
345	regulators {
346		vdd_gpu: regulator@100 {
347			compatible = "pwm-regulator";
348			reg = <100>;
349			pwms = <&pwm 1 4880>;
350			regulator-name = "VDD_GPU";
351			regulator-min-microvolt = <710000>;
352			regulator-max-microvolt = <1320000>;
353			enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
354			regulator-ramp-delay = <80>;
355			regulator-enable-ramp-delay = <2000>;
356			regulator-settling-time-us = <160>;
357		};
358	};
359};
360