1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 apbmisc: misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 gpio-ranges = <&pinmux 0 0 169>; 90 }; 91 92 cbb-noc@2300000 { 93 compatible = "nvidia,tegra194-cbb-noc"; 94 reg = <0x02300000 0x1000>; 95 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 97 nvidia,axi2apb = <&axi2apb>; 98 nvidia,apbmisc = <&apbmisc>; 99 status = "okay"; 100 }; 101 102 axi2apb: axi2apb@2390000 { 103 compatible = "nvidia,tegra194-axi2apb"; 104 reg = <0x2390000 0x1000>, 105 <0x23a0000 0x1000>, 106 <0x23b0000 0x1000>, 107 <0x23c0000 0x1000>, 108 <0x23d0000 0x1000>, 109 <0x23e0000 0x1000>; 110 status = "okay"; 111 }; 112 113 ethernet@2490000 { 114 compatible = "nvidia,tegra194-eqos", 115 "nvidia,tegra186-eqos", 116 "snps,dwc-qos-ethernet-4.10"; 117 reg = <0x02490000 0x10000>; 118 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 120 <&bpmp TEGRA194_CLK_EQOS_AXI>, 121 <&bpmp TEGRA194_CLK_EQOS_RX>, 122 <&bpmp TEGRA194_CLK_EQOS_TX>, 123 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 124 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 125 resets = <&bpmp TEGRA194_RESET_EQOS>; 126 reset-names = "eqos"; 127 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 128 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 129 interconnect-names = "dma-mem", "write"; 130 iommus = <&smmu TEGRA194_SID_EQOS>; 131 status = "disabled"; 132 133 snps,write-requests = <1>; 134 snps,read-requests = <3>; 135 snps,burst-map = <0x7>; 136 snps,txpbl = <16>; 137 snps,rxpbl = <8>; 138 }; 139 140 gpcdma: dma-controller@2600000 { 141 compatible = "nvidia,tegra194-gpcdma", 142 "nvidia,tegra186-gpcdma"; 143 reg = <0x2600000 0x210000>; 144 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 145 reset-names = "gpcdma"; 146 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 178 #dma-cells = <1>; 179 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 180 dma-coherent; 181 dma-channel-mask = <0xfffffffe>; 182 status = "okay"; 183 }; 184 185 aconnect@2900000 { 186 compatible = "nvidia,tegra194-aconnect", 187 "nvidia,tegra210-aconnect"; 188 clocks = <&bpmp TEGRA194_CLK_APE>, 189 <&bpmp TEGRA194_CLK_APB2APE>; 190 clock-names = "ape", "apb2ape"; 191 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 ranges = <0x02900000 0x02900000 0x200000>; 195 status = "disabled"; 196 197 adma: dma-controller@2930000 { 198 compatible = "nvidia,tegra194-adma", 199 "nvidia,tegra186-adma"; 200 reg = <0x02930000 0x20000>; 201 interrupt-parent = <&agic>; 202 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 234 #dma-cells = <1>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "d_audio"; 237 status = "disabled"; 238 }; 239 240 agic: interrupt-controller@2a40000 { 241 compatible = "nvidia,tegra194-agic", 242 "nvidia,tegra210-agic"; 243 #interrupt-cells = <3>; 244 interrupt-controller; 245 reg = <0x02a41000 0x1000>, 246 <0x02a42000 0x2000>; 247 interrupts = <GIC_SPI 145 248 (GIC_CPU_MASK_SIMPLE(4) | 249 IRQ_TYPE_LEVEL_HIGH)>; 250 clocks = <&bpmp TEGRA194_CLK_APE>; 251 clock-names = "clk"; 252 status = "disabled"; 253 }; 254 255 tegra_ahub: ahub@2900800 { 256 compatible = "nvidia,tegra194-ahub", 257 "nvidia,tegra186-ahub"; 258 reg = <0x02900800 0x800>; 259 clocks = <&bpmp TEGRA194_CLK_AHUB>; 260 clock-names = "ahub"; 261 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 262 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 263 #address-cells = <1>; 264 #size-cells = <1>; 265 ranges = <0x02900800 0x02900800 0x11800>; 266 status = "disabled"; 267 268 tegra_admaif: admaif@290f000 { 269 compatible = "nvidia,tegra194-admaif", 270 "nvidia,tegra186-admaif"; 271 reg = <0x0290f000 0x1000>; 272 dmas = <&adma 1>, <&adma 1>, 273 <&adma 2>, <&adma 2>, 274 <&adma 3>, <&adma 3>, 275 <&adma 4>, <&adma 4>, 276 <&adma 5>, <&adma 5>, 277 <&adma 6>, <&adma 6>, 278 <&adma 7>, <&adma 7>, 279 <&adma 8>, <&adma 8>, 280 <&adma 9>, <&adma 9>, 281 <&adma 10>, <&adma 10>, 282 <&adma 11>, <&adma 11>, 283 <&adma 12>, <&adma 12>, 284 <&adma 13>, <&adma 13>, 285 <&adma 14>, <&adma 14>, 286 <&adma 15>, <&adma 15>, 287 <&adma 16>, <&adma 16>, 288 <&adma 17>, <&adma 17>, 289 <&adma 18>, <&adma 18>, 290 <&adma 19>, <&adma 19>, 291 <&adma 20>, <&adma 20>; 292 dma-names = "rx1", "tx1", 293 "rx2", "tx2", 294 "rx3", "tx3", 295 "rx4", "tx4", 296 "rx5", "tx5", 297 "rx6", "tx6", 298 "rx7", "tx7", 299 "rx8", "tx8", 300 "rx9", "tx9", 301 "rx10", "tx10", 302 "rx11", "tx11", 303 "rx12", "tx12", 304 "rx13", "tx13", 305 "rx14", "tx14", 306 "rx15", "tx15", 307 "rx16", "tx16", 308 "rx17", "tx17", 309 "rx18", "tx18", 310 "rx19", "tx19", 311 "rx20", "tx20"; 312 status = "disabled"; 313 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 314 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 315 interconnect-names = "dma-mem", "write"; 316 iommus = <&smmu TEGRA194_SID_APE>; 317 }; 318 319 tegra_i2s1: i2s@2901000 { 320 compatible = "nvidia,tegra194-i2s", 321 "nvidia,tegra210-i2s"; 322 reg = <0x2901000 0x100>; 323 clocks = <&bpmp TEGRA194_CLK_I2S1>, 324 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 325 clock-names = "i2s", "sync_input"; 326 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 327 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 328 assigned-clock-rates = <1536000>; 329 sound-name-prefix = "I2S1"; 330 status = "disabled"; 331 }; 332 333 tegra_i2s2: i2s@2901100 { 334 compatible = "nvidia,tegra194-i2s", 335 "nvidia,tegra210-i2s"; 336 reg = <0x2901100 0x100>; 337 clocks = <&bpmp TEGRA194_CLK_I2S2>, 338 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 339 clock-names = "i2s", "sync_input"; 340 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 341 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 342 assigned-clock-rates = <1536000>; 343 sound-name-prefix = "I2S2"; 344 status = "disabled"; 345 }; 346 347 tegra_i2s3: i2s@2901200 { 348 compatible = "nvidia,tegra194-i2s", 349 "nvidia,tegra210-i2s"; 350 reg = <0x2901200 0x100>; 351 clocks = <&bpmp TEGRA194_CLK_I2S3>, 352 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 353 clock-names = "i2s", "sync_input"; 354 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 355 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 356 assigned-clock-rates = <1536000>; 357 sound-name-prefix = "I2S3"; 358 status = "disabled"; 359 }; 360 361 tegra_i2s4: i2s@2901300 { 362 compatible = "nvidia,tegra194-i2s", 363 "nvidia,tegra210-i2s"; 364 reg = <0x2901300 0x100>; 365 clocks = <&bpmp TEGRA194_CLK_I2S4>, 366 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 367 clock-names = "i2s", "sync_input"; 368 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 369 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 370 assigned-clock-rates = <1536000>; 371 sound-name-prefix = "I2S4"; 372 status = "disabled"; 373 }; 374 375 tegra_i2s5: i2s@2901400 { 376 compatible = "nvidia,tegra194-i2s", 377 "nvidia,tegra210-i2s"; 378 reg = <0x2901400 0x100>; 379 clocks = <&bpmp TEGRA194_CLK_I2S5>, 380 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 381 clock-names = "i2s", "sync_input"; 382 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 383 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 384 assigned-clock-rates = <1536000>; 385 sound-name-prefix = "I2S5"; 386 status = "disabled"; 387 }; 388 389 tegra_i2s6: i2s@2901500 { 390 compatible = "nvidia,tegra194-i2s", 391 "nvidia,tegra210-i2s"; 392 reg = <0x2901500 0x100>; 393 clocks = <&bpmp TEGRA194_CLK_I2S6>, 394 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 395 clock-names = "i2s", "sync_input"; 396 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 397 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <1536000>; 399 sound-name-prefix = "I2S6"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic1: dmic@2904000 { 404 compatible = "nvidia,tegra194-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x2904000 0x100>; 407 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 410 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC1"; 413 status = "disabled"; 414 }; 415 416 tegra_dmic2: dmic@2904100 { 417 compatible = "nvidia,tegra194-dmic", 418 "nvidia,tegra210-dmic"; 419 reg = <0x2904100 0x100>; 420 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 421 clock-names = "dmic"; 422 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 423 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <3072000>; 425 sound-name-prefix = "DMIC2"; 426 status = "disabled"; 427 }; 428 429 tegra_dmic3: dmic@2904200 { 430 compatible = "nvidia,tegra194-dmic", 431 "nvidia,tegra210-dmic"; 432 reg = <0x2904200 0x100>; 433 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 434 clock-names = "dmic"; 435 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 436 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <3072000>; 438 sound-name-prefix = "DMIC3"; 439 status = "disabled"; 440 }; 441 442 tegra_dmic4: dmic@2904300 { 443 compatible = "nvidia,tegra194-dmic", 444 "nvidia,tegra210-dmic"; 445 reg = <0x2904300 0x100>; 446 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 447 clock-names = "dmic"; 448 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 449 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 450 assigned-clock-rates = <3072000>; 451 sound-name-prefix = "DMIC4"; 452 status = "disabled"; 453 }; 454 455 tegra_dspk1: dspk@2905000 { 456 compatible = "nvidia,tegra194-dspk", 457 "nvidia,tegra186-dspk"; 458 reg = <0x2905000 0x100>; 459 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 460 clock-names = "dspk"; 461 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 462 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 463 assigned-clock-rates = <12288000>; 464 sound-name-prefix = "DSPK1"; 465 status = "disabled"; 466 }; 467 468 tegra_dspk2: dspk@2905100 { 469 compatible = "nvidia,tegra194-dspk", 470 "nvidia,tegra186-dspk"; 471 reg = <0x2905100 0x100>; 472 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 473 clock-names = "dspk"; 474 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 475 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 476 assigned-clock-rates = <12288000>; 477 sound-name-prefix = "DSPK2"; 478 status = "disabled"; 479 }; 480 481 tegra_sfc1: sfc@2902000 { 482 compatible = "nvidia,tegra194-sfc", 483 "nvidia,tegra210-sfc"; 484 reg = <0x2902000 0x200>; 485 sound-name-prefix = "SFC1"; 486 status = "disabled"; 487 }; 488 489 tegra_sfc2: sfc@2902200 { 490 compatible = "nvidia,tegra194-sfc", 491 "nvidia,tegra210-sfc"; 492 reg = <0x2902200 0x200>; 493 sound-name-prefix = "SFC2"; 494 status = "disabled"; 495 }; 496 497 tegra_sfc3: sfc@2902400 { 498 compatible = "nvidia,tegra194-sfc", 499 "nvidia,tegra210-sfc"; 500 reg = <0x2902400 0x200>; 501 sound-name-prefix = "SFC3"; 502 status = "disabled"; 503 }; 504 505 tegra_sfc4: sfc@2902600 { 506 compatible = "nvidia,tegra194-sfc", 507 "nvidia,tegra210-sfc"; 508 reg = <0x2902600 0x200>; 509 sound-name-prefix = "SFC4"; 510 status = "disabled"; 511 }; 512 513 tegra_mvc1: mvc@290a000 { 514 compatible = "nvidia,tegra194-mvc", 515 "nvidia,tegra210-mvc"; 516 reg = <0x290a000 0x200>; 517 sound-name-prefix = "MVC1"; 518 status = "disabled"; 519 }; 520 521 tegra_mvc2: mvc@290a200 { 522 compatible = "nvidia,tegra194-mvc", 523 "nvidia,tegra210-mvc"; 524 reg = <0x290a200 0x200>; 525 sound-name-prefix = "MVC2"; 526 status = "disabled"; 527 }; 528 529 tegra_amx1: amx@2903000 { 530 compatible = "nvidia,tegra194-amx"; 531 reg = <0x2903000 0x100>; 532 sound-name-prefix = "AMX1"; 533 status = "disabled"; 534 }; 535 536 tegra_amx2: amx@2903100 { 537 compatible = "nvidia,tegra194-amx"; 538 reg = <0x2903100 0x100>; 539 sound-name-prefix = "AMX2"; 540 status = "disabled"; 541 }; 542 543 tegra_amx3: amx@2903200 { 544 compatible = "nvidia,tegra194-amx"; 545 reg = <0x2903200 0x100>; 546 sound-name-prefix = "AMX3"; 547 status = "disabled"; 548 }; 549 550 tegra_amx4: amx@2903300 { 551 compatible = "nvidia,tegra194-amx"; 552 reg = <0x2903300 0x100>; 553 sound-name-prefix = "AMX4"; 554 status = "disabled"; 555 }; 556 557 tegra_adx1: adx@2903800 { 558 compatible = "nvidia,tegra194-adx", 559 "nvidia,tegra210-adx"; 560 reg = <0x2903800 0x100>; 561 sound-name-prefix = "ADX1"; 562 status = "disabled"; 563 }; 564 565 tegra_adx2: adx@2903900 { 566 compatible = "nvidia,tegra194-adx", 567 "nvidia,tegra210-adx"; 568 reg = <0x2903900 0x100>; 569 sound-name-prefix = "ADX2"; 570 status = "disabled"; 571 }; 572 573 tegra_adx3: adx@2903a00 { 574 compatible = "nvidia,tegra194-adx", 575 "nvidia,tegra210-adx"; 576 reg = <0x2903a00 0x100>; 577 sound-name-prefix = "ADX3"; 578 status = "disabled"; 579 }; 580 581 tegra_adx4: adx@2903b00 { 582 compatible = "nvidia,tegra194-adx", 583 "nvidia,tegra210-adx"; 584 reg = <0x2903b00 0x100>; 585 sound-name-prefix = "ADX4"; 586 status = "disabled"; 587 }; 588 589 tegra_ope1: processing-engine@2908000 { 590 compatible = "nvidia,tegra194-ope", 591 "nvidia,tegra210-ope"; 592 reg = <0x2908000 0x100>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges; 596 sound-name-prefix = "OPE1"; 597 status = "disabled"; 598 599 equalizer@2908100 { 600 compatible = "nvidia,tegra194-peq", 601 "nvidia,tegra210-peq"; 602 reg = <0x2908100 0x100>; 603 }; 604 605 dynamic-range-compressor@2908200 { 606 compatible = "nvidia,tegra194-mbdrc", 607 "nvidia,tegra210-mbdrc"; 608 reg = <0x2908200 0x200>; 609 }; 610 }; 611 612 tegra_amixer: amixer@290bb00 { 613 compatible = "nvidia,tegra194-amixer", 614 "nvidia,tegra210-amixer"; 615 reg = <0x290bb00 0x800>; 616 sound-name-prefix = "MIXER1"; 617 status = "disabled"; 618 }; 619 620 tegra_asrc: asrc@2910000 { 621 compatible = "nvidia,tegra194-asrc", 622 "nvidia,tegra186-asrc"; 623 reg = <0x2910000 0x2000>; 624 sound-name-prefix = "ASRC1"; 625 status = "disabled"; 626 }; 627 }; 628 }; 629 630 pinmux: pinmux@2430000 { 631 compatible = "nvidia,tegra194-pinmux"; 632 reg = <0x2430000 0x17000>; 633 status = "okay"; 634 635 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 636 pex_rst { 637 nvidia,pins = "pex_l5_rst_n_pgg1"; 638 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 639 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 640 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 641 nvidia,tristate = <TEGRA_PIN_DISABLE>; 642 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 643 }; 644 }; 645 646 clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { 647 clkreq { 648 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 649 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 650 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 651 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 652 nvidia,tristate = <TEGRA_PIN_DISABLE>; 653 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 654 }; 655 }; 656 }; 657 658 mc: memory-controller@2c00000 { 659 compatible = "nvidia,tegra194-mc"; 660 reg = <0x02c00000 0x10000>, /* MC-SID */ 661 <0x02c10000 0x10000>, /* MC Broadcast*/ 662 <0x02c20000 0x10000>, /* MC0 */ 663 <0x02c30000 0x10000>, /* MC1 */ 664 <0x02c40000 0x10000>, /* MC2 */ 665 <0x02c50000 0x10000>, /* MC3 */ 666 <0x02b80000 0x10000>, /* MC4 */ 667 <0x02b90000 0x10000>, /* MC5 */ 668 <0x02ba0000 0x10000>, /* MC6 */ 669 <0x02bb0000 0x10000>, /* MC7 */ 670 <0x01700000 0x10000>, /* MC8 */ 671 <0x01710000 0x10000>, /* MC9 */ 672 <0x01720000 0x10000>, /* MC10 */ 673 <0x01730000 0x10000>, /* MC11 */ 674 <0x01740000 0x10000>, /* MC12 */ 675 <0x01750000 0x10000>, /* MC13 */ 676 <0x01760000 0x10000>, /* MC14 */ 677 <0x01770000 0x10000>; /* MC15 */ 678 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 679 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 680 "ch11", "ch12", "ch13", "ch14", "ch15"; 681 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 682 #interconnect-cells = <1>; 683 status = "disabled"; 684 685 #address-cells = <2>; 686 #size-cells = <2>; 687 688 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 689 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 690 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 691 692 /* 693 * Bit 39 of addresses passing through the memory 694 * controller selects the XBAR format used when memory 695 * is accessed. This is used to transparently access 696 * memory in the XBAR format used by the discrete GPU 697 * (bit 39 set) or Tegra (bit 39 clear). 698 * 699 * As a consequence, the operating system must ensure 700 * that bit 39 is never used implicitly, for example 701 * via an I/O virtual address mapping of an IOMMU. If 702 * devices require access to the XBAR switch, their 703 * drivers must set this bit explicitly. 704 * 705 * Limit the DMA range for memory clients to [38:0]. 706 */ 707 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 708 709 emc: external-memory-controller@2c60000 { 710 compatible = "nvidia,tegra194-emc"; 711 reg = <0x0 0x02c60000 0x0 0x90000>, 712 <0x0 0x01780000 0x0 0x80000>; 713 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&bpmp TEGRA194_CLK_EMC>; 715 clock-names = "emc"; 716 717 #interconnect-cells = <0>; 718 719 nvidia,bpmp = <&bpmp>; 720 }; 721 }; 722 723 timer@3010000 { 724 compatible = "nvidia,tegra186-timer"; 725 reg = <0x03010000 0x000e0000>; 726 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 736 status = "okay"; 737 }; 738 739 uarta: serial@3100000 { 740 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 741 reg = <0x03100000 0x40>; 742 reg-shift = <2>; 743 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&bpmp TEGRA194_CLK_UARTA>; 745 clock-names = "serial"; 746 resets = <&bpmp TEGRA194_RESET_UARTA>; 747 reset-names = "serial"; 748 status = "disabled"; 749 }; 750 751 uartb: serial@3110000 { 752 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 753 reg = <0x03110000 0x40>; 754 reg-shift = <2>; 755 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&bpmp TEGRA194_CLK_UARTB>; 757 clock-names = "serial"; 758 resets = <&bpmp TEGRA194_RESET_UARTB>; 759 reset-names = "serial"; 760 status = "disabled"; 761 }; 762 763 uartd: serial@3130000 { 764 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 765 reg = <0x03130000 0x40>; 766 reg-shift = <2>; 767 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&bpmp TEGRA194_CLK_UARTD>; 769 clock-names = "serial"; 770 resets = <&bpmp TEGRA194_RESET_UARTD>; 771 reset-names = "serial"; 772 status = "disabled"; 773 }; 774 775 uarte: serial@3140000 { 776 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 777 reg = <0x03140000 0x40>; 778 reg-shift = <2>; 779 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&bpmp TEGRA194_CLK_UARTE>; 781 clock-names = "serial"; 782 resets = <&bpmp TEGRA194_RESET_UARTE>; 783 reset-names = "serial"; 784 status = "disabled"; 785 }; 786 787 uartf: serial@3150000 { 788 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 789 reg = <0x03150000 0x40>; 790 reg-shift = <2>; 791 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&bpmp TEGRA194_CLK_UARTF>; 793 clock-names = "serial"; 794 resets = <&bpmp TEGRA194_RESET_UARTF>; 795 reset-names = "serial"; 796 status = "disabled"; 797 }; 798 799 gen1_i2c: i2c@3160000 { 800 compatible = "nvidia,tegra194-i2c"; 801 reg = <0x03160000 0x10000>; 802 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 clocks = <&bpmp TEGRA194_CLK_I2C1>; 806 clock-names = "div-clk"; 807 resets = <&bpmp TEGRA194_RESET_I2C1>; 808 reset-names = "i2c"; 809 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 810 dma-coherent; 811 dmas = <&gpcdma 21>, <&gpcdma 21>; 812 dma-names = "rx", "tx"; 813 status = "disabled"; 814 }; 815 816 uarth: serial@3170000 { 817 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 818 reg = <0x03170000 0x40>; 819 reg-shift = <2>; 820 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&bpmp TEGRA194_CLK_UARTH>; 822 clock-names = "serial"; 823 resets = <&bpmp TEGRA194_RESET_UARTH>; 824 reset-names = "serial"; 825 status = "disabled"; 826 }; 827 828 cam_i2c: i2c@3180000 { 829 compatible = "nvidia,tegra194-i2c"; 830 reg = <0x03180000 0x10000>; 831 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 clocks = <&bpmp TEGRA194_CLK_I2C3>; 835 clock-names = "div-clk"; 836 resets = <&bpmp TEGRA194_RESET_I2C3>; 837 reset-names = "i2c"; 838 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 839 dma-coherent; 840 dmas = <&gpcdma 23>, <&gpcdma 23>; 841 dma-names = "rx", "tx"; 842 status = "disabled"; 843 }; 844 845 /* shares pads with dpaux1 */ 846 dp_aux_ch1_i2c: i2c@3190000 { 847 compatible = "nvidia,tegra194-i2c"; 848 reg = <0x03190000 0x10000>; 849 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 clocks = <&bpmp TEGRA194_CLK_I2C4>; 853 clock-names = "div-clk"; 854 resets = <&bpmp TEGRA194_RESET_I2C4>; 855 reset-names = "i2c"; 856 pinctrl-0 = <&state_dpaux1_i2c>; 857 pinctrl-1 = <&state_dpaux1_off>; 858 pinctrl-names = "default", "idle"; 859 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 860 dma-coherent; 861 dmas = <&gpcdma 26>, <&gpcdma 26>; 862 dma-names = "rx", "tx"; 863 status = "disabled"; 864 }; 865 866 /* shares pads with dpaux0 */ 867 dp_aux_ch0_i2c: i2c@31b0000 { 868 compatible = "nvidia,tegra194-i2c"; 869 reg = <0x031b0000 0x10000>; 870 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 clocks = <&bpmp TEGRA194_CLK_I2C6>; 874 clock-names = "div-clk"; 875 resets = <&bpmp TEGRA194_RESET_I2C6>; 876 reset-names = "i2c"; 877 pinctrl-0 = <&state_dpaux0_i2c>; 878 pinctrl-1 = <&state_dpaux0_off>; 879 pinctrl-names = "default", "idle"; 880 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 881 dma-coherent; 882 dmas = <&gpcdma 30>, <&gpcdma 30>; 883 dma-names = "rx", "tx"; 884 status = "disabled"; 885 }; 886 887 /* shares pads with dpaux2 */ 888 dp_aux_ch2_i2c: i2c@31c0000 { 889 compatible = "nvidia,tegra194-i2c"; 890 reg = <0x031c0000 0x10000>; 891 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 clocks = <&bpmp TEGRA194_CLK_I2C7>; 895 clock-names = "div-clk"; 896 resets = <&bpmp TEGRA194_RESET_I2C7>; 897 reset-names = "i2c"; 898 pinctrl-0 = <&state_dpaux2_i2c>; 899 pinctrl-1 = <&state_dpaux2_off>; 900 pinctrl-names = "default", "idle"; 901 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 902 dma-coherent; 903 dmas = <&gpcdma 27>, <&gpcdma 27>; 904 dma-names = "rx", "tx"; 905 status = "disabled"; 906 }; 907 908 /* shares pads with dpaux3 */ 909 dp_aux_ch3_i2c: i2c@31e0000 { 910 compatible = "nvidia,tegra194-i2c"; 911 reg = <0x031e0000 0x10000>; 912 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 clocks = <&bpmp TEGRA194_CLK_I2C9>; 916 clock-names = "div-clk"; 917 resets = <&bpmp TEGRA194_RESET_I2C9>; 918 reset-names = "i2c"; 919 pinctrl-0 = <&state_dpaux3_i2c>; 920 pinctrl-1 = <&state_dpaux3_off>; 921 pinctrl-names = "default", "idle"; 922 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 923 dma-coherent; 924 dmas = <&gpcdma 31>, <&gpcdma 31>; 925 dma-names = "rx", "tx"; 926 status = "disabled"; 927 }; 928 929 spi@3270000 { 930 compatible = "nvidia,tegra194-qspi"; 931 reg = <0x3270000 0x1000>; 932 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 936 <&bpmp TEGRA194_CLK_QSPI0_PM>; 937 clock-names = "qspi", "qspi_out"; 938 resets = <&bpmp TEGRA194_RESET_QSPI0>; 939 status = "disabled"; 940 }; 941 942 spi@3300000 { 943 compatible = "nvidia,tegra194-qspi"; 944 reg = <0x3300000 0x1000>; 945 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 949 <&bpmp TEGRA194_CLK_QSPI1_PM>; 950 clock-names = "qspi", "qspi_out"; 951 resets = <&bpmp TEGRA194_RESET_QSPI1>; 952 status = "disabled"; 953 }; 954 955 pwm1: pwm@3280000 { 956 compatible = "nvidia,tegra194-pwm", 957 "nvidia,tegra186-pwm"; 958 reg = <0x3280000 0x10000>; 959 clocks = <&bpmp TEGRA194_CLK_PWM1>; 960 resets = <&bpmp TEGRA194_RESET_PWM1>; 961 reset-names = "pwm"; 962 status = "disabled"; 963 #pwm-cells = <2>; 964 }; 965 966 pwm2: pwm@3290000 { 967 compatible = "nvidia,tegra194-pwm", 968 "nvidia,tegra186-pwm"; 969 reg = <0x3290000 0x10000>; 970 clocks = <&bpmp TEGRA194_CLK_PWM2>; 971 resets = <&bpmp TEGRA194_RESET_PWM2>; 972 reset-names = "pwm"; 973 status = "disabled"; 974 #pwm-cells = <2>; 975 }; 976 977 pwm3: pwm@32a0000 { 978 compatible = "nvidia,tegra194-pwm", 979 "nvidia,tegra186-pwm"; 980 reg = <0x32a0000 0x10000>; 981 clocks = <&bpmp TEGRA194_CLK_PWM3>; 982 resets = <&bpmp TEGRA194_RESET_PWM3>; 983 reset-names = "pwm"; 984 status = "disabled"; 985 #pwm-cells = <2>; 986 }; 987 988 pwm5: pwm@32c0000 { 989 compatible = "nvidia,tegra194-pwm", 990 "nvidia,tegra186-pwm"; 991 reg = <0x32c0000 0x10000>; 992 clocks = <&bpmp TEGRA194_CLK_PWM5>; 993 resets = <&bpmp TEGRA194_RESET_PWM5>; 994 reset-names = "pwm"; 995 status = "disabled"; 996 #pwm-cells = <2>; 997 }; 998 999 pwm6: pwm@32d0000 { 1000 compatible = "nvidia,tegra194-pwm", 1001 "nvidia,tegra186-pwm"; 1002 reg = <0x32d0000 0x10000>; 1003 clocks = <&bpmp TEGRA194_CLK_PWM6>; 1004 resets = <&bpmp TEGRA194_RESET_PWM6>; 1005 reset-names = "pwm"; 1006 status = "disabled"; 1007 #pwm-cells = <2>; 1008 }; 1009 1010 pwm7: pwm@32e0000 { 1011 compatible = "nvidia,tegra194-pwm", 1012 "nvidia,tegra186-pwm"; 1013 reg = <0x32e0000 0x10000>; 1014 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1015 resets = <&bpmp TEGRA194_RESET_PWM7>; 1016 reset-names = "pwm"; 1017 status = "disabled"; 1018 #pwm-cells = <2>; 1019 }; 1020 1021 pwm8: pwm@32f0000 { 1022 compatible = "nvidia,tegra194-pwm", 1023 "nvidia,tegra186-pwm"; 1024 reg = <0x32f0000 0x10000>; 1025 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1026 resets = <&bpmp TEGRA194_RESET_PWM8>; 1027 reset-names = "pwm"; 1028 status = "disabled"; 1029 #pwm-cells = <2>; 1030 }; 1031 1032 sdmmc1: mmc@3400000 { 1033 compatible = "nvidia,tegra194-sdhci"; 1034 reg = <0x03400000 0x10000>; 1035 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1037 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1038 clock-names = "sdhci", "tmclk"; 1039 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1040 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1041 assigned-clock-parents = 1042 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1043 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1044 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1045 reset-names = "sdhci"; 1046 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1047 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1048 interconnect-names = "dma-mem", "write"; 1049 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1050 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1051 pinctrl-0 = <&sdmmc1_3v3>; 1052 pinctrl-1 = <&sdmmc1_1v8>; 1053 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1054 <0x07>; 1055 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1056 <0x07>; 1057 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1058 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1059 <0x07>; 1060 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1061 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1062 nvidia,default-tap = <0x9>; 1063 nvidia,default-trim = <0x5>; 1064 sd-uhs-sdr25; 1065 sd-uhs-sdr50; 1066 sd-uhs-ddr50; 1067 sd-uhs-sdr104; 1068 status = "disabled"; 1069 }; 1070 1071 sdmmc3: mmc@3440000 { 1072 compatible = "nvidia,tegra194-sdhci"; 1073 reg = <0x03440000 0x10000>; 1074 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1076 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1077 clock-names = "sdhci", "tmclk"; 1078 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1079 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1080 assigned-clock-parents = 1081 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1082 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1083 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1084 reset-names = "sdhci"; 1085 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1086 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1087 interconnect-names = "dma-mem", "write"; 1088 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1089 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1090 pinctrl-0 = <&sdmmc3_3v3>; 1091 pinctrl-1 = <&sdmmc3_1v8>; 1092 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1093 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1094 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1095 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1096 <0x07>; 1097 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1098 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1099 <0x07>; 1100 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1101 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1102 nvidia,default-tap = <0x9>; 1103 nvidia,default-trim = <0x5>; 1104 sd-uhs-sdr25; 1105 sd-uhs-sdr50; 1106 sd-uhs-ddr50; 1107 sd-uhs-sdr104; 1108 status = "disabled"; 1109 }; 1110 1111 sdmmc4: mmc@3460000 { 1112 compatible = "nvidia,tegra194-sdhci"; 1113 reg = <0x03460000 0x10000>; 1114 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1116 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1117 clock-names = "sdhci", "tmclk"; 1118 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1119 <&bpmp TEGRA194_CLK_PLLC4>; 1120 assigned-clock-parents = 1121 <&bpmp TEGRA194_CLK_PLLC4>; 1122 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1123 reset-names = "sdhci"; 1124 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1125 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1126 interconnect-names = "dma-mem", "write"; 1127 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1128 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1129 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1130 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1131 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1132 <0x0a>; 1133 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1134 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1135 <0x0a>; 1136 nvidia,default-tap = <0x8>; 1137 nvidia,default-trim = <0x14>; 1138 nvidia,dqs-trim = <40>; 1139 cap-mmc-highspeed; 1140 mmc-ddr-1_8v; 1141 mmc-hs200-1_8v; 1142 mmc-hs400-1_8v; 1143 mmc-hs400-enhanced-strobe; 1144 supports-cqe; 1145 status = "disabled"; 1146 }; 1147 1148 hda@3510000 { 1149 compatible = "nvidia,tegra194-hda"; 1150 reg = <0x3510000 0x10000>; 1151 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&bpmp TEGRA194_CLK_HDA>, 1153 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1154 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1155 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1156 resets = <&bpmp TEGRA194_RESET_HDA>, 1157 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1158 reset-names = "hda", "hda2hdmi"; 1159 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1160 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1161 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1162 interconnect-names = "dma-mem", "write"; 1163 iommus = <&smmu TEGRA194_SID_HDA>; 1164 status = "disabled"; 1165 }; 1166 1167 xusb_padctl: padctl@3520000 { 1168 compatible = "nvidia,tegra194-xusb-padctl"; 1169 reg = <0x03520000 0x1000>, 1170 <0x03540000 0x1000>; 1171 reg-names = "padctl", "ao"; 1172 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1173 1174 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1175 reset-names = "padctl"; 1176 1177 status = "disabled"; 1178 1179 pads { 1180 usb2 { 1181 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1182 clock-names = "trk"; 1183 1184 lanes { 1185 usb2-0 { 1186 nvidia,function = "xusb"; 1187 status = "disabled"; 1188 #phy-cells = <0>; 1189 }; 1190 1191 usb2-1 { 1192 nvidia,function = "xusb"; 1193 status = "disabled"; 1194 #phy-cells = <0>; 1195 }; 1196 1197 usb2-2 { 1198 nvidia,function = "xusb"; 1199 status = "disabled"; 1200 #phy-cells = <0>; 1201 }; 1202 1203 usb2-3 { 1204 nvidia,function = "xusb"; 1205 status = "disabled"; 1206 #phy-cells = <0>; 1207 }; 1208 }; 1209 }; 1210 1211 usb3 { 1212 lanes { 1213 usb3-0 { 1214 nvidia,function = "xusb"; 1215 status = "disabled"; 1216 #phy-cells = <0>; 1217 }; 1218 1219 usb3-1 { 1220 nvidia,function = "xusb"; 1221 status = "disabled"; 1222 #phy-cells = <0>; 1223 }; 1224 1225 usb3-2 { 1226 nvidia,function = "xusb"; 1227 status = "disabled"; 1228 #phy-cells = <0>; 1229 }; 1230 1231 usb3-3 { 1232 nvidia,function = "xusb"; 1233 status = "disabled"; 1234 #phy-cells = <0>; 1235 }; 1236 }; 1237 }; 1238 }; 1239 1240 ports { 1241 usb2-0 { 1242 status = "disabled"; 1243 }; 1244 1245 usb2-1 { 1246 status = "disabled"; 1247 }; 1248 1249 usb2-2 { 1250 status = "disabled"; 1251 }; 1252 1253 usb2-3 { 1254 status = "disabled"; 1255 }; 1256 1257 usb3-0 { 1258 status = "disabled"; 1259 }; 1260 1261 usb3-1 { 1262 status = "disabled"; 1263 }; 1264 1265 usb3-2 { 1266 status = "disabled"; 1267 }; 1268 1269 usb3-3 { 1270 status = "disabled"; 1271 }; 1272 }; 1273 }; 1274 1275 usb@3550000 { 1276 compatible = "nvidia,tegra194-xudc"; 1277 reg = <0x03550000 0x8000>, 1278 <0x03558000 0x1000>; 1279 reg-names = "base", "fpci"; 1280 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1282 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1283 <&bpmp TEGRA194_CLK_XUSB_SS>, 1284 <&bpmp TEGRA194_CLK_XUSB_FS>; 1285 clock-names = "dev", "ss", "ss_src", "fs_src"; 1286 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1287 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1288 interconnect-names = "dma-mem", "write"; 1289 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1290 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1291 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1292 power-domain-names = "dev", "ss"; 1293 nvidia,xusb-padctl = <&xusb_padctl>; 1294 status = "disabled"; 1295 }; 1296 1297 usb@3610000 { 1298 compatible = "nvidia,tegra194-xusb"; 1299 reg = <0x03610000 0x40000>, 1300 <0x03600000 0x10000>; 1301 reg-names = "hcd", "fpci"; 1302 1303 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1305 1306 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1307 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1308 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1309 <&bpmp TEGRA194_CLK_XUSB_SS>, 1310 <&bpmp TEGRA194_CLK_CLK_M>, 1311 <&bpmp TEGRA194_CLK_XUSB_FS>, 1312 <&bpmp TEGRA194_CLK_UTMIPLL>, 1313 <&bpmp TEGRA194_CLK_CLK_M>, 1314 <&bpmp TEGRA194_CLK_PLLE>; 1315 clock-names = "xusb_host", "xusb_falcon_src", 1316 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1317 "xusb_fs_src", "pll_u_480m", "clk_m", 1318 "pll_e"; 1319 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1320 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1321 interconnect-names = "dma-mem", "write"; 1322 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1323 1324 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1325 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1326 power-domain-names = "xusb_host", "xusb_ss"; 1327 1328 nvidia,xusb-padctl = <&xusb_padctl>; 1329 status = "disabled"; 1330 }; 1331 1332 fuse@3820000 { 1333 compatible = "nvidia,tegra194-efuse"; 1334 reg = <0x03820000 0x10000>; 1335 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1336 clock-names = "fuse"; 1337 }; 1338 1339 gic: interrupt-controller@3881000 { 1340 compatible = "arm,gic-400"; 1341 #interrupt-cells = <3>; 1342 interrupt-controller; 1343 reg = <0x03881000 0x1000>, 1344 <0x03882000 0x2000>, 1345 <0x03884000 0x2000>, 1346 <0x03886000 0x2000>; 1347 interrupts = <GIC_PPI 9 1348 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1349 interrupt-parent = <&gic>; 1350 }; 1351 1352 cec@3960000 { 1353 compatible = "nvidia,tegra194-cec"; 1354 reg = <0x03960000 0x10000>; 1355 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1356 clocks = <&bpmp TEGRA194_CLK_CEC>; 1357 clock-names = "cec"; 1358 status = "disabled"; 1359 }; 1360 1361 hte_lic: hardware-timestamp@3aa0000 { 1362 compatible = "nvidia,tegra194-gte-lic"; 1363 reg = <0x3aa0000 0x10000>; 1364 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1365 nvidia,int-threshold = <1>; 1366 nvidia,slices = <11>; 1367 #timestamp-cells = <1>; 1368 status = "okay"; 1369 }; 1370 1371 hsp_top0: hsp@3c00000 { 1372 compatible = "nvidia,tegra194-hsp"; 1373 reg = <0x03c00000 0xa0000>; 1374 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1383 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1384 "shared3", "shared4", "shared5", "shared6", 1385 "shared7"; 1386 #mbox-cells = <2>; 1387 }; 1388 1389 p2u_hsio_0: phy@3e10000 { 1390 compatible = "nvidia,tegra194-p2u"; 1391 reg = <0x03e10000 0x10000>; 1392 reg-names = "ctl"; 1393 1394 #phy-cells = <0>; 1395 }; 1396 1397 p2u_hsio_1: phy@3e20000 { 1398 compatible = "nvidia,tegra194-p2u"; 1399 reg = <0x03e20000 0x10000>; 1400 reg-names = "ctl"; 1401 1402 #phy-cells = <0>; 1403 }; 1404 1405 p2u_hsio_2: phy@3e30000 { 1406 compatible = "nvidia,tegra194-p2u"; 1407 reg = <0x03e30000 0x10000>; 1408 reg-names = "ctl"; 1409 1410 #phy-cells = <0>; 1411 }; 1412 1413 p2u_hsio_3: phy@3e40000 { 1414 compatible = "nvidia,tegra194-p2u"; 1415 reg = <0x03e40000 0x10000>; 1416 reg-names = "ctl"; 1417 1418 #phy-cells = <0>; 1419 }; 1420 1421 p2u_hsio_4: phy@3e50000 { 1422 compatible = "nvidia,tegra194-p2u"; 1423 reg = <0x03e50000 0x10000>; 1424 reg-names = "ctl"; 1425 1426 #phy-cells = <0>; 1427 }; 1428 1429 p2u_hsio_5: phy@3e60000 { 1430 compatible = "nvidia,tegra194-p2u"; 1431 reg = <0x03e60000 0x10000>; 1432 reg-names = "ctl"; 1433 1434 #phy-cells = <0>; 1435 }; 1436 1437 p2u_hsio_6: phy@3e70000 { 1438 compatible = "nvidia,tegra194-p2u"; 1439 reg = <0x03e70000 0x10000>; 1440 reg-names = "ctl"; 1441 1442 #phy-cells = <0>; 1443 }; 1444 1445 p2u_hsio_7: phy@3e80000 { 1446 compatible = "nvidia,tegra194-p2u"; 1447 reg = <0x03e80000 0x10000>; 1448 reg-names = "ctl"; 1449 1450 #phy-cells = <0>; 1451 }; 1452 1453 p2u_hsio_8: phy@3e90000 { 1454 compatible = "nvidia,tegra194-p2u"; 1455 reg = <0x03e90000 0x10000>; 1456 reg-names = "ctl"; 1457 1458 #phy-cells = <0>; 1459 }; 1460 1461 p2u_hsio_9: phy@3ea0000 { 1462 compatible = "nvidia,tegra194-p2u"; 1463 reg = <0x03ea0000 0x10000>; 1464 reg-names = "ctl"; 1465 1466 #phy-cells = <0>; 1467 }; 1468 1469 p2u_nvhs_0: phy@3eb0000 { 1470 compatible = "nvidia,tegra194-p2u"; 1471 reg = <0x03eb0000 0x10000>; 1472 reg-names = "ctl"; 1473 1474 #phy-cells = <0>; 1475 }; 1476 1477 p2u_nvhs_1: phy@3ec0000 { 1478 compatible = "nvidia,tegra194-p2u"; 1479 reg = <0x03ec0000 0x10000>; 1480 reg-names = "ctl"; 1481 1482 #phy-cells = <0>; 1483 }; 1484 1485 p2u_nvhs_2: phy@3ed0000 { 1486 compatible = "nvidia,tegra194-p2u"; 1487 reg = <0x03ed0000 0x10000>; 1488 reg-names = "ctl"; 1489 1490 #phy-cells = <0>; 1491 }; 1492 1493 p2u_nvhs_3: phy@3ee0000 { 1494 compatible = "nvidia,tegra194-p2u"; 1495 reg = <0x03ee0000 0x10000>; 1496 reg-names = "ctl"; 1497 1498 #phy-cells = <0>; 1499 }; 1500 1501 p2u_nvhs_4: phy@3ef0000 { 1502 compatible = "nvidia,tegra194-p2u"; 1503 reg = <0x03ef0000 0x10000>; 1504 reg-names = "ctl"; 1505 1506 #phy-cells = <0>; 1507 }; 1508 1509 p2u_nvhs_5: phy@3f00000 { 1510 compatible = "nvidia,tegra194-p2u"; 1511 reg = <0x03f00000 0x10000>; 1512 reg-names = "ctl"; 1513 1514 #phy-cells = <0>; 1515 }; 1516 1517 p2u_nvhs_6: phy@3f10000 { 1518 compatible = "nvidia,tegra194-p2u"; 1519 reg = <0x03f10000 0x10000>; 1520 reg-names = "ctl"; 1521 1522 #phy-cells = <0>; 1523 }; 1524 1525 p2u_nvhs_7: phy@3f20000 { 1526 compatible = "nvidia,tegra194-p2u"; 1527 reg = <0x03f20000 0x10000>; 1528 reg-names = "ctl"; 1529 1530 #phy-cells = <0>; 1531 }; 1532 1533 p2u_hsio_10: phy@3f30000 { 1534 compatible = "nvidia,tegra194-p2u"; 1535 reg = <0x03f30000 0x10000>; 1536 reg-names = "ctl"; 1537 1538 #phy-cells = <0>; 1539 }; 1540 1541 p2u_hsio_11: phy@3f40000 { 1542 compatible = "nvidia,tegra194-p2u"; 1543 reg = <0x03f40000 0x10000>; 1544 reg-names = "ctl"; 1545 1546 #phy-cells = <0>; 1547 }; 1548 1549 sce-noc@b600000 { 1550 compatible = "nvidia,tegra194-sce-noc"; 1551 reg = <0xb600000 0x1000>; 1552 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1554 nvidia,axi2apb = <&axi2apb>; 1555 nvidia,apbmisc = <&apbmisc>; 1556 status = "okay"; 1557 }; 1558 1559 rce-noc@be00000 { 1560 compatible = "nvidia,tegra194-rce-noc"; 1561 reg = <0xbe00000 0x1000>; 1562 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1564 nvidia,axi2apb = <&axi2apb>; 1565 nvidia,apbmisc = <&apbmisc>; 1566 status = "okay"; 1567 }; 1568 1569 hsp_aon: hsp@c150000 { 1570 compatible = "nvidia,tegra194-hsp"; 1571 reg = <0x0c150000 0x90000>; 1572 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1576 /* 1577 * Shared interrupt 0 is routed only to AON/SPE, so 1578 * we only have 4 shared interrupts for the CCPLEX. 1579 */ 1580 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1581 #mbox-cells = <2>; 1582 }; 1583 1584 hte_aon: hardware-timestamp@c1e0000 { 1585 compatible = "nvidia,tegra194-gte-aon"; 1586 reg = <0xc1e0000 0x10000>; 1587 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1588 nvidia,int-threshold = <1>; 1589 nvidia,slices = <3>; 1590 #timestamp-cells = <1>; 1591 status = "okay"; 1592 }; 1593 1594 gen2_i2c: i2c@c240000 { 1595 compatible = "nvidia,tegra194-i2c"; 1596 reg = <0x0c240000 0x10000>; 1597 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1601 clock-names = "div-clk"; 1602 resets = <&bpmp TEGRA194_RESET_I2C2>; 1603 reset-names = "i2c"; 1604 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1605 dma-coherent; 1606 dmas = <&gpcdma 22>, <&gpcdma 22>; 1607 dma-names = "rx", "tx"; 1608 status = "disabled"; 1609 }; 1610 1611 gen8_i2c: i2c@c250000 { 1612 compatible = "nvidia,tegra194-i2c"; 1613 reg = <0x0c250000 0x10000>; 1614 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1618 clock-names = "div-clk"; 1619 resets = <&bpmp TEGRA194_RESET_I2C8>; 1620 reset-names = "i2c"; 1621 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1622 dma-coherent; 1623 dmas = <&gpcdma 0>, <&gpcdma 0>; 1624 dma-names = "rx", "tx"; 1625 status = "disabled"; 1626 }; 1627 1628 uartc: serial@c280000 { 1629 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1630 reg = <0x0c280000 0x40>; 1631 reg-shift = <2>; 1632 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1634 clock-names = "serial"; 1635 resets = <&bpmp TEGRA194_RESET_UARTC>; 1636 reset-names = "serial"; 1637 status = "disabled"; 1638 }; 1639 1640 uartg: serial@c290000 { 1641 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1642 reg = <0x0c290000 0x40>; 1643 reg-shift = <2>; 1644 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1645 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1646 clock-names = "serial"; 1647 resets = <&bpmp TEGRA194_RESET_UARTG>; 1648 reset-names = "serial"; 1649 status = "disabled"; 1650 }; 1651 1652 rtc: rtc@c2a0000 { 1653 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1654 reg = <0x0c2a0000 0x10000>; 1655 interrupt-parent = <&pmc>; 1656 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1657 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1658 clock-names = "rtc"; 1659 status = "disabled"; 1660 }; 1661 1662 gpio_aon: gpio@c2f0000 { 1663 compatible = "nvidia,tegra194-gpio-aon"; 1664 reg-names = "security", "gpio"; 1665 reg = <0xc2f0000 0x1000>, 1666 <0xc2f1000 0x1000>; 1667 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1671 gpio-controller; 1672 #gpio-cells = <2>; 1673 interrupt-controller; 1674 #interrupt-cells = <2>; 1675 gpio-range = <&pinmux_aon 0 0 30>; 1676 }; 1677 1678 pinmux_aon: pinmux@c300000 { 1679 compatible = "nvidia,tegra194-pinmux-aon"; 1680 reg = <0xc300000 0x4000>; 1681 1682 status = "okay"; 1683 }; 1684 1685 pwm4: pwm@c340000 { 1686 compatible = "nvidia,tegra194-pwm", 1687 "nvidia,tegra186-pwm"; 1688 reg = <0xc340000 0x10000>; 1689 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1690 resets = <&bpmp TEGRA194_RESET_PWM4>; 1691 reset-names = "pwm"; 1692 status = "disabled"; 1693 #pwm-cells = <2>; 1694 }; 1695 1696 pmc: pmc@c360000 { 1697 compatible = "nvidia,tegra194-pmc"; 1698 reg = <0x0c360000 0x10000>, 1699 <0x0c370000 0x10000>, 1700 <0x0c380000 0x10000>, 1701 <0x0c390000 0x10000>, 1702 <0x0c3a0000 0x10000>; 1703 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1704 1705 #interrupt-cells = <2>; 1706 interrupt-controller; 1707 sdmmc1_3v3: sdmmc1-3v3 { 1708 pins = "sdmmc1-hv"; 1709 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1710 }; 1711 1712 sdmmc1_1v8: sdmmc1-1v8 { 1713 pins = "sdmmc1-hv"; 1714 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1715 }; 1716 sdmmc3_3v3: sdmmc3-3v3 { 1717 pins = "sdmmc3-hv"; 1718 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1719 }; 1720 1721 sdmmc3_1v8: sdmmc3-1v8 { 1722 pins = "sdmmc3-hv"; 1723 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1724 }; 1725 1726 }; 1727 1728 aon-noc@c600000 { 1729 compatible = "nvidia,tegra194-aon-noc"; 1730 reg = <0xc600000 0x1000>; 1731 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1733 nvidia,apbmisc = <&apbmisc>; 1734 status = "okay"; 1735 }; 1736 1737 bpmp-noc@d600000 { 1738 compatible = "nvidia,tegra194-bpmp-noc"; 1739 reg = <0xd600000 0x1000>; 1740 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1742 nvidia,axi2apb = <&axi2apb>; 1743 nvidia,apbmisc = <&apbmisc>; 1744 status = "okay"; 1745 }; 1746 1747 iommu@10000000 { 1748 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1749 reg = <0x10000000 0x800000>; 1750 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1815 stream-match-mask = <0x7f80>; 1816 #global-interrupts = <1>; 1817 #iommu-cells = <1>; 1818 1819 nvidia,memory-controller = <&mc>; 1820 status = "disabled"; 1821 }; 1822 1823 smmu: iommu@12000000 { 1824 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1825 reg = <0x12000000 0x800000>, 1826 <0x11000000 0x800000>; 1827 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1893 stream-match-mask = <0x7f80>; 1894 #global-interrupts = <2>; 1895 #iommu-cells = <1>; 1896 1897 nvidia,memory-controller = <&mc>; 1898 status = "okay"; 1899 }; 1900 1901 host1x@13e00000 { 1902 compatible = "nvidia,tegra194-host1x"; 1903 reg = <0x13e00000 0x10000>, 1904 <0x13e10000 0x10000>; 1905 reg-names = "hypervisor", "vm"; 1906 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1908 interrupt-names = "syncpt", "host1x"; 1909 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1910 clock-names = "host1x"; 1911 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1912 reset-names = "host1x"; 1913 1914 #address-cells = <1>; 1915 #size-cells = <1>; 1916 1917 ranges = <0x14800000 0x14800000 0x02800000>; 1918 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1919 interconnect-names = "dma-mem"; 1920 iommus = <&smmu TEGRA194_SID_HOST1X>; 1921 1922 /* Context isolation domains */ 1923 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1924 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1925 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1926 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1927 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1928 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1929 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1930 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1931 1932 nvdec@15140000 { 1933 compatible = "nvidia,tegra194-nvdec"; 1934 reg = <0x15140000 0x00040000>; 1935 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1936 clock-names = "nvdec"; 1937 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1938 reset-names = "nvdec"; 1939 1940 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1941 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1942 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1943 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1944 interconnect-names = "dma-mem", "read-1", "write"; 1945 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1946 dma-coherent; 1947 1948 nvidia,host1x-class = <0xf5>; 1949 }; 1950 1951 display-hub@15200000 { 1952 compatible = "nvidia,tegra194-display"; 1953 reg = <0x15200000 0x00040000>; 1954 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1955 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1956 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1957 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1958 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1959 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1960 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1961 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1962 "wgrp3", "wgrp4", "wgrp5"; 1963 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1964 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1965 clock-names = "disp", "hub"; 1966 status = "disabled"; 1967 1968 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1969 1970 #address-cells = <1>; 1971 #size-cells = <1>; 1972 1973 ranges = <0x15200000 0x15200000 0x40000>; 1974 1975 display@15200000 { 1976 compatible = "nvidia,tegra194-dc"; 1977 reg = <0x15200000 0x10000>; 1978 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1979 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1980 clock-names = "dc"; 1981 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1982 reset-names = "dc"; 1983 1984 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1985 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1986 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1987 interconnect-names = "dma-mem", "read-1"; 1988 1989 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1990 nvidia,head = <0>; 1991 }; 1992 1993 display@15210000 { 1994 compatible = "nvidia,tegra194-dc"; 1995 reg = <0x15210000 0x10000>; 1996 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1997 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1998 clock-names = "dc"; 1999 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 2000 reset-names = "dc"; 2001 2002 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2003 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2004 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2005 interconnect-names = "dma-mem", "read-1"; 2006 2007 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2008 nvidia,head = <1>; 2009 }; 2010 2011 display@15220000 { 2012 compatible = "nvidia,tegra194-dc"; 2013 reg = <0x15220000 0x10000>; 2014 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2015 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2016 clock-names = "dc"; 2017 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2018 reset-names = "dc"; 2019 2020 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2021 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2022 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2023 interconnect-names = "dma-mem", "read-1"; 2024 2025 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2026 nvidia,head = <2>; 2027 }; 2028 2029 display@15230000 { 2030 compatible = "nvidia,tegra194-dc"; 2031 reg = <0x15230000 0x10000>; 2032 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2033 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2034 clock-names = "dc"; 2035 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2036 reset-names = "dc"; 2037 2038 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2039 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2040 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2041 interconnect-names = "dma-mem", "read-1"; 2042 2043 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2044 nvidia,head = <3>; 2045 }; 2046 }; 2047 2048 vic@15340000 { 2049 compatible = "nvidia,tegra194-vic"; 2050 reg = <0x15340000 0x00040000>; 2051 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2052 clocks = <&bpmp TEGRA194_CLK_VIC>; 2053 clock-names = "vic"; 2054 resets = <&bpmp TEGRA194_RESET_VIC>; 2055 reset-names = "vic"; 2056 2057 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2058 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2059 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2060 interconnect-names = "dma-mem", "write"; 2061 iommus = <&smmu TEGRA194_SID_VIC>; 2062 dma-coherent; 2063 }; 2064 2065 nvjpg@15380000 { 2066 compatible = "nvidia,tegra194-nvjpg"; 2067 reg = <0x15380000 0x40000>; 2068 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2069 clock-names = "nvjpg"; 2070 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2071 reset-names = "nvjpg"; 2072 2073 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2074 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2075 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2076 interconnect-names = "dma-mem", "write"; 2077 iommus = <&smmu TEGRA194_SID_NVJPG>; 2078 dma-coherent; 2079 }; 2080 2081 nvdec@15480000 { 2082 compatible = "nvidia,tegra194-nvdec"; 2083 reg = <0x15480000 0x00040000>; 2084 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2085 clock-names = "nvdec"; 2086 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2087 reset-names = "nvdec"; 2088 2089 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2090 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2091 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2092 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2093 interconnect-names = "dma-mem", "read-1", "write"; 2094 iommus = <&smmu TEGRA194_SID_NVDEC>; 2095 dma-coherent; 2096 2097 nvidia,host1x-class = <0xf0>; 2098 }; 2099 2100 nvenc@154c0000 { 2101 compatible = "nvidia,tegra194-nvenc"; 2102 reg = <0x154c0000 0x40000>; 2103 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2104 clock-names = "nvenc"; 2105 resets = <&bpmp TEGRA194_RESET_NVENC>; 2106 reset-names = "nvenc"; 2107 2108 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2109 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2110 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2111 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2112 interconnect-names = "dma-mem", "read-1", "write"; 2113 iommus = <&smmu TEGRA194_SID_NVENC>; 2114 dma-coherent; 2115 2116 nvidia,host1x-class = <0x21>; 2117 }; 2118 2119 dpaux0: dpaux@155c0000 { 2120 compatible = "nvidia,tegra194-dpaux"; 2121 reg = <0x155c0000 0x10000>; 2122 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2123 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2124 <&bpmp TEGRA194_CLK_PLLDP>; 2125 clock-names = "dpaux", "parent"; 2126 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2127 reset-names = "dpaux"; 2128 status = "disabled"; 2129 2130 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2131 2132 state_dpaux0_aux: pinmux-aux { 2133 groups = "dpaux-io"; 2134 function = "aux"; 2135 }; 2136 2137 state_dpaux0_i2c: pinmux-i2c { 2138 groups = "dpaux-io"; 2139 function = "i2c"; 2140 }; 2141 2142 state_dpaux0_off: pinmux-off { 2143 groups = "dpaux-io"; 2144 function = "off"; 2145 }; 2146 2147 i2c-bus { 2148 #address-cells = <1>; 2149 #size-cells = <0>; 2150 }; 2151 }; 2152 2153 dpaux1: dpaux@155d0000 { 2154 compatible = "nvidia,tegra194-dpaux"; 2155 reg = <0x155d0000 0x10000>; 2156 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2157 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2158 <&bpmp TEGRA194_CLK_PLLDP>; 2159 clock-names = "dpaux", "parent"; 2160 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2161 reset-names = "dpaux"; 2162 status = "disabled"; 2163 2164 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2165 2166 state_dpaux1_aux: pinmux-aux { 2167 groups = "dpaux-io"; 2168 function = "aux"; 2169 }; 2170 2171 state_dpaux1_i2c: pinmux-i2c { 2172 groups = "dpaux-io"; 2173 function = "i2c"; 2174 }; 2175 2176 state_dpaux1_off: pinmux-off { 2177 groups = "dpaux-io"; 2178 function = "off"; 2179 }; 2180 2181 i2c-bus { 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 }; 2185 }; 2186 2187 dpaux2: dpaux@155e0000 { 2188 compatible = "nvidia,tegra194-dpaux"; 2189 reg = <0x155e0000 0x10000>; 2190 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2191 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2192 <&bpmp TEGRA194_CLK_PLLDP>; 2193 clock-names = "dpaux", "parent"; 2194 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2195 reset-names = "dpaux"; 2196 status = "disabled"; 2197 2198 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2199 2200 state_dpaux2_aux: pinmux-aux { 2201 groups = "dpaux-io"; 2202 function = "aux"; 2203 }; 2204 2205 state_dpaux2_i2c: pinmux-i2c { 2206 groups = "dpaux-io"; 2207 function = "i2c"; 2208 }; 2209 2210 state_dpaux2_off: pinmux-off { 2211 groups = "dpaux-io"; 2212 function = "off"; 2213 }; 2214 2215 i2c-bus { 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 }; 2219 }; 2220 2221 dpaux3: dpaux@155f0000 { 2222 compatible = "nvidia,tegra194-dpaux"; 2223 reg = <0x155f0000 0x10000>; 2224 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2225 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2226 <&bpmp TEGRA194_CLK_PLLDP>; 2227 clock-names = "dpaux", "parent"; 2228 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2229 reset-names = "dpaux"; 2230 status = "disabled"; 2231 2232 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2233 2234 state_dpaux3_aux: pinmux-aux { 2235 groups = "dpaux-io"; 2236 function = "aux"; 2237 }; 2238 2239 state_dpaux3_i2c: pinmux-i2c { 2240 groups = "dpaux-io"; 2241 function = "i2c"; 2242 }; 2243 2244 state_dpaux3_off: pinmux-off { 2245 groups = "dpaux-io"; 2246 function = "off"; 2247 }; 2248 2249 i2c-bus { 2250 #address-cells = <1>; 2251 #size-cells = <0>; 2252 }; 2253 }; 2254 2255 nvenc@15a80000 { 2256 compatible = "nvidia,tegra194-nvenc"; 2257 reg = <0x15a80000 0x00040000>; 2258 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2259 clock-names = "nvenc"; 2260 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2261 reset-names = "nvenc"; 2262 2263 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2264 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2265 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2266 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2267 interconnect-names = "dma-mem", "read-1", "write"; 2268 iommus = <&smmu TEGRA194_SID_NVENC1>; 2269 dma-coherent; 2270 2271 nvidia,host1x-class = <0x22>; 2272 }; 2273 2274 sor0: sor@15b00000 { 2275 compatible = "nvidia,tegra194-sor"; 2276 reg = <0x15b00000 0x40000>; 2277 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2278 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2279 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2280 <&bpmp TEGRA194_CLK_PLLD>, 2281 <&bpmp TEGRA194_CLK_PLLDP>, 2282 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2283 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2284 clock-names = "sor", "out", "parent", "dp", "safe", 2285 "pad"; 2286 resets = <&bpmp TEGRA194_RESET_SOR0>; 2287 reset-names = "sor"; 2288 pinctrl-0 = <&state_dpaux0_aux>; 2289 pinctrl-1 = <&state_dpaux0_i2c>; 2290 pinctrl-2 = <&state_dpaux0_off>; 2291 pinctrl-names = "aux", "i2c", "off"; 2292 status = "disabled"; 2293 2294 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2295 nvidia,interface = <0>; 2296 }; 2297 2298 sor1: sor@15b40000 { 2299 compatible = "nvidia,tegra194-sor"; 2300 reg = <0x15b40000 0x40000>; 2301 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2303 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2304 <&bpmp TEGRA194_CLK_PLLD2>, 2305 <&bpmp TEGRA194_CLK_PLLDP>, 2306 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2307 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2308 clock-names = "sor", "out", "parent", "dp", "safe", 2309 "pad"; 2310 resets = <&bpmp TEGRA194_RESET_SOR1>; 2311 reset-names = "sor"; 2312 pinctrl-0 = <&state_dpaux1_aux>; 2313 pinctrl-1 = <&state_dpaux1_i2c>; 2314 pinctrl-2 = <&state_dpaux1_off>; 2315 pinctrl-names = "aux", "i2c", "off"; 2316 status = "disabled"; 2317 2318 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2319 nvidia,interface = <1>; 2320 }; 2321 2322 sor2: sor@15b80000 { 2323 compatible = "nvidia,tegra194-sor"; 2324 reg = <0x15b80000 0x40000>; 2325 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2326 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2327 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2328 <&bpmp TEGRA194_CLK_PLLD3>, 2329 <&bpmp TEGRA194_CLK_PLLDP>, 2330 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2331 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2332 clock-names = "sor", "out", "parent", "dp", "safe", 2333 "pad"; 2334 resets = <&bpmp TEGRA194_RESET_SOR2>; 2335 reset-names = "sor"; 2336 pinctrl-0 = <&state_dpaux2_aux>; 2337 pinctrl-1 = <&state_dpaux2_i2c>; 2338 pinctrl-2 = <&state_dpaux2_off>; 2339 pinctrl-names = "aux", "i2c", "off"; 2340 status = "disabled"; 2341 2342 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2343 nvidia,interface = <2>; 2344 }; 2345 2346 sor3: sor@15bc0000 { 2347 compatible = "nvidia,tegra194-sor"; 2348 reg = <0x15bc0000 0x40000>; 2349 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2350 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2351 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2352 <&bpmp TEGRA194_CLK_PLLD4>, 2353 <&bpmp TEGRA194_CLK_PLLDP>, 2354 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2355 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2356 clock-names = "sor", "out", "parent", "dp", "safe", 2357 "pad"; 2358 resets = <&bpmp TEGRA194_RESET_SOR3>; 2359 reset-names = "sor"; 2360 pinctrl-0 = <&state_dpaux3_aux>; 2361 pinctrl-1 = <&state_dpaux3_i2c>; 2362 pinctrl-2 = <&state_dpaux3_off>; 2363 pinctrl-names = "aux", "i2c", "off"; 2364 status = "disabled"; 2365 2366 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2367 nvidia,interface = <3>; 2368 }; 2369 }; 2370 2371 gpu@17000000 { 2372 compatible = "nvidia,gv11b"; 2373 reg = <0x17000000 0x1000000>, 2374 <0x18000000 0x1000000>; 2375 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2377 interrupt-names = "stall", "nonstall"; 2378 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2379 <&bpmp TEGRA194_CLK_GPU_PWR>, 2380 <&bpmp TEGRA194_CLK_FUSE>; 2381 clock-names = "gpu", "pwr", "fuse"; 2382 resets = <&bpmp TEGRA194_RESET_GPU>; 2383 reset-names = "gpu"; 2384 dma-coherent; 2385 2386 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2387 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2388 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2389 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2390 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2391 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2392 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2393 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2394 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2395 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2396 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2397 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2398 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2399 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2400 "read-1", "read-1-hp", "write-1", 2401 "read-2", "read-2-hp", "write-2", 2402 "read-3", "read-3-hp", "write-3"; 2403 }; 2404 }; 2405 2406 pcie@14100000 { 2407 compatible = "nvidia,tegra194-pcie"; 2408 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2409 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2410 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2411 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2412 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2413 reg-names = "appl", "config", "atu_dma", "dbi"; 2414 2415 status = "disabled"; 2416 2417 #address-cells = <3>; 2418 #size-cells = <2>; 2419 device_type = "pci"; 2420 num-lanes = <1>; 2421 linux,pci-domain = <1>; 2422 2423 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2424 clock-names = "core"; 2425 2426 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2427 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2428 reset-names = "apb", "core"; 2429 2430 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2431 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2432 interrupt-names = "intr", "msi"; 2433 2434 #interrupt-cells = <1>; 2435 interrupt-map-mask = <0 0 0 0>; 2436 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2437 2438 nvidia,bpmp = <&bpmp 1>; 2439 2440 nvidia,aspm-cmrt-us = <60>; 2441 nvidia,aspm-pwr-on-t-us = <20>; 2442 nvidia,aspm-l0s-entrance-latency-us = <3>; 2443 2444 bus-range = <0x0 0xff>; 2445 2446 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2447 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2448 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2449 2450 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2451 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2452 interconnect-names = "dma-mem", "write"; 2453 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2454 iommu-map-mask = <0x0>; 2455 dma-coherent; 2456 }; 2457 2458 pcie@14120000 { 2459 compatible = "nvidia,tegra194-pcie"; 2460 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2461 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2462 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2463 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2464 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2465 reg-names = "appl", "config", "atu_dma", "dbi"; 2466 2467 status = "disabled"; 2468 2469 #address-cells = <3>; 2470 #size-cells = <2>; 2471 device_type = "pci"; 2472 num-lanes = <1>; 2473 linux,pci-domain = <2>; 2474 2475 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2476 clock-names = "core"; 2477 2478 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2479 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2480 reset-names = "apb", "core"; 2481 2482 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2483 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2484 interrupt-names = "intr", "msi"; 2485 2486 #interrupt-cells = <1>; 2487 interrupt-map-mask = <0 0 0 0>; 2488 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2489 2490 nvidia,bpmp = <&bpmp 2>; 2491 2492 nvidia,aspm-cmrt-us = <60>; 2493 nvidia,aspm-pwr-on-t-us = <20>; 2494 nvidia,aspm-l0s-entrance-latency-us = <3>; 2495 2496 bus-range = <0x0 0xff>; 2497 2498 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2499 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2500 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2501 2502 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2503 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2504 interconnect-names = "dma-mem", "write"; 2505 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2506 iommu-map-mask = <0x0>; 2507 dma-coherent; 2508 }; 2509 2510 pcie@14140000 { 2511 compatible = "nvidia,tegra194-pcie"; 2512 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2513 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2514 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2515 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2516 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2517 reg-names = "appl", "config", "atu_dma", "dbi"; 2518 2519 status = "disabled"; 2520 2521 #address-cells = <3>; 2522 #size-cells = <2>; 2523 device_type = "pci"; 2524 num-lanes = <1>; 2525 linux,pci-domain = <3>; 2526 2527 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2528 clock-names = "core"; 2529 2530 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2531 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2532 reset-names = "apb", "core"; 2533 2534 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2535 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2536 interrupt-names = "intr", "msi"; 2537 2538 #interrupt-cells = <1>; 2539 interrupt-map-mask = <0 0 0 0>; 2540 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2541 2542 nvidia,bpmp = <&bpmp 3>; 2543 2544 nvidia,aspm-cmrt-us = <60>; 2545 nvidia,aspm-pwr-on-t-us = <20>; 2546 nvidia,aspm-l0s-entrance-latency-us = <3>; 2547 2548 bus-range = <0x0 0xff>; 2549 2550 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2551 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2552 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2553 2554 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2555 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2556 interconnect-names = "dma-mem", "write"; 2557 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2558 iommu-map-mask = <0x0>; 2559 dma-coherent; 2560 }; 2561 2562 pcie@14160000 { 2563 compatible = "nvidia,tegra194-pcie"; 2564 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2565 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2566 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2567 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2568 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2569 reg-names = "appl", "config", "atu_dma", "dbi"; 2570 2571 status = "disabled"; 2572 2573 #address-cells = <3>; 2574 #size-cells = <2>; 2575 device_type = "pci"; 2576 num-lanes = <4>; 2577 linux,pci-domain = <4>; 2578 2579 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2580 clock-names = "core"; 2581 2582 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2583 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2584 reset-names = "apb", "core"; 2585 2586 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2587 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2588 interrupt-names = "intr", "msi"; 2589 2590 #interrupt-cells = <1>; 2591 interrupt-map-mask = <0 0 0 0>; 2592 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2593 2594 nvidia,bpmp = <&bpmp 4>; 2595 2596 nvidia,aspm-cmrt-us = <60>; 2597 nvidia,aspm-pwr-on-t-us = <20>; 2598 nvidia,aspm-l0s-entrance-latency-us = <3>; 2599 2600 bus-range = <0x0 0xff>; 2601 2602 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2603 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2604 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2605 2606 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2607 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2608 interconnect-names = "dma-mem", "write"; 2609 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2610 iommu-map-mask = <0x0>; 2611 dma-coherent; 2612 }; 2613 2614 pcie@14180000 { 2615 compatible = "nvidia,tegra194-pcie"; 2616 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2617 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2618 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2619 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2620 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2621 reg-names = "appl", "config", "atu_dma", "dbi"; 2622 2623 status = "disabled"; 2624 2625 #address-cells = <3>; 2626 #size-cells = <2>; 2627 device_type = "pci"; 2628 num-lanes = <8>; 2629 linux,pci-domain = <0>; 2630 2631 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2632 clock-names = "core"; 2633 2634 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2635 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2636 reset-names = "apb", "core"; 2637 2638 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2639 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2640 interrupt-names = "intr", "msi"; 2641 2642 #interrupt-cells = <1>; 2643 interrupt-map-mask = <0 0 0 0>; 2644 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2645 2646 nvidia,bpmp = <&bpmp 0>; 2647 2648 nvidia,aspm-cmrt-us = <60>; 2649 nvidia,aspm-pwr-on-t-us = <20>; 2650 nvidia,aspm-l0s-entrance-latency-us = <3>; 2651 2652 bus-range = <0x0 0xff>; 2653 2654 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2655 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2656 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2657 2658 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2659 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2660 interconnect-names = "dma-mem", "write"; 2661 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2662 iommu-map-mask = <0x0>; 2663 dma-coherent; 2664 }; 2665 2666 pcie@141a0000 { 2667 compatible = "nvidia,tegra194-pcie"; 2668 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2669 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2670 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2671 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2672 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2673 reg-names = "appl", "config", "atu_dma", "dbi"; 2674 2675 status = "disabled"; 2676 2677 #address-cells = <3>; 2678 #size-cells = <2>; 2679 device_type = "pci"; 2680 num-lanes = <8>; 2681 linux,pci-domain = <5>; 2682 2683 pinctrl-names = "default"; 2684 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2685 2686 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2687 clock-names = "core"; 2688 2689 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2690 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2691 reset-names = "apb", "core"; 2692 2693 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2694 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2695 interrupt-names = "intr", "msi"; 2696 2697 nvidia,bpmp = <&bpmp 5>; 2698 2699 #interrupt-cells = <1>; 2700 interrupt-map-mask = <0 0 0 0>; 2701 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2702 2703 nvidia,aspm-cmrt-us = <60>; 2704 nvidia,aspm-pwr-on-t-us = <20>; 2705 nvidia,aspm-l0s-entrance-latency-us = <3>; 2706 2707 bus-range = <0x0 0xff>; 2708 2709 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2710 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2711 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2712 2713 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2714 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2715 interconnect-names = "dma-mem", "write"; 2716 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2717 iommu-map-mask = <0x0>; 2718 dma-coherent; 2719 }; 2720 2721 pcie-ep@14160000 { 2722 compatible = "nvidia,tegra194-pcie-ep"; 2723 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2724 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2725 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2726 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2727 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2728 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2729 2730 status = "disabled"; 2731 2732 num-lanes = <4>; 2733 num-ib-windows = <2>; 2734 num-ob-windows = <8>; 2735 2736 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2737 clock-names = "core"; 2738 2739 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2740 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2741 reset-names = "apb", "core"; 2742 2743 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2744 interrupt-names = "intr"; 2745 2746 nvidia,bpmp = <&bpmp 4>; 2747 2748 nvidia,aspm-cmrt-us = <60>; 2749 nvidia,aspm-pwr-on-t-us = <20>; 2750 nvidia,aspm-l0s-entrance-latency-us = <3>; 2751 2752 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2753 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2754 interconnect-names = "dma-mem", "write"; 2755 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2756 iommu-map-mask = <0x0>; 2757 dma-coherent; 2758 }; 2759 2760 pcie-ep@14180000 { 2761 compatible = "nvidia,tegra194-pcie-ep"; 2762 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2763 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2764 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2765 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2766 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2767 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2768 2769 status = "disabled"; 2770 2771 num-lanes = <8>; 2772 num-ib-windows = <2>; 2773 num-ob-windows = <8>; 2774 2775 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2776 clock-names = "core"; 2777 2778 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2779 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2780 reset-names = "apb", "core"; 2781 2782 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2783 interrupt-names = "intr"; 2784 2785 nvidia,bpmp = <&bpmp 0>; 2786 2787 nvidia,aspm-cmrt-us = <60>; 2788 nvidia,aspm-pwr-on-t-us = <20>; 2789 nvidia,aspm-l0s-entrance-latency-us = <3>; 2790 2791 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2792 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2793 interconnect-names = "dma-mem", "write"; 2794 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2795 iommu-map-mask = <0x0>; 2796 dma-coherent; 2797 }; 2798 2799 pcie-ep@141a0000 { 2800 compatible = "nvidia,tegra194-pcie-ep"; 2801 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2802 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2803 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2804 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2805 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2806 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2807 2808 status = "disabled"; 2809 2810 num-lanes = <8>; 2811 num-ib-windows = <2>; 2812 num-ob-windows = <8>; 2813 2814 pinctrl-names = "default"; 2815 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2816 2817 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2818 clock-names = "core"; 2819 2820 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2821 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2822 reset-names = "apb", "core"; 2823 2824 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2825 interrupt-names = "intr"; 2826 2827 nvidia,bpmp = <&bpmp 5>; 2828 2829 nvidia,aspm-cmrt-us = <60>; 2830 nvidia,aspm-pwr-on-t-us = <20>; 2831 nvidia,aspm-l0s-entrance-latency-us = <3>; 2832 2833 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2834 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2835 interconnect-names = "dma-mem", "write"; 2836 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2837 iommu-map-mask = <0x0>; 2838 dma-coherent; 2839 }; 2840 2841 sram@40000000 { 2842 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2843 reg = <0x0 0x40000000 0x0 0x50000>; 2844 #address-cells = <1>; 2845 #size-cells = <1>; 2846 ranges = <0x0 0x0 0x40000000 0x50000>; 2847 no-memory-wc; 2848 2849 cpu_bpmp_tx: sram@4e000 { 2850 reg = <0x4e000 0x1000>; 2851 label = "cpu-bpmp-tx"; 2852 pool; 2853 }; 2854 2855 cpu_bpmp_rx: sram@4f000 { 2856 reg = <0x4f000 0x1000>; 2857 label = "cpu-bpmp-rx"; 2858 pool; 2859 }; 2860 }; 2861 2862 bpmp: bpmp { 2863 compatible = "nvidia,tegra186-bpmp"; 2864 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2865 TEGRA_HSP_DB_MASTER_BPMP>; 2866 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2867 #clock-cells = <1>; 2868 #reset-cells = <1>; 2869 #power-domain-cells = <1>; 2870 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2871 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2872 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2873 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2874 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2875 iommus = <&smmu TEGRA194_SID_BPMP>; 2876 2877 bpmp_i2c: i2c { 2878 compatible = "nvidia,tegra186-bpmp-i2c"; 2879 nvidia,bpmp-bus-id = <5>; 2880 #address-cells = <1>; 2881 #size-cells = <0>; 2882 }; 2883 2884 bpmp_thermal: thermal { 2885 compatible = "nvidia,tegra186-bpmp-thermal"; 2886 #thermal-sensor-cells = <1>; 2887 }; 2888 }; 2889 2890 cpus { 2891 compatible = "nvidia,tegra194-ccplex"; 2892 nvidia,bpmp = <&bpmp>; 2893 #address-cells = <1>; 2894 #size-cells = <0>; 2895 2896 cpu0_0: cpu@0 { 2897 compatible = "nvidia,tegra194-carmel"; 2898 device_type = "cpu"; 2899 reg = <0x000>; 2900 enable-method = "psci"; 2901 i-cache-size = <131072>; 2902 i-cache-line-size = <64>; 2903 i-cache-sets = <512>; 2904 d-cache-size = <65536>; 2905 d-cache-line-size = <64>; 2906 d-cache-sets = <256>; 2907 next-level-cache = <&l2c_0>; 2908 }; 2909 2910 cpu0_1: cpu@1 { 2911 compatible = "nvidia,tegra194-carmel"; 2912 device_type = "cpu"; 2913 reg = <0x001>; 2914 enable-method = "psci"; 2915 i-cache-size = <131072>; 2916 i-cache-line-size = <64>; 2917 i-cache-sets = <512>; 2918 d-cache-size = <65536>; 2919 d-cache-line-size = <64>; 2920 d-cache-sets = <256>; 2921 next-level-cache = <&l2c_0>; 2922 }; 2923 2924 cpu1_0: cpu@100 { 2925 compatible = "nvidia,tegra194-carmel"; 2926 device_type = "cpu"; 2927 reg = <0x100>; 2928 enable-method = "psci"; 2929 i-cache-size = <131072>; 2930 i-cache-line-size = <64>; 2931 i-cache-sets = <512>; 2932 d-cache-size = <65536>; 2933 d-cache-line-size = <64>; 2934 d-cache-sets = <256>; 2935 next-level-cache = <&l2c_1>; 2936 }; 2937 2938 cpu1_1: cpu@101 { 2939 compatible = "nvidia,tegra194-carmel"; 2940 device_type = "cpu"; 2941 reg = <0x101>; 2942 enable-method = "psci"; 2943 i-cache-size = <131072>; 2944 i-cache-line-size = <64>; 2945 i-cache-sets = <512>; 2946 d-cache-size = <65536>; 2947 d-cache-line-size = <64>; 2948 d-cache-sets = <256>; 2949 next-level-cache = <&l2c_1>; 2950 }; 2951 2952 cpu2_0: cpu@200 { 2953 compatible = "nvidia,tegra194-carmel"; 2954 device_type = "cpu"; 2955 reg = <0x200>; 2956 enable-method = "psci"; 2957 i-cache-size = <131072>; 2958 i-cache-line-size = <64>; 2959 i-cache-sets = <512>; 2960 d-cache-size = <65536>; 2961 d-cache-line-size = <64>; 2962 d-cache-sets = <256>; 2963 next-level-cache = <&l2c_2>; 2964 }; 2965 2966 cpu2_1: cpu@201 { 2967 compatible = "nvidia,tegra194-carmel"; 2968 device_type = "cpu"; 2969 reg = <0x201>; 2970 enable-method = "psci"; 2971 i-cache-size = <131072>; 2972 i-cache-line-size = <64>; 2973 i-cache-sets = <512>; 2974 d-cache-size = <65536>; 2975 d-cache-line-size = <64>; 2976 d-cache-sets = <256>; 2977 next-level-cache = <&l2c_2>; 2978 }; 2979 2980 cpu3_0: cpu@300 { 2981 compatible = "nvidia,tegra194-carmel"; 2982 device_type = "cpu"; 2983 reg = <0x300>; 2984 enable-method = "psci"; 2985 i-cache-size = <131072>; 2986 i-cache-line-size = <64>; 2987 i-cache-sets = <512>; 2988 d-cache-size = <65536>; 2989 d-cache-line-size = <64>; 2990 d-cache-sets = <256>; 2991 next-level-cache = <&l2c_3>; 2992 }; 2993 2994 cpu3_1: cpu@301 { 2995 compatible = "nvidia,tegra194-carmel"; 2996 device_type = "cpu"; 2997 reg = <0x301>; 2998 enable-method = "psci"; 2999 i-cache-size = <131072>; 3000 i-cache-line-size = <64>; 3001 i-cache-sets = <512>; 3002 d-cache-size = <65536>; 3003 d-cache-line-size = <64>; 3004 d-cache-sets = <256>; 3005 next-level-cache = <&l2c_3>; 3006 }; 3007 3008 cpu-map { 3009 cluster0 { 3010 core0 { 3011 cpu = <&cpu0_0>; 3012 }; 3013 3014 core1 { 3015 cpu = <&cpu0_1>; 3016 }; 3017 }; 3018 3019 cluster1 { 3020 core0 { 3021 cpu = <&cpu1_0>; 3022 }; 3023 3024 core1 { 3025 cpu = <&cpu1_1>; 3026 }; 3027 }; 3028 3029 cluster2 { 3030 core0 { 3031 cpu = <&cpu2_0>; 3032 }; 3033 3034 core1 { 3035 cpu = <&cpu2_1>; 3036 }; 3037 }; 3038 3039 cluster3 { 3040 core0 { 3041 cpu = <&cpu3_0>; 3042 }; 3043 3044 core1 { 3045 cpu = <&cpu3_1>; 3046 }; 3047 }; 3048 }; 3049 3050 l2c_0: l2-cache0 { 3051 compatible = "cache"; 3052 cache-unified; 3053 cache-size = <2097152>; 3054 cache-line-size = <64>; 3055 cache-sets = <2048>; 3056 cache-level = <2>; 3057 next-level-cache = <&l3c>; 3058 }; 3059 3060 l2c_1: l2-cache1 { 3061 compatible = "cache"; 3062 cache-unified; 3063 cache-size = <2097152>; 3064 cache-line-size = <64>; 3065 cache-sets = <2048>; 3066 cache-level = <2>; 3067 next-level-cache = <&l3c>; 3068 }; 3069 3070 l2c_2: l2-cache2 { 3071 compatible = "cache"; 3072 cache-unified; 3073 cache-size = <2097152>; 3074 cache-line-size = <64>; 3075 cache-sets = <2048>; 3076 cache-level = <2>; 3077 next-level-cache = <&l3c>; 3078 }; 3079 3080 l2c_3: l2-cache3 { 3081 compatible = "cache"; 3082 cache-unified; 3083 cache-size = <2097152>; 3084 cache-line-size = <64>; 3085 cache-sets = <2048>; 3086 cache-level = <2>; 3087 next-level-cache = <&l3c>; 3088 }; 3089 3090 l3c: l3-cache { 3091 compatible = "cache"; 3092 cache-unified; 3093 cache-size = <4194304>; 3094 cache-line-size = <64>; 3095 cache-level = <3>; 3096 cache-sets = <4096>; 3097 }; 3098 }; 3099 3100 pmu { 3101 compatible = "nvidia,carmel-pmu"; 3102 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3110 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3111 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3112 }; 3113 3114 psci { 3115 compatible = "arm,psci-1.0"; 3116 status = "okay"; 3117 method = "smc"; 3118 }; 3119 3120 sound { 3121 status = "disabled"; 3122 3123 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3124 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3125 clock-names = "pll_a", "plla_out0"; 3126 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3127 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3128 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3129 assigned-clock-parents = <0>, 3130 <&bpmp TEGRA194_CLK_PLLA>, 3131 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3132 /* 3133 * PLLA supports dynamic ramp. Below initial rate is chosen 3134 * for this to work and oscillate between base rates required 3135 * for 8x and 11.025x sample rate streams. 3136 */ 3137 assigned-clock-rates = <258000000>; 3138 }; 3139 3140 tcu: serial { 3141 compatible = "nvidia,tegra194-tcu"; 3142 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3143 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3144 mbox-names = "rx", "tx"; 3145 }; 3146 3147 thermal-zones { 3148 cpu-thermal { 3149 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3150 status = "disabled"; 3151 }; 3152 3153 gpu-thermal { 3154 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3155 status = "disabled"; 3156 }; 3157 3158 aux-thermal { 3159 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3160 status = "disabled"; 3161 }; 3162 3163 pllx-thermal { 3164 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3165 status = "disabled"; 3166 }; 3167 3168 ao-thermal { 3169 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3170 status = "disabled"; 3171 }; 3172 3173 tj-thermal { 3174 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3175 status = "disabled"; 3176 }; 3177 }; 3178 3179 timer { 3180 compatible = "arm,armv8-timer"; 3181 interrupts = <GIC_PPI 13 3182 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3183 <GIC_PPI 14 3184 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3185 <GIC_PPI 11 3186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3187 <GIC_PPI 10 3188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3189 interrupt-parent = <&gic>; 3190 always-on; 3191 }; 3192}; 3193