1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7 8/ { 9 compatible = "nvidia,tegra194"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 /* control backbone */ 15 cbb { 16 compatible = "simple-bus"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 ranges = <0x0 0x0 0x0 0x40000000>; 20 21 uarta: serial@3100000 { 22 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 23 reg = <0x03100000 0x40>; 24 reg-shift = <2>; 25 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 26 clocks = <&bpmp TEGRA194_CLK_UARTA>; 27 clock-names = "serial"; 28 resets = <&bpmp TEGRA194_RESET_UARTA>; 29 reset-names = "serial"; 30 status = "disabled"; 31 }; 32 33 uartb: serial@3110000 { 34 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 35 reg = <0x03110000 0x40>; 36 reg-shift = <2>; 37 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&bpmp TEGRA194_CLK_UARTB>; 39 clock-names = "serial"; 40 resets = <&bpmp TEGRA194_RESET_UARTB>; 41 reset-names = "serial"; 42 status = "disabled"; 43 }; 44 45 uartd: serial@3130000 { 46 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 47 reg = <0x03130000 0x40>; 48 reg-shift = <2>; 49 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 50 clocks = <&bpmp TEGRA194_CLK_UARTD>; 51 clock-names = "serial"; 52 resets = <&bpmp TEGRA194_RESET_UARTD>; 53 reset-names = "serial"; 54 status = "disabled"; 55 }; 56 57 uarte: serial@3140000 { 58 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 59 reg = <0x03140000 0x40>; 60 reg-shift = <2>; 61 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 62 clocks = <&bpmp TEGRA194_CLK_UARTE>; 63 clock-names = "serial"; 64 resets = <&bpmp TEGRA194_RESET_UARTE>; 65 reset-names = "serial"; 66 status = "disabled"; 67 }; 68 69 uartf: serial@3150000 { 70 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 71 reg = <0x03150000 0x40>; 72 reg-shift = <2>; 73 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 74 clocks = <&bpmp TEGRA194_CLK_UARTF>; 75 clock-names = "serial"; 76 resets = <&bpmp TEGRA194_RESET_UARTF>; 77 reset-names = "serial"; 78 status = "disabled"; 79 }; 80 81 gen1_i2c: i2c@3160000 { 82 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 83 reg = <0x03160000 0x10000>; 84 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 clocks = <&bpmp TEGRA194_CLK_I2C1>; 88 clock-names = "div-clk"; 89 resets = <&bpmp TEGRA194_RESET_I2C1>; 90 reset-names = "i2c"; 91 status = "disabled"; 92 }; 93 94 uarth: serial@3170000 { 95 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 96 reg = <0x03170000 0x40>; 97 reg-shift = <2>; 98 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&bpmp TEGRA194_CLK_UARTH>; 100 clock-names = "serial"; 101 resets = <&bpmp TEGRA194_RESET_UARTH>; 102 reset-names = "serial"; 103 status = "disabled"; 104 }; 105 106 cam_i2c: i2c@3180000 { 107 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 108 reg = <0x03180000 0x10000>; 109 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clocks = <&bpmp TEGRA194_CLK_I2C3>; 113 clock-names = "div-clk"; 114 resets = <&bpmp TEGRA194_RESET_I2C3>; 115 reset-names = "i2c"; 116 status = "disabled"; 117 }; 118 119 /* shares pads with dpaux1 */ 120 dp_aux_ch1_i2c: i2c@3190000 { 121 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 122 reg = <0x03190000 0x10000>; 123 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 clocks = <&bpmp TEGRA194_CLK_I2C4>; 127 clock-names = "div-clk"; 128 resets = <&bpmp TEGRA194_RESET_I2C4>; 129 reset-names = "i2c"; 130 status = "disabled"; 131 }; 132 133 /* shares pads with dpaux0 */ 134 dp_aux_ch0_i2c: i2c@31b0000 { 135 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 136 reg = <0x031b0000 0x10000>; 137 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 clocks = <&bpmp TEGRA194_CLK_I2C6>; 141 clock-names = "div-clk"; 142 resets = <&bpmp TEGRA194_RESET_I2C6>; 143 reset-names = "i2c"; 144 status = "disabled"; 145 }; 146 147 gen7_i2c: i2c@31c0000 { 148 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 149 reg = <0x031c0000 0x10000>; 150 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C7>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C7>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 gen9_i2c: i2c@31e0000 { 161 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 162 reg = <0x031e0000 0x10000>; 163 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clocks = <&bpmp TEGRA194_CLK_I2C9>; 167 clock-names = "div-clk"; 168 resets = <&bpmp TEGRA194_RESET_I2C9>; 169 reset-names = "i2c"; 170 status = "disabled"; 171 }; 172 173 sdmmc1: sdhci@3400000 { 174 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 175 reg = <0x03400000 0x10000>; 176 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 178 clock-names = "sdhci"; 179 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 180 reset-names = "sdhci"; 181 status = "disabled"; 182 }; 183 184 sdmmc3: sdhci@3440000 { 185 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 186 reg = <0x03440000 0x10000>; 187 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 189 clock-names = "sdhci"; 190 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 191 reset-names = "sdhci"; 192 status = "disabled"; 193 }; 194 195 sdmmc4: sdhci@3460000 { 196 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 197 reg = <0x03460000 0x10000>; 198 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 200 clock-names = "sdhci"; 201 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 202 reset-names = "sdhci"; 203 status = "disabled"; 204 }; 205 206 gic: interrupt-controller@3881000 { 207 compatible = "arm,gic-400"; 208 #interrupt-cells = <3>; 209 interrupt-controller; 210 reg = <0x03881000 0x1000>, 211 <0x03882000 0x2000>, 212 <0x03884000 0x2000>, 213 <0x03886000 0x2000>; 214 interrupts = <GIC_PPI 9 215 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 216 interrupt-parent = <&gic>; 217 }; 218 219 hsp_top0: hsp@3c00000 { 220 compatible = "nvidia,tegra186-hsp"; 221 reg = <0x03c00000 0xa0000>; 222 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 223 interrupt-names = "doorbell"; 224 #mbox-cells = <2>; 225 }; 226 227 gen2_i2c: i2c@c240000 { 228 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 229 reg = <0x0c240000 0x10000>; 230 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 clocks = <&bpmp TEGRA194_CLK_I2C2>; 234 clock-names = "div-clk"; 235 resets = <&bpmp TEGRA194_RESET_I2C2>; 236 reset-names = "i2c"; 237 status = "disabled"; 238 }; 239 240 gen8_i2c: i2c@c250000 { 241 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 242 reg = <0x0c250000 0x10000>; 243 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 clocks = <&bpmp TEGRA194_CLK_I2C8>; 247 clock-names = "div-clk"; 248 resets = <&bpmp TEGRA194_RESET_I2C8>; 249 reset-names = "i2c"; 250 status = "disabled"; 251 }; 252 253 uartc: serial@c280000 { 254 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 255 reg = <0x0c280000 0x40>; 256 reg-shift = <2>; 257 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&bpmp TEGRA194_CLK_UARTC>; 259 clock-names = "serial"; 260 resets = <&bpmp TEGRA194_RESET_UARTC>; 261 reset-names = "serial"; 262 status = "disabled"; 263 }; 264 265 uartg: serial@c290000 { 266 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 267 reg = <0x0c290000 0x40>; 268 reg-shift = <2>; 269 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&bpmp TEGRA194_CLK_UARTG>; 271 clock-names = "serial"; 272 resets = <&bpmp TEGRA194_RESET_UARTG>; 273 reset-names = "serial"; 274 status = "disabled"; 275 }; 276 277 pmc@c360000 { 278 compatible = "nvidia,tegra194-pmc"; 279 reg = <0x0c360000 0x10000>, 280 <0x0c370000 0x10000>, 281 <0x0c380000 0x10000>, 282 <0x0c390000 0x10000>, 283 <0x0c3a0000 0x10000>; 284 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 285 }; 286 }; 287 288 sysram@40000000 { 289 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 290 reg = <0x0 0x40000000 0x0 0x50000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges = <0x0 0x0 0x40000000 0x50000>; 294 295 cpu_bpmp_tx: shmem@4e000 { 296 compatible = "nvidia,tegra194-bpmp-shmem"; 297 reg = <0x4e000 0x1000>; 298 label = "cpu-bpmp-tx"; 299 pool; 300 }; 301 302 cpu_bpmp_rx: shmem@4f000 { 303 compatible = "nvidia,tegra194-bpmp-shmem"; 304 reg = <0x4f000 0x1000>; 305 label = "cpu-bpmp-rx"; 306 pool; 307 }; 308 }; 309 310 bpmp: bpmp { 311 compatible = "nvidia,tegra186-bpmp"; 312 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 313 TEGRA_HSP_DB_MASTER_BPMP>; 314 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 315 #clock-cells = <1>; 316 #reset-cells = <1>; 317 #power-domain-cells = <1>; 318 319 bpmp_i2c: i2c { 320 compatible = "nvidia,tegra186-bpmp-i2c"; 321 nvidia,bpmp-bus-id = <5>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 }; 325 326 bpmp_thermal: thermal { 327 compatible = "nvidia,tegra186-bpmp-thermal"; 328 #thermal-sensor-cells = <1>; 329 }; 330 }; 331 332 timer { 333 compatible = "arm,armv8-timer"; 334 interrupts = <GIC_PPI 13 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 336 <GIC_PPI 14 337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 338 <GIC_PPI 11 339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 340 <GIC_PPI 10 341 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 342 interrupt-parent = <&gic>; 343 }; 344}; 345