1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra.h>
8#include <dt-bindings/power/tegra194-powergate.h>
9#include <dt-bindings/reset/tegra194-reset.h>
10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11#include <dt-bindings/memory/tegra194-mc.h>
12
13/ {
14	compatible = "nvidia,tegra194";
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	/* control backbone */
20	bus@0 {
21		compatible = "simple-bus";
22		#address-cells = <1>;
23		#size-cells = <1>;
24		ranges = <0x0 0x0 0x0 0x40000000>;
25
26		misc@100000 {
27			compatible = "nvidia,tegra194-misc";
28			reg = <0x00100000 0xf000>,
29			      <0x0010f000 0x1000>;
30		};
31
32		gpio: gpio@2200000 {
33			compatible = "nvidia,tegra194-gpio";
34			reg-names = "security", "gpio";
35			reg = <0x2200000 0x10000>,
36			      <0x2210000 0x10000>;
37			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
38				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
39				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
40				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
41				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
42				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
43				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
44				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
45				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
46				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
47				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
48				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
49				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
50				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
51				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
52				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
53				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
54				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
55				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
56				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
57				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
58				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
59				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
60				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
61				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
62				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
63				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
64				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
65				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
66				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
67				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
68				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
69				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
70				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
71				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
72				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
73				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
74				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
75				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
76				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
77				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
78				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
79				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
80				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
81				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
82				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
83				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
84				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
85			#interrupt-cells = <2>;
86			interrupt-controller;
87			#gpio-cells = <2>;
88			gpio-controller;
89		};
90
91		ethernet@2490000 {
92			compatible = "nvidia,tegra194-eqos",
93				     "nvidia,tegra186-eqos",
94				     "snps,dwc-qos-ethernet-4.10";
95			reg = <0x02490000 0x10000>;
96			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
97			clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
98				 <&bpmp TEGRA194_CLK_EQOS_AXI>,
99				 <&bpmp TEGRA194_CLK_EQOS_RX>,
100				 <&bpmp TEGRA194_CLK_EQOS_TX>,
101				 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
102			clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
103			resets = <&bpmp TEGRA194_RESET_EQOS>;
104			reset-names = "eqos";
105			interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
106					<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
107			interconnect-names = "dma-mem", "write";
108			iommus = <&smmu TEGRA194_SID_EQOS>;
109			status = "disabled";
110
111			snps,write-requests = <1>;
112			snps,read-requests = <3>;
113			snps,burst-map = <0x7>;
114			snps,txpbl = <16>;
115			snps,rxpbl = <8>;
116		};
117
118		aconnect@2900000 {
119			compatible = "nvidia,tegra194-aconnect",
120				     "nvidia,tegra210-aconnect";
121			clocks = <&bpmp TEGRA194_CLK_APE>,
122				 <&bpmp TEGRA194_CLK_APB2APE>;
123			clock-names = "ape", "apb2ape";
124			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
125			#address-cells = <1>;
126			#size-cells = <1>;
127			ranges = <0x02900000 0x02900000 0x200000>;
128			status = "disabled";
129
130			adma: dma-controller@2930000 {
131				compatible = "nvidia,tegra194-adma",
132					     "nvidia,tegra186-adma";
133				reg = <0x02930000 0x20000>;
134				interrupt-parent = <&agic>;
135				interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136					      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
137					      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
138					      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
139					      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
140					      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
141					      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
142					      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
143					      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
144					      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
145					      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
146					      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
147					      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
148					      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
149					      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
150					      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
151					      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
152					      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
153					      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
154					      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
155					      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
156					      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
157					      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
158					      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
159					      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
160					      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
161					      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
162					      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
163					      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
164					      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
165					      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
166					      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
167				#dma-cells = <1>;
168				clocks = <&bpmp TEGRA194_CLK_AHUB>;
169				clock-names = "d_audio";
170				status = "disabled";
171			};
172
173			agic: interrupt-controller@2a40000 {
174				compatible = "nvidia,tegra194-agic",
175					     "nvidia,tegra210-agic";
176				#interrupt-cells = <3>;
177				interrupt-controller;
178				reg = <0x02a41000 0x1000>,
179				      <0x02a42000 0x2000>;
180				interrupts = <GIC_SPI 145
181					      (GIC_CPU_MASK_SIMPLE(4) |
182					       IRQ_TYPE_LEVEL_HIGH)>;
183				clocks = <&bpmp TEGRA194_CLK_APE>;
184				clock-names = "clk";
185				status = "disabled";
186			};
187
188			tegra_ahub: ahub@2900800 {
189				compatible = "nvidia,tegra194-ahub",
190					     "nvidia,tegra186-ahub";
191				reg = <0x02900800 0x800>;
192				clocks = <&bpmp TEGRA194_CLK_AHUB>;
193				clock-names = "ahub";
194				assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
195				assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
196				#address-cells = <1>;
197				#size-cells = <1>;
198				ranges = <0x02900800 0x02900800 0x11800>;
199				status = "disabled";
200
201				tegra_admaif: admaif@290f000 {
202					compatible = "nvidia,tegra194-admaif",
203						     "nvidia,tegra186-admaif";
204					reg = <0x0290f000 0x1000>;
205					dmas = <&adma 1>, <&adma 1>,
206					       <&adma 2>, <&adma 2>,
207					       <&adma 3>, <&adma 3>,
208					       <&adma 4>, <&adma 4>,
209					       <&adma 5>, <&adma 5>,
210					       <&adma 6>, <&adma 6>,
211					       <&adma 7>, <&adma 7>,
212					       <&adma 8>, <&adma 8>,
213					       <&adma 9>, <&adma 9>,
214					       <&adma 10>, <&adma 10>,
215					       <&adma 11>, <&adma 11>,
216					       <&adma 12>, <&adma 12>,
217					       <&adma 13>, <&adma 13>,
218					       <&adma 14>, <&adma 14>,
219					       <&adma 15>, <&adma 15>,
220					       <&adma 16>, <&adma 16>,
221					       <&adma 17>, <&adma 17>,
222					       <&adma 18>, <&adma 18>,
223					       <&adma 19>, <&adma 19>,
224					       <&adma 20>, <&adma 20>;
225					dma-names = "rx1", "tx1",
226						    "rx2", "tx2",
227						    "rx3", "tx3",
228						    "rx4", "tx4",
229						    "rx5", "tx5",
230						    "rx6", "tx6",
231						    "rx7", "tx7",
232						    "rx8", "tx8",
233						    "rx9", "tx9",
234						    "rx10", "tx10",
235						    "rx11", "tx11",
236						    "rx12", "tx12",
237						    "rx13", "tx13",
238						    "rx14", "tx14",
239						    "rx15", "tx15",
240						    "rx16", "tx16",
241						    "rx17", "tx17",
242						    "rx18", "tx18",
243						    "rx19", "tx19",
244						    "rx20", "tx20";
245					status = "disabled";
246				};
247
248				tegra_i2s1: i2s@2901000 {
249					compatible = "nvidia,tegra194-i2s",
250						     "nvidia,tegra210-i2s";
251					reg = <0x2901000 0x100>;
252					clocks = <&bpmp TEGRA194_CLK_I2S1>,
253						 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
254					clock-names = "i2s", "sync_input";
255					assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
256					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
257					assigned-clock-rates = <1536000>;
258					sound-name-prefix = "I2S1";
259					status = "disabled";
260				};
261
262				tegra_i2s2: i2s@2901100 {
263					compatible = "nvidia,tegra194-i2s",
264						     "nvidia,tegra210-i2s";
265					reg = <0x2901100 0x100>;
266					clocks = <&bpmp TEGRA194_CLK_I2S2>,
267						 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
268					clock-names = "i2s", "sync_input";
269					assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
270					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
271					assigned-clock-rates = <1536000>;
272					sound-name-prefix = "I2S2";
273					status = "disabled";
274				};
275
276				tegra_i2s3: i2s@2901200 {
277					compatible = "nvidia,tegra194-i2s",
278						     "nvidia,tegra210-i2s";
279					reg = <0x2901200 0x100>;
280					clocks = <&bpmp TEGRA194_CLK_I2S3>,
281						 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
282					clock-names = "i2s", "sync_input";
283					assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
284					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
285					assigned-clock-rates = <1536000>;
286					sound-name-prefix = "I2S3";
287					status = "disabled";
288				};
289
290				tegra_i2s4: i2s@2901300 {
291					compatible = "nvidia,tegra194-i2s",
292						     "nvidia,tegra210-i2s";
293					reg = <0x2901300 0x100>;
294					clocks = <&bpmp TEGRA194_CLK_I2S4>,
295						 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
296					clock-names = "i2s", "sync_input";
297					assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
298					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
299					assigned-clock-rates = <1536000>;
300					sound-name-prefix = "I2S4";
301					status = "disabled";
302				};
303
304				tegra_i2s5: i2s@2901400 {
305					compatible = "nvidia,tegra194-i2s",
306						     "nvidia,tegra210-i2s";
307					reg = <0x2901400 0x100>;
308					clocks = <&bpmp TEGRA194_CLK_I2S5>,
309						 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
310					clock-names = "i2s", "sync_input";
311					assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
312					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
313					assigned-clock-rates = <1536000>;
314					sound-name-prefix = "I2S5";
315					status = "disabled";
316				};
317
318				tegra_i2s6: i2s@2901500 {
319					compatible = "nvidia,tegra194-i2s",
320						     "nvidia,tegra210-i2s";
321					reg = <0x2901500 0x100>;
322					clocks = <&bpmp TEGRA194_CLK_I2S6>,
323						 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
324					clock-names = "i2s", "sync_input";
325					assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
326					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
327					assigned-clock-rates = <1536000>;
328					sound-name-prefix = "I2S6";
329					status = "disabled";
330				};
331
332				tegra_dmic1: dmic@2904000 {
333					compatible = "nvidia,tegra194-dmic",
334						     "nvidia,tegra210-dmic";
335					reg = <0x2904000 0x100>;
336					clocks = <&bpmp TEGRA194_CLK_DMIC1>;
337					clock-names = "dmic";
338					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
339					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
340					assigned-clock-rates = <3072000>;
341					sound-name-prefix = "DMIC1";
342					status = "disabled";
343				};
344
345				tegra_dmic2: dmic@2904100 {
346					compatible = "nvidia,tegra194-dmic",
347						     "nvidia,tegra210-dmic";
348					reg = <0x2904100 0x100>;
349					clocks = <&bpmp TEGRA194_CLK_DMIC2>;
350					clock-names = "dmic";
351					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
352					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
353					assigned-clock-rates = <3072000>;
354					sound-name-prefix = "DMIC2";
355					status = "disabled";
356				};
357
358				tegra_dmic3: dmic@2904200 {
359					compatible = "nvidia,tegra194-dmic",
360						     "nvidia,tegra210-dmic";
361					reg = <0x2904200 0x100>;
362					clocks = <&bpmp TEGRA194_CLK_DMIC3>;
363					clock-names = "dmic";
364					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
365					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
366					assigned-clock-rates = <3072000>;
367					sound-name-prefix = "DMIC3";
368					status = "disabled";
369				};
370
371				tegra_dmic4: dmic@2904300 {
372					compatible = "nvidia,tegra194-dmic",
373						     "nvidia,tegra210-dmic";
374					reg = <0x2904300 0x100>;
375					clocks = <&bpmp TEGRA194_CLK_DMIC4>;
376					clock-names = "dmic";
377					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
378					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
379					assigned-clock-rates = <3072000>;
380					sound-name-prefix = "DMIC4";
381					status = "disabled";
382				};
383
384				tegra_dspk1: dspk@2905000 {
385					compatible = "nvidia,tegra194-dspk",
386						     "nvidia,tegra186-dspk";
387					reg = <0x2905000 0x100>;
388					clocks = <&bpmp TEGRA194_CLK_DSPK1>;
389					clock-names = "dspk";
390					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
391					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
392					assigned-clock-rates = <12288000>;
393					sound-name-prefix = "DSPK1";
394					status = "disabled";
395				};
396
397				tegra_dspk2: dspk@2905100 {
398					compatible = "nvidia,tegra194-dspk",
399						     "nvidia,tegra186-dspk";
400					reg = <0x2905100 0x100>;
401					clocks = <&bpmp TEGRA194_CLK_DSPK2>;
402					clock-names = "dspk";
403					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
404					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
405					assigned-clock-rates = <12288000>;
406					sound-name-prefix = "DSPK2";
407					status = "disabled";
408				};
409
410				tegra_sfc1: sfc@2902000 {
411					compatible = "nvidia,tegra194-sfc",
412						     "nvidia,tegra210-sfc";
413					reg = <0x2902000 0x200>;
414					sound-name-prefix = "SFC1";
415					status = "disabled";
416				};
417
418				tegra_sfc2: sfc@2902200 {
419					compatible = "nvidia,tegra194-sfc",
420						     "nvidia,tegra210-sfc";
421					reg = <0x2902200 0x200>;
422					sound-name-prefix = "SFC2";
423					status = "disabled";
424				};
425
426				tegra_sfc3: sfc@2902400 {
427					compatible = "nvidia,tegra194-sfc",
428						     "nvidia,tegra210-sfc";
429					reg = <0x2902400 0x200>;
430					sound-name-prefix = "SFC3";
431					status = "disabled";
432				};
433
434				tegra_sfc4: sfc@2902600 {
435					compatible = "nvidia,tegra194-sfc",
436						     "nvidia,tegra210-sfc";
437					reg = <0x2902600 0x200>;
438					sound-name-prefix = "SFC4";
439					status = "disabled";
440				};
441
442				tegra_mvc1: mvc@290a000 {
443					compatible = "nvidia,tegra194-mvc",
444						     "nvidia,tegra210-mvc";
445					reg = <0x290a000 0x200>;
446					sound-name-prefix = "MVC1";
447					status = "disabled";
448				};
449
450				tegra_mvc2: mvc@290a200 {
451					compatible = "nvidia,tegra194-mvc",
452						     "nvidia,tegra210-mvc";
453					reg = <0x290a200 0x200>;
454					sound-name-prefix = "MVC2";
455					status = "disabled";
456				};
457
458				tegra_amx1: amx@2903000 {
459					compatible = "nvidia,tegra194-amx";
460					reg = <0x2903000 0x100>;
461					sound-name-prefix = "AMX1";
462					status = "disabled";
463				};
464
465				tegra_amx2: amx@2903100 {
466					compatible = "nvidia,tegra194-amx";
467					reg = <0x2903100 0x100>;
468					sound-name-prefix = "AMX2";
469					status = "disabled";
470				};
471
472				tegra_amx3: amx@2903200 {
473					compatible = "nvidia,tegra194-amx";
474					reg = <0x2903200 0x100>;
475					sound-name-prefix = "AMX3";
476					status = "disabled";
477				};
478
479				tegra_amx4: amx@2903300 {
480					compatible = "nvidia,tegra194-amx";
481					reg = <0x2903300 0x100>;
482					sound-name-prefix = "AMX4";
483					status = "disabled";
484				};
485
486				tegra_adx1: adx@2903800 {
487					compatible = "nvidia,tegra194-adx",
488						     "nvidia,tegra210-adx";
489					reg = <0x2903800 0x100>;
490					sound-name-prefix = "ADX1";
491					status = "disabled";
492				};
493
494				tegra_adx2: adx@2903900 {
495					compatible = "nvidia,tegra194-adx",
496						     "nvidia,tegra210-adx";
497					reg = <0x2903900 0x100>;
498					sound-name-prefix = "ADX2";
499					status = "disabled";
500				};
501
502				tegra_adx3: adx@2903a00 {
503					compatible = "nvidia,tegra194-adx",
504						     "nvidia,tegra210-adx";
505					reg = <0x2903a00 0x100>;
506					sound-name-prefix = "ADX3";
507					status = "disabled";
508				};
509
510				tegra_adx4: adx@2903b00 {
511					compatible = "nvidia,tegra194-adx",
512						     "nvidia,tegra210-adx";
513					reg = <0x2903b00 0x100>;
514					sound-name-prefix = "ADX4";
515					status = "disabled";
516				};
517
518				tegra_amixer: amixer@290bb00 {
519					compatible = "nvidia,tegra194-amixer",
520						     "nvidia,tegra210-amixer";
521					reg = <0x290bb00 0x800>;
522					sound-name-prefix = "MIXER1";
523					status = "disabled";
524				};
525			};
526		};
527
528		pinmux: pinmux@2430000 {
529			compatible = "nvidia,tegra194-pinmux";
530			reg = <0x2430000 0x17000>,
531			      <0xc300000 0x4000>;
532
533			status = "okay";
534
535			pex_rst_c5_out_state: pex_rst_c5_out {
536				pex_rst {
537					nvidia,pins = "pex_l5_rst_n_pgg1";
538					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
539					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
540					nvidia,io-hv = <TEGRA_PIN_ENABLE>;
541					nvidia,tristate = <TEGRA_PIN_DISABLE>;
542					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
543				};
544			};
545
546			clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
547				clkreq {
548					nvidia,pins = "pex_l5_clkreq_n_pgg0";
549					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
550					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
551					nvidia,io-hv = <TEGRA_PIN_ENABLE>;
552					nvidia,tristate = <TEGRA_PIN_DISABLE>;
553					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
554				};
555			};
556		};
557
558		mc: memory-controller@2c00000 {
559			compatible = "nvidia,tegra194-mc";
560			reg = <0x02c00000 0x100000>,
561			      <0x02b80000 0x040000>,
562			      <0x01700000 0x100000>;
563			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
564			#interconnect-cells = <1>;
565			status = "disabled";
566
567			#address-cells = <2>;
568			#size-cells = <2>;
569
570			ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
571				 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
572				 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
573
574			/*
575			 * Bit 39 of addresses passing through the memory
576			 * controller selects the XBAR format used when memory
577			 * is accessed. This is used to transparently access
578			 * memory in the XBAR format used by the discrete GPU
579			 * (bit 39 set) or Tegra (bit 39 clear).
580			 *
581			 * As a consequence, the operating system must ensure
582			 * that bit 39 is never used implicitly, for example
583			 * via an I/O virtual address mapping of an IOMMU. If
584			 * devices require access to the XBAR switch, their
585			 * drivers must set this bit explicitly.
586			 *
587			 * Limit the DMA range for memory clients to [38:0].
588			 */
589			dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
590
591			emc: external-memory-controller@2c60000 {
592				compatible = "nvidia,tegra194-emc";
593				reg = <0x0 0x02c60000 0x0 0x90000>,
594				      <0x0 0x01780000 0x0 0x80000>;
595				interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
596				clocks = <&bpmp TEGRA194_CLK_EMC>;
597				clock-names = "emc";
598
599				#interconnect-cells = <0>;
600
601				nvidia,bpmp = <&bpmp>;
602			};
603		};
604
605		uarta: serial@3100000 {
606			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
607			reg = <0x03100000 0x40>;
608			reg-shift = <2>;
609			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
610			clocks = <&bpmp TEGRA194_CLK_UARTA>;
611			clock-names = "serial";
612			resets = <&bpmp TEGRA194_RESET_UARTA>;
613			reset-names = "serial";
614			status = "disabled";
615		};
616
617		uartb: serial@3110000 {
618			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
619			reg = <0x03110000 0x40>;
620			reg-shift = <2>;
621			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
622			clocks = <&bpmp TEGRA194_CLK_UARTB>;
623			clock-names = "serial";
624			resets = <&bpmp TEGRA194_RESET_UARTB>;
625			reset-names = "serial";
626			status = "disabled";
627		};
628
629		uartd: serial@3130000 {
630			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
631			reg = <0x03130000 0x40>;
632			reg-shift = <2>;
633			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
634			clocks = <&bpmp TEGRA194_CLK_UARTD>;
635			clock-names = "serial";
636			resets = <&bpmp TEGRA194_RESET_UARTD>;
637			reset-names = "serial";
638			status = "disabled";
639		};
640
641		uarte: serial@3140000 {
642			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
643			reg = <0x03140000 0x40>;
644			reg-shift = <2>;
645			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
646			clocks = <&bpmp TEGRA194_CLK_UARTE>;
647			clock-names = "serial";
648			resets = <&bpmp TEGRA194_RESET_UARTE>;
649			reset-names = "serial";
650			status = "disabled";
651		};
652
653		uartf: serial@3150000 {
654			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
655			reg = <0x03150000 0x40>;
656			reg-shift = <2>;
657			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
658			clocks = <&bpmp TEGRA194_CLK_UARTF>;
659			clock-names = "serial";
660			resets = <&bpmp TEGRA194_RESET_UARTF>;
661			reset-names = "serial";
662			status = "disabled";
663		};
664
665		gen1_i2c: i2c@3160000 {
666			compatible = "nvidia,tegra194-i2c";
667			reg = <0x03160000 0x10000>;
668			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
669			#address-cells = <1>;
670			#size-cells = <0>;
671			clocks = <&bpmp TEGRA194_CLK_I2C1>;
672			clock-names = "div-clk";
673			resets = <&bpmp TEGRA194_RESET_I2C1>;
674			reset-names = "i2c";
675			status = "disabled";
676		};
677
678		uarth: serial@3170000 {
679			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
680			reg = <0x03170000 0x40>;
681			reg-shift = <2>;
682			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
683			clocks = <&bpmp TEGRA194_CLK_UARTH>;
684			clock-names = "serial";
685			resets = <&bpmp TEGRA194_RESET_UARTH>;
686			reset-names = "serial";
687			status = "disabled";
688		};
689
690		cam_i2c: i2c@3180000 {
691			compatible = "nvidia,tegra194-i2c";
692			reg = <0x03180000 0x10000>;
693			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
694			#address-cells = <1>;
695			#size-cells = <0>;
696			clocks = <&bpmp TEGRA194_CLK_I2C3>;
697			clock-names = "div-clk";
698			resets = <&bpmp TEGRA194_RESET_I2C3>;
699			reset-names = "i2c";
700			status = "disabled";
701		};
702
703		/* shares pads with dpaux1 */
704		dp_aux_ch1_i2c: i2c@3190000 {
705			compatible = "nvidia,tegra194-i2c";
706			reg = <0x03190000 0x10000>;
707			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
708			#address-cells = <1>;
709			#size-cells = <0>;
710			clocks = <&bpmp TEGRA194_CLK_I2C4>;
711			clock-names = "div-clk";
712			resets = <&bpmp TEGRA194_RESET_I2C4>;
713			reset-names = "i2c";
714			pinctrl-0 = <&state_dpaux1_i2c>;
715			pinctrl-1 = <&state_dpaux1_off>;
716			pinctrl-names = "default", "idle";
717			status = "disabled";
718		};
719
720		/* shares pads with dpaux0 */
721		dp_aux_ch0_i2c: i2c@31b0000 {
722			compatible = "nvidia,tegra194-i2c";
723			reg = <0x031b0000 0x10000>;
724			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
725			#address-cells = <1>;
726			#size-cells = <0>;
727			clocks = <&bpmp TEGRA194_CLK_I2C6>;
728			clock-names = "div-clk";
729			resets = <&bpmp TEGRA194_RESET_I2C6>;
730			reset-names = "i2c";
731			pinctrl-0 = <&state_dpaux0_i2c>;
732			pinctrl-1 = <&state_dpaux0_off>;
733			pinctrl-names = "default", "idle";
734			status = "disabled";
735		};
736
737		/* shares pads with dpaux2 */
738		dp_aux_ch2_i2c: i2c@31c0000 {
739			compatible = "nvidia,tegra194-i2c";
740			reg = <0x031c0000 0x10000>;
741			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
742			#address-cells = <1>;
743			#size-cells = <0>;
744			clocks = <&bpmp TEGRA194_CLK_I2C7>;
745			clock-names = "div-clk";
746			resets = <&bpmp TEGRA194_RESET_I2C7>;
747			reset-names = "i2c";
748			pinctrl-0 = <&state_dpaux2_i2c>;
749			pinctrl-1 = <&state_dpaux2_off>;
750			pinctrl-names = "default", "idle";
751			status = "disabled";
752		};
753
754		/* shares pads with dpaux3 */
755		dp_aux_ch3_i2c: i2c@31e0000 {
756			compatible = "nvidia,tegra194-i2c";
757			reg = <0x031e0000 0x10000>;
758			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
759			#address-cells = <1>;
760			#size-cells = <0>;
761			clocks = <&bpmp TEGRA194_CLK_I2C9>;
762			clock-names = "div-clk";
763			resets = <&bpmp TEGRA194_RESET_I2C9>;
764			reset-names = "i2c";
765			pinctrl-0 = <&state_dpaux3_i2c>;
766			pinctrl-1 = <&state_dpaux3_off>;
767			pinctrl-names = "default", "idle";
768			status = "disabled";
769		};
770
771		spi@3270000 {
772			compatible = "nvidia,tegra194-qspi";
773			reg = <0x3270000 0x1000>;
774			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
775			#address-cells = <1>;
776			#size-cells = <0>;
777			clocks = <&bpmp TEGRA194_CLK_QSPI0>,
778				 <&bpmp TEGRA194_CLK_QSPI0_PM>;
779			clock-names = "qspi", "qspi_out";
780			resets = <&bpmp TEGRA194_RESET_QSPI0>;
781			reset-names = "qspi";
782			status = "disabled";
783		};
784
785		spi@3300000 {
786			compatible = "nvidia,tegra194-qspi";
787			reg = <0x3300000 0x1000>;
788			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
789			#address-cells = <1>;
790			#size-cells = <0>;
791			clocks = <&bpmp TEGRA194_CLK_QSPI1>,
792				 <&bpmp TEGRA194_CLK_QSPI1_PM>;
793			clock-names = "qspi", "qspi_out";
794			resets = <&bpmp TEGRA194_RESET_QSPI1>;
795			reset-names = "qspi";
796			status = "disabled";
797		};
798
799		pwm1: pwm@3280000 {
800			compatible = "nvidia,tegra194-pwm",
801				     "nvidia,tegra186-pwm";
802			reg = <0x3280000 0x10000>;
803			clocks = <&bpmp TEGRA194_CLK_PWM1>;
804			clock-names = "pwm";
805			resets = <&bpmp TEGRA194_RESET_PWM1>;
806			reset-names = "pwm";
807			status = "disabled";
808			#pwm-cells = <2>;
809		};
810
811		pwm2: pwm@3290000 {
812			compatible = "nvidia,tegra194-pwm",
813				     "nvidia,tegra186-pwm";
814			reg = <0x3290000 0x10000>;
815			clocks = <&bpmp TEGRA194_CLK_PWM2>;
816			clock-names = "pwm";
817			resets = <&bpmp TEGRA194_RESET_PWM2>;
818			reset-names = "pwm";
819			status = "disabled";
820			#pwm-cells = <2>;
821		};
822
823		pwm3: pwm@32a0000 {
824			compatible = "nvidia,tegra194-pwm",
825				     "nvidia,tegra186-pwm";
826			reg = <0x32a0000 0x10000>;
827			clocks = <&bpmp TEGRA194_CLK_PWM3>;
828			clock-names = "pwm";
829			resets = <&bpmp TEGRA194_RESET_PWM3>;
830			reset-names = "pwm";
831			status = "disabled";
832			#pwm-cells = <2>;
833		};
834
835		pwm5: pwm@32c0000 {
836			compatible = "nvidia,tegra194-pwm",
837				     "nvidia,tegra186-pwm";
838			reg = <0x32c0000 0x10000>;
839			clocks = <&bpmp TEGRA194_CLK_PWM5>;
840			clock-names = "pwm";
841			resets = <&bpmp TEGRA194_RESET_PWM5>;
842			reset-names = "pwm";
843			status = "disabled";
844			#pwm-cells = <2>;
845		};
846
847		pwm6: pwm@32d0000 {
848			compatible = "nvidia,tegra194-pwm",
849				     "nvidia,tegra186-pwm";
850			reg = <0x32d0000 0x10000>;
851			clocks = <&bpmp TEGRA194_CLK_PWM6>;
852			clock-names = "pwm";
853			resets = <&bpmp TEGRA194_RESET_PWM6>;
854			reset-names = "pwm";
855			status = "disabled";
856			#pwm-cells = <2>;
857		};
858
859		pwm7: pwm@32e0000 {
860			compatible = "nvidia,tegra194-pwm",
861				     "nvidia,tegra186-pwm";
862			reg = <0x32e0000 0x10000>;
863			clocks = <&bpmp TEGRA194_CLK_PWM7>;
864			clock-names = "pwm";
865			resets = <&bpmp TEGRA194_RESET_PWM7>;
866			reset-names = "pwm";
867			status = "disabled";
868			#pwm-cells = <2>;
869		};
870
871		pwm8: pwm@32f0000 {
872			compatible = "nvidia,tegra194-pwm",
873				     "nvidia,tegra186-pwm";
874			reg = <0x32f0000 0x10000>;
875			clocks = <&bpmp TEGRA194_CLK_PWM8>;
876			clock-names = "pwm";
877			resets = <&bpmp TEGRA194_RESET_PWM8>;
878			reset-names = "pwm";
879			status = "disabled";
880			#pwm-cells = <2>;
881		};
882
883		sdmmc1: mmc@3400000 {
884			compatible = "nvidia,tegra194-sdhci";
885			reg = <0x03400000 0x10000>;
886			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
887			clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
888				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
889			clock-names = "sdhci", "tmclk";
890			resets = <&bpmp TEGRA194_RESET_SDMMC1>;
891			reset-names = "sdhci";
892			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
893					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
894			interconnect-names = "dma-mem", "write";
895			iommus = <&smmu TEGRA194_SID_SDMMC1>;
896			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
897			pinctrl-0 = <&sdmmc1_3v3>;
898			pinctrl-1 = <&sdmmc1_1v8>;
899			nvidia,pad-autocal-pull-up-offset-3v3-timeout =
900									<0x07>;
901			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
902									<0x07>;
903			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
904			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
905									<0x07>;
906			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
907			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
908			nvidia,default-tap = <0x9>;
909			nvidia,default-trim = <0x5>;
910			sd-uhs-sdr25;
911			sd-uhs-sdr50;
912			sd-uhs-ddr50;
913			sd-uhs-sdr104;
914			status = "disabled";
915		};
916
917		sdmmc3: mmc@3440000 {
918			compatible = "nvidia,tegra194-sdhci";
919			reg = <0x03440000 0x10000>;
920			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
921			clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
922				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
923			clock-names = "sdhci", "tmclk";
924			resets = <&bpmp TEGRA194_RESET_SDMMC3>;
925			reset-names = "sdhci";
926			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
927					<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
928			interconnect-names = "dma-mem", "write";
929			iommus = <&smmu TEGRA194_SID_SDMMC3>;
930			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
931			pinctrl-0 = <&sdmmc3_3v3>;
932			pinctrl-1 = <&sdmmc3_1v8>;
933			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
934			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
935			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
936			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
937									<0x07>;
938			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
939			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
940									<0x07>;
941			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
942			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
943			nvidia,default-tap = <0x9>;
944			nvidia,default-trim = <0x5>;
945			sd-uhs-sdr25;
946			sd-uhs-sdr50;
947			sd-uhs-ddr50;
948			sd-uhs-sdr104;
949			status = "disabled";
950		};
951
952		sdmmc4: mmc@3460000 {
953			compatible = "nvidia,tegra194-sdhci";
954			reg = <0x03460000 0x10000>;
955			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
956			clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
957				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
958			clock-names = "sdhci", "tmclk";
959			assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
960					  <&bpmp TEGRA194_CLK_PLLC4>;
961			assigned-clock-parents =
962					  <&bpmp TEGRA194_CLK_PLLC4>;
963			resets = <&bpmp TEGRA194_RESET_SDMMC4>;
964			reset-names = "sdhci";
965			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
966					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
967			interconnect-names = "dma-mem", "write";
968			iommus = <&smmu TEGRA194_SID_SDMMC4>;
969			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
970			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
971			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
972			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
973									<0x0a>;
974			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
975			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
976									<0x0a>;
977			nvidia,default-tap = <0x8>;
978			nvidia,default-trim = <0x14>;
979			nvidia,dqs-trim = <40>;
980			cap-mmc-highspeed;
981			mmc-ddr-1_8v;
982			mmc-hs200-1_8v;
983			mmc-hs400-1_8v;
984			mmc-hs400-enhanced-strobe;
985			supports-cqe;
986			status = "disabled";
987		};
988
989		hda@3510000 {
990			compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
991			reg = <0x3510000 0x10000>;
992			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
993			clocks = <&bpmp TEGRA194_CLK_HDA>,
994				 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
995				 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
996			clock-names = "hda", "hda2hdmi", "hda2codec_2x";
997			resets = <&bpmp TEGRA194_RESET_HDA>,
998				 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
999			reset-names = "hda", "hda2hdmi";
1000			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1001			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1002					<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1003			interconnect-names = "dma-mem", "write";
1004			iommus = <&smmu TEGRA194_SID_HDA>;
1005			status = "disabled";
1006		};
1007
1008		xusb_padctl: padctl@3520000 {
1009			compatible = "nvidia,tegra194-xusb-padctl";
1010			reg = <0x03520000 0x1000>,
1011			      <0x03540000 0x1000>;
1012			reg-names = "padctl", "ao";
1013			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1014
1015			resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1016			reset-names = "padctl";
1017
1018			status = "disabled";
1019
1020			pads {
1021				usb2 {
1022					clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1023					clock-names = "trk";
1024
1025					lanes {
1026						usb2-0 {
1027							nvidia,function = "xusb";
1028							status = "disabled";
1029							#phy-cells = <0>;
1030						};
1031
1032						usb2-1 {
1033							nvidia,function = "xusb";
1034							status = "disabled";
1035							#phy-cells = <0>;
1036						};
1037
1038						usb2-2 {
1039							nvidia,function = "xusb";
1040							status = "disabled";
1041							#phy-cells = <0>;
1042						};
1043
1044						usb2-3 {
1045							nvidia,function = "xusb";
1046							status = "disabled";
1047							#phy-cells = <0>;
1048						};
1049					};
1050				};
1051
1052				usb3 {
1053					lanes {
1054						usb3-0 {
1055							nvidia,function = "xusb";
1056							status = "disabled";
1057							#phy-cells = <0>;
1058						};
1059
1060						usb3-1 {
1061							nvidia,function = "xusb";
1062							status = "disabled";
1063							#phy-cells = <0>;
1064						};
1065
1066						usb3-2 {
1067							nvidia,function = "xusb";
1068							status = "disabled";
1069							#phy-cells = <0>;
1070						};
1071
1072						usb3-3 {
1073							nvidia,function = "xusb";
1074							status = "disabled";
1075							#phy-cells = <0>;
1076						};
1077					};
1078				};
1079			};
1080
1081			ports {
1082				usb2-0 {
1083					status = "disabled";
1084				};
1085
1086				usb2-1 {
1087					status = "disabled";
1088				};
1089
1090				usb2-2 {
1091					status = "disabled";
1092				};
1093
1094				usb2-3 {
1095					status = "disabled";
1096				};
1097
1098				usb3-0 {
1099					status = "disabled";
1100				};
1101
1102				usb3-1 {
1103					status = "disabled";
1104				};
1105
1106				usb3-2 {
1107					status = "disabled";
1108				};
1109
1110				usb3-3 {
1111					status = "disabled";
1112				};
1113			};
1114		};
1115
1116		usb@3550000 {
1117			compatible = "nvidia,tegra194-xudc";
1118			reg = <0x03550000 0x8000>,
1119			      <0x03558000 0x1000>;
1120			reg-names = "base", "fpci";
1121			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1122			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1123				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1124				 <&bpmp TEGRA194_CLK_XUSB_SS>,
1125				 <&bpmp TEGRA194_CLK_XUSB_FS>;
1126			clock-names = "dev", "ss", "ss_src", "fs_src";
1127			interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
1128					<&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
1129			interconnect-names = "dma-mem", "write";
1130			iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1131			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1132					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1133			power-domain-names = "dev", "ss";
1134			nvidia,xusb-padctl = <&xusb_padctl>;
1135			status = "disabled";
1136		};
1137
1138		usb@3610000 {
1139			compatible = "nvidia,tegra194-xusb";
1140			reg = <0x03610000 0x40000>,
1141			      <0x03600000 0x10000>;
1142			reg-names = "hcd", "fpci";
1143
1144			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1145				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1146
1147			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1148				 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1149				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1150				 <&bpmp TEGRA194_CLK_XUSB_SS>,
1151				 <&bpmp TEGRA194_CLK_CLK_M>,
1152				 <&bpmp TEGRA194_CLK_XUSB_FS>,
1153				 <&bpmp TEGRA194_CLK_UTMIPLL>,
1154				 <&bpmp TEGRA194_CLK_CLK_M>,
1155				 <&bpmp TEGRA194_CLK_PLLE>;
1156			clock-names = "xusb_host", "xusb_falcon_src",
1157				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1158				      "xusb_fs_src", "pll_u_480m", "clk_m",
1159				      "pll_e";
1160			interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1161					<&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1162			interconnect-names = "dma-mem", "write";
1163			iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1164
1165			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1166					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1167			power-domain-names = "xusb_host", "xusb_ss";
1168
1169			nvidia,xusb-padctl = <&xusb_padctl>;
1170			status = "disabled";
1171		};
1172
1173		fuse@3820000 {
1174			compatible = "nvidia,tegra194-efuse";
1175			reg = <0x03820000 0x10000>;
1176			clocks = <&bpmp TEGRA194_CLK_FUSE>;
1177			clock-names = "fuse";
1178		};
1179
1180		gic: interrupt-controller@3881000 {
1181			compatible = "arm,gic-400";
1182			#interrupt-cells = <3>;
1183			interrupt-controller;
1184			reg = <0x03881000 0x1000>,
1185			      <0x03882000 0x2000>,
1186			      <0x03884000 0x2000>,
1187			      <0x03886000 0x2000>;
1188			interrupts = <GIC_PPI 9
1189				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1190			interrupt-parent = <&gic>;
1191		};
1192
1193		cec@3960000 {
1194			compatible = "nvidia,tegra194-cec";
1195			reg = <0x03960000 0x10000>;
1196			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1197			clocks = <&bpmp TEGRA194_CLK_CEC>;
1198			clock-names = "cec";
1199			status = "disabled";
1200		};
1201
1202		hsp_top0: hsp@3c00000 {
1203			compatible = "nvidia,tegra194-hsp";
1204			reg = <0x03c00000 0xa0000>;
1205			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1206			             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1207			             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1208			             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1209			             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1210			             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1211			             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1212			             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1213			             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1214			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1215			                  "shared3", "shared4", "shared5", "shared6",
1216			                  "shared7";
1217			#mbox-cells = <2>;
1218		};
1219
1220		p2u_hsio_0: phy@3e10000 {
1221			compatible = "nvidia,tegra194-p2u";
1222			reg = <0x03e10000 0x10000>;
1223			reg-names = "ctl";
1224
1225			#phy-cells = <0>;
1226		};
1227
1228		p2u_hsio_1: phy@3e20000 {
1229			compatible = "nvidia,tegra194-p2u";
1230			reg = <0x03e20000 0x10000>;
1231			reg-names = "ctl";
1232
1233			#phy-cells = <0>;
1234		};
1235
1236		p2u_hsio_2: phy@3e30000 {
1237			compatible = "nvidia,tegra194-p2u";
1238			reg = <0x03e30000 0x10000>;
1239			reg-names = "ctl";
1240
1241			#phy-cells = <0>;
1242		};
1243
1244		p2u_hsio_3: phy@3e40000 {
1245			compatible = "nvidia,tegra194-p2u";
1246			reg = <0x03e40000 0x10000>;
1247			reg-names = "ctl";
1248
1249			#phy-cells = <0>;
1250		};
1251
1252		p2u_hsio_4: phy@3e50000 {
1253			compatible = "nvidia,tegra194-p2u";
1254			reg = <0x03e50000 0x10000>;
1255			reg-names = "ctl";
1256
1257			#phy-cells = <0>;
1258		};
1259
1260		p2u_hsio_5: phy@3e60000 {
1261			compatible = "nvidia,tegra194-p2u";
1262			reg = <0x03e60000 0x10000>;
1263			reg-names = "ctl";
1264
1265			#phy-cells = <0>;
1266		};
1267
1268		p2u_hsio_6: phy@3e70000 {
1269			compatible = "nvidia,tegra194-p2u";
1270			reg = <0x03e70000 0x10000>;
1271			reg-names = "ctl";
1272
1273			#phy-cells = <0>;
1274		};
1275
1276		p2u_hsio_7: phy@3e80000 {
1277			compatible = "nvidia,tegra194-p2u";
1278			reg = <0x03e80000 0x10000>;
1279			reg-names = "ctl";
1280
1281			#phy-cells = <0>;
1282		};
1283
1284		p2u_hsio_8: phy@3e90000 {
1285			compatible = "nvidia,tegra194-p2u";
1286			reg = <0x03e90000 0x10000>;
1287			reg-names = "ctl";
1288
1289			#phy-cells = <0>;
1290		};
1291
1292		p2u_hsio_9: phy@3ea0000 {
1293			compatible = "nvidia,tegra194-p2u";
1294			reg = <0x03ea0000 0x10000>;
1295			reg-names = "ctl";
1296
1297			#phy-cells = <0>;
1298		};
1299
1300		p2u_nvhs_0: phy@3eb0000 {
1301			compatible = "nvidia,tegra194-p2u";
1302			reg = <0x03eb0000 0x10000>;
1303			reg-names = "ctl";
1304
1305			#phy-cells = <0>;
1306		};
1307
1308		p2u_nvhs_1: phy@3ec0000 {
1309			compatible = "nvidia,tegra194-p2u";
1310			reg = <0x03ec0000 0x10000>;
1311			reg-names = "ctl";
1312
1313			#phy-cells = <0>;
1314		};
1315
1316		p2u_nvhs_2: phy@3ed0000 {
1317			compatible = "nvidia,tegra194-p2u";
1318			reg = <0x03ed0000 0x10000>;
1319			reg-names = "ctl";
1320
1321			#phy-cells = <0>;
1322		};
1323
1324		p2u_nvhs_3: phy@3ee0000 {
1325			compatible = "nvidia,tegra194-p2u";
1326			reg = <0x03ee0000 0x10000>;
1327			reg-names = "ctl";
1328
1329			#phy-cells = <0>;
1330		};
1331
1332		p2u_nvhs_4: phy@3ef0000 {
1333			compatible = "nvidia,tegra194-p2u";
1334			reg = <0x03ef0000 0x10000>;
1335			reg-names = "ctl";
1336
1337			#phy-cells = <0>;
1338		};
1339
1340		p2u_nvhs_5: phy@3f00000 {
1341			compatible = "nvidia,tegra194-p2u";
1342			reg = <0x03f00000 0x10000>;
1343			reg-names = "ctl";
1344
1345			#phy-cells = <0>;
1346		};
1347
1348		p2u_nvhs_6: phy@3f10000 {
1349			compatible = "nvidia,tegra194-p2u";
1350			reg = <0x03f10000 0x10000>;
1351			reg-names = "ctl";
1352
1353			#phy-cells = <0>;
1354		};
1355
1356		p2u_nvhs_7: phy@3f20000 {
1357			compatible = "nvidia,tegra194-p2u";
1358			reg = <0x03f20000 0x10000>;
1359			reg-names = "ctl";
1360
1361			#phy-cells = <0>;
1362		};
1363
1364		p2u_hsio_10: phy@3f30000 {
1365			compatible = "nvidia,tegra194-p2u";
1366			reg = <0x03f30000 0x10000>;
1367			reg-names = "ctl";
1368
1369			#phy-cells = <0>;
1370		};
1371
1372		p2u_hsio_11: phy@3f40000 {
1373			compatible = "nvidia,tegra194-p2u";
1374			reg = <0x03f40000 0x10000>;
1375			reg-names = "ctl";
1376
1377			#phy-cells = <0>;
1378		};
1379
1380		hsp_aon: hsp@c150000 {
1381			compatible = "nvidia,tegra194-hsp";
1382			reg = <0x0c150000 0x90000>;
1383			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1384			             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1385			             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1386			             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1387			/*
1388			 * Shared interrupt 0 is routed only to AON/SPE, so
1389			 * we only have 4 shared interrupts for the CCPLEX.
1390			 */
1391			interrupt-names = "shared1", "shared2", "shared3", "shared4";
1392			#mbox-cells = <2>;
1393		};
1394
1395		gen2_i2c: i2c@c240000 {
1396			compatible = "nvidia,tegra194-i2c";
1397			reg = <0x0c240000 0x10000>;
1398			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1399			#address-cells = <1>;
1400			#size-cells = <0>;
1401			clocks = <&bpmp TEGRA194_CLK_I2C2>;
1402			clock-names = "div-clk";
1403			resets = <&bpmp TEGRA194_RESET_I2C2>;
1404			reset-names = "i2c";
1405			status = "disabled";
1406		};
1407
1408		gen8_i2c: i2c@c250000 {
1409			compatible = "nvidia,tegra194-i2c";
1410			reg = <0x0c250000 0x10000>;
1411			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1412			#address-cells = <1>;
1413			#size-cells = <0>;
1414			clocks = <&bpmp TEGRA194_CLK_I2C8>;
1415			clock-names = "div-clk";
1416			resets = <&bpmp TEGRA194_RESET_I2C8>;
1417			reset-names = "i2c";
1418			status = "disabled";
1419		};
1420
1421		uartc: serial@c280000 {
1422			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1423			reg = <0x0c280000 0x40>;
1424			reg-shift = <2>;
1425			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1426			clocks = <&bpmp TEGRA194_CLK_UARTC>;
1427			clock-names = "serial";
1428			resets = <&bpmp TEGRA194_RESET_UARTC>;
1429			reset-names = "serial";
1430			status = "disabled";
1431		};
1432
1433		uartg: serial@c290000 {
1434			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1435			reg = <0x0c290000 0x40>;
1436			reg-shift = <2>;
1437			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1438			clocks = <&bpmp TEGRA194_CLK_UARTG>;
1439			clock-names = "serial";
1440			resets = <&bpmp TEGRA194_RESET_UARTG>;
1441			reset-names = "serial";
1442			status = "disabled";
1443		};
1444
1445		rtc: rtc@c2a0000 {
1446			compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1447			reg = <0x0c2a0000 0x10000>;
1448			interrupt-parent = <&pmc>;
1449			interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1450			clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1451			clock-names = "rtc";
1452			status = "disabled";
1453		};
1454
1455		gpio_aon: gpio@c2f0000 {
1456			compatible = "nvidia,tegra194-gpio-aon";
1457			reg-names = "security", "gpio";
1458			reg = <0xc2f0000 0x1000>,
1459			      <0xc2f1000 0x1000>;
1460			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1461				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1462				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1463				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1464			gpio-controller;
1465			#gpio-cells = <2>;
1466			interrupt-controller;
1467			#interrupt-cells = <2>;
1468		};
1469
1470		pwm4: pwm@c340000 {
1471			compatible = "nvidia,tegra194-pwm",
1472				     "nvidia,tegra186-pwm";
1473			reg = <0xc340000 0x10000>;
1474			clocks = <&bpmp TEGRA194_CLK_PWM4>;
1475			clock-names = "pwm";
1476			resets = <&bpmp TEGRA194_RESET_PWM4>;
1477			reset-names = "pwm";
1478			status = "disabled";
1479			#pwm-cells = <2>;
1480		};
1481
1482		pmc: pmc@c360000 {
1483			compatible = "nvidia,tegra194-pmc";
1484			reg = <0x0c360000 0x10000>,
1485			      <0x0c370000 0x10000>,
1486			      <0x0c380000 0x10000>,
1487			      <0x0c390000 0x10000>,
1488			      <0x0c3a0000 0x10000>;
1489			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1490
1491			#interrupt-cells = <2>;
1492			interrupt-controller;
1493			sdmmc1_3v3: sdmmc1-3v3 {
1494				pins = "sdmmc1-hv";
1495				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1496			};
1497
1498			sdmmc1_1v8: sdmmc1-1v8 {
1499				pins = "sdmmc1-hv";
1500				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1501			};
1502			sdmmc3_3v3: sdmmc3-3v3 {
1503				pins = "sdmmc3-hv";
1504				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1505			};
1506
1507			sdmmc3_1v8: sdmmc3-1v8 {
1508				pins = "sdmmc3-hv";
1509				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1510			};
1511
1512		};
1513
1514		iommu@10000000 {
1515			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1516			reg = <0x10000000 0x800000>;
1517			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1518				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1519				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1520				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1521				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1522				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1523				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1524				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1525				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1526				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1527				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1528				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1529				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1530				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1531				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1532				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1533				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1534				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1535				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1536				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1537				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1538				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1539				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1540				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1541				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1542				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1543				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1544				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1545				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1546				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1547				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1548				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1549				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1550				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1551				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1552				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1553				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1554				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1555				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1556				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1557				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1558				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1559				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1560				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1561				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1562				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1563				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1564				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1565				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1566				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1567				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1568				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1569				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1570				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1571				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1572				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1573				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1574				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1575				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1576				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1577				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1578				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1579				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1580				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1581				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1582			stream-match-mask = <0x7f80>;
1583			#global-interrupts = <1>;
1584			#iommu-cells = <1>;
1585
1586			nvidia,memory-controller = <&mc>;
1587			status = "okay";
1588		};
1589
1590		smmu: iommu@12000000 {
1591			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1592			reg = <0x12000000 0x800000>,
1593			      <0x11000000 0x800000>;
1594			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1595				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1596				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1597				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1598				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1599				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1600				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1601				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1602				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1603				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1604				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1605				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1606				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1607				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1608				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1609				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1610				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1611				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1612				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1613				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1614				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1615				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1616				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1617				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1618				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1619				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1620				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1621				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1622				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1623				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1624				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1625				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1626				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1627				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1628				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1629				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1630				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1631				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1632				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1633				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1634				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1635				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1636				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1637				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1638				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1639				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1640				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1641				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1642				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1643				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1644				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1645				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1646				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1647				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1648				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1649				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1650				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1651				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1652				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1653				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1654				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1655				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1656				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1657				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1658				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1659				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1660			stream-match-mask = <0x7f80>;
1661			#global-interrupts = <2>;
1662			#iommu-cells = <1>;
1663
1664			nvidia,memory-controller = <&mc>;
1665			status = "okay";
1666		};
1667
1668		host1x@13e00000 {
1669			compatible = "nvidia,tegra194-host1x";
1670			reg = <0x13e00000 0x10000>,
1671			      <0x13e10000 0x10000>;
1672			reg-names = "hypervisor", "vm";
1673			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1674				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1675			interrupt-names = "syncpt", "host1x";
1676			clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1677			clock-names = "host1x";
1678			resets = <&bpmp TEGRA194_RESET_HOST1X>;
1679			reset-names = "host1x";
1680
1681			#address-cells = <1>;
1682			#size-cells = <1>;
1683
1684			ranges = <0x15000000 0x15000000 0x01000000>;
1685			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1686			interconnect-names = "dma-mem";
1687			iommus = <&smmu TEGRA194_SID_HOST1X>;
1688
1689			nvdec@15140000 {
1690				compatible = "nvidia,tegra194-nvdec";
1691				reg = <0x15140000 0x00040000>;
1692				clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1693				clock-names = "nvdec";
1694				resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1695				reset-names = "nvdec";
1696
1697				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1698				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
1699						<&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
1700						<&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
1701				interconnect-names = "dma-mem", "read-1", "write";
1702				iommus = <&smmu TEGRA194_SID_NVDEC1>;
1703				dma-coherent;
1704
1705				nvidia,host1x-class = <0xf5>;
1706			};
1707
1708			display-hub@15200000 {
1709				compatible = "nvidia,tegra194-display";
1710				reg = <0x15200000 0x00040000>;
1711				resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1712					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1713					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1714					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1715					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1716					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1717					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1718				reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1719					      "wgrp3", "wgrp4", "wgrp5";
1720				clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1721					 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1722				clock-names = "disp", "hub";
1723				status = "disabled";
1724
1725				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1726
1727				#address-cells = <1>;
1728				#size-cells = <1>;
1729
1730				ranges = <0x15200000 0x15200000 0x40000>;
1731
1732				display@15200000 {
1733					compatible = "nvidia,tegra194-dc";
1734					reg = <0x15200000 0x10000>;
1735					interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1736					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1737					clock-names = "dc";
1738					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1739					reset-names = "dc";
1740
1741					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1742					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1743							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1744					interconnect-names = "dma-mem", "read-1";
1745
1746					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1747					nvidia,head = <0>;
1748				};
1749
1750				display@15210000 {
1751					compatible = "nvidia,tegra194-dc";
1752					reg = <0x15210000 0x10000>;
1753					interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1754					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1755					clock-names = "dc";
1756					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1757					reset-names = "dc";
1758
1759					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1760					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1761							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1762					interconnect-names = "dma-mem", "read-1";
1763
1764					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1765					nvidia,head = <1>;
1766				};
1767
1768				display@15220000 {
1769					compatible = "nvidia,tegra194-dc";
1770					reg = <0x15220000 0x10000>;
1771					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1772					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1773					clock-names = "dc";
1774					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1775					reset-names = "dc";
1776
1777					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1778					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1779							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1780					interconnect-names = "dma-mem", "read-1";
1781
1782					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1783					nvidia,head = <2>;
1784				};
1785
1786				display@15230000 {
1787					compatible = "nvidia,tegra194-dc";
1788					reg = <0x15230000 0x10000>;
1789					interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1790					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1791					clock-names = "dc";
1792					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1793					reset-names = "dc";
1794
1795					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1796					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1797							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1798					interconnect-names = "dma-mem", "read-1";
1799
1800					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1801					nvidia,head = <3>;
1802				};
1803			};
1804
1805			vic@15340000 {
1806				compatible = "nvidia,tegra194-vic";
1807				reg = <0x15340000 0x00040000>;
1808				interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1809				clocks = <&bpmp TEGRA194_CLK_VIC>;
1810				clock-names = "vic";
1811				resets = <&bpmp TEGRA194_RESET_VIC>;
1812				reset-names = "vic";
1813
1814				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1815				interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
1816						<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
1817				interconnect-names = "dma-mem", "write";
1818				iommus = <&smmu TEGRA194_SID_VIC>;
1819				dma-coherent;
1820			};
1821
1822			nvjpg@15380000 {
1823				compatible = "nvidia,tegra194-nvjpg";
1824				reg = <0x15380000 0x40000>;
1825				clocks = <&bpmp TEGRA194_CLK_NVJPG>;
1826				clock-names = "nvjpg";
1827				resets = <&bpmp TEGRA194_RESET_NVJPG>;
1828				reset-names = "nvjpg";
1829
1830				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
1831				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
1832						<&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
1833				interconnect-names = "dma-mem", "write";
1834				iommus = <&smmu TEGRA194_SID_NVJPG>;
1835				dma-coherent;
1836			};
1837
1838			nvdec@15480000 {
1839				compatible = "nvidia,tegra194-nvdec";
1840				reg = <0x15480000 0x00040000>;
1841				clocks = <&bpmp TEGRA194_CLK_NVDEC>;
1842				clock-names = "nvdec";
1843				resets = <&bpmp TEGRA194_RESET_NVDEC>;
1844				reset-names = "nvdec";
1845
1846				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
1847				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
1848						<&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
1849						<&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
1850				interconnect-names = "dma-mem", "read-1", "write";
1851				iommus = <&smmu TEGRA194_SID_NVDEC>;
1852				dma-coherent;
1853
1854				nvidia,host1x-class = <0xf0>;
1855			};
1856
1857			nvenc@154c0000 {
1858				compatible = "nvidia,tegra194-nvenc";
1859				reg = <0x154c0000 0x40000>;
1860				clocks = <&bpmp TEGRA194_CLK_NVENC>;
1861				clock-names = "nvenc";
1862				resets = <&bpmp TEGRA194_RESET_NVENC>;
1863				reset-names = "nvenc";
1864
1865				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
1866				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
1867						<&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
1868						<&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
1869				interconnect-names = "dma-mem", "read-1", "write";
1870				iommus = <&smmu TEGRA194_SID_NVENC>;
1871				dma-coherent;
1872
1873				nvidia,host1x-class = <0x21>;
1874			};
1875
1876			dpaux0: dpaux@155c0000 {
1877				compatible = "nvidia,tegra194-dpaux";
1878				reg = <0x155c0000 0x10000>;
1879				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1880				clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1881					 <&bpmp TEGRA194_CLK_PLLDP>;
1882				clock-names = "dpaux", "parent";
1883				resets = <&bpmp TEGRA194_RESET_DPAUX>;
1884				reset-names = "dpaux";
1885				status = "disabled";
1886
1887				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1888
1889				state_dpaux0_aux: pinmux-aux {
1890					groups = "dpaux-io";
1891					function = "aux";
1892				};
1893
1894				state_dpaux0_i2c: pinmux-i2c {
1895					groups = "dpaux-io";
1896					function = "i2c";
1897				};
1898
1899				state_dpaux0_off: pinmux-off {
1900					groups = "dpaux-io";
1901					function = "off";
1902				};
1903
1904				i2c-bus {
1905					#address-cells = <1>;
1906					#size-cells = <0>;
1907				};
1908			};
1909
1910			dpaux1: dpaux@155d0000 {
1911				compatible = "nvidia,tegra194-dpaux";
1912				reg = <0x155d0000 0x10000>;
1913				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1914				clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1915					 <&bpmp TEGRA194_CLK_PLLDP>;
1916				clock-names = "dpaux", "parent";
1917				resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1918				reset-names = "dpaux";
1919				status = "disabled";
1920
1921				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1922
1923				state_dpaux1_aux: pinmux-aux {
1924					groups = "dpaux-io";
1925					function = "aux";
1926				};
1927
1928				state_dpaux1_i2c: pinmux-i2c {
1929					groups = "dpaux-io";
1930					function = "i2c";
1931				};
1932
1933				state_dpaux1_off: pinmux-off {
1934					groups = "dpaux-io";
1935					function = "off";
1936				};
1937
1938				i2c-bus {
1939					#address-cells = <1>;
1940					#size-cells = <0>;
1941				};
1942			};
1943
1944			dpaux2: dpaux@155e0000 {
1945				compatible = "nvidia,tegra194-dpaux";
1946				reg = <0x155e0000 0x10000>;
1947				interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1948				clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1949					 <&bpmp TEGRA194_CLK_PLLDP>;
1950				clock-names = "dpaux", "parent";
1951				resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1952				reset-names = "dpaux";
1953				status = "disabled";
1954
1955				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956
1957				state_dpaux2_aux: pinmux-aux {
1958					groups = "dpaux-io";
1959					function = "aux";
1960				};
1961
1962				state_dpaux2_i2c: pinmux-i2c {
1963					groups = "dpaux-io";
1964					function = "i2c";
1965				};
1966
1967				state_dpaux2_off: pinmux-off {
1968					groups = "dpaux-io";
1969					function = "off";
1970				};
1971
1972				i2c-bus {
1973					#address-cells = <1>;
1974					#size-cells = <0>;
1975				};
1976			};
1977
1978			dpaux3: dpaux@155f0000 {
1979				compatible = "nvidia,tegra194-dpaux";
1980				reg = <0x155f0000 0x10000>;
1981				interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1982				clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1983					 <&bpmp TEGRA194_CLK_PLLDP>;
1984				clock-names = "dpaux", "parent";
1985				resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1986				reset-names = "dpaux";
1987				status = "disabled";
1988
1989				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1990
1991				state_dpaux3_aux: pinmux-aux {
1992					groups = "dpaux-io";
1993					function = "aux";
1994				};
1995
1996				state_dpaux3_i2c: pinmux-i2c {
1997					groups = "dpaux-io";
1998					function = "i2c";
1999				};
2000
2001				state_dpaux3_off: pinmux-off {
2002					groups = "dpaux-io";
2003					function = "off";
2004				};
2005
2006				i2c-bus {
2007					#address-cells = <1>;
2008					#size-cells = <0>;
2009				};
2010			};
2011
2012			nvenc@15a80000 {
2013				compatible = "nvidia,tegra194-nvenc";
2014				reg = <0x15a80000 0x00040000>;
2015				clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2016				clock-names = "nvenc";
2017				resets = <&bpmp TEGRA194_RESET_NVENC1>;
2018				reset-names = "nvenc";
2019
2020				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2021				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
2022						<&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
2023						<&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
2024				interconnect-names = "dma-mem", "read-1", "write";
2025				iommus = <&smmu TEGRA194_SID_NVENC1>;
2026				dma-coherent;
2027
2028				nvidia,host1x-class = <0x22>;
2029			};
2030
2031			sor0: sor@15b00000 {
2032				compatible = "nvidia,tegra194-sor";
2033				reg = <0x15b00000 0x40000>;
2034				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2035				clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2036					 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2037					 <&bpmp TEGRA194_CLK_PLLD>,
2038					 <&bpmp TEGRA194_CLK_PLLDP>,
2039					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2040					 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2041				clock-names = "sor", "out", "parent", "dp", "safe",
2042					      "pad";
2043				resets = <&bpmp TEGRA194_RESET_SOR0>;
2044				reset-names = "sor";
2045				pinctrl-0 = <&state_dpaux0_aux>;
2046				pinctrl-1 = <&state_dpaux0_i2c>;
2047				pinctrl-2 = <&state_dpaux0_off>;
2048				pinctrl-names = "aux", "i2c", "off";
2049				status = "disabled";
2050
2051				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2052				nvidia,interface = <0>;
2053			};
2054
2055			sor1: sor@15b40000 {
2056				compatible = "nvidia,tegra194-sor";
2057				reg = <0x15b40000 0x40000>;
2058				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2059				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2060					 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2061					 <&bpmp TEGRA194_CLK_PLLD2>,
2062					 <&bpmp TEGRA194_CLK_PLLDP>,
2063					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2064					 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2065				clock-names = "sor", "out", "parent", "dp", "safe",
2066					      "pad";
2067				resets = <&bpmp TEGRA194_RESET_SOR1>;
2068				reset-names = "sor";
2069				pinctrl-0 = <&state_dpaux1_aux>;
2070				pinctrl-1 = <&state_dpaux1_i2c>;
2071				pinctrl-2 = <&state_dpaux1_off>;
2072				pinctrl-names = "aux", "i2c", "off";
2073				status = "disabled";
2074
2075				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2076				nvidia,interface = <1>;
2077			};
2078
2079			sor2: sor@15b80000 {
2080				compatible = "nvidia,tegra194-sor";
2081				reg = <0x15b80000 0x40000>;
2082				interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2083				clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2084					 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2085					 <&bpmp TEGRA194_CLK_PLLD3>,
2086					 <&bpmp TEGRA194_CLK_PLLDP>,
2087					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2088					 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2089				clock-names = "sor", "out", "parent", "dp", "safe",
2090					      "pad";
2091				resets = <&bpmp TEGRA194_RESET_SOR2>;
2092				reset-names = "sor";
2093				pinctrl-0 = <&state_dpaux2_aux>;
2094				pinctrl-1 = <&state_dpaux2_i2c>;
2095				pinctrl-2 = <&state_dpaux2_off>;
2096				pinctrl-names = "aux", "i2c", "off";
2097				status = "disabled";
2098
2099				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2100				nvidia,interface = <2>;
2101			};
2102
2103			sor3: sor@15bc0000 {
2104				compatible = "nvidia,tegra194-sor";
2105				reg = <0x15bc0000 0x40000>;
2106				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2107				clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2108					 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2109					 <&bpmp TEGRA194_CLK_PLLD4>,
2110					 <&bpmp TEGRA194_CLK_PLLDP>,
2111					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2112					 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2113				clock-names = "sor", "out", "parent", "dp", "safe",
2114					      "pad";
2115				resets = <&bpmp TEGRA194_RESET_SOR3>;
2116				reset-names = "sor";
2117				pinctrl-0 = <&state_dpaux3_aux>;
2118				pinctrl-1 = <&state_dpaux3_i2c>;
2119				pinctrl-2 = <&state_dpaux3_off>;
2120				pinctrl-names = "aux", "i2c", "off";
2121				status = "disabled";
2122
2123				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2124				nvidia,interface = <3>;
2125			};
2126		};
2127
2128		gpu@17000000 {
2129			compatible = "nvidia,gv11b";
2130			reg = <0x17000000 0x1000000>,
2131			      <0x18000000 0x1000000>;
2132			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2133				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2134			interrupt-names = "stall", "nonstall";
2135			clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2136				 <&bpmp TEGRA194_CLK_GPU_PWR>,
2137				 <&bpmp TEGRA194_CLK_FUSE>;
2138			clock-names = "gpu", "pwr", "fuse";
2139			resets = <&bpmp TEGRA194_RESET_GPU>;
2140			reset-names = "gpu";
2141			dma-coherent;
2142
2143			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2144			interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2145					<&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
2146					<&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
2147					<&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
2148					<&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
2149					<&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
2150					<&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
2151					<&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
2152					<&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
2153					<&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
2154					<&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
2155					<&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
2156			interconnect-names = "dma-mem", "read-0-hp", "write-0",
2157					     "read-1", "read-1-hp", "write-1",
2158					     "read-2", "read-2-hp", "write-2",
2159					     "read-3", "read-3-hp", "write-3";
2160		};
2161	};
2162
2163	pcie@14100000 {
2164		compatible = "nvidia,tegra194-pcie";
2165		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2166		reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
2167		      <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2168		      <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2169		      <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2170		reg-names = "appl", "config", "atu_dma", "dbi";
2171
2172		status = "disabled";
2173
2174		#address-cells = <3>;
2175		#size-cells = <2>;
2176		device_type = "pci";
2177		num-lanes = <1>;
2178		linux,pci-domain = <1>;
2179
2180		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2181		clock-names = "core";
2182
2183		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
2184			 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
2185		reset-names = "apb", "core";
2186
2187		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2188			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2189		interrupt-names = "intr", "msi";
2190
2191		#interrupt-cells = <1>;
2192		interrupt-map-mask = <0 0 0 0>;
2193		interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2194
2195		nvidia,bpmp = <&bpmp 1>;
2196
2197		nvidia,aspm-cmrt-us = <60>;
2198		nvidia,aspm-pwr-on-t-us = <20>;
2199		nvidia,aspm-l0s-entrance-latency-us = <3>;
2200
2201		bus-range = <0x0 0xff>;
2202
2203		ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2204			 <0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2205			 <0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2206
2207		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
2208				<&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
2209		interconnect-names = "dma-mem", "write";
2210		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2211		iommu-map-mask = <0x0>;
2212		dma-coherent;
2213	};
2214
2215	pcie@14120000 {
2216		compatible = "nvidia,tegra194-pcie";
2217		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2218		reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
2219		      <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2220		      <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2221		      <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2222		reg-names = "appl", "config", "atu_dma", "dbi";
2223
2224		status = "disabled";
2225
2226		#address-cells = <3>;
2227		#size-cells = <2>;
2228		device_type = "pci";
2229		num-lanes = <1>;
2230		linux,pci-domain = <2>;
2231
2232		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2233		clock-names = "core";
2234
2235		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
2236			 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
2237		reset-names = "apb", "core";
2238
2239		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2240			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2241		interrupt-names = "intr", "msi";
2242
2243		#interrupt-cells = <1>;
2244		interrupt-map-mask = <0 0 0 0>;
2245		interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2246
2247		nvidia,bpmp = <&bpmp 2>;
2248
2249		nvidia,aspm-cmrt-us = <60>;
2250		nvidia,aspm-pwr-on-t-us = <20>;
2251		nvidia,aspm-l0s-entrance-latency-us = <3>;
2252
2253		bus-range = <0x0 0xff>;
2254
2255		ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2256			 <0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2257			 <0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2258
2259		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
2260				<&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
2261		interconnect-names = "dma-mem", "write";
2262		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2263		iommu-map-mask = <0x0>;
2264		dma-coherent;
2265	};
2266
2267	pcie@14140000 {
2268		compatible = "nvidia,tegra194-pcie";
2269		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2270		reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
2271		      <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2272		      <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2273		      <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2274		reg-names = "appl", "config", "atu_dma", "dbi";
2275
2276		status = "disabled";
2277
2278		#address-cells = <3>;
2279		#size-cells = <2>;
2280		device_type = "pci";
2281		num-lanes = <1>;
2282		linux,pci-domain = <3>;
2283
2284		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2285		clock-names = "core";
2286
2287		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
2288			 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
2289		reset-names = "apb", "core";
2290
2291		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2292			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2293		interrupt-names = "intr", "msi";
2294
2295		#interrupt-cells = <1>;
2296		interrupt-map-mask = <0 0 0 0>;
2297		interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2298
2299		nvidia,bpmp = <&bpmp 3>;
2300
2301		nvidia,aspm-cmrt-us = <60>;
2302		nvidia,aspm-pwr-on-t-us = <20>;
2303		nvidia,aspm-l0s-entrance-latency-us = <3>;
2304
2305		bus-range = <0x0 0xff>;
2306
2307		ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2308			 <0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
2309			 <0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2310
2311		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
2312				<&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
2313		interconnect-names = "dma-mem", "write";
2314		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2315		iommu-map-mask = <0x0>;
2316		dma-coherent;
2317	};
2318
2319	pcie@14160000 {
2320		compatible = "nvidia,tegra194-pcie";
2321		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2322		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2323		      <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2324		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2325		      <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2326		reg-names = "appl", "config", "atu_dma", "dbi";
2327
2328		status = "disabled";
2329
2330		#address-cells = <3>;
2331		#size-cells = <2>;
2332		device_type = "pci";
2333		num-lanes = <4>;
2334		linux,pci-domain = <4>;
2335
2336		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2337		clock-names = "core";
2338
2339		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2340			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2341		reset-names = "apb", "core";
2342
2343		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2344			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2345		interrupt-names = "intr", "msi";
2346
2347		#interrupt-cells = <1>;
2348		interrupt-map-mask = <0 0 0 0>;
2349		interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2350
2351		nvidia,bpmp = <&bpmp 4>;
2352
2353		nvidia,aspm-cmrt-us = <60>;
2354		nvidia,aspm-pwr-on-t-us = <20>;
2355		nvidia,aspm-l0s-entrance-latency-us = <3>;
2356
2357		bus-range = <0x0 0xff>;
2358
2359		ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2360			 <0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2361			 <0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2362
2363		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2364				<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2365		interconnect-names = "dma-mem", "write";
2366		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2367		iommu-map-mask = <0x0>;
2368		dma-coherent;
2369	};
2370
2371	pcie@14180000 {
2372		compatible = "nvidia,tegra194-pcie";
2373		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2374		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2375		      <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2376		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2377		      <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2378		reg-names = "appl", "config", "atu_dma", "dbi";
2379
2380		status = "disabled";
2381
2382		#address-cells = <3>;
2383		#size-cells = <2>;
2384		device_type = "pci";
2385		num-lanes = <8>;
2386		linux,pci-domain = <0>;
2387
2388		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2389		clock-names = "core";
2390
2391		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2392			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2393		reset-names = "apb", "core";
2394
2395		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2396			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2397		interrupt-names = "intr", "msi";
2398
2399		#interrupt-cells = <1>;
2400		interrupt-map-mask = <0 0 0 0>;
2401		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2402
2403		nvidia,bpmp = <&bpmp 0>;
2404
2405		nvidia,aspm-cmrt-us = <60>;
2406		nvidia,aspm-pwr-on-t-us = <20>;
2407		nvidia,aspm-l0s-entrance-latency-us = <3>;
2408
2409		bus-range = <0x0 0xff>;
2410
2411		ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2412			 <0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2413			 <0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2414
2415		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2416				<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2417		interconnect-names = "dma-mem", "write";
2418		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2419		iommu-map-mask = <0x0>;
2420		dma-coherent;
2421	};
2422
2423	pcie@141a0000 {
2424		compatible = "nvidia,tegra194-pcie";
2425		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2426		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2427		      <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2428		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2429		      <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2430		reg-names = "appl", "config", "atu_dma", "dbi";
2431
2432		status = "disabled";
2433
2434		#address-cells = <3>;
2435		#size-cells = <2>;
2436		device_type = "pci";
2437		num-lanes = <8>;
2438		linux,pci-domain = <5>;
2439
2440		pinctrl-names = "default";
2441		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2442
2443		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2444		clock-names = "core";
2445
2446		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2447			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2448		reset-names = "apb", "core";
2449
2450		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2451			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2452		interrupt-names = "intr", "msi";
2453
2454		nvidia,bpmp = <&bpmp 5>;
2455
2456		#interrupt-cells = <1>;
2457		interrupt-map-mask = <0 0 0 0>;
2458		interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2459
2460		nvidia,aspm-cmrt-us = <60>;
2461		nvidia,aspm-pwr-on-t-us = <20>;
2462		nvidia,aspm-l0s-entrance-latency-us = <3>;
2463
2464		bus-range = <0x0 0xff>;
2465
2466		ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2467			 <0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2468			 <0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2469
2470		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2471				<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2472		interconnect-names = "dma-mem", "write";
2473		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2474		iommu-map-mask = <0x0>;
2475		dma-coherent;
2476	};
2477
2478	pcie-ep@14160000 {
2479		compatible = "nvidia,tegra194-pcie-ep";
2480		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2481		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2482		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2483		      <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2484		      <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2485		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2486
2487		status = "disabled";
2488
2489		num-lanes = <4>;
2490		num-ib-windows = <2>;
2491		num-ob-windows = <8>;
2492
2493		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2494		clock-names = "core";
2495
2496		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2497			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2498		reset-names = "apb", "core";
2499
2500		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2501		interrupt-names = "intr";
2502
2503		nvidia,bpmp = <&bpmp 4>;
2504
2505		nvidia,aspm-cmrt-us = <60>;
2506		nvidia,aspm-pwr-on-t-us = <20>;
2507		nvidia,aspm-l0s-entrance-latency-us = <3>;
2508
2509		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2510				<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2511		interconnect-names = "dma-mem", "write";
2512		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2513		iommu-map-mask = <0x0>;
2514		dma-coherent;
2515	};
2516
2517	pcie-ep@14180000 {
2518		compatible = "nvidia,tegra194-pcie-ep";
2519		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2520		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2521		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2522		      <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2523		      <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2524		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2525
2526		status = "disabled";
2527
2528		num-lanes = <8>;
2529		num-ib-windows = <2>;
2530		num-ob-windows = <8>;
2531
2532		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2533		clock-names = "core";
2534
2535		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2536			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2537		reset-names = "apb", "core";
2538
2539		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2540		interrupt-names = "intr";
2541
2542		nvidia,bpmp = <&bpmp 0>;
2543
2544		nvidia,aspm-cmrt-us = <60>;
2545		nvidia,aspm-pwr-on-t-us = <20>;
2546		nvidia,aspm-l0s-entrance-latency-us = <3>;
2547
2548		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2549				<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2550		interconnect-names = "dma-mem", "write";
2551		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2552		iommu-map-mask = <0x0>;
2553		dma-coherent;
2554	};
2555
2556	pcie-ep@141a0000 {
2557		compatible = "nvidia,tegra194-pcie-ep";
2558		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2559		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2560		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2561		      <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2562		      <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2563		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2564
2565		status = "disabled";
2566
2567		num-lanes = <8>;
2568		num-ib-windows = <2>;
2569		num-ob-windows = <8>;
2570
2571		pinctrl-names = "default";
2572		pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2573
2574		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2575		clock-names = "core";
2576
2577		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2578			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2579		reset-names = "apb", "core";
2580
2581		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2582		interrupt-names = "intr";
2583
2584		nvidia,bpmp = <&bpmp 5>;
2585
2586		nvidia,aspm-cmrt-us = <60>;
2587		nvidia,aspm-pwr-on-t-us = <20>;
2588		nvidia,aspm-l0s-entrance-latency-us = <3>;
2589
2590		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2591				<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2592		interconnect-names = "dma-mem", "write";
2593		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2594		iommu-map-mask = <0x0>;
2595		dma-coherent;
2596	};
2597
2598	sram@40000000 {
2599		compatible = "nvidia,tegra194-sysram", "mmio-sram";
2600		reg = <0x0 0x40000000 0x0 0x50000>;
2601		#address-cells = <1>;
2602		#size-cells = <1>;
2603		ranges = <0x0 0x0 0x40000000 0x50000>;
2604
2605		cpu_bpmp_tx: sram@4e000 {
2606			reg = <0x4e000 0x1000>;
2607			label = "cpu-bpmp-tx";
2608			pool;
2609		};
2610
2611		cpu_bpmp_rx: sram@4f000 {
2612			reg = <0x4f000 0x1000>;
2613			label = "cpu-bpmp-rx";
2614			pool;
2615		};
2616	};
2617
2618	bpmp: bpmp {
2619		compatible = "nvidia,tegra186-bpmp";
2620		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2621				    TEGRA_HSP_DB_MASTER_BPMP>;
2622		shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2623		#clock-cells = <1>;
2624		#reset-cells = <1>;
2625		#power-domain-cells = <1>;
2626		interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2627				<&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2628				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2629				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2630		interconnect-names = "read", "write", "dma-mem", "dma-write";
2631		iommus = <&smmu TEGRA194_SID_BPMP>;
2632
2633		bpmp_i2c: i2c {
2634			compatible = "nvidia,tegra186-bpmp-i2c";
2635			nvidia,bpmp-bus-id = <5>;
2636			#address-cells = <1>;
2637			#size-cells = <0>;
2638		};
2639
2640		bpmp_thermal: thermal {
2641			compatible = "nvidia,tegra186-bpmp-thermal";
2642			#thermal-sensor-cells = <1>;
2643		};
2644	};
2645
2646	cpus {
2647		compatible = "nvidia,tegra194-ccplex";
2648		nvidia,bpmp = <&bpmp>;
2649		#address-cells = <1>;
2650		#size-cells = <0>;
2651
2652		cpu0_0: cpu@0 {
2653			compatible = "nvidia,tegra194-carmel";
2654			device_type = "cpu";
2655			reg = <0x000>;
2656			enable-method = "psci";
2657			i-cache-size = <131072>;
2658			i-cache-line-size = <64>;
2659			i-cache-sets = <512>;
2660			d-cache-size = <65536>;
2661			d-cache-line-size = <64>;
2662			d-cache-sets = <256>;
2663			next-level-cache = <&l2c_0>;
2664		};
2665
2666		cpu0_1: cpu@1 {
2667			compatible = "nvidia,tegra194-carmel";
2668			device_type = "cpu";
2669			reg = <0x001>;
2670			enable-method = "psci";
2671			i-cache-size = <131072>;
2672			i-cache-line-size = <64>;
2673			i-cache-sets = <512>;
2674			d-cache-size = <65536>;
2675			d-cache-line-size = <64>;
2676			d-cache-sets = <256>;
2677			next-level-cache = <&l2c_0>;
2678		};
2679
2680		cpu1_0: cpu@100 {
2681			compatible = "nvidia,tegra194-carmel";
2682			device_type = "cpu";
2683			reg = <0x100>;
2684			enable-method = "psci";
2685			i-cache-size = <131072>;
2686			i-cache-line-size = <64>;
2687			i-cache-sets = <512>;
2688			d-cache-size = <65536>;
2689			d-cache-line-size = <64>;
2690			d-cache-sets = <256>;
2691			next-level-cache = <&l2c_1>;
2692		};
2693
2694		cpu1_1: cpu@101 {
2695			compatible = "nvidia,tegra194-carmel";
2696			device_type = "cpu";
2697			reg = <0x101>;
2698			enable-method = "psci";
2699			i-cache-size = <131072>;
2700			i-cache-line-size = <64>;
2701			i-cache-sets = <512>;
2702			d-cache-size = <65536>;
2703			d-cache-line-size = <64>;
2704			d-cache-sets = <256>;
2705			next-level-cache = <&l2c_1>;
2706		};
2707
2708		cpu2_0: cpu@200 {
2709			compatible = "nvidia,tegra194-carmel";
2710			device_type = "cpu";
2711			reg = <0x200>;
2712			enable-method = "psci";
2713			i-cache-size = <131072>;
2714			i-cache-line-size = <64>;
2715			i-cache-sets = <512>;
2716			d-cache-size = <65536>;
2717			d-cache-line-size = <64>;
2718			d-cache-sets = <256>;
2719			next-level-cache = <&l2c_2>;
2720		};
2721
2722		cpu2_1: cpu@201 {
2723			compatible = "nvidia,tegra194-carmel";
2724			device_type = "cpu";
2725			reg = <0x201>;
2726			enable-method = "psci";
2727			i-cache-size = <131072>;
2728			i-cache-line-size = <64>;
2729			i-cache-sets = <512>;
2730			d-cache-size = <65536>;
2731			d-cache-line-size = <64>;
2732			d-cache-sets = <256>;
2733			next-level-cache = <&l2c_2>;
2734		};
2735
2736		cpu3_0: cpu@300 {
2737			compatible = "nvidia,tegra194-carmel";
2738			device_type = "cpu";
2739			reg = <0x300>;
2740			enable-method = "psci";
2741			i-cache-size = <131072>;
2742			i-cache-line-size = <64>;
2743			i-cache-sets = <512>;
2744			d-cache-size = <65536>;
2745			d-cache-line-size = <64>;
2746			d-cache-sets = <256>;
2747			next-level-cache = <&l2c_3>;
2748		};
2749
2750		cpu3_1: cpu@301 {
2751			compatible = "nvidia,tegra194-carmel";
2752			device_type = "cpu";
2753			reg = <0x301>;
2754			enable-method = "psci";
2755			i-cache-size = <131072>;
2756			i-cache-line-size = <64>;
2757			i-cache-sets = <512>;
2758			d-cache-size = <65536>;
2759			d-cache-line-size = <64>;
2760			d-cache-sets = <256>;
2761			next-level-cache = <&l2c_3>;
2762		};
2763
2764		cpu-map {
2765			cluster0 {
2766				core0 {
2767					cpu = <&cpu0_0>;
2768				};
2769
2770				core1 {
2771					cpu = <&cpu0_1>;
2772				};
2773			};
2774
2775			cluster1 {
2776				core0 {
2777					cpu = <&cpu1_0>;
2778				};
2779
2780				core1 {
2781					cpu = <&cpu1_1>;
2782				};
2783			};
2784
2785			cluster2 {
2786				core0 {
2787					cpu = <&cpu2_0>;
2788				};
2789
2790				core1 {
2791					cpu = <&cpu2_1>;
2792				};
2793			};
2794
2795			cluster3 {
2796				core0 {
2797					cpu = <&cpu3_0>;
2798				};
2799
2800				core1 {
2801					cpu = <&cpu3_1>;
2802				};
2803			};
2804		};
2805
2806		l2c_0: l2-cache0 {
2807			cache-size = <2097152>;
2808			cache-line-size = <64>;
2809			cache-sets = <2048>;
2810			next-level-cache = <&l3c>;
2811		};
2812
2813		l2c_1: l2-cache1 {
2814			cache-size = <2097152>;
2815			cache-line-size = <64>;
2816			cache-sets = <2048>;
2817			next-level-cache = <&l3c>;
2818		};
2819
2820		l2c_2: l2-cache2 {
2821			cache-size = <2097152>;
2822			cache-line-size = <64>;
2823			cache-sets = <2048>;
2824			next-level-cache = <&l3c>;
2825		};
2826
2827		l2c_3: l2-cache3 {
2828			cache-size = <2097152>;
2829			cache-line-size = <64>;
2830			cache-sets = <2048>;
2831			next-level-cache = <&l3c>;
2832		};
2833
2834		l3c: l3-cache {
2835			cache-size = <4194304>;
2836			cache-line-size = <64>;
2837			cache-sets = <4096>;
2838		};
2839	};
2840
2841	pmu {
2842		compatible = "arm,armv8-pmuv3";
2843		interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2844			     <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
2845			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
2846			     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
2847			     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
2848			     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
2849			     <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
2850			     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
2851		interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
2852				      &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
2853	};
2854
2855	psci {
2856		compatible = "arm,psci-1.0";
2857		status = "okay";
2858		method = "smc";
2859	};
2860
2861	sound {
2862		status = "disabled";
2863
2864		clocks = <&bpmp TEGRA194_CLK_PLLA>,
2865			 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2866		clock-names = "pll_a", "plla_out0";
2867		assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
2868				  <&bpmp TEGRA194_CLK_PLLA_OUT0>,
2869				  <&bpmp TEGRA194_CLK_AUD_MCLK>;
2870		assigned-clock-parents = <0>,
2871					 <&bpmp TEGRA194_CLK_PLLA>,
2872					 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2873		/*
2874		 * PLLA supports dynamic ramp. Below initial rate is chosen
2875		 * for this to work and oscillate between base rates required
2876		 * for 8x and 11.025x sample rate streams.
2877		 */
2878		assigned-clock-rates = <258000000>;
2879
2880		interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
2881				<&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
2882		interconnect-names = "dma-mem", "write";
2883		iommus = <&smmu TEGRA194_SID_APE>;
2884	};
2885
2886	tcu: serial {
2887		compatible = "nvidia,tegra194-tcu";
2888		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
2889		         <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
2890		mbox-names = "rx", "tx";
2891	};
2892
2893	thermal-zones {
2894		cpu-thermal {
2895			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
2896			status = "disabled";
2897		};
2898
2899		gpu-thermal {
2900			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2901			status = "disabled";
2902		};
2903
2904		aux-thermal {
2905			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2906			status = "disabled";
2907		};
2908
2909		pllx-thermal {
2910			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2911			status = "disabled";
2912		};
2913
2914		ao-thermal {
2915			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
2916			status = "disabled";
2917		};
2918
2919		tj-thermal {
2920			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2921			status = "disabled";
2922		};
2923	};
2924
2925	timer {
2926		compatible = "arm,armv8-timer";
2927		interrupts = <GIC_PPI 13
2928				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2929			     <GIC_PPI 14
2930				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2931			     <GIC_PPI 11
2932				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2933			     <GIC_PPI 10
2934				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2935		interrupt-parent = <&gic>;
2936		always-on;
2937	};
2938};
2939