1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 gpcdma: dma-controller@2600000 { 119 compatible = "nvidia,tegra194-gpcdma", 120 "nvidia,tegra186-gpcdma"; 121 reg = <0x2600000 0x210000>; 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123 reset-names = "gpcdma"; 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155 #dma-cells = <1>; 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157 dma-coherent; 158 status = "okay"; 159 }; 160 161 aconnect@2900000 { 162 compatible = "nvidia,tegra194-aconnect", 163 "nvidia,tegra210-aconnect"; 164 clocks = <&bpmp TEGRA194_CLK_APE>, 165 <&bpmp TEGRA194_CLK_APB2APE>; 166 clock-names = "ape", "apb2ape"; 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0x02900000 0x02900000 0x200000>; 171 status = "disabled"; 172 173 adma: dma-controller@2930000 { 174 compatible = "nvidia,tegra194-adma", 175 "nvidia,tegra186-adma"; 176 reg = <0x02930000 0x20000>; 177 interrupt-parent = <&agic>; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #dma-cells = <1>; 211 clocks = <&bpmp TEGRA194_CLK_AHUB>; 212 clock-names = "d_audio"; 213 status = "disabled"; 214 }; 215 216 agic: interrupt-controller@2a40000 { 217 compatible = "nvidia,tegra194-agic", 218 "nvidia,tegra210-agic"; 219 #interrupt-cells = <3>; 220 interrupt-controller; 221 reg = <0x02a41000 0x1000>, 222 <0x02a42000 0x2000>; 223 interrupts = <GIC_SPI 145 224 (GIC_CPU_MASK_SIMPLE(4) | 225 IRQ_TYPE_LEVEL_HIGH)>; 226 clocks = <&bpmp TEGRA194_CLK_APE>; 227 clock-names = "clk"; 228 status = "disabled"; 229 }; 230 231 tegra_ahub: ahub@2900800 { 232 compatible = "nvidia,tegra194-ahub", 233 "nvidia,tegra186-ahub"; 234 reg = <0x02900800 0x800>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "ahub"; 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x02900800 0x02900800 0x11800>; 242 status = "disabled"; 243 244 tegra_admaif: admaif@290f000 { 245 compatible = "nvidia,tegra194-admaif", 246 "nvidia,tegra186-admaif"; 247 reg = <0x0290f000 0x1000>; 248 dmas = <&adma 1>, <&adma 1>, 249 <&adma 2>, <&adma 2>, 250 <&adma 3>, <&adma 3>, 251 <&adma 4>, <&adma 4>, 252 <&adma 5>, <&adma 5>, 253 <&adma 6>, <&adma 6>, 254 <&adma 7>, <&adma 7>, 255 <&adma 8>, <&adma 8>, 256 <&adma 9>, <&adma 9>, 257 <&adma 10>, <&adma 10>, 258 <&adma 11>, <&adma 11>, 259 <&adma 12>, <&adma 12>, 260 <&adma 13>, <&adma 13>, 261 <&adma 14>, <&adma 14>, 262 <&adma 15>, <&adma 15>, 263 <&adma 16>, <&adma 16>, 264 <&adma 17>, <&adma 17>, 265 <&adma 18>, <&adma 18>, 266 <&adma 19>, <&adma 19>, 267 <&adma 20>, <&adma 20>; 268 dma-names = "rx1", "tx1", 269 "rx2", "tx2", 270 "rx3", "tx3", 271 "rx4", "tx4", 272 "rx5", "tx5", 273 "rx6", "tx6", 274 "rx7", "tx7", 275 "rx8", "tx8", 276 "rx9", "tx9", 277 "rx10", "tx10", 278 "rx11", "tx11", 279 "rx12", "tx12", 280 "rx13", "tx13", 281 "rx14", "tx14", 282 "rx15", "tx15", 283 "rx16", "tx16", 284 "rx17", "tx17", 285 "rx18", "tx18", 286 "rx19", "tx19", 287 "rx20", "tx20"; 288 status = "disabled"; 289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 290 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 291 interconnect-names = "dma-mem", "write"; 292 iommus = <&smmu TEGRA194_SID_APE>; 293 }; 294 295 tegra_i2s1: i2s@2901000 { 296 compatible = "nvidia,tegra194-i2s", 297 "nvidia,tegra210-i2s"; 298 reg = <0x2901000 0x100>; 299 clocks = <&bpmp TEGRA194_CLK_I2S1>, 300 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 301 clock-names = "i2s", "sync_input"; 302 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 303 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 304 assigned-clock-rates = <1536000>; 305 sound-name-prefix = "I2S1"; 306 status = "disabled"; 307 }; 308 309 tegra_i2s2: i2s@2901100 { 310 compatible = "nvidia,tegra194-i2s", 311 "nvidia,tegra210-i2s"; 312 reg = <0x2901100 0x100>; 313 clocks = <&bpmp TEGRA194_CLK_I2S2>, 314 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 315 clock-names = "i2s", "sync_input"; 316 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 317 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 318 assigned-clock-rates = <1536000>; 319 sound-name-prefix = "I2S2"; 320 status = "disabled"; 321 }; 322 323 tegra_i2s3: i2s@2901200 { 324 compatible = "nvidia,tegra194-i2s", 325 "nvidia,tegra210-i2s"; 326 reg = <0x2901200 0x100>; 327 clocks = <&bpmp TEGRA194_CLK_I2S3>, 328 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 329 clock-names = "i2s", "sync_input"; 330 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 331 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 332 assigned-clock-rates = <1536000>; 333 sound-name-prefix = "I2S3"; 334 status = "disabled"; 335 }; 336 337 tegra_i2s4: i2s@2901300 { 338 compatible = "nvidia,tegra194-i2s", 339 "nvidia,tegra210-i2s"; 340 reg = <0x2901300 0x100>; 341 clocks = <&bpmp TEGRA194_CLK_I2S4>, 342 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 343 clock-names = "i2s", "sync_input"; 344 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 345 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 346 assigned-clock-rates = <1536000>; 347 sound-name-prefix = "I2S4"; 348 status = "disabled"; 349 }; 350 351 tegra_i2s5: i2s@2901400 { 352 compatible = "nvidia,tegra194-i2s", 353 "nvidia,tegra210-i2s"; 354 reg = <0x2901400 0x100>; 355 clocks = <&bpmp TEGRA194_CLK_I2S5>, 356 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 357 clock-names = "i2s", "sync_input"; 358 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 359 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 360 assigned-clock-rates = <1536000>; 361 sound-name-prefix = "I2S5"; 362 status = "disabled"; 363 }; 364 365 tegra_i2s6: i2s@2901500 { 366 compatible = "nvidia,tegra194-i2s", 367 "nvidia,tegra210-i2s"; 368 reg = <0x2901500 0x100>; 369 clocks = <&bpmp TEGRA194_CLK_I2S6>, 370 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 371 clock-names = "i2s", "sync_input"; 372 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 373 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 374 assigned-clock-rates = <1536000>; 375 sound-name-prefix = "I2S6"; 376 status = "disabled"; 377 }; 378 379 tegra_dmic1: dmic@2904000 { 380 compatible = "nvidia,tegra194-dmic", 381 "nvidia,tegra210-dmic"; 382 reg = <0x2904000 0x100>; 383 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 384 clock-names = "dmic"; 385 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387 assigned-clock-rates = <3072000>; 388 sound-name-prefix = "DMIC1"; 389 status = "disabled"; 390 }; 391 392 tegra_dmic2: dmic@2904100 { 393 compatible = "nvidia,tegra194-dmic", 394 "nvidia,tegra210-dmic"; 395 reg = <0x2904100 0x100>; 396 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 397 clock-names = "dmic"; 398 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 399 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 400 assigned-clock-rates = <3072000>; 401 sound-name-prefix = "DMIC2"; 402 status = "disabled"; 403 }; 404 405 tegra_dmic3: dmic@2904200 { 406 compatible = "nvidia,tegra194-dmic", 407 "nvidia,tegra210-dmic"; 408 reg = <0x2904200 0x100>; 409 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 410 clock-names = "dmic"; 411 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 412 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 413 assigned-clock-rates = <3072000>; 414 sound-name-prefix = "DMIC3"; 415 status = "disabled"; 416 }; 417 418 tegra_dmic4: dmic@2904300 { 419 compatible = "nvidia,tegra194-dmic", 420 "nvidia,tegra210-dmic"; 421 reg = <0x2904300 0x100>; 422 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 423 clock-names = "dmic"; 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426 assigned-clock-rates = <3072000>; 427 sound-name-prefix = "DMIC4"; 428 status = "disabled"; 429 }; 430 431 tegra_dspk1: dspk@2905000 { 432 compatible = "nvidia,tegra194-dspk", 433 "nvidia,tegra186-dspk"; 434 reg = <0x2905000 0x100>; 435 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 436 clock-names = "dspk"; 437 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439 assigned-clock-rates = <12288000>; 440 sound-name-prefix = "DSPK1"; 441 status = "disabled"; 442 }; 443 444 tegra_dspk2: dspk@2905100 { 445 compatible = "nvidia,tegra194-dspk", 446 "nvidia,tegra186-dspk"; 447 reg = <0x2905100 0x100>; 448 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 449 clock-names = "dspk"; 450 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452 assigned-clock-rates = <12288000>; 453 sound-name-prefix = "DSPK2"; 454 status = "disabled"; 455 }; 456 457 tegra_sfc1: sfc@2902000 { 458 compatible = "nvidia,tegra194-sfc", 459 "nvidia,tegra210-sfc"; 460 reg = <0x2902000 0x200>; 461 sound-name-prefix = "SFC1"; 462 status = "disabled"; 463 }; 464 465 tegra_sfc2: sfc@2902200 { 466 compatible = "nvidia,tegra194-sfc", 467 "nvidia,tegra210-sfc"; 468 reg = <0x2902200 0x200>; 469 sound-name-prefix = "SFC2"; 470 status = "disabled"; 471 }; 472 473 tegra_sfc3: sfc@2902400 { 474 compatible = "nvidia,tegra194-sfc", 475 "nvidia,tegra210-sfc"; 476 reg = <0x2902400 0x200>; 477 sound-name-prefix = "SFC3"; 478 status = "disabled"; 479 }; 480 481 tegra_sfc4: sfc@2902600 { 482 compatible = "nvidia,tegra194-sfc", 483 "nvidia,tegra210-sfc"; 484 reg = <0x2902600 0x200>; 485 sound-name-prefix = "SFC4"; 486 status = "disabled"; 487 }; 488 489 tegra_mvc1: mvc@290a000 { 490 compatible = "nvidia,tegra194-mvc", 491 "nvidia,tegra210-mvc"; 492 reg = <0x290a000 0x200>; 493 sound-name-prefix = "MVC1"; 494 status = "disabled"; 495 }; 496 497 tegra_mvc2: mvc@290a200 { 498 compatible = "nvidia,tegra194-mvc", 499 "nvidia,tegra210-mvc"; 500 reg = <0x290a200 0x200>; 501 sound-name-prefix = "MVC2"; 502 status = "disabled"; 503 }; 504 505 tegra_amx1: amx@2903000 { 506 compatible = "nvidia,tegra194-amx"; 507 reg = <0x2903000 0x100>; 508 sound-name-prefix = "AMX1"; 509 status = "disabled"; 510 }; 511 512 tegra_amx2: amx@2903100 { 513 compatible = "nvidia,tegra194-amx"; 514 reg = <0x2903100 0x100>; 515 sound-name-prefix = "AMX2"; 516 status = "disabled"; 517 }; 518 519 tegra_amx3: amx@2903200 { 520 compatible = "nvidia,tegra194-amx"; 521 reg = <0x2903200 0x100>; 522 sound-name-prefix = "AMX3"; 523 status = "disabled"; 524 }; 525 526 tegra_amx4: amx@2903300 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903300 0x100>; 529 sound-name-prefix = "AMX4"; 530 status = "disabled"; 531 }; 532 533 tegra_adx1: adx@2903800 { 534 compatible = "nvidia,tegra194-adx", 535 "nvidia,tegra210-adx"; 536 reg = <0x2903800 0x100>; 537 sound-name-prefix = "ADX1"; 538 status = "disabled"; 539 }; 540 541 tegra_adx2: adx@2903900 { 542 compatible = "nvidia,tegra194-adx", 543 "nvidia,tegra210-adx"; 544 reg = <0x2903900 0x100>; 545 sound-name-prefix = "ADX2"; 546 status = "disabled"; 547 }; 548 549 tegra_adx3: adx@2903a00 { 550 compatible = "nvidia,tegra194-adx", 551 "nvidia,tegra210-adx"; 552 reg = <0x2903a00 0x100>; 553 sound-name-prefix = "ADX3"; 554 status = "disabled"; 555 }; 556 557 tegra_adx4: adx@2903b00 { 558 compatible = "nvidia,tegra194-adx", 559 "nvidia,tegra210-adx"; 560 reg = <0x2903b00 0x100>; 561 sound-name-prefix = "ADX4"; 562 status = "disabled"; 563 }; 564 565 tegra_amixer: amixer@290bb00 { 566 compatible = "nvidia,tegra194-amixer", 567 "nvidia,tegra210-amixer"; 568 reg = <0x290bb00 0x800>; 569 sound-name-prefix = "MIXER1"; 570 status = "disabled"; 571 }; 572 573 tegra_asrc: asrc@2910000 { 574 compatible = "nvidia,tegra194-asrc", 575 "nvidia,tegra186-asrc"; 576 reg = <0x2910000 0x2000>; 577 sound-name-prefix = "ASRC1"; 578 status = "disabled"; 579 }; 580 }; 581 }; 582 583 pinmux: pinmux@2430000 { 584 compatible = "nvidia,tegra194-pinmux"; 585 reg = <0x2430000 0x17000>, 586 <0xc300000 0x4000>; 587 588 status = "okay"; 589 590 pex_rst_c5_out_state: pex_rst_c5_out { 591 pex_rst { 592 nvidia,pins = "pex_l5_rst_n_pgg1"; 593 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 594 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 595 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 596 nvidia,tristate = <TEGRA_PIN_DISABLE>; 597 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 598 }; 599 }; 600 601 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 602 clkreq { 603 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 604 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 605 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 606 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 607 nvidia,tristate = <TEGRA_PIN_DISABLE>; 608 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 609 }; 610 }; 611 }; 612 613 mc: memory-controller@2c00000 { 614 compatible = "nvidia,tegra194-mc"; 615 reg = <0x02c00000 0x10000>, /* MC-SID */ 616 <0x02c10000 0x10000>, /* MC Broadcast*/ 617 <0x02c20000 0x10000>, /* MC0 */ 618 <0x02c30000 0x10000>, /* MC1 */ 619 <0x02c40000 0x10000>, /* MC2 */ 620 <0x02c50000 0x10000>, /* MC3 */ 621 <0x02b80000 0x10000>, /* MC4 */ 622 <0x02b90000 0x10000>, /* MC5 */ 623 <0x02ba0000 0x10000>, /* MC6 */ 624 <0x02bb0000 0x10000>, /* MC7 */ 625 <0x01700000 0x10000>, /* MC8 */ 626 <0x01710000 0x10000>, /* MC9 */ 627 <0x01720000 0x10000>, /* MC10 */ 628 <0x01730000 0x10000>, /* MC11 */ 629 <0x01740000 0x10000>, /* MC12 */ 630 <0x01750000 0x10000>, /* MC13 */ 631 <0x01760000 0x10000>, /* MC14 */ 632 <0x01770000 0x10000>; /* MC15 */ 633 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 634 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 635 "ch11", "ch12", "ch13", "ch14", "ch15"; 636 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 637 #interconnect-cells = <1>; 638 status = "disabled"; 639 640 #address-cells = <2>; 641 #size-cells = <2>; 642 643 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 644 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 645 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 646 647 /* 648 * Bit 39 of addresses passing through the memory 649 * controller selects the XBAR format used when memory 650 * is accessed. This is used to transparently access 651 * memory in the XBAR format used by the discrete GPU 652 * (bit 39 set) or Tegra (bit 39 clear). 653 * 654 * As a consequence, the operating system must ensure 655 * that bit 39 is never used implicitly, for example 656 * via an I/O virtual address mapping of an IOMMU. If 657 * devices require access to the XBAR switch, their 658 * drivers must set this bit explicitly. 659 * 660 * Limit the DMA range for memory clients to [38:0]. 661 */ 662 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 663 664 emc: external-memory-controller@2c60000 { 665 compatible = "nvidia,tegra194-emc"; 666 reg = <0x0 0x02c60000 0x0 0x90000>, 667 <0x0 0x01780000 0x0 0x80000>; 668 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&bpmp TEGRA194_CLK_EMC>; 670 clock-names = "emc"; 671 672 #interconnect-cells = <0>; 673 674 nvidia,bpmp = <&bpmp>; 675 }; 676 }; 677 678 uarta: serial@3100000 { 679 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 680 reg = <0x03100000 0x40>; 681 reg-shift = <2>; 682 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&bpmp TEGRA194_CLK_UARTA>; 684 clock-names = "serial"; 685 resets = <&bpmp TEGRA194_RESET_UARTA>; 686 reset-names = "serial"; 687 status = "disabled"; 688 }; 689 690 uartb: serial@3110000 { 691 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 692 reg = <0x03110000 0x40>; 693 reg-shift = <2>; 694 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&bpmp TEGRA194_CLK_UARTB>; 696 clock-names = "serial"; 697 resets = <&bpmp TEGRA194_RESET_UARTB>; 698 reset-names = "serial"; 699 status = "disabled"; 700 }; 701 702 uartd: serial@3130000 { 703 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 704 reg = <0x03130000 0x40>; 705 reg-shift = <2>; 706 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&bpmp TEGRA194_CLK_UARTD>; 708 clock-names = "serial"; 709 resets = <&bpmp TEGRA194_RESET_UARTD>; 710 reset-names = "serial"; 711 status = "disabled"; 712 }; 713 714 uarte: serial@3140000 { 715 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 716 reg = <0x03140000 0x40>; 717 reg-shift = <2>; 718 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&bpmp TEGRA194_CLK_UARTE>; 720 clock-names = "serial"; 721 resets = <&bpmp TEGRA194_RESET_UARTE>; 722 reset-names = "serial"; 723 status = "disabled"; 724 }; 725 726 uartf: serial@3150000 { 727 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 728 reg = <0x03150000 0x40>; 729 reg-shift = <2>; 730 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&bpmp TEGRA194_CLK_UARTF>; 732 clock-names = "serial"; 733 resets = <&bpmp TEGRA194_RESET_UARTF>; 734 reset-names = "serial"; 735 status = "disabled"; 736 }; 737 738 gen1_i2c: i2c@3160000 { 739 compatible = "nvidia,tegra194-i2c"; 740 reg = <0x03160000 0x10000>; 741 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&bpmp TEGRA194_CLK_I2C1>; 745 clock-names = "div-clk"; 746 resets = <&bpmp TEGRA194_RESET_I2C1>; 747 reset-names = "i2c"; 748 status = "disabled"; 749 }; 750 751 uarth: serial@3170000 { 752 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 753 reg = <0x03170000 0x40>; 754 reg-shift = <2>; 755 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&bpmp TEGRA194_CLK_UARTH>; 757 clock-names = "serial"; 758 resets = <&bpmp TEGRA194_RESET_UARTH>; 759 reset-names = "serial"; 760 status = "disabled"; 761 }; 762 763 cam_i2c: i2c@3180000 { 764 compatible = "nvidia,tegra194-i2c"; 765 reg = <0x03180000 0x10000>; 766 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 clocks = <&bpmp TEGRA194_CLK_I2C3>; 770 clock-names = "div-clk"; 771 resets = <&bpmp TEGRA194_RESET_I2C3>; 772 reset-names = "i2c"; 773 status = "disabled"; 774 }; 775 776 /* shares pads with dpaux1 */ 777 dp_aux_ch1_i2c: i2c@3190000 { 778 compatible = "nvidia,tegra194-i2c"; 779 reg = <0x03190000 0x10000>; 780 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 clocks = <&bpmp TEGRA194_CLK_I2C4>; 784 clock-names = "div-clk"; 785 resets = <&bpmp TEGRA194_RESET_I2C4>; 786 reset-names = "i2c"; 787 pinctrl-0 = <&state_dpaux1_i2c>; 788 pinctrl-1 = <&state_dpaux1_off>; 789 pinctrl-names = "default", "idle"; 790 status = "disabled"; 791 }; 792 793 /* shares pads with dpaux0 */ 794 dp_aux_ch0_i2c: i2c@31b0000 { 795 compatible = "nvidia,tegra194-i2c"; 796 reg = <0x031b0000 0x10000>; 797 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 clocks = <&bpmp TEGRA194_CLK_I2C6>; 801 clock-names = "div-clk"; 802 resets = <&bpmp TEGRA194_RESET_I2C6>; 803 reset-names = "i2c"; 804 pinctrl-0 = <&state_dpaux0_i2c>; 805 pinctrl-1 = <&state_dpaux0_off>; 806 pinctrl-names = "default", "idle"; 807 status = "disabled"; 808 }; 809 810 /* shares pads with dpaux2 */ 811 dp_aux_ch2_i2c: i2c@31c0000 { 812 compatible = "nvidia,tegra194-i2c"; 813 reg = <0x031c0000 0x10000>; 814 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 clocks = <&bpmp TEGRA194_CLK_I2C7>; 818 clock-names = "div-clk"; 819 resets = <&bpmp TEGRA194_RESET_I2C7>; 820 reset-names = "i2c"; 821 pinctrl-0 = <&state_dpaux2_i2c>; 822 pinctrl-1 = <&state_dpaux2_off>; 823 pinctrl-names = "default", "idle"; 824 status = "disabled"; 825 }; 826 827 /* shares pads with dpaux3 */ 828 dp_aux_ch3_i2c: i2c@31e0000 { 829 compatible = "nvidia,tegra194-i2c"; 830 reg = <0x031e0000 0x10000>; 831 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 clocks = <&bpmp TEGRA194_CLK_I2C9>; 835 clock-names = "div-clk"; 836 resets = <&bpmp TEGRA194_RESET_I2C9>; 837 reset-names = "i2c"; 838 pinctrl-0 = <&state_dpaux3_i2c>; 839 pinctrl-1 = <&state_dpaux3_off>; 840 pinctrl-names = "default", "idle"; 841 status = "disabled"; 842 }; 843 844 spi@3270000 { 845 compatible = "nvidia,tegra194-qspi"; 846 reg = <0x3270000 0x1000>; 847 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 851 <&bpmp TEGRA194_CLK_QSPI0_PM>; 852 clock-names = "qspi", "qspi_out"; 853 resets = <&bpmp TEGRA194_RESET_QSPI0>; 854 reset-names = "qspi"; 855 status = "disabled"; 856 }; 857 858 spi@3300000 { 859 compatible = "nvidia,tegra194-qspi"; 860 reg = <0x3300000 0x1000>; 861 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 865 <&bpmp TEGRA194_CLK_QSPI1_PM>; 866 clock-names = "qspi", "qspi_out"; 867 resets = <&bpmp TEGRA194_RESET_QSPI1>; 868 reset-names = "qspi"; 869 status = "disabled"; 870 }; 871 872 pwm1: pwm@3280000 { 873 compatible = "nvidia,tegra194-pwm", 874 "nvidia,tegra186-pwm"; 875 reg = <0x3280000 0x10000>; 876 clocks = <&bpmp TEGRA194_CLK_PWM1>; 877 clock-names = "pwm"; 878 resets = <&bpmp TEGRA194_RESET_PWM1>; 879 reset-names = "pwm"; 880 status = "disabled"; 881 #pwm-cells = <2>; 882 }; 883 884 pwm2: pwm@3290000 { 885 compatible = "nvidia,tegra194-pwm", 886 "nvidia,tegra186-pwm"; 887 reg = <0x3290000 0x10000>; 888 clocks = <&bpmp TEGRA194_CLK_PWM2>; 889 clock-names = "pwm"; 890 resets = <&bpmp TEGRA194_RESET_PWM2>; 891 reset-names = "pwm"; 892 status = "disabled"; 893 #pwm-cells = <2>; 894 }; 895 896 pwm3: pwm@32a0000 { 897 compatible = "nvidia,tegra194-pwm", 898 "nvidia,tegra186-pwm"; 899 reg = <0x32a0000 0x10000>; 900 clocks = <&bpmp TEGRA194_CLK_PWM3>; 901 clock-names = "pwm"; 902 resets = <&bpmp TEGRA194_RESET_PWM3>; 903 reset-names = "pwm"; 904 status = "disabled"; 905 #pwm-cells = <2>; 906 }; 907 908 pwm5: pwm@32c0000 { 909 compatible = "nvidia,tegra194-pwm", 910 "nvidia,tegra186-pwm"; 911 reg = <0x32c0000 0x10000>; 912 clocks = <&bpmp TEGRA194_CLK_PWM5>; 913 clock-names = "pwm"; 914 resets = <&bpmp TEGRA194_RESET_PWM5>; 915 reset-names = "pwm"; 916 status = "disabled"; 917 #pwm-cells = <2>; 918 }; 919 920 pwm6: pwm@32d0000 { 921 compatible = "nvidia,tegra194-pwm", 922 "nvidia,tegra186-pwm"; 923 reg = <0x32d0000 0x10000>; 924 clocks = <&bpmp TEGRA194_CLK_PWM6>; 925 clock-names = "pwm"; 926 resets = <&bpmp TEGRA194_RESET_PWM6>; 927 reset-names = "pwm"; 928 status = "disabled"; 929 #pwm-cells = <2>; 930 }; 931 932 pwm7: pwm@32e0000 { 933 compatible = "nvidia,tegra194-pwm", 934 "nvidia,tegra186-pwm"; 935 reg = <0x32e0000 0x10000>; 936 clocks = <&bpmp TEGRA194_CLK_PWM7>; 937 clock-names = "pwm"; 938 resets = <&bpmp TEGRA194_RESET_PWM7>; 939 reset-names = "pwm"; 940 status = "disabled"; 941 #pwm-cells = <2>; 942 }; 943 944 pwm8: pwm@32f0000 { 945 compatible = "nvidia,tegra194-pwm", 946 "nvidia,tegra186-pwm"; 947 reg = <0x32f0000 0x10000>; 948 clocks = <&bpmp TEGRA194_CLK_PWM8>; 949 clock-names = "pwm"; 950 resets = <&bpmp TEGRA194_RESET_PWM8>; 951 reset-names = "pwm"; 952 status = "disabled"; 953 #pwm-cells = <2>; 954 }; 955 956 sdmmc1: mmc@3400000 { 957 compatible = "nvidia,tegra194-sdhci"; 958 reg = <0x03400000 0x10000>; 959 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 961 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 962 clock-names = "sdhci", "tmclk"; 963 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 964 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 965 assigned-clock-parents = 966 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 967 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 968 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 969 reset-names = "sdhci"; 970 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 971 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 972 interconnect-names = "dma-mem", "write"; 973 iommus = <&smmu TEGRA194_SID_SDMMC1>; 974 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 975 pinctrl-0 = <&sdmmc1_3v3>; 976 pinctrl-1 = <&sdmmc1_1v8>; 977 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 978 <0x07>; 979 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 980 <0x07>; 981 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 982 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 983 <0x07>; 984 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 985 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 986 nvidia,default-tap = <0x9>; 987 nvidia,default-trim = <0x5>; 988 sd-uhs-sdr25; 989 sd-uhs-sdr50; 990 sd-uhs-ddr50; 991 sd-uhs-sdr104; 992 status = "disabled"; 993 }; 994 995 sdmmc3: mmc@3440000 { 996 compatible = "nvidia,tegra194-sdhci"; 997 reg = <0x03440000 0x10000>; 998 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1000 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1001 clock-names = "sdhci", "tmclk"; 1002 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1003 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1004 assigned-clock-parents = 1005 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1006 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1007 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1008 reset-names = "sdhci"; 1009 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1010 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1011 interconnect-names = "dma-mem", "write"; 1012 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1013 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1014 pinctrl-0 = <&sdmmc3_3v3>; 1015 pinctrl-1 = <&sdmmc3_1v8>; 1016 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1017 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1018 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1019 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1020 <0x07>; 1021 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1022 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1023 <0x07>; 1024 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1025 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1026 nvidia,default-tap = <0x9>; 1027 nvidia,default-trim = <0x5>; 1028 sd-uhs-sdr25; 1029 sd-uhs-sdr50; 1030 sd-uhs-ddr50; 1031 sd-uhs-sdr104; 1032 status = "disabled"; 1033 }; 1034 1035 sdmmc4: mmc@3460000 { 1036 compatible = "nvidia,tegra194-sdhci"; 1037 reg = <0x03460000 0x10000>; 1038 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1040 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1041 clock-names = "sdhci", "tmclk"; 1042 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1043 <&bpmp TEGRA194_CLK_PLLC4>; 1044 assigned-clock-parents = 1045 <&bpmp TEGRA194_CLK_PLLC4>; 1046 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1047 reset-names = "sdhci"; 1048 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1049 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1050 interconnect-names = "dma-mem", "write"; 1051 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1052 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1053 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1054 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1055 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1056 <0x0a>; 1057 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1059 <0x0a>; 1060 nvidia,default-tap = <0x8>; 1061 nvidia,default-trim = <0x14>; 1062 nvidia,dqs-trim = <40>; 1063 cap-mmc-highspeed; 1064 mmc-ddr-1_8v; 1065 mmc-hs200-1_8v; 1066 mmc-hs400-1_8v; 1067 mmc-hs400-enhanced-strobe; 1068 supports-cqe; 1069 status = "disabled"; 1070 }; 1071 1072 hda@3510000 { 1073 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1074 reg = <0x3510000 0x10000>; 1075 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&bpmp TEGRA194_CLK_HDA>, 1077 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1078 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1079 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1080 resets = <&bpmp TEGRA194_RESET_HDA>, 1081 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1082 reset-names = "hda", "hda2hdmi"; 1083 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1084 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1085 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1086 interconnect-names = "dma-mem", "write"; 1087 iommus = <&smmu TEGRA194_SID_HDA>; 1088 status = "disabled"; 1089 }; 1090 1091 xusb_padctl: padctl@3520000 { 1092 compatible = "nvidia,tegra194-xusb-padctl"; 1093 reg = <0x03520000 0x1000>, 1094 <0x03540000 0x1000>; 1095 reg-names = "padctl", "ao"; 1096 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1097 1098 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1099 reset-names = "padctl"; 1100 1101 status = "disabled"; 1102 1103 pads { 1104 usb2 { 1105 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1106 clock-names = "trk"; 1107 1108 lanes { 1109 usb2-0 { 1110 nvidia,function = "xusb"; 1111 status = "disabled"; 1112 #phy-cells = <0>; 1113 }; 1114 1115 usb2-1 { 1116 nvidia,function = "xusb"; 1117 status = "disabled"; 1118 #phy-cells = <0>; 1119 }; 1120 1121 usb2-2 { 1122 nvidia,function = "xusb"; 1123 status = "disabled"; 1124 #phy-cells = <0>; 1125 }; 1126 1127 usb2-3 { 1128 nvidia,function = "xusb"; 1129 status = "disabled"; 1130 #phy-cells = <0>; 1131 }; 1132 }; 1133 }; 1134 1135 usb3 { 1136 lanes { 1137 usb3-0 { 1138 nvidia,function = "xusb"; 1139 status = "disabled"; 1140 #phy-cells = <0>; 1141 }; 1142 1143 usb3-1 { 1144 nvidia,function = "xusb"; 1145 status = "disabled"; 1146 #phy-cells = <0>; 1147 }; 1148 1149 usb3-2 { 1150 nvidia,function = "xusb"; 1151 status = "disabled"; 1152 #phy-cells = <0>; 1153 }; 1154 1155 usb3-3 { 1156 nvidia,function = "xusb"; 1157 status = "disabled"; 1158 #phy-cells = <0>; 1159 }; 1160 }; 1161 }; 1162 }; 1163 1164 ports { 1165 usb2-0 { 1166 status = "disabled"; 1167 }; 1168 1169 usb2-1 { 1170 status = "disabled"; 1171 }; 1172 1173 usb2-2 { 1174 status = "disabled"; 1175 }; 1176 1177 usb2-3 { 1178 status = "disabled"; 1179 }; 1180 1181 usb3-0 { 1182 status = "disabled"; 1183 }; 1184 1185 usb3-1 { 1186 status = "disabled"; 1187 }; 1188 1189 usb3-2 { 1190 status = "disabled"; 1191 }; 1192 1193 usb3-3 { 1194 status = "disabled"; 1195 }; 1196 }; 1197 }; 1198 1199 usb@3550000 { 1200 compatible = "nvidia,tegra194-xudc"; 1201 reg = <0x03550000 0x8000>, 1202 <0x03558000 0x1000>; 1203 reg-names = "base", "fpci"; 1204 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1206 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1207 <&bpmp TEGRA194_CLK_XUSB_SS>, 1208 <&bpmp TEGRA194_CLK_XUSB_FS>; 1209 clock-names = "dev", "ss", "ss_src", "fs_src"; 1210 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1211 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1212 interconnect-names = "dma-mem", "write"; 1213 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1214 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1215 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1216 power-domain-names = "dev", "ss"; 1217 nvidia,xusb-padctl = <&xusb_padctl>; 1218 status = "disabled"; 1219 }; 1220 1221 usb@3610000 { 1222 compatible = "nvidia,tegra194-xusb"; 1223 reg = <0x03610000 0x40000>, 1224 <0x03600000 0x10000>; 1225 reg-names = "hcd", "fpci"; 1226 1227 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1229 1230 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1231 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1232 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1233 <&bpmp TEGRA194_CLK_XUSB_SS>, 1234 <&bpmp TEGRA194_CLK_CLK_M>, 1235 <&bpmp TEGRA194_CLK_XUSB_FS>, 1236 <&bpmp TEGRA194_CLK_UTMIPLL>, 1237 <&bpmp TEGRA194_CLK_CLK_M>, 1238 <&bpmp TEGRA194_CLK_PLLE>; 1239 clock-names = "xusb_host", "xusb_falcon_src", 1240 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1241 "xusb_fs_src", "pll_u_480m", "clk_m", 1242 "pll_e"; 1243 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1244 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1245 interconnect-names = "dma-mem", "write"; 1246 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1247 1248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1249 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1250 power-domain-names = "xusb_host", "xusb_ss"; 1251 1252 nvidia,xusb-padctl = <&xusb_padctl>; 1253 status = "disabled"; 1254 }; 1255 1256 fuse@3820000 { 1257 compatible = "nvidia,tegra194-efuse"; 1258 reg = <0x03820000 0x10000>; 1259 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1260 clock-names = "fuse"; 1261 }; 1262 1263 gic: interrupt-controller@3881000 { 1264 compatible = "arm,gic-400"; 1265 #interrupt-cells = <3>; 1266 interrupt-controller; 1267 reg = <0x03881000 0x1000>, 1268 <0x03882000 0x2000>, 1269 <0x03884000 0x2000>, 1270 <0x03886000 0x2000>; 1271 interrupts = <GIC_PPI 9 1272 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1273 interrupt-parent = <&gic>; 1274 }; 1275 1276 cec@3960000 { 1277 compatible = "nvidia,tegra194-cec"; 1278 reg = <0x03960000 0x10000>; 1279 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1280 clocks = <&bpmp TEGRA194_CLK_CEC>; 1281 clock-names = "cec"; 1282 status = "disabled"; 1283 }; 1284 1285 hsp_top0: hsp@3c00000 { 1286 compatible = "nvidia,tegra194-hsp"; 1287 reg = <0x03c00000 0xa0000>; 1288 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1297 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1298 "shared3", "shared4", "shared5", "shared6", 1299 "shared7"; 1300 #mbox-cells = <2>; 1301 }; 1302 1303 p2u_hsio_0: phy@3e10000 { 1304 compatible = "nvidia,tegra194-p2u"; 1305 reg = <0x03e10000 0x10000>; 1306 reg-names = "ctl"; 1307 1308 #phy-cells = <0>; 1309 }; 1310 1311 p2u_hsio_1: phy@3e20000 { 1312 compatible = "nvidia,tegra194-p2u"; 1313 reg = <0x03e20000 0x10000>; 1314 reg-names = "ctl"; 1315 1316 #phy-cells = <0>; 1317 }; 1318 1319 p2u_hsio_2: phy@3e30000 { 1320 compatible = "nvidia,tegra194-p2u"; 1321 reg = <0x03e30000 0x10000>; 1322 reg-names = "ctl"; 1323 1324 #phy-cells = <0>; 1325 }; 1326 1327 p2u_hsio_3: phy@3e40000 { 1328 compatible = "nvidia,tegra194-p2u"; 1329 reg = <0x03e40000 0x10000>; 1330 reg-names = "ctl"; 1331 1332 #phy-cells = <0>; 1333 }; 1334 1335 p2u_hsio_4: phy@3e50000 { 1336 compatible = "nvidia,tegra194-p2u"; 1337 reg = <0x03e50000 0x10000>; 1338 reg-names = "ctl"; 1339 1340 #phy-cells = <0>; 1341 }; 1342 1343 p2u_hsio_5: phy@3e60000 { 1344 compatible = "nvidia,tegra194-p2u"; 1345 reg = <0x03e60000 0x10000>; 1346 reg-names = "ctl"; 1347 1348 #phy-cells = <0>; 1349 }; 1350 1351 p2u_hsio_6: phy@3e70000 { 1352 compatible = "nvidia,tegra194-p2u"; 1353 reg = <0x03e70000 0x10000>; 1354 reg-names = "ctl"; 1355 1356 #phy-cells = <0>; 1357 }; 1358 1359 p2u_hsio_7: phy@3e80000 { 1360 compatible = "nvidia,tegra194-p2u"; 1361 reg = <0x03e80000 0x10000>; 1362 reg-names = "ctl"; 1363 1364 #phy-cells = <0>; 1365 }; 1366 1367 p2u_hsio_8: phy@3e90000 { 1368 compatible = "nvidia,tegra194-p2u"; 1369 reg = <0x03e90000 0x10000>; 1370 reg-names = "ctl"; 1371 1372 #phy-cells = <0>; 1373 }; 1374 1375 p2u_hsio_9: phy@3ea0000 { 1376 compatible = "nvidia,tegra194-p2u"; 1377 reg = <0x03ea0000 0x10000>; 1378 reg-names = "ctl"; 1379 1380 #phy-cells = <0>; 1381 }; 1382 1383 p2u_nvhs_0: phy@3eb0000 { 1384 compatible = "nvidia,tegra194-p2u"; 1385 reg = <0x03eb0000 0x10000>; 1386 reg-names = "ctl"; 1387 1388 #phy-cells = <0>; 1389 }; 1390 1391 p2u_nvhs_1: phy@3ec0000 { 1392 compatible = "nvidia,tegra194-p2u"; 1393 reg = <0x03ec0000 0x10000>; 1394 reg-names = "ctl"; 1395 1396 #phy-cells = <0>; 1397 }; 1398 1399 p2u_nvhs_2: phy@3ed0000 { 1400 compatible = "nvidia,tegra194-p2u"; 1401 reg = <0x03ed0000 0x10000>; 1402 reg-names = "ctl"; 1403 1404 #phy-cells = <0>; 1405 }; 1406 1407 p2u_nvhs_3: phy@3ee0000 { 1408 compatible = "nvidia,tegra194-p2u"; 1409 reg = <0x03ee0000 0x10000>; 1410 reg-names = "ctl"; 1411 1412 #phy-cells = <0>; 1413 }; 1414 1415 p2u_nvhs_4: phy@3ef0000 { 1416 compatible = "nvidia,tegra194-p2u"; 1417 reg = <0x03ef0000 0x10000>; 1418 reg-names = "ctl"; 1419 1420 #phy-cells = <0>; 1421 }; 1422 1423 p2u_nvhs_5: phy@3f00000 { 1424 compatible = "nvidia,tegra194-p2u"; 1425 reg = <0x03f00000 0x10000>; 1426 reg-names = "ctl"; 1427 1428 #phy-cells = <0>; 1429 }; 1430 1431 p2u_nvhs_6: phy@3f10000 { 1432 compatible = "nvidia,tegra194-p2u"; 1433 reg = <0x03f10000 0x10000>; 1434 reg-names = "ctl"; 1435 1436 #phy-cells = <0>; 1437 }; 1438 1439 p2u_nvhs_7: phy@3f20000 { 1440 compatible = "nvidia,tegra194-p2u"; 1441 reg = <0x03f20000 0x10000>; 1442 reg-names = "ctl"; 1443 1444 #phy-cells = <0>; 1445 }; 1446 1447 p2u_hsio_10: phy@3f30000 { 1448 compatible = "nvidia,tegra194-p2u"; 1449 reg = <0x03f30000 0x10000>; 1450 reg-names = "ctl"; 1451 1452 #phy-cells = <0>; 1453 }; 1454 1455 p2u_hsio_11: phy@3f40000 { 1456 compatible = "nvidia,tegra194-p2u"; 1457 reg = <0x03f40000 0x10000>; 1458 reg-names = "ctl"; 1459 1460 #phy-cells = <0>; 1461 }; 1462 1463 hsp_aon: hsp@c150000 { 1464 compatible = "nvidia,tegra194-hsp"; 1465 reg = <0x0c150000 0x90000>; 1466 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1470 /* 1471 * Shared interrupt 0 is routed only to AON/SPE, so 1472 * we only have 4 shared interrupts for the CCPLEX. 1473 */ 1474 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1475 #mbox-cells = <2>; 1476 }; 1477 1478 gen2_i2c: i2c@c240000 { 1479 compatible = "nvidia,tegra194-i2c"; 1480 reg = <0x0c240000 0x10000>; 1481 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1485 clock-names = "div-clk"; 1486 resets = <&bpmp TEGRA194_RESET_I2C2>; 1487 reset-names = "i2c"; 1488 status = "disabled"; 1489 }; 1490 1491 gen8_i2c: i2c@c250000 { 1492 compatible = "nvidia,tegra194-i2c"; 1493 reg = <0x0c250000 0x10000>; 1494 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1498 clock-names = "div-clk"; 1499 resets = <&bpmp TEGRA194_RESET_I2C8>; 1500 reset-names = "i2c"; 1501 status = "disabled"; 1502 }; 1503 1504 uartc: serial@c280000 { 1505 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1506 reg = <0x0c280000 0x40>; 1507 reg-shift = <2>; 1508 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1509 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1510 clock-names = "serial"; 1511 resets = <&bpmp TEGRA194_RESET_UARTC>; 1512 reset-names = "serial"; 1513 status = "disabled"; 1514 }; 1515 1516 uartg: serial@c290000 { 1517 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1518 reg = <0x0c290000 0x40>; 1519 reg-shift = <2>; 1520 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1522 clock-names = "serial"; 1523 resets = <&bpmp TEGRA194_RESET_UARTG>; 1524 reset-names = "serial"; 1525 status = "disabled"; 1526 }; 1527 1528 rtc: rtc@c2a0000 { 1529 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1530 reg = <0x0c2a0000 0x10000>; 1531 interrupt-parent = <&pmc>; 1532 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1534 clock-names = "rtc"; 1535 status = "disabled"; 1536 }; 1537 1538 gpio_aon: gpio@c2f0000 { 1539 compatible = "nvidia,tegra194-gpio-aon"; 1540 reg-names = "security", "gpio"; 1541 reg = <0xc2f0000 0x1000>, 1542 <0xc2f1000 0x1000>; 1543 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1547 gpio-controller; 1548 #gpio-cells = <2>; 1549 interrupt-controller; 1550 #interrupt-cells = <2>; 1551 }; 1552 1553 pwm4: pwm@c340000 { 1554 compatible = "nvidia,tegra194-pwm", 1555 "nvidia,tegra186-pwm"; 1556 reg = <0xc340000 0x10000>; 1557 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1558 clock-names = "pwm"; 1559 resets = <&bpmp TEGRA194_RESET_PWM4>; 1560 reset-names = "pwm"; 1561 status = "disabled"; 1562 #pwm-cells = <2>; 1563 }; 1564 1565 pmc: pmc@c360000 { 1566 compatible = "nvidia,tegra194-pmc"; 1567 reg = <0x0c360000 0x10000>, 1568 <0x0c370000 0x10000>, 1569 <0x0c380000 0x10000>, 1570 <0x0c390000 0x10000>, 1571 <0x0c3a0000 0x10000>; 1572 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1573 1574 #interrupt-cells = <2>; 1575 interrupt-controller; 1576 sdmmc1_3v3: sdmmc1-3v3 { 1577 pins = "sdmmc1-hv"; 1578 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1579 }; 1580 1581 sdmmc1_1v8: sdmmc1-1v8 { 1582 pins = "sdmmc1-hv"; 1583 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1584 }; 1585 sdmmc3_3v3: sdmmc3-3v3 { 1586 pins = "sdmmc3-hv"; 1587 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1588 }; 1589 1590 sdmmc3_1v8: sdmmc3-1v8 { 1591 pins = "sdmmc3-hv"; 1592 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1593 }; 1594 1595 }; 1596 1597 iommu@10000000 { 1598 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1599 reg = <0x10000000 0x800000>; 1600 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1665 stream-match-mask = <0x7f80>; 1666 #global-interrupts = <1>; 1667 #iommu-cells = <1>; 1668 1669 nvidia,memory-controller = <&mc>; 1670 status = "disabled"; 1671 }; 1672 1673 smmu: iommu@12000000 { 1674 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1675 reg = <0x12000000 0x800000>, 1676 <0x11000000 0x800000>; 1677 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1743 stream-match-mask = <0x7f80>; 1744 #global-interrupts = <2>; 1745 #iommu-cells = <1>; 1746 1747 nvidia,memory-controller = <&mc>; 1748 status = "okay"; 1749 }; 1750 1751 host1x@13e00000 { 1752 compatible = "nvidia,tegra194-host1x"; 1753 reg = <0x13e00000 0x10000>, 1754 <0x13e10000 0x10000>; 1755 reg-names = "hypervisor", "vm"; 1756 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1758 interrupt-names = "syncpt", "host1x"; 1759 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1760 clock-names = "host1x"; 1761 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1762 reset-names = "host1x"; 1763 1764 #address-cells = <1>; 1765 #size-cells = <1>; 1766 1767 ranges = <0x15000000 0x15000000 0x01000000>; 1768 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1769 interconnect-names = "dma-mem"; 1770 iommus = <&smmu TEGRA194_SID_HOST1X>; 1771 1772 nvdec@15140000 { 1773 compatible = "nvidia,tegra194-nvdec"; 1774 reg = <0x15140000 0x00040000>; 1775 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1776 clock-names = "nvdec"; 1777 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1778 reset-names = "nvdec"; 1779 1780 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1781 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1782 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1783 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1784 interconnect-names = "dma-mem", "read-1", "write"; 1785 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1786 dma-coherent; 1787 1788 nvidia,host1x-class = <0xf5>; 1789 }; 1790 1791 display-hub@15200000 { 1792 compatible = "nvidia,tegra194-display"; 1793 reg = <0x15200000 0x00040000>; 1794 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1795 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1796 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1797 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1798 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1799 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1800 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1801 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1802 "wgrp3", "wgrp4", "wgrp5"; 1803 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1804 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1805 clock-names = "disp", "hub"; 1806 status = "disabled"; 1807 1808 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1809 1810 #address-cells = <1>; 1811 #size-cells = <1>; 1812 1813 ranges = <0x15200000 0x15200000 0x40000>; 1814 1815 display@15200000 { 1816 compatible = "nvidia,tegra194-dc"; 1817 reg = <0x15200000 0x10000>; 1818 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1820 clock-names = "dc"; 1821 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1822 reset-names = "dc"; 1823 1824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1825 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1826 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1827 interconnect-names = "dma-mem", "read-1"; 1828 1829 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1830 nvidia,head = <0>; 1831 }; 1832 1833 display@15210000 { 1834 compatible = "nvidia,tegra194-dc"; 1835 reg = <0x15210000 0x10000>; 1836 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1837 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1838 clock-names = "dc"; 1839 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1840 reset-names = "dc"; 1841 1842 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1843 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1844 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1845 interconnect-names = "dma-mem", "read-1"; 1846 1847 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1848 nvidia,head = <1>; 1849 }; 1850 1851 display@15220000 { 1852 compatible = "nvidia,tegra194-dc"; 1853 reg = <0x15220000 0x10000>; 1854 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1855 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1856 clock-names = "dc"; 1857 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1858 reset-names = "dc"; 1859 1860 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1861 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1862 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1863 interconnect-names = "dma-mem", "read-1"; 1864 1865 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1866 nvidia,head = <2>; 1867 }; 1868 1869 display@15230000 { 1870 compatible = "nvidia,tegra194-dc"; 1871 reg = <0x15230000 0x10000>; 1872 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1873 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1874 clock-names = "dc"; 1875 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1876 reset-names = "dc"; 1877 1878 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1879 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1880 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1881 interconnect-names = "dma-mem", "read-1"; 1882 1883 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1884 nvidia,head = <3>; 1885 }; 1886 }; 1887 1888 vic@15340000 { 1889 compatible = "nvidia,tegra194-vic"; 1890 reg = <0x15340000 0x00040000>; 1891 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1892 clocks = <&bpmp TEGRA194_CLK_VIC>; 1893 clock-names = "vic"; 1894 resets = <&bpmp TEGRA194_RESET_VIC>; 1895 reset-names = "vic"; 1896 1897 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1898 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1899 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1900 interconnect-names = "dma-mem", "write"; 1901 iommus = <&smmu TEGRA194_SID_VIC>; 1902 dma-coherent; 1903 }; 1904 1905 nvjpg@15380000 { 1906 compatible = "nvidia,tegra194-nvjpg"; 1907 reg = <0x15380000 0x40000>; 1908 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1909 clock-names = "nvjpg"; 1910 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1911 reset-names = "nvjpg"; 1912 1913 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1914 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1915 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1916 interconnect-names = "dma-mem", "write"; 1917 iommus = <&smmu TEGRA194_SID_NVJPG>; 1918 dma-coherent; 1919 }; 1920 1921 nvdec@15480000 { 1922 compatible = "nvidia,tegra194-nvdec"; 1923 reg = <0x15480000 0x00040000>; 1924 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1925 clock-names = "nvdec"; 1926 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1927 reset-names = "nvdec"; 1928 1929 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1930 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1931 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1932 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1933 interconnect-names = "dma-mem", "read-1", "write"; 1934 iommus = <&smmu TEGRA194_SID_NVDEC>; 1935 dma-coherent; 1936 1937 nvidia,host1x-class = <0xf0>; 1938 }; 1939 1940 nvenc@154c0000 { 1941 compatible = "nvidia,tegra194-nvenc"; 1942 reg = <0x154c0000 0x40000>; 1943 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1944 clock-names = "nvenc"; 1945 resets = <&bpmp TEGRA194_RESET_NVENC>; 1946 reset-names = "nvenc"; 1947 1948 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1949 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1950 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1951 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1952 interconnect-names = "dma-mem", "read-1", "write"; 1953 iommus = <&smmu TEGRA194_SID_NVENC>; 1954 dma-coherent; 1955 1956 nvidia,host1x-class = <0x21>; 1957 }; 1958 1959 dpaux0: dpaux@155c0000 { 1960 compatible = "nvidia,tegra194-dpaux"; 1961 reg = <0x155c0000 0x10000>; 1962 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1963 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1964 <&bpmp TEGRA194_CLK_PLLDP>; 1965 clock-names = "dpaux", "parent"; 1966 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1967 reset-names = "dpaux"; 1968 status = "disabled"; 1969 1970 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1971 1972 state_dpaux0_aux: pinmux-aux { 1973 groups = "dpaux-io"; 1974 function = "aux"; 1975 }; 1976 1977 state_dpaux0_i2c: pinmux-i2c { 1978 groups = "dpaux-io"; 1979 function = "i2c"; 1980 }; 1981 1982 state_dpaux0_off: pinmux-off { 1983 groups = "dpaux-io"; 1984 function = "off"; 1985 }; 1986 1987 i2c-bus { 1988 #address-cells = <1>; 1989 #size-cells = <0>; 1990 }; 1991 }; 1992 1993 dpaux1: dpaux@155d0000 { 1994 compatible = "nvidia,tegra194-dpaux"; 1995 reg = <0x155d0000 0x10000>; 1996 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1997 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1998 <&bpmp TEGRA194_CLK_PLLDP>; 1999 clock-names = "dpaux", "parent"; 2000 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2001 reset-names = "dpaux"; 2002 status = "disabled"; 2003 2004 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2005 2006 state_dpaux1_aux: pinmux-aux { 2007 groups = "dpaux-io"; 2008 function = "aux"; 2009 }; 2010 2011 state_dpaux1_i2c: pinmux-i2c { 2012 groups = "dpaux-io"; 2013 function = "i2c"; 2014 }; 2015 2016 state_dpaux1_off: pinmux-off { 2017 groups = "dpaux-io"; 2018 function = "off"; 2019 }; 2020 2021 i2c-bus { 2022 #address-cells = <1>; 2023 #size-cells = <0>; 2024 }; 2025 }; 2026 2027 dpaux2: dpaux@155e0000 { 2028 compatible = "nvidia,tegra194-dpaux"; 2029 reg = <0x155e0000 0x10000>; 2030 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2031 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2032 <&bpmp TEGRA194_CLK_PLLDP>; 2033 clock-names = "dpaux", "parent"; 2034 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2035 reset-names = "dpaux"; 2036 status = "disabled"; 2037 2038 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2039 2040 state_dpaux2_aux: pinmux-aux { 2041 groups = "dpaux-io"; 2042 function = "aux"; 2043 }; 2044 2045 state_dpaux2_i2c: pinmux-i2c { 2046 groups = "dpaux-io"; 2047 function = "i2c"; 2048 }; 2049 2050 state_dpaux2_off: pinmux-off { 2051 groups = "dpaux-io"; 2052 function = "off"; 2053 }; 2054 2055 i2c-bus { 2056 #address-cells = <1>; 2057 #size-cells = <0>; 2058 }; 2059 }; 2060 2061 dpaux3: dpaux@155f0000 { 2062 compatible = "nvidia,tegra194-dpaux"; 2063 reg = <0x155f0000 0x10000>; 2064 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2065 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2066 <&bpmp TEGRA194_CLK_PLLDP>; 2067 clock-names = "dpaux", "parent"; 2068 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2069 reset-names = "dpaux"; 2070 status = "disabled"; 2071 2072 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2073 2074 state_dpaux3_aux: pinmux-aux { 2075 groups = "dpaux-io"; 2076 function = "aux"; 2077 }; 2078 2079 state_dpaux3_i2c: pinmux-i2c { 2080 groups = "dpaux-io"; 2081 function = "i2c"; 2082 }; 2083 2084 state_dpaux3_off: pinmux-off { 2085 groups = "dpaux-io"; 2086 function = "off"; 2087 }; 2088 2089 i2c-bus { 2090 #address-cells = <1>; 2091 #size-cells = <0>; 2092 }; 2093 }; 2094 2095 nvenc@15a80000 { 2096 compatible = "nvidia,tegra194-nvenc"; 2097 reg = <0x15a80000 0x00040000>; 2098 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2099 clock-names = "nvenc"; 2100 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2101 reset-names = "nvenc"; 2102 2103 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2104 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2105 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2106 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2107 interconnect-names = "dma-mem", "read-1", "write"; 2108 iommus = <&smmu TEGRA194_SID_NVENC1>; 2109 dma-coherent; 2110 2111 nvidia,host1x-class = <0x22>; 2112 }; 2113 2114 sor0: sor@15b00000 { 2115 compatible = "nvidia,tegra194-sor"; 2116 reg = <0x15b00000 0x40000>; 2117 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2118 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2119 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2120 <&bpmp TEGRA194_CLK_PLLD>, 2121 <&bpmp TEGRA194_CLK_PLLDP>, 2122 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2123 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2124 clock-names = "sor", "out", "parent", "dp", "safe", 2125 "pad"; 2126 resets = <&bpmp TEGRA194_RESET_SOR0>; 2127 reset-names = "sor"; 2128 pinctrl-0 = <&state_dpaux0_aux>; 2129 pinctrl-1 = <&state_dpaux0_i2c>; 2130 pinctrl-2 = <&state_dpaux0_off>; 2131 pinctrl-names = "aux", "i2c", "off"; 2132 status = "disabled"; 2133 2134 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2135 nvidia,interface = <0>; 2136 }; 2137 2138 sor1: sor@15b40000 { 2139 compatible = "nvidia,tegra194-sor"; 2140 reg = <0x15b40000 0x40000>; 2141 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2142 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2143 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2144 <&bpmp TEGRA194_CLK_PLLD2>, 2145 <&bpmp TEGRA194_CLK_PLLDP>, 2146 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2147 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2148 clock-names = "sor", "out", "parent", "dp", "safe", 2149 "pad"; 2150 resets = <&bpmp TEGRA194_RESET_SOR1>; 2151 reset-names = "sor"; 2152 pinctrl-0 = <&state_dpaux1_aux>; 2153 pinctrl-1 = <&state_dpaux1_i2c>; 2154 pinctrl-2 = <&state_dpaux1_off>; 2155 pinctrl-names = "aux", "i2c", "off"; 2156 status = "disabled"; 2157 2158 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2159 nvidia,interface = <1>; 2160 }; 2161 2162 sor2: sor@15b80000 { 2163 compatible = "nvidia,tegra194-sor"; 2164 reg = <0x15b80000 0x40000>; 2165 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2166 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2167 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2168 <&bpmp TEGRA194_CLK_PLLD3>, 2169 <&bpmp TEGRA194_CLK_PLLDP>, 2170 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2171 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2172 clock-names = "sor", "out", "parent", "dp", "safe", 2173 "pad"; 2174 resets = <&bpmp TEGRA194_RESET_SOR2>; 2175 reset-names = "sor"; 2176 pinctrl-0 = <&state_dpaux2_aux>; 2177 pinctrl-1 = <&state_dpaux2_i2c>; 2178 pinctrl-2 = <&state_dpaux2_off>; 2179 pinctrl-names = "aux", "i2c", "off"; 2180 status = "disabled"; 2181 2182 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2183 nvidia,interface = <2>; 2184 }; 2185 2186 sor3: sor@15bc0000 { 2187 compatible = "nvidia,tegra194-sor"; 2188 reg = <0x15bc0000 0x40000>; 2189 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2190 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2191 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2192 <&bpmp TEGRA194_CLK_PLLD4>, 2193 <&bpmp TEGRA194_CLK_PLLDP>, 2194 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2195 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2196 clock-names = "sor", "out", "parent", "dp", "safe", 2197 "pad"; 2198 resets = <&bpmp TEGRA194_RESET_SOR3>; 2199 reset-names = "sor"; 2200 pinctrl-0 = <&state_dpaux3_aux>; 2201 pinctrl-1 = <&state_dpaux3_i2c>; 2202 pinctrl-2 = <&state_dpaux3_off>; 2203 pinctrl-names = "aux", "i2c", "off"; 2204 status = "disabled"; 2205 2206 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2207 nvidia,interface = <3>; 2208 }; 2209 }; 2210 2211 gpu@17000000 { 2212 compatible = "nvidia,gv11b"; 2213 reg = <0x17000000 0x1000000>, 2214 <0x18000000 0x1000000>; 2215 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2217 interrupt-names = "stall", "nonstall"; 2218 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2219 <&bpmp TEGRA194_CLK_GPU_PWR>, 2220 <&bpmp TEGRA194_CLK_FUSE>; 2221 clock-names = "gpu", "pwr", "fuse"; 2222 resets = <&bpmp TEGRA194_RESET_GPU>; 2223 reset-names = "gpu"; 2224 dma-coherent; 2225 2226 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2227 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2228 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2229 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2230 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2231 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2232 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2233 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2234 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2235 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2236 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2237 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2238 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2239 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2240 "read-1", "read-1-hp", "write-1", 2241 "read-2", "read-2-hp", "write-2", 2242 "read-3", "read-3-hp", "write-3"; 2243 }; 2244 }; 2245 2246 pcie@14100000 { 2247 compatible = "nvidia,tegra194-pcie"; 2248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2249 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2250 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2251 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2252 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2253 reg-names = "appl", "config", "atu_dma", "dbi"; 2254 2255 status = "disabled"; 2256 2257 #address-cells = <3>; 2258 #size-cells = <2>; 2259 device_type = "pci"; 2260 num-lanes = <1>; 2261 linux,pci-domain = <1>; 2262 2263 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2264 clock-names = "core"; 2265 2266 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2267 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2268 reset-names = "apb", "core"; 2269 2270 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2271 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2272 interrupt-names = "intr", "msi"; 2273 2274 #interrupt-cells = <1>; 2275 interrupt-map-mask = <0 0 0 0>; 2276 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2277 2278 nvidia,bpmp = <&bpmp 1>; 2279 2280 nvidia,aspm-cmrt-us = <60>; 2281 nvidia,aspm-pwr-on-t-us = <20>; 2282 nvidia,aspm-l0s-entrance-latency-us = <3>; 2283 2284 bus-range = <0x0 0xff>; 2285 2286 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2287 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2288 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2289 2290 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2291 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2292 interconnect-names = "dma-mem", "write"; 2293 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2294 iommu-map-mask = <0x0>; 2295 dma-coherent; 2296 }; 2297 2298 pcie@14120000 { 2299 compatible = "nvidia,tegra194-pcie"; 2300 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2301 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2302 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2303 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2304 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2305 reg-names = "appl", "config", "atu_dma", "dbi"; 2306 2307 status = "disabled"; 2308 2309 #address-cells = <3>; 2310 #size-cells = <2>; 2311 device_type = "pci"; 2312 num-lanes = <1>; 2313 linux,pci-domain = <2>; 2314 2315 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2316 clock-names = "core"; 2317 2318 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2319 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2320 reset-names = "apb", "core"; 2321 2322 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2323 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2324 interrupt-names = "intr", "msi"; 2325 2326 #interrupt-cells = <1>; 2327 interrupt-map-mask = <0 0 0 0>; 2328 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2329 2330 nvidia,bpmp = <&bpmp 2>; 2331 2332 nvidia,aspm-cmrt-us = <60>; 2333 nvidia,aspm-pwr-on-t-us = <20>; 2334 nvidia,aspm-l0s-entrance-latency-us = <3>; 2335 2336 bus-range = <0x0 0xff>; 2337 2338 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2339 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2340 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2341 2342 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2343 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2344 interconnect-names = "dma-mem", "write"; 2345 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2346 iommu-map-mask = <0x0>; 2347 dma-coherent; 2348 }; 2349 2350 pcie@14140000 { 2351 compatible = "nvidia,tegra194-pcie"; 2352 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2353 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2354 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2355 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2356 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2357 reg-names = "appl", "config", "atu_dma", "dbi"; 2358 2359 status = "disabled"; 2360 2361 #address-cells = <3>; 2362 #size-cells = <2>; 2363 device_type = "pci"; 2364 num-lanes = <1>; 2365 linux,pci-domain = <3>; 2366 2367 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2368 clock-names = "core"; 2369 2370 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2371 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2372 reset-names = "apb", "core"; 2373 2374 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2375 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2376 interrupt-names = "intr", "msi"; 2377 2378 #interrupt-cells = <1>; 2379 interrupt-map-mask = <0 0 0 0>; 2380 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2381 2382 nvidia,bpmp = <&bpmp 3>; 2383 2384 nvidia,aspm-cmrt-us = <60>; 2385 nvidia,aspm-pwr-on-t-us = <20>; 2386 nvidia,aspm-l0s-entrance-latency-us = <3>; 2387 2388 bus-range = <0x0 0xff>; 2389 2390 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2391 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2392 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2393 2394 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2395 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2396 interconnect-names = "dma-mem", "write"; 2397 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2398 iommu-map-mask = <0x0>; 2399 dma-coherent; 2400 }; 2401 2402 pcie@14160000 { 2403 compatible = "nvidia,tegra194-pcie"; 2404 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2405 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2406 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2407 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2408 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2409 reg-names = "appl", "config", "atu_dma", "dbi"; 2410 2411 status = "disabled"; 2412 2413 #address-cells = <3>; 2414 #size-cells = <2>; 2415 device_type = "pci"; 2416 num-lanes = <4>; 2417 linux,pci-domain = <4>; 2418 2419 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2420 clock-names = "core"; 2421 2422 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2423 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2424 reset-names = "apb", "core"; 2425 2426 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2427 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2428 interrupt-names = "intr", "msi"; 2429 2430 #interrupt-cells = <1>; 2431 interrupt-map-mask = <0 0 0 0>; 2432 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2433 2434 nvidia,bpmp = <&bpmp 4>; 2435 2436 nvidia,aspm-cmrt-us = <60>; 2437 nvidia,aspm-pwr-on-t-us = <20>; 2438 nvidia,aspm-l0s-entrance-latency-us = <3>; 2439 2440 bus-range = <0x0 0xff>; 2441 2442 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2443 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2444 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2445 2446 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2447 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2448 interconnect-names = "dma-mem", "write"; 2449 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2450 iommu-map-mask = <0x0>; 2451 dma-coherent; 2452 }; 2453 2454 pcie@14180000 { 2455 compatible = "nvidia,tegra194-pcie"; 2456 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2457 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2458 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2459 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2460 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2461 reg-names = "appl", "config", "atu_dma", "dbi"; 2462 2463 status = "disabled"; 2464 2465 #address-cells = <3>; 2466 #size-cells = <2>; 2467 device_type = "pci"; 2468 num-lanes = <8>; 2469 linux,pci-domain = <0>; 2470 2471 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2472 clock-names = "core"; 2473 2474 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2475 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2476 reset-names = "apb", "core"; 2477 2478 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2479 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2480 interrupt-names = "intr", "msi"; 2481 2482 #interrupt-cells = <1>; 2483 interrupt-map-mask = <0 0 0 0>; 2484 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2485 2486 nvidia,bpmp = <&bpmp 0>; 2487 2488 nvidia,aspm-cmrt-us = <60>; 2489 nvidia,aspm-pwr-on-t-us = <20>; 2490 nvidia,aspm-l0s-entrance-latency-us = <3>; 2491 2492 bus-range = <0x0 0xff>; 2493 2494 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2495 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2496 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2497 2498 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2499 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2500 interconnect-names = "dma-mem", "write"; 2501 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2502 iommu-map-mask = <0x0>; 2503 dma-coherent; 2504 }; 2505 2506 pcie@141a0000 { 2507 compatible = "nvidia,tegra194-pcie"; 2508 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2509 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2510 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2511 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2512 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2513 reg-names = "appl", "config", "atu_dma", "dbi"; 2514 2515 status = "disabled"; 2516 2517 #address-cells = <3>; 2518 #size-cells = <2>; 2519 device_type = "pci"; 2520 num-lanes = <8>; 2521 linux,pci-domain = <5>; 2522 2523 pinctrl-names = "default"; 2524 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2525 2526 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2527 clock-names = "core"; 2528 2529 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2530 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2531 reset-names = "apb", "core"; 2532 2533 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2534 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2535 interrupt-names = "intr", "msi"; 2536 2537 nvidia,bpmp = <&bpmp 5>; 2538 2539 #interrupt-cells = <1>; 2540 interrupt-map-mask = <0 0 0 0>; 2541 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2542 2543 nvidia,aspm-cmrt-us = <60>; 2544 nvidia,aspm-pwr-on-t-us = <20>; 2545 nvidia,aspm-l0s-entrance-latency-us = <3>; 2546 2547 bus-range = <0x0 0xff>; 2548 2549 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2550 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2551 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2552 2553 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2554 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2555 interconnect-names = "dma-mem", "write"; 2556 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2557 iommu-map-mask = <0x0>; 2558 dma-coherent; 2559 }; 2560 2561 pcie-ep@14160000 { 2562 compatible = "nvidia,tegra194-pcie-ep"; 2563 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2564 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2565 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2566 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2567 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2568 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2569 2570 status = "disabled"; 2571 2572 num-lanes = <4>; 2573 num-ib-windows = <2>; 2574 num-ob-windows = <8>; 2575 2576 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2577 clock-names = "core"; 2578 2579 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2580 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2581 reset-names = "apb", "core"; 2582 2583 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2584 interrupt-names = "intr"; 2585 2586 nvidia,bpmp = <&bpmp 4>; 2587 2588 nvidia,aspm-cmrt-us = <60>; 2589 nvidia,aspm-pwr-on-t-us = <20>; 2590 nvidia,aspm-l0s-entrance-latency-us = <3>; 2591 2592 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2593 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2594 interconnect-names = "dma-mem", "write"; 2595 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2596 iommu-map-mask = <0x0>; 2597 dma-coherent; 2598 }; 2599 2600 pcie-ep@14180000 { 2601 compatible = "nvidia,tegra194-pcie-ep"; 2602 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2603 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2604 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2605 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2606 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2607 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2608 2609 status = "disabled"; 2610 2611 num-lanes = <8>; 2612 num-ib-windows = <2>; 2613 num-ob-windows = <8>; 2614 2615 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2616 clock-names = "core"; 2617 2618 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2619 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2620 reset-names = "apb", "core"; 2621 2622 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2623 interrupt-names = "intr"; 2624 2625 nvidia,bpmp = <&bpmp 0>; 2626 2627 nvidia,aspm-cmrt-us = <60>; 2628 nvidia,aspm-pwr-on-t-us = <20>; 2629 nvidia,aspm-l0s-entrance-latency-us = <3>; 2630 2631 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2632 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2633 interconnect-names = "dma-mem", "write"; 2634 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2635 iommu-map-mask = <0x0>; 2636 dma-coherent; 2637 }; 2638 2639 pcie-ep@141a0000 { 2640 compatible = "nvidia,tegra194-pcie-ep"; 2641 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2642 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2643 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2644 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2645 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2646 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2647 2648 status = "disabled"; 2649 2650 num-lanes = <8>; 2651 num-ib-windows = <2>; 2652 num-ob-windows = <8>; 2653 2654 pinctrl-names = "default"; 2655 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2656 2657 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2658 clock-names = "core"; 2659 2660 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2661 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2662 reset-names = "apb", "core"; 2663 2664 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2665 interrupt-names = "intr"; 2666 2667 nvidia,bpmp = <&bpmp 5>; 2668 2669 nvidia,aspm-cmrt-us = <60>; 2670 nvidia,aspm-pwr-on-t-us = <20>; 2671 nvidia,aspm-l0s-entrance-latency-us = <3>; 2672 2673 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2674 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2675 interconnect-names = "dma-mem", "write"; 2676 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2677 iommu-map-mask = <0x0>; 2678 dma-coherent; 2679 }; 2680 2681 sram@40000000 { 2682 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2683 reg = <0x0 0x40000000 0x0 0x50000>; 2684 #address-cells = <1>; 2685 #size-cells = <1>; 2686 ranges = <0x0 0x0 0x40000000 0x50000>; 2687 2688 cpu_bpmp_tx: sram@4e000 { 2689 reg = <0x4e000 0x1000>; 2690 label = "cpu-bpmp-tx"; 2691 pool; 2692 }; 2693 2694 cpu_bpmp_rx: sram@4f000 { 2695 reg = <0x4f000 0x1000>; 2696 label = "cpu-bpmp-rx"; 2697 pool; 2698 }; 2699 }; 2700 2701 bpmp: bpmp { 2702 compatible = "nvidia,tegra186-bpmp"; 2703 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2704 TEGRA_HSP_DB_MASTER_BPMP>; 2705 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2706 #clock-cells = <1>; 2707 #reset-cells = <1>; 2708 #power-domain-cells = <1>; 2709 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2710 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2711 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2712 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2713 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2714 iommus = <&smmu TEGRA194_SID_BPMP>; 2715 2716 bpmp_i2c: i2c { 2717 compatible = "nvidia,tegra186-bpmp-i2c"; 2718 nvidia,bpmp-bus-id = <5>; 2719 #address-cells = <1>; 2720 #size-cells = <0>; 2721 }; 2722 2723 bpmp_thermal: thermal { 2724 compatible = "nvidia,tegra186-bpmp-thermal"; 2725 #thermal-sensor-cells = <1>; 2726 }; 2727 }; 2728 2729 cpus { 2730 compatible = "nvidia,tegra194-ccplex"; 2731 nvidia,bpmp = <&bpmp>; 2732 #address-cells = <1>; 2733 #size-cells = <0>; 2734 2735 cpu0_0: cpu@0 { 2736 compatible = "nvidia,tegra194-carmel"; 2737 device_type = "cpu"; 2738 reg = <0x000>; 2739 enable-method = "psci"; 2740 i-cache-size = <131072>; 2741 i-cache-line-size = <64>; 2742 i-cache-sets = <512>; 2743 d-cache-size = <65536>; 2744 d-cache-line-size = <64>; 2745 d-cache-sets = <256>; 2746 next-level-cache = <&l2c_0>; 2747 }; 2748 2749 cpu0_1: cpu@1 { 2750 compatible = "nvidia,tegra194-carmel"; 2751 device_type = "cpu"; 2752 reg = <0x001>; 2753 enable-method = "psci"; 2754 i-cache-size = <131072>; 2755 i-cache-line-size = <64>; 2756 i-cache-sets = <512>; 2757 d-cache-size = <65536>; 2758 d-cache-line-size = <64>; 2759 d-cache-sets = <256>; 2760 next-level-cache = <&l2c_0>; 2761 }; 2762 2763 cpu1_0: cpu@100 { 2764 compatible = "nvidia,tegra194-carmel"; 2765 device_type = "cpu"; 2766 reg = <0x100>; 2767 enable-method = "psci"; 2768 i-cache-size = <131072>; 2769 i-cache-line-size = <64>; 2770 i-cache-sets = <512>; 2771 d-cache-size = <65536>; 2772 d-cache-line-size = <64>; 2773 d-cache-sets = <256>; 2774 next-level-cache = <&l2c_1>; 2775 }; 2776 2777 cpu1_1: cpu@101 { 2778 compatible = "nvidia,tegra194-carmel"; 2779 device_type = "cpu"; 2780 reg = <0x101>; 2781 enable-method = "psci"; 2782 i-cache-size = <131072>; 2783 i-cache-line-size = <64>; 2784 i-cache-sets = <512>; 2785 d-cache-size = <65536>; 2786 d-cache-line-size = <64>; 2787 d-cache-sets = <256>; 2788 next-level-cache = <&l2c_1>; 2789 }; 2790 2791 cpu2_0: cpu@200 { 2792 compatible = "nvidia,tegra194-carmel"; 2793 device_type = "cpu"; 2794 reg = <0x200>; 2795 enable-method = "psci"; 2796 i-cache-size = <131072>; 2797 i-cache-line-size = <64>; 2798 i-cache-sets = <512>; 2799 d-cache-size = <65536>; 2800 d-cache-line-size = <64>; 2801 d-cache-sets = <256>; 2802 next-level-cache = <&l2c_2>; 2803 }; 2804 2805 cpu2_1: cpu@201 { 2806 compatible = "nvidia,tegra194-carmel"; 2807 device_type = "cpu"; 2808 reg = <0x201>; 2809 enable-method = "psci"; 2810 i-cache-size = <131072>; 2811 i-cache-line-size = <64>; 2812 i-cache-sets = <512>; 2813 d-cache-size = <65536>; 2814 d-cache-line-size = <64>; 2815 d-cache-sets = <256>; 2816 next-level-cache = <&l2c_2>; 2817 }; 2818 2819 cpu3_0: cpu@300 { 2820 compatible = "nvidia,tegra194-carmel"; 2821 device_type = "cpu"; 2822 reg = <0x300>; 2823 enable-method = "psci"; 2824 i-cache-size = <131072>; 2825 i-cache-line-size = <64>; 2826 i-cache-sets = <512>; 2827 d-cache-size = <65536>; 2828 d-cache-line-size = <64>; 2829 d-cache-sets = <256>; 2830 next-level-cache = <&l2c_3>; 2831 }; 2832 2833 cpu3_1: cpu@301 { 2834 compatible = "nvidia,tegra194-carmel"; 2835 device_type = "cpu"; 2836 reg = <0x301>; 2837 enable-method = "psci"; 2838 i-cache-size = <131072>; 2839 i-cache-line-size = <64>; 2840 i-cache-sets = <512>; 2841 d-cache-size = <65536>; 2842 d-cache-line-size = <64>; 2843 d-cache-sets = <256>; 2844 next-level-cache = <&l2c_3>; 2845 }; 2846 2847 cpu-map { 2848 cluster0 { 2849 core0 { 2850 cpu = <&cpu0_0>; 2851 }; 2852 2853 core1 { 2854 cpu = <&cpu0_1>; 2855 }; 2856 }; 2857 2858 cluster1 { 2859 core0 { 2860 cpu = <&cpu1_0>; 2861 }; 2862 2863 core1 { 2864 cpu = <&cpu1_1>; 2865 }; 2866 }; 2867 2868 cluster2 { 2869 core0 { 2870 cpu = <&cpu2_0>; 2871 }; 2872 2873 core1 { 2874 cpu = <&cpu2_1>; 2875 }; 2876 }; 2877 2878 cluster3 { 2879 core0 { 2880 cpu = <&cpu3_0>; 2881 }; 2882 2883 core1 { 2884 cpu = <&cpu3_1>; 2885 }; 2886 }; 2887 }; 2888 2889 l2c_0: l2-cache0 { 2890 cache-size = <2097152>; 2891 cache-line-size = <64>; 2892 cache-sets = <2048>; 2893 next-level-cache = <&l3c>; 2894 }; 2895 2896 l2c_1: l2-cache1 { 2897 cache-size = <2097152>; 2898 cache-line-size = <64>; 2899 cache-sets = <2048>; 2900 next-level-cache = <&l3c>; 2901 }; 2902 2903 l2c_2: l2-cache2 { 2904 cache-size = <2097152>; 2905 cache-line-size = <64>; 2906 cache-sets = <2048>; 2907 next-level-cache = <&l3c>; 2908 }; 2909 2910 l2c_3: l2-cache3 { 2911 cache-size = <2097152>; 2912 cache-line-size = <64>; 2913 cache-sets = <2048>; 2914 next-level-cache = <&l3c>; 2915 }; 2916 2917 l3c: l3-cache { 2918 cache-size = <4194304>; 2919 cache-line-size = <64>; 2920 cache-sets = <4096>; 2921 }; 2922 }; 2923 2924 pmu { 2925 compatible = "nvidia,carmel-pmu"; 2926 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2932 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2933 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2934 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2935 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2936 }; 2937 2938 psci { 2939 compatible = "arm,psci-1.0"; 2940 status = "okay"; 2941 method = "smc"; 2942 }; 2943 2944 sound { 2945 status = "disabled"; 2946 2947 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2948 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2949 clock-names = "pll_a", "plla_out0"; 2950 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2951 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2952 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2953 assigned-clock-parents = <0>, 2954 <&bpmp TEGRA194_CLK_PLLA>, 2955 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2956 /* 2957 * PLLA supports dynamic ramp. Below initial rate is chosen 2958 * for this to work and oscillate between base rates required 2959 * for 8x and 11.025x sample rate streams. 2960 */ 2961 assigned-clock-rates = <258000000>; 2962 }; 2963 2964 tcu: serial { 2965 compatible = "nvidia,tegra194-tcu"; 2966 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2967 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2968 mbox-names = "rx", "tx"; 2969 }; 2970 2971 thermal-zones { 2972 cpu-thermal { 2973 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2974 status = "disabled"; 2975 }; 2976 2977 gpu-thermal { 2978 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2979 status = "disabled"; 2980 }; 2981 2982 aux-thermal { 2983 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2984 status = "disabled"; 2985 }; 2986 2987 pllx-thermal { 2988 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2989 status = "disabled"; 2990 }; 2991 2992 ao-thermal { 2993 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2994 status = "disabled"; 2995 }; 2996 2997 tj-thermal { 2998 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2999 status = "disabled"; 3000 }; 3001 }; 3002 3003 timer { 3004 compatible = "arm,armv8-timer"; 3005 interrupts = <GIC_PPI 13 3006 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3007 <GIC_PPI 14 3008 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3009 <GIC_PPI 11 3010 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3011 <GIC_PPI 10 3012 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3013 interrupt-parent = <&gic>; 3014 always-on; 3015 }; 3016}; 3017