1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra.h>
7#include <dt-bindings/power/tegra194-powergate.h>
8#include <dt-bindings/reset/tegra194-reset.h>
9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10#include <dt-bindings/memory/tegra194-mc.h>
11
12/ {
13	compatible = "nvidia,tegra194";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	/* control backbone */
19	bus@0 {
20		compatible = "simple-bus";
21		#address-cells = <1>;
22		#size-cells = <1>;
23		ranges = <0x0 0x0 0x0 0x40000000>;
24
25		misc@100000 {
26			compatible = "nvidia,tegra194-misc";
27			reg = <0x00100000 0xf000>,
28			      <0x0010f000 0x1000>;
29		};
30
31		gpio: gpio@2200000 {
32			compatible = "nvidia,tegra194-gpio";
33			reg-names = "security", "gpio";
34			reg = <0x2200000 0x10000>,
35			      <0x2210000 0x10000>;
36			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
37				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
38				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
39				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
40				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
41				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
42			#interrupt-cells = <2>;
43			interrupt-controller;
44			#gpio-cells = <2>;
45			gpio-controller;
46		};
47
48		ethernet@2490000 {
49			compatible = "nvidia,tegra194-eqos",
50				     "nvidia,tegra186-eqos",
51				     "snps,dwc-qos-ethernet-4.10";
52			reg = <0x02490000 0x10000>;
53			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
54			clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
55				 <&bpmp TEGRA194_CLK_EQOS_AXI>,
56				 <&bpmp TEGRA194_CLK_EQOS_RX>,
57				 <&bpmp TEGRA194_CLK_EQOS_TX>,
58				 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
59			clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
60			resets = <&bpmp TEGRA194_RESET_EQOS>;
61			reset-names = "eqos";
62			interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
63					<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
64			interconnect-names = "dma-mem", "write";
65			iommus = <&smmu TEGRA194_SID_EQOS>;
66			status = "disabled";
67
68			snps,write-requests = <1>;
69			snps,read-requests = <3>;
70			snps,burst-map = <0x7>;
71			snps,txpbl = <16>;
72			snps,rxpbl = <8>;
73		};
74
75		aconnect@2900000 {
76			compatible = "nvidia,tegra194-aconnect",
77				     "nvidia,tegra210-aconnect";
78			clocks = <&bpmp TEGRA194_CLK_APE>,
79				 <&bpmp TEGRA194_CLK_APB2APE>;
80			clock-names = "ape", "apb2ape";
81			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
82			#address-cells = <1>;
83			#size-cells = <1>;
84			ranges = <0x02900000 0x02900000 0x200000>;
85			status = "disabled";
86
87			adma: dma-controller@2930000 {
88				compatible = "nvidia,tegra194-adma",
89					     "nvidia,tegra186-adma";
90				reg = <0x02930000 0x20000>;
91				interrupt-parent = <&agic>;
92				interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93					      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
94					      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
95					      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
96					      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97					      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
98					      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
99					      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100					      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101					      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102					      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103					      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104					      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105					      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106					      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107					      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
108					      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
109					      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
110					      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
111					      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
112					      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
113					      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
114					      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
115					      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
116					      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
117					      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
118					      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
119					      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
120					      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
121					      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
122					      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
123					      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
124				#dma-cells = <1>;
125				clocks = <&bpmp TEGRA194_CLK_AHUB>;
126				clock-names = "d_audio";
127				status = "disabled";
128			};
129
130			agic: interrupt-controller@2a40000 {
131				compatible = "nvidia,tegra194-agic",
132					     "nvidia,tegra210-agic";
133				#interrupt-cells = <3>;
134				interrupt-controller;
135				reg = <0x02a41000 0x1000>,
136				      <0x02a42000 0x2000>;
137				interrupts = <GIC_SPI 145
138					      (GIC_CPU_MASK_SIMPLE(4) |
139					       IRQ_TYPE_LEVEL_HIGH)>;
140				clocks = <&bpmp TEGRA194_CLK_APE>;
141				clock-names = "clk";
142				status = "disabled";
143			};
144
145			tegra_ahub: ahub@2900800 {
146				compatible = "nvidia,tegra194-ahub",
147					     "nvidia,tegra186-ahub";
148				reg = <0x02900800 0x800>;
149				clocks = <&bpmp TEGRA194_CLK_AHUB>;
150				clock-names = "ahub";
151				assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
152				assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
153				#address-cells = <1>;
154				#size-cells = <1>;
155				ranges = <0x02900800 0x02900800 0x11800>;
156				status = "disabled";
157
158				tegra_admaif: admaif@290f000 {
159					compatible = "nvidia,tegra194-admaif",
160						     "nvidia,tegra186-admaif";
161					reg = <0x0290f000 0x1000>;
162					dmas = <&adma 1>, <&adma 1>,
163					       <&adma 2>, <&adma 2>,
164					       <&adma 3>, <&adma 3>,
165					       <&adma 4>, <&adma 4>,
166					       <&adma 5>, <&adma 5>,
167					       <&adma 6>, <&adma 6>,
168					       <&adma 7>, <&adma 7>,
169					       <&adma 8>, <&adma 8>,
170					       <&adma 9>, <&adma 9>,
171					       <&adma 10>, <&adma 10>,
172					       <&adma 11>, <&adma 11>,
173					       <&adma 12>, <&adma 12>,
174					       <&adma 13>, <&adma 13>,
175					       <&adma 14>, <&adma 14>,
176					       <&adma 15>, <&adma 15>,
177					       <&adma 16>, <&adma 16>,
178					       <&adma 17>, <&adma 17>,
179					       <&adma 18>, <&adma 18>,
180					       <&adma 19>, <&adma 19>,
181					       <&adma 20>, <&adma 20>;
182					dma-names = "rx1", "tx1",
183						    "rx2", "tx2",
184						    "rx3", "tx3",
185						    "rx4", "tx4",
186						    "rx5", "tx5",
187						    "rx6", "tx6",
188						    "rx7", "tx7",
189						    "rx8", "tx8",
190						    "rx9", "tx9",
191						    "rx10", "tx10",
192						    "rx11", "tx11",
193						    "rx12", "tx12",
194						    "rx13", "tx13",
195						    "rx14", "tx14",
196						    "rx15", "tx15",
197						    "rx16", "tx16",
198						    "rx17", "tx17",
199						    "rx18", "tx18",
200						    "rx19", "tx19",
201						    "rx20", "tx20";
202					status = "disabled";
203				};
204
205				tegra_i2s1: i2s@2901000 {
206					compatible = "nvidia,tegra194-i2s",
207						     "nvidia,tegra210-i2s";
208					reg = <0x2901000 0x100>;
209					clocks = <&bpmp TEGRA194_CLK_I2S1>,
210						 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
211					clock-names = "i2s", "sync_input";
212					assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
213					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
214					assigned-clock-rates = <1536000>;
215					sound-name-prefix = "I2S1";
216					status = "disabled";
217				};
218
219				tegra_i2s2: i2s@2901100 {
220					compatible = "nvidia,tegra194-i2s",
221						     "nvidia,tegra210-i2s";
222					reg = <0x2901100 0x100>;
223					clocks = <&bpmp TEGRA194_CLK_I2S2>,
224						 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
225					clock-names = "i2s", "sync_input";
226					assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
227					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
228					assigned-clock-rates = <1536000>;
229					sound-name-prefix = "I2S2";
230					status = "disabled";
231				};
232
233				tegra_i2s3: i2s@2901200 {
234					compatible = "nvidia,tegra194-i2s",
235						     "nvidia,tegra210-i2s";
236					reg = <0x2901200 0x100>;
237					clocks = <&bpmp TEGRA194_CLK_I2S3>,
238						 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
239					clock-names = "i2s", "sync_input";
240					assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
241					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
242					assigned-clock-rates = <1536000>;
243					sound-name-prefix = "I2S3";
244					status = "disabled";
245				};
246
247				tegra_i2s4: i2s@2901300 {
248					compatible = "nvidia,tegra194-i2s",
249						     "nvidia,tegra210-i2s";
250					reg = <0x2901300 0x100>;
251					clocks = <&bpmp TEGRA194_CLK_I2S4>,
252						 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
253					clock-names = "i2s", "sync_input";
254					assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
255					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
256					assigned-clock-rates = <1536000>;
257					sound-name-prefix = "I2S4";
258					status = "disabled";
259				};
260
261				tegra_i2s5: i2s@2901400 {
262					compatible = "nvidia,tegra194-i2s",
263						     "nvidia,tegra210-i2s";
264					reg = <0x2901400 0x100>;
265					clocks = <&bpmp TEGRA194_CLK_I2S5>,
266						 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
267					clock-names = "i2s", "sync_input";
268					assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
269					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
270					assigned-clock-rates = <1536000>;
271					sound-name-prefix = "I2S5";
272					status = "disabled";
273				};
274
275				tegra_i2s6: i2s@2901500 {
276					compatible = "nvidia,tegra194-i2s",
277						     "nvidia,tegra210-i2s";
278					reg = <0x2901500 0x100>;
279					clocks = <&bpmp TEGRA194_CLK_I2S6>,
280						 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
281					clock-names = "i2s", "sync_input";
282					assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
283					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
284					assigned-clock-rates = <1536000>;
285					sound-name-prefix = "I2S6";
286					status = "disabled";
287				};
288
289				tegra_dmic1: dmic@2904000 {
290					compatible = "nvidia,tegra194-dmic",
291						     "nvidia,tegra210-dmic";
292					reg = <0x2904000 0x100>;
293					clocks = <&bpmp TEGRA194_CLK_DMIC1>;
294					clock-names = "dmic";
295					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
296					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
297					assigned-clock-rates = <3072000>;
298					sound-name-prefix = "DMIC1";
299					status = "disabled";
300				};
301
302				tegra_dmic2: dmic@2904100 {
303					compatible = "nvidia,tegra194-dmic",
304						     "nvidia,tegra210-dmic";
305					reg = <0x2904100 0x100>;
306					clocks = <&bpmp TEGRA194_CLK_DMIC2>;
307					clock-names = "dmic";
308					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
309					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
310					assigned-clock-rates = <3072000>;
311					sound-name-prefix = "DMIC2";
312					status = "disabled";
313				};
314
315				tegra_dmic3: dmic@2904200 {
316					compatible = "nvidia,tegra194-dmic",
317						     "nvidia,tegra210-dmic";
318					reg = <0x2904200 0x100>;
319					clocks = <&bpmp TEGRA194_CLK_DMIC3>;
320					clock-names = "dmic";
321					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
322					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
323					assigned-clock-rates = <3072000>;
324					sound-name-prefix = "DMIC3";
325					status = "disabled";
326				};
327
328				tegra_dmic4: dmic@2904300 {
329					compatible = "nvidia,tegra194-dmic",
330						     "nvidia,tegra210-dmic";
331					reg = <0x2904300 0x100>;
332					clocks = <&bpmp TEGRA194_CLK_DMIC4>;
333					clock-names = "dmic";
334					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
335					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
336					assigned-clock-rates = <3072000>;
337					sound-name-prefix = "DMIC4";
338					status = "disabled";
339				};
340
341				tegra_dspk1: dspk@2905000 {
342					compatible = "nvidia,tegra194-dspk",
343						     "nvidia,tegra186-dspk";
344					reg = <0x2905000 0x100>;
345					clocks = <&bpmp TEGRA194_CLK_DSPK1>;
346					clock-names = "dspk";
347					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
348					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
349					assigned-clock-rates = <12288000>;
350					sound-name-prefix = "DSPK1";
351					status = "disabled";
352				};
353
354				tegra_dspk2: dspk@2905100 {
355					compatible = "nvidia,tegra194-dspk",
356						     "nvidia,tegra186-dspk";
357					reg = <0x2905100 0x100>;
358					clocks = <&bpmp TEGRA194_CLK_DSPK2>;
359					clock-names = "dspk";
360					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
361					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
362					assigned-clock-rates = <12288000>;
363					sound-name-prefix = "DSPK2";
364					status = "disabled";
365				};
366			};
367		};
368
369		pinmux: pinmux@2430000 {
370			compatible = "nvidia,tegra194-pinmux";
371			reg = <0x2430000 0x17000>,
372			      <0xc300000 0x4000>;
373
374			status = "okay";
375
376			pex_rst_c5_out_state: pex_rst_c5_out {
377				pex_rst {
378					nvidia,pins = "pex_l5_rst_n_pgg1";
379					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
380					nvidia,lpdr = <TEGRA_PIN_ENABLE>;
381					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382					nvidia,io-hv = <TEGRA_PIN_ENABLE>;
383					nvidia,tristate = <TEGRA_PIN_DISABLE>;
384					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385				};
386			};
387
388			clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
389				clkreq {
390					nvidia,pins = "pex_l5_clkreq_n_pgg0";
391					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
392					nvidia,lpdr = <TEGRA_PIN_ENABLE>;
393					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
394					nvidia,io-hv = <TEGRA_PIN_ENABLE>;
395					nvidia,tristate = <TEGRA_PIN_DISABLE>;
396					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
397				};
398			};
399		};
400
401		mc: memory-controller@2c00000 {
402			compatible = "nvidia,tegra194-mc";
403			reg = <0x02c00000 0x100000>,
404			      <0x02b80000 0x040000>,
405			      <0x01700000 0x100000>;
406			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
407			#interconnect-cells = <1>;
408			status = "disabled";
409
410			#address-cells = <2>;
411			#size-cells = <2>;
412
413			ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
414				 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
415				 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
416
417			/*
418			 * Bit 39 of addresses passing through the memory
419			 * controller selects the XBAR format used when memory
420			 * is accessed. This is used to transparently access
421			 * memory in the XBAR format used by the discrete GPU
422			 * (bit 39 set) or Tegra (bit 39 clear).
423			 *
424			 * As a consequence, the operating system must ensure
425			 * that bit 39 is never used implicitly, for example
426			 * via an I/O virtual address mapping of an IOMMU. If
427			 * devices require access to the XBAR switch, their
428			 * drivers must set this bit explicitly.
429			 *
430			 * Limit the DMA range for memory clients to [38:0].
431			 */
432			dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
433
434			emc: external-memory-controller@2c60000 {
435				compatible = "nvidia,tegra194-emc";
436				reg = <0x0 0x02c60000 0x0 0x90000>,
437				      <0x0 0x01780000 0x0 0x80000>;
438				clocks = <&bpmp TEGRA194_CLK_EMC>;
439				clock-names = "emc";
440
441				#interconnect-cells = <0>;
442
443				nvidia,bpmp = <&bpmp>;
444			};
445		};
446
447		uarta: serial@3100000 {
448			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
449			reg = <0x03100000 0x40>;
450			reg-shift = <2>;
451			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
452			clocks = <&bpmp TEGRA194_CLK_UARTA>;
453			clock-names = "serial";
454			resets = <&bpmp TEGRA194_RESET_UARTA>;
455			reset-names = "serial";
456			status = "disabled";
457		};
458
459		uartb: serial@3110000 {
460			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
461			reg = <0x03110000 0x40>;
462			reg-shift = <2>;
463			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
464			clocks = <&bpmp TEGRA194_CLK_UARTB>;
465			clock-names = "serial";
466			resets = <&bpmp TEGRA194_RESET_UARTB>;
467			reset-names = "serial";
468			status = "disabled";
469		};
470
471		uartd: serial@3130000 {
472			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
473			reg = <0x03130000 0x40>;
474			reg-shift = <2>;
475			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
476			clocks = <&bpmp TEGRA194_CLK_UARTD>;
477			clock-names = "serial";
478			resets = <&bpmp TEGRA194_RESET_UARTD>;
479			reset-names = "serial";
480			status = "disabled";
481		};
482
483		uarte: serial@3140000 {
484			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
485			reg = <0x03140000 0x40>;
486			reg-shift = <2>;
487			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
488			clocks = <&bpmp TEGRA194_CLK_UARTE>;
489			clock-names = "serial";
490			resets = <&bpmp TEGRA194_RESET_UARTE>;
491			reset-names = "serial";
492			status = "disabled";
493		};
494
495		uartf: serial@3150000 {
496			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
497			reg = <0x03150000 0x40>;
498			reg-shift = <2>;
499			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
500			clocks = <&bpmp TEGRA194_CLK_UARTF>;
501			clock-names = "serial";
502			resets = <&bpmp TEGRA194_RESET_UARTF>;
503			reset-names = "serial";
504			status = "disabled";
505		};
506
507		gen1_i2c: i2c@3160000 {
508			compatible = "nvidia,tegra194-i2c";
509			reg = <0x03160000 0x10000>;
510			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
511			#address-cells = <1>;
512			#size-cells = <0>;
513			clocks = <&bpmp TEGRA194_CLK_I2C1>;
514			clock-names = "div-clk";
515			resets = <&bpmp TEGRA194_RESET_I2C1>;
516			reset-names = "i2c";
517			status = "disabled";
518		};
519
520		uarth: serial@3170000 {
521			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
522			reg = <0x03170000 0x40>;
523			reg-shift = <2>;
524			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
525			clocks = <&bpmp TEGRA194_CLK_UARTH>;
526			clock-names = "serial";
527			resets = <&bpmp TEGRA194_RESET_UARTH>;
528			reset-names = "serial";
529			status = "disabled";
530		};
531
532		cam_i2c: i2c@3180000 {
533			compatible = "nvidia,tegra194-i2c";
534			reg = <0x03180000 0x10000>;
535			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
536			#address-cells = <1>;
537			#size-cells = <0>;
538			clocks = <&bpmp TEGRA194_CLK_I2C3>;
539			clock-names = "div-clk";
540			resets = <&bpmp TEGRA194_RESET_I2C3>;
541			reset-names = "i2c";
542			status = "disabled";
543		};
544
545		/* shares pads with dpaux1 */
546		dp_aux_ch1_i2c: i2c@3190000 {
547			compatible = "nvidia,tegra194-i2c";
548			reg = <0x03190000 0x10000>;
549			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
550			#address-cells = <1>;
551			#size-cells = <0>;
552			clocks = <&bpmp TEGRA194_CLK_I2C4>;
553			clock-names = "div-clk";
554			resets = <&bpmp TEGRA194_RESET_I2C4>;
555			reset-names = "i2c";
556			pinctrl-0 = <&state_dpaux1_i2c>;
557			pinctrl-1 = <&state_dpaux1_off>;
558			pinctrl-names = "default", "idle";
559			status = "disabled";
560		};
561
562		/* shares pads with dpaux0 */
563		dp_aux_ch0_i2c: i2c@31b0000 {
564			compatible = "nvidia,tegra194-i2c";
565			reg = <0x031b0000 0x10000>;
566			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
567			#address-cells = <1>;
568			#size-cells = <0>;
569			clocks = <&bpmp TEGRA194_CLK_I2C6>;
570			clock-names = "div-clk";
571			resets = <&bpmp TEGRA194_RESET_I2C6>;
572			reset-names = "i2c";
573			pinctrl-0 = <&state_dpaux0_i2c>;
574			pinctrl-1 = <&state_dpaux0_off>;
575			pinctrl-names = "default", "idle";
576			status = "disabled";
577		};
578
579		/* shares pads with dpaux2 */
580		dp_aux_ch2_i2c: i2c@31c0000 {
581			compatible = "nvidia,tegra194-i2c";
582			reg = <0x031c0000 0x10000>;
583			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
584			#address-cells = <1>;
585			#size-cells = <0>;
586			clocks = <&bpmp TEGRA194_CLK_I2C7>;
587			clock-names = "div-clk";
588			resets = <&bpmp TEGRA194_RESET_I2C7>;
589			reset-names = "i2c";
590			pinctrl-0 = <&state_dpaux2_i2c>;
591			pinctrl-1 = <&state_dpaux2_off>;
592			pinctrl-names = "default", "idle";
593			status = "disabled";
594		};
595
596		/* shares pads with dpaux3 */
597		dp_aux_ch3_i2c: i2c@31e0000 {
598			compatible = "nvidia,tegra194-i2c";
599			reg = <0x031e0000 0x10000>;
600			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
601			#address-cells = <1>;
602			#size-cells = <0>;
603			clocks = <&bpmp TEGRA194_CLK_I2C9>;
604			clock-names = "div-clk";
605			resets = <&bpmp TEGRA194_RESET_I2C9>;
606			reset-names = "i2c";
607			pinctrl-0 = <&state_dpaux3_i2c>;
608			pinctrl-1 = <&state_dpaux3_off>;
609			pinctrl-names = "default", "idle";
610			status = "disabled";
611		};
612
613		spi@3270000 {
614			compatible = "nvidia,tegra194-qspi";
615			reg = <0x3270000 0x1000>;
616			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
617			#address-cells = <1>;
618			#size-cells = <0>;
619			clocks = <&bpmp TEGRA194_CLK_QSPI0>,
620				 <&bpmp TEGRA194_CLK_QSPI0_PM>;
621			clock-names = "qspi", "qspi_out";
622			resets = <&bpmp TEGRA194_RESET_QSPI0>;
623			reset-names = "qspi";
624			status = "disabled";
625		};
626
627		spi@3300000 {
628			compatible = "nvidia,tegra194-qspi";
629			reg = <0x3300000 0x1000>;
630			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
631			#address-cells = <1>;
632			#size-cells = <0>;
633			clocks = <&bpmp TEGRA194_CLK_QSPI1>,
634				 <&bpmp TEGRA194_CLK_QSPI1_PM>;
635			clock-names = "qspi", "qspi_out";
636			resets = <&bpmp TEGRA194_RESET_QSPI1>;
637			reset-names = "qspi";
638			status = "disabled";
639		};
640
641		pwm1: pwm@3280000 {
642			compatible = "nvidia,tegra194-pwm",
643				     "nvidia,tegra186-pwm";
644			reg = <0x3280000 0x10000>;
645			clocks = <&bpmp TEGRA194_CLK_PWM1>;
646			clock-names = "pwm";
647			resets = <&bpmp TEGRA194_RESET_PWM1>;
648			reset-names = "pwm";
649			status = "disabled";
650			#pwm-cells = <2>;
651		};
652
653		pwm2: pwm@3290000 {
654			compatible = "nvidia,tegra194-pwm",
655				     "nvidia,tegra186-pwm";
656			reg = <0x3290000 0x10000>;
657			clocks = <&bpmp TEGRA194_CLK_PWM2>;
658			clock-names = "pwm";
659			resets = <&bpmp TEGRA194_RESET_PWM2>;
660			reset-names = "pwm";
661			status = "disabled";
662			#pwm-cells = <2>;
663		};
664
665		pwm3: pwm@32a0000 {
666			compatible = "nvidia,tegra194-pwm",
667				     "nvidia,tegra186-pwm";
668			reg = <0x32a0000 0x10000>;
669			clocks = <&bpmp TEGRA194_CLK_PWM3>;
670			clock-names = "pwm";
671			resets = <&bpmp TEGRA194_RESET_PWM3>;
672			reset-names = "pwm";
673			status = "disabled";
674			#pwm-cells = <2>;
675		};
676
677		pwm5: pwm@32c0000 {
678			compatible = "nvidia,tegra194-pwm",
679				     "nvidia,tegra186-pwm";
680			reg = <0x32c0000 0x10000>;
681			clocks = <&bpmp TEGRA194_CLK_PWM5>;
682			clock-names = "pwm";
683			resets = <&bpmp TEGRA194_RESET_PWM5>;
684			reset-names = "pwm";
685			status = "disabled";
686			#pwm-cells = <2>;
687		};
688
689		pwm6: pwm@32d0000 {
690			compatible = "nvidia,tegra194-pwm",
691				     "nvidia,tegra186-pwm";
692			reg = <0x32d0000 0x10000>;
693			clocks = <&bpmp TEGRA194_CLK_PWM6>;
694			clock-names = "pwm";
695			resets = <&bpmp TEGRA194_RESET_PWM6>;
696			reset-names = "pwm";
697			status = "disabled";
698			#pwm-cells = <2>;
699		};
700
701		pwm7: pwm@32e0000 {
702			compatible = "nvidia,tegra194-pwm",
703				     "nvidia,tegra186-pwm";
704			reg = <0x32e0000 0x10000>;
705			clocks = <&bpmp TEGRA194_CLK_PWM7>;
706			clock-names = "pwm";
707			resets = <&bpmp TEGRA194_RESET_PWM7>;
708			reset-names = "pwm";
709			status = "disabled";
710			#pwm-cells = <2>;
711		};
712
713		pwm8: pwm@32f0000 {
714			compatible = "nvidia,tegra194-pwm",
715				     "nvidia,tegra186-pwm";
716			reg = <0x32f0000 0x10000>;
717			clocks = <&bpmp TEGRA194_CLK_PWM8>;
718			clock-names = "pwm";
719			resets = <&bpmp TEGRA194_RESET_PWM8>;
720			reset-names = "pwm";
721			status = "disabled";
722			#pwm-cells = <2>;
723		};
724
725		sdmmc1: mmc@3400000 {
726			compatible = "nvidia,tegra194-sdhci";
727			reg = <0x03400000 0x10000>;
728			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
729			clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
730				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
731			clock-names = "sdhci", "tmclk";
732			resets = <&bpmp TEGRA194_RESET_SDMMC1>;
733			reset-names = "sdhci";
734			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
735					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
736			interconnect-names = "dma-mem", "write";
737			iommus = <&smmu TEGRA194_SID_SDMMC1>;
738			nvidia,pad-autocal-pull-up-offset-3v3-timeout =
739									<0x07>;
740			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
741									<0x07>;
742			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
743			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
744									<0x07>;
745			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
746			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
747			nvidia,default-tap = <0x9>;
748			nvidia,default-trim = <0x5>;
749			status = "disabled";
750		};
751
752		sdmmc3: mmc@3440000 {
753			compatible = "nvidia,tegra194-sdhci";
754			reg = <0x03440000 0x10000>;
755			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
756			clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
757				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
758			clock-names = "sdhci", "tmclk";
759			resets = <&bpmp TEGRA194_RESET_SDMMC3>;
760			reset-names = "sdhci";
761			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
762					<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
763			interconnect-names = "dma-mem", "write";
764			iommus = <&smmu TEGRA194_SID_SDMMC3>;
765			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
766			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
767			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
768			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
769									<0x07>;
770			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
771			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
772									<0x07>;
773			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
774			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
775			nvidia,default-tap = <0x9>;
776			nvidia,default-trim = <0x5>;
777			status = "disabled";
778		};
779
780		sdmmc4: mmc@3460000 {
781			compatible = "nvidia,tegra194-sdhci";
782			reg = <0x03460000 0x10000>;
783			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
784			clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
785				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
786			clock-names = "sdhci", "tmclk";
787			assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
788					  <&bpmp TEGRA194_CLK_PLLC4>;
789			assigned-clock-parents =
790					  <&bpmp TEGRA194_CLK_PLLC4>;
791			resets = <&bpmp TEGRA194_RESET_SDMMC4>;
792			reset-names = "sdhci";
793			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
794					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
795			interconnect-names = "dma-mem", "write";
796			iommus = <&smmu TEGRA194_SID_SDMMC4>;
797			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
798			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
799			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
800			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
801									<0x0a>;
802			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
803			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
804									<0x0a>;
805			nvidia,default-tap = <0x8>;
806			nvidia,default-trim = <0x14>;
807			nvidia,dqs-trim = <40>;
808			supports-cqe;
809			status = "disabled";
810		};
811
812		hda@3510000 {
813			compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
814			reg = <0x3510000 0x10000>;
815			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
816			clocks = <&bpmp TEGRA194_CLK_HDA>,
817				 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
818				 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
819			clock-names = "hda", "hda2hdmi", "hda2codec_2x";
820			resets = <&bpmp TEGRA194_RESET_HDA>,
821				 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
822				 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
823			reset-names = "hda", "hda2hdmi", "hda2codec_2x";
824			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
825			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
826					<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
827			interconnect-names = "dma-mem", "write";
828			iommus = <&smmu TEGRA194_SID_HDA>;
829			status = "disabled";
830		};
831
832		xusb_padctl: padctl@3520000 {
833			compatible = "nvidia,tegra194-xusb-padctl";
834			reg = <0x03520000 0x1000>,
835			      <0x03540000 0x1000>;
836			reg-names = "padctl", "ao";
837			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
838
839			resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
840			reset-names = "padctl";
841
842			status = "disabled";
843
844			pads {
845				usb2 {
846					clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
847					clock-names = "trk";
848
849					lanes {
850						usb2-0 {
851							nvidia,function = "xusb";
852							status = "disabled";
853							#phy-cells = <0>;
854						};
855
856						usb2-1 {
857							nvidia,function = "xusb";
858							status = "disabled";
859							#phy-cells = <0>;
860						};
861
862						usb2-2 {
863							nvidia,function = "xusb";
864							status = "disabled";
865							#phy-cells = <0>;
866						};
867
868						usb2-3 {
869							nvidia,function = "xusb";
870							status = "disabled";
871							#phy-cells = <0>;
872						};
873					};
874				};
875
876				usb3 {
877					lanes {
878						usb3-0 {
879							nvidia,function = "xusb";
880							status = "disabled";
881							#phy-cells = <0>;
882						};
883
884						usb3-1 {
885							nvidia,function = "xusb";
886							status = "disabled";
887							#phy-cells = <0>;
888						};
889
890						usb3-2 {
891							nvidia,function = "xusb";
892							status = "disabled";
893							#phy-cells = <0>;
894						};
895
896						usb3-3 {
897							nvidia,function = "xusb";
898							status = "disabled";
899							#phy-cells = <0>;
900						};
901					};
902				};
903			};
904
905			ports {
906				usb2-0 {
907					status = "disabled";
908				};
909
910				usb2-1 {
911					status = "disabled";
912				};
913
914				usb2-2 {
915					status = "disabled";
916				};
917
918				usb2-3 {
919					status = "disabled";
920				};
921
922				usb3-0 {
923					status = "disabled";
924				};
925
926				usb3-1 {
927					status = "disabled";
928				};
929
930				usb3-2 {
931					status = "disabled";
932				};
933
934				usb3-3 {
935					status = "disabled";
936				};
937			};
938		};
939
940		usb@3550000 {
941			compatible = "nvidia,tegra194-xudc";
942			reg = <0x03550000 0x8000>,
943			      <0x03558000 0x1000>;
944			reg-names = "base", "fpci";
945			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
946			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
947				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
948				 <&bpmp TEGRA194_CLK_XUSB_SS>,
949				 <&bpmp TEGRA194_CLK_XUSB_FS>;
950			clock-names = "dev", "ss", "ss_src", "fs_src";
951			interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
952					<&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
953			interconnect-names = "dma-mem", "write";
954			iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
955			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
956					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
957			power-domain-names = "dev", "ss";
958			nvidia,xusb-padctl = <&xusb_padctl>;
959			status = "disabled";
960		};
961
962		usb@3610000 {
963			compatible = "nvidia,tegra194-xusb";
964			reg = <0x03610000 0x40000>,
965			      <0x03600000 0x10000>;
966			reg-names = "hcd", "fpci";
967
968			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
969				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
970
971			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
972				 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
973				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
974				 <&bpmp TEGRA194_CLK_XUSB_SS>,
975				 <&bpmp TEGRA194_CLK_CLK_M>,
976				 <&bpmp TEGRA194_CLK_XUSB_FS>,
977				 <&bpmp TEGRA194_CLK_UTMIPLL>,
978				 <&bpmp TEGRA194_CLK_CLK_M>,
979				 <&bpmp TEGRA194_CLK_PLLE>;
980			clock-names = "xusb_host", "xusb_falcon_src",
981				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
982				      "xusb_fs_src", "pll_u_480m", "clk_m",
983				      "pll_e";
984			interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
985					<&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
986			interconnect-names = "dma-mem", "write";
987			iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
988
989			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
990					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
991			power-domain-names = "xusb_host", "xusb_ss";
992
993			nvidia,xusb-padctl = <&xusb_padctl>;
994			status = "disabled";
995		};
996
997		fuse@3820000 {
998			compatible = "nvidia,tegra194-efuse";
999			reg = <0x03820000 0x10000>;
1000			clocks = <&bpmp TEGRA194_CLK_FUSE>;
1001			clock-names = "fuse";
1002		};
1003
1004		gic: interrupt-controller@3881000 {
1005			compatible = "arm,gic-400";
1006			#interrupt-cells = <3>;
1007			interrupt-controller;
1008			reg = <0x03881000 0x1000>,
1009			      <0x03882000 0x2000>,
1010			      <0x03884000 0x2000>,
1011			      <0x03886000 0x2000>;
1012			interrupts = <GIC_PPI 9
1013				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1014			interrupt-parent = <&gic>;
1015		};
1016
1017		cec@3960000 {
1018			compatible = "nvidia,tegra194-cec";
1019			reg = <0x03960000 0x10000>;
1020			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1021			clocks = <&bpmp TEGRA194_CLK_CEC>;
1022			clock-names = "cec";
1023			status = "disabled";
1024		};
1025
1026		hsp_top0: hsp@3c00000 {
1027			compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1028			reg = <0x03c00000 0xa0000>;
1029			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1030			             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1031			             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1032			             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1033			             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1034			             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1035			             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1036			             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1037			             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1038			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1039			                  "shared3", "shared4", "shared5", "shared6",
1040			                  "shared7";
1041			#mbox-cells = <2>;
1042		};
1043
1044		p2u_hsio_0: phy@3e10000 {
1045			compatible = "nvidia,tegra194-p2u";
1046			reg = <0x03e10000 0x10000>;
1047			reg-names = "ctl";
1048
1049			#phy-cells = <0>;
1050		};
1051
1052		p2u_hsio_1: phy@3e20000 {
1053			compatible = "nvidia,tegra194-p2u";
1054			reg = <0x03e20000 0x10000>;
1055			reg-names = "ctl";
1056
1057			#phy-cells = <0>;
1058		};
1059
1060		p2u_hsio_2: phy@3e30000 {
1061			compatible = "nvidia,tegra194-p2u";
1062			reg = <0x03e30000 0x10000>;
1063			reg-names = "ctl";
1064
1065			#phy-cells = <0>;
1066		};
1067
1068		p2u_hsio_3: phy@3e40000 {
1069			compatible = "nvidia,tegra194-p2u";
1070			reg = <0x03e40000 0x10000>;
1071			reg-names = "ctl";
1072
1073			#phy-cells = <0>;
1074		};
1075
1076		p2u_hsio_4: phy@3e50000 {
1077			compatible = "nvidia,tegra194-p2u";
1078			reg = <0x03e50000 0x10000>;
1079			reg-names = "ctl";
1080
1081			#phy-cells = <0>;
1082		};
1083
1084		p2u_hsio_5: phy@3e60000 {
1085			compatible = "nvidia,tegra194-p2u";
1086			reg = <0x03e60000 0x10000>;
1087			reg-names = "ctl";
1088
1089			#phy-cells = <0>;
1090		};
1091
1092		p2u_hsio_6: phy@3e70000 {
1093			compatible = "nvidia,tegra194-p2u";
1094			reg = <0x03e70000 0x10000>;
1095			reg-names = "ctl";
1096
1097			#phy-cells = <0>;
1098		};
1099
1100		p2u_hsio_7: phy@3e80000 {
1101			compatible = "nvidia,tegra194-p2u";
1102			reg = <0x03e80000 0x10000>;
1103			reg-names = "ctl";
1104
1105			#phy-cells = <0>;
1106		};
1107
1108		p2u_hsio_8: phy@3e90000 {
1109			compatible = "nvidia,tegra194-p2u";
1110			reg = <0x03e90000 0x10000>;
1111			reg-names = "ctl";
1112
1113			#phy-cells = <0>;
1114		};
1115
1116		p2u_hsio_9: phy@3ea0000 {
1117			compatible = "nvidia,tegra194-p2u";
1118			reg = <0x03ea0000 0x10000>;
1119			reg-names = "ctl";
1120
1121			#phy-cells = <0>;
1122		};
1123
1124		p2u_nvhs_0: phy@3eb0000 {
1125			compatible = "nvidia,tegra194-p2u";
1126			reg = <0x03eb0000 0x10000>;
1127			reg-names = "ctl";
1128
1129			#phy-cells = <0>;
1130		};
1131
1132		p2u_nvhs_1: phy@3ec0000 {
1133			compatible = "nvidia,tegra194-p2u";
1134			reg = <0x03ec0000 0x10000>;
1135			reg-names = "ctl";
1136
1137			#phy-cells = <0>;
1138		};
1139
1140		p2u_nvhs_2: phy@3ed0000 {
1141			compatible = "nvidia,tegra194-p2u";
1142			reg = <0x03ed0000 0x10000>;
1143			reg-names = "ctl";
1144
1145			#phy-cells = <0>;
1146		};
1147
1148		p2u_nvhs_3: phy@3ee0000 {
1149			compatible = "nvidia,tegra194-p2u";
1150			reg = <0x03ee0000 0x10000>;
1151			reg-names = "ctl";
1152
1153			#phy-cells = <0>;
1154		};
1155
1156		p2u_nvhs_4: phy@3ef0000 {
1157			compatible = "nvidia,tegra194-p2u";
1158			reg = <0x03ef0000 0x10000>;
1159			reg-names = "ctl";
1160
1161			#phy-cells = <0>;
1162		};
1163
1164		p2u_nvhs_5: phy@3f00000 {
1165			compatible = "nvidia,tegra194-p2u";
1166			reg = <0x03f00000 0x10000>;
1167			reg-names = "ctl";
1168
1169			#phy-cells = <0>;
1170		};
1171
1172		p2u_nvhs_6: phy@3f10000 {
1173			compatible = "nvidia,tegra194-p2u";
1174			reg = <0x03f10000 0x10000>;
1175			reg-names = "ctl";
1176
1177			#phy-cells = <0>;
1178		};
1179
1180		p2u_nvhs_7: phy@3f20000 {
1181			compatible = "nvidia,tegra194-p2u";
1182			reg = <0x03f20000 0x10000>;
1183			reg-names = "ctl";
1184
1185			#phy-cells = <0>;
1186		};
1187
1188		p2u_hsio_10: phy@3f30000 {
1189			compatible = "nvidia,tegra194-p2u";
1190			reg = <0x03f30000 0x10000>;
1191			reg-names = "ctl";
1192
1193			#phy-cells = <0>;
1194		};
1195
1196		p2u_hsio_11: phy@3f40000 {
1197			compatible = "nvidia,tegra194-p2u";
1198			reg = <0x03f40000 0x10000>;
1199			reg-names = "ctl";
1200
1201			#phy-cells = <0>;
1202		};
1203
1204		hsp_aon: hsp@c150000 {
1205			compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1206			reg = <0x0c150000 0x90000>;
1207			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1208			             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1209			             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1210			             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1211			/*
1212			 * Shared interrupt 0 is routed only to AON/SPE, so
1213			 * we only have 4 shared interrupts for the CCPLEX.
1214			 */
1215			interrupt-names = "shared1", "shared2", "shared3", "shared4";
1216			#mbox-cells = <2>;
1217		};
1218
1219		gen2_i2c: i2c@c240000 {
1220			compatible = "nvidia,tegra194-i2c";
1221			reg = <0x0c240000 0x10000>;
1222			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1223			#address-cells = <1>;
1224			#size-cells = <0>;
1225			clocks = <&bpmp TEGRA194_CLK_I2C2>;
1226			clock-names = "div-clk";
1227			resets = <&bpmp TEGRA194_RESET_I2C2>;
1228			reset-names = "i2c";
1229			status = "disabled";
1230		};
1231
1232		gen8_i2c: i2c@c250000 {
1233			compatible = "nvidia,tegra194-i2c";
1234			reg = <0x0c250000 0x10000>;
1235			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1236			#address-cells = <1>;
1237			#size-cells = <0>;
1238			clocks = <&bpmp TEGRA194_CLK_I2C8>;
1239			clock-names = "div-clk";
1240			resets = <&bpmp TEGRA194_RESET_I2C8>;
1241			reset-names = "i2c";
1242			status = "disabled";
1243		};
1244
1245		uartc: serial@c280000 {
1246			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1247			reg = <0x0c280000 0x40>;
1248			reg-shift = <2>;
1249			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1250			clocks = <&bpmp TEGRA194_CLK_UARTC>;
1251			clock-names = "serial";
1252			resets = <&bpmp TEGRA194_RESET_UARTC>;
1253			reset-names = "serial";
1254			status = "disabled";
1255		};
1256
1257		uartg: serial@c290000 {
1258			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1259			reg = <0x0c290000 0x40>;
1260			reg-shift = <2>;
1261			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1262			clocks = <&bpmp TEGRA194_CLK_UARTG>;
1263			clock-names = "serial";
1264			resets = <&bpmp TEGRA194_RESET_UARTG>;
1265			reset-names = "serial";
1266			status = "disabled";
1267		};
1268
1269		rtc: rtc@c2a0000 {
1270			compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1271			reg = <0x0c2a0000 0x10000>;
1272			interrupt-parent = <&pmc>;
1273			interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1274			clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1275			clock-names = "rtc";
1276			status = "disabled";
1277		};
1278
1279		gpio_aon: gpio@c2f0000 {
1280			compatible = "nvidia,tegra194-gpio-aon";
1281			reg-names = "security", "gpio";
1282			reg = <0xc2f0000 0x1000>,
1283			      <0xc2f1000 0x1000>;
1284			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1285			gpio-controller;
1286			#gpio-cells = <2>;
1287			interrupt-controller;
1288			#interrupt-cells = <2>;
1289		};
1290
1291		pwm4: pwm@c340000 {
1292			compatible = "nvidia,tegra194-pwm",
1293				     "nvidia,tegra186-pwm";
1294			reg = <0xc340000 0x10000>;
1295			clocks = <&bpmp TEGRA194_CLK_PWM4>;
1296			clock-names = "pwm";
1297			resets = <&bpmp TEGRA194_RESET_PWM4>;
1298			reset-names = "pwm";
1299			status = "disabled";
1300			#pwm-cells = <2>;
1301		};
1302
1303		pmc: pmc@c360000 {
1304			compatible = "nvidia,tegra194-pmc";
1305			reg = <0x0c360000 0x10000>,
1306			      <0x0c370000 0x10000>,
1307			      <0x0c380000 0x10000>,
1308			      <0x0c390000 0x10000>,
1309			      <0x0c3a0000 0x10000>;
1310			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1311
1312			#interrupt-cells = <2>;
1313			interrupt-controller;
1314		};
1315
1316		smmu: iommu@12000000 {
1317			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1318			reg = <0x12000000 0x800000>,
1319			      <0x11000000 0x800000>;
1320			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1321				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1322				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1323				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1324				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1325				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1326				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1327				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1328				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1329				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1330				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1331				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1332				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1333				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1334				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1335				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1336				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1337				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1338				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1340				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1341				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1342				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1343				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1344				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1345				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1346				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1347				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1348				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1349				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1350				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1351				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1352				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1353				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1354				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1355				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1356				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1357				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1358				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1359				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1360				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1361				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1362				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1363				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1364				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1365				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1366				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1367				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1368				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1369				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1370				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1371				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1372				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1373				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1374				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1375				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1376				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1377				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1378				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1379				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1380				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1381				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1382				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1383				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1384				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1385				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1386			stream-match-mask = <0x7f80>;
1387			#global-interrupts = <2>;
1388			#iommu-cells = <1>;
1389
1390			nvidia,memory-controller = <&mc>;
1391			status = "okay";
1392		};
1393
1394		host1x@13e00000 {
1395			compatible = "nvidia,tegra194-host1x";
1396			reg = <0x13e00000 0x10000>,
1397			      <0x13e10000 0x10000>;
1398			reg-names = "hypervisor", "vm";
1399			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1400				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1401			interrupt-names = "syncpt", "host1x";
1402			clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1403			clock-names = "host1x";
1404			resets = <&bpmp TEGRA194_RESET_HOST1X>;
1405			reset-names = "host1x";
1406
1407			#address-cells = <1>;
1408			#size-cells = <1>;
1409
1410			ranges = <0x15000000 0x15000000 0x01000000>;
1411			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1412			interconnect-names = "dma-mem";
1413			iommus = <&smmu TEGRA194_SID_HOST1X>;
1414
1415			display-hub@15200000 {
1416				compatible = "nvidia,tegra194-display";
1417				reg = <0x15200000 0x00040000>;
1418				resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1419					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1420					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1421					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1422					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1423					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1424					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1425				reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1426					      "wgrp3", "wgrp4", "wgrp5";
1427				clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1428					 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1429				clock-names = "disp", "hub";
1430				status = "disabled";
1431
1432				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1433
1434				#address-cells = <1>;
1435				#size-cells = <1>;
1436
1437				ranges = <0x15200000 0x15200000 0x40000>;
1438
1439				display@15200000 {
1440					compatible = "nvidia,tegra194-dc";
1441					reg = <0x15200000 0x10000>;
1442					interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1443					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1444					clock-names = "dc";
1445					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1446					reset-names = "dc";
1447
1448					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1449					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1450							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1451					interconnect-names = "dma-mem", "read-1";
1452
1453					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1454					nvidia,head = <0>;
1455				};
1456
1457				display@15210000 {
1458					compatible = "nvidia,tegra194-dc";
1459					reg = <0x15210000 0x10000>;
1460					interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1461					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1462					clock-names = "dc";
1463					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1464					reset-names = "dc";
1465
1466					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1467					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1468							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1469					interconnect-names = "dma-mem", "read-1";
1470
1471					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1472					nvidia,head = <1>;
1473				};
1474
1475				display@15220000 {
1476					compatible = "nvidia,tegra194-dc";
1477					reg = <0x15220000 0x10000>;
1478					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1479					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1480					clock-names = "dc";
1481					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1482					reset-names = "dc";
1483
1484					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1485					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1486							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1487					interconnect-names = "dma-mem", "read-1";
1488
1489					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1490					nvidia,head = <2>;
1491				};
1492
1493				display@15230000 {
1494					compatible = "nvidia,tegra194-dc";
1495					reg = <0x15230000 0x10000>;
1496					interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1497					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1498					clock-names = "dc";
1499					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1500					reset-names = "dc";
1501
1502					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1503					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1504							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1505					interconnect-names = "dma-mem", "read-1";
1506
1507					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1508					nvidia,head = <3>;
1509				};
1510			};
1511
1512			vic@15340000 {
1513				compatible = "nvidia,tegra194-vic";
1514				reg = <0x15340000 0x00040000>;
1515				interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1516				clocks = <&bpmp TEGRA194_CLK_VIC>;
1517				clock-names = "vic";
1518				resets = <&bpmp TEGRA194_RESET_VIC>;
1519				reset-names = "vic";
1520
1521				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1522				interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
1523						<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
1524				interconnect-names = "dma-mem", "write";
1525				iommus = <&smmu TEGRA194_SID_VIC>;
1526			};
1527
1528			dpaux0: dpaux@155c0000 {
1529				compatible = "nvidia,tegra194-dpaux";
1530				reg = <0x155c0000 0x10000>;
1531				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1532				clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1533					 <&bpmp TEGRA194_CLK_PLLDP>;
1534				clock-names = "dpaux", "parent";
1535				resets = <&bpmp TEGRA194_RESET_DPAUX>;
1536				reset-names = "dpaux";
1537				status = "disabled";
1538
1539				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1540
1541				state_dpaux0_aux: pinmux-aux {
1542					groups = "dpaux-io";
1543					function = "aux";
1544				};
1545
1546				state_dpaux0_i2c: pinmux-i2c {
1547					groups = "dpaux-io";
1548					function = "i2c";
1549				};
1550
1551				state_dpaux0_off: pinmux-off {
1552					groups = "dpaux-io";
1553					function = "off";
1554				};
1555
1556				i2c-bus {
1557					#address-cells = <1>;
1558					#size-cells = <0>;
1559				};
1560			};
1561
1562			dpaux1: dpaux@155d0000 {
1563				compatible = "nvidia,tegra194-dpaux";
1564				reg = <0x155d0000 0x10000>;
1565				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1566				clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1567					 <&bpmp TEGRA194_CLK_PLLDP>;
1568				clock-names = "dpaux", "parent";
1569				resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1570				reset-names = "dpaux";
1571				status = "disabled";
1572
1573				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1574
1575				state_dpaux1_aux: pinmux-aux {
1576					groups = "dpaux-io";
1577					function = "aux";
1578				};
1579
1580				state_dpaux1_i2c: pinmux-i2c {
1581					groups = "dpaux-io";
1582					function = "i2c";
1583				};
1584
1585				state_dpaux1_off: pinmux-off {
1586					groups = "dpaux-io";
1587					function = "off";
1588				};
1589
1590				i2c-bus {
1591					#address-cells = <1>;
1592					#size-cells = <0>;
1593				};
1594			};
1595
1596			dpaux2: dpaux@155e0000 {
1597				compatible = "nvidia,tegra194-dpaux";
1598				reg = <0x155e0000 0x10000>;
1599				interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1600				clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1601					 <&bpmp TEGRA194_CLK_PLLDP>;
1602				clock-names = "dpaux", "parent";
1603				resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1604				reset-names = "dpaux";
1605				status = "disabled";
1606
1607				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1608
1609				state_dpaux2_aux: pinmux-aux {
1610					groups = "dpaux-io";
1611					function = "aux";
1612				};
1613
1614				state_dpaux2_i2c: pinmux-i2c {
1615					groups = "dpaux-io";
1616					function = "i2c";
1617				};
1618
1619				state_dpaux2_off: pinmux-off {
1620					groups = "dpaux-io";
1621					function = "off";
1622				};
1623
1624				i2c-bus {
1625					#address-cells = <1>;
1626					#size-cells = <0>;
1627				};
1628			};
1629
1630			dpaux3: dpaux@155f0000 {
1631				compatible = "nvidia,tegra194-dpaux";
1632				reg = <0x155f0000 0x10000>;
1633				interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1634				clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1635					 <&bpmp TEGRA194_CLK_PLLDP>;
1636				clock-names = "dpaux", "parent";
1637				resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1638				reset-names = "dpaux";
1639				status = "disabled";
1640
1641				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1642
1643				state_dpaux3_aux: pinmux-aux {
1644					groups = "dpaux-io";
1645					function = "aux";
1646				};
1647
1648				state_dpaux3_i2c: pinmux-i2c {
1649					groups = "dpaux-io";
1650					function = "i2c";
1651				};
1652
1653				state_dpaux3_off: pinmux-off {
1654					groups = "dpaux-io";
1655					function = "off";
1656				};
1657
1658				i2c-bus {
1659					#address-cells = <1>;
1660					#size-cells = <0>;
1661				};
1662			};
1663
1664			sor0: sor@15b00000 {
1665				compatible = "nvidia,tegra194-sor";
1666				reg = <0x15b00000 0x40000>;
1667				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1668				clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1669					 <&bpmp TEGRA194_CLK_SOR0_OUT>,
1670					 <&bpmp TEGRA194_CLK_PLLD>,
1671					 <&bpmp TEGRA194_CLK_PLLDP>,
1672					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1673					 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1674				clock-names = "sor", "out", "parent", "dp", "safe",
1675					      "pad";
1676				resets = <&bpmp TEGRA194_RESET_SOR0>;
1677				reset-names = "sor";
1678				pinctrl-0 = <&state_dpaux0_aux>;
1679				pinctrl-1 = <&state_dpaux0_i2c>;
1680				pinctrl-2 = <&state_dpaux0_off>;
1681				pinctrl-names = "aux", "i2c", "off";
1682				status = "disabled";
1683
1684				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1685				nvidia,interface = <0>;
1686			};
1687
1688			sor1: sor@15b40000 {
1689				compatible = "nvidia,tegra194-sor";
1690				reg = <0x15b40000 0x40000>;
1691				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1692				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1693					 <&bpmp TEGRA194_CLK_SOR1_OUT>,
1694					 <&bpmp TEGRA194_CLK_PLLD2>,
1695					 <&bpmp TEGRA194_CLK_PLLDP>,
1696					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1697					 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1698				clock-names = "sor", "out", "parent", "dp", "safe",
1699					      "pad";
1700				resets = <&bpmp TEGRA194_RESET_SOR1>;
1701				reset-names = "sor";
1702				pinctrl-0 = <&state_dpaux1_aux>;
1703				pinctrl-1 = <&state_dpaux1_i2c>;
1704				pinctrl-2 = <&state_dpaux1_off>;
1705				pinctrl-names = "aux", "i2c", "off";
1706				status = "disabled";
1707
1708				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1709				nvidia,interface = <1>;
1710			};
1711
1712			sor2: sor@15b80000 {
1713				compatible = "nvidia,tegra194-sor";
1714				reg = <0x15b80000 0x40000>;
1715				interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1716				clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1717					 <&bpmp TEGRA194_CLK_SOR2_OUT>,
1718					 <&bpmp TEGRA194_CLK_PLLD3>,
1719					 <&bpmp TEGRA194_CLK_PLLDP>,
1720					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1721					 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1722				clock-names = "sor", "out", "parent", "dp", "safe",
1723					      "pad";
1724				resets = <&bpmp TEGRA194_RESET_SOR2>;
1725				reset-names = "sor";
1726				pinctrl-0 = <&state_dpaux2_aux>;
1727				pinctrl-1 = <&state_dpaux2_i2c>;
1728				pinctrl-2 = <&state_dpaux2_off>;
1729				pinctrl-names = "aux", "i2c", "off";
1730				status = "disabled";
1731
1732				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1733				nvidia,interface = <2>;
1734			};
1735
1736			sor3: sor@15bc0000 {
1737				compatible = "nvidia,tegra194-sor";
1738				reg = <0x15bc0000 0x40000>;
1739				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1740				clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1741					 <&bpmp TEGRA194_CLK_SOR3_OUT>,
1742					 <&bpmp TEGRA194_CLK_PLLD4>,
1743					 <&bpmp TEGRA194_CLK_PLLDP>,
1744					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1745					 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1746				clock-names = "sor", "out", "parent", "dp", "safe",
1747					      "pad";
1748				resets = <&bpmp TEGRA194_RESET_SOR3>;
1749				reset-names = "sor";
1750				pinctrl-0 = <&state_dpaux3_aux>;
1751				pinctrl-1 = <&state_dpaux3_i2c>;
1752				pinctrl-2 = <&state_dpaux3_off>;
1753				pinctrl-names = "aux", "i2c", "off";
1754				status = "disabled";
1755
1756				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1757				nvidia,interface = <3>;
1758			};
1759		};
1760
1761		gpu@17000000 {
1762			compatible = "nvidia,gv11b";
1763			reg = <0x17000000 0x1000000>,
1764			      <0x18000000 0x1000000>;
1765			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1766				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1767			interrupt-names = "stall", "nonstall";
1768			clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
1769				 <&bpmp TEGRA194_CLK_GPU_PWR>,
1770				 <&bpmp TEGRA194_CLK_FUSE>;
1771			clock-names = "gpu", "pwr", "fuse";
1772			resets = <&bpmp TEGRA194_RESET_GPU>;
1773			reset-names = "gpu";
1774			dma-coherent;
1775
1776			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1777			interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
1778					<&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
1779					<&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
1780					<&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
1781					<&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
1782					<&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
1783					<&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
1784					<&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
1785					<&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
1786					<&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
1787					<&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
1788					<&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
1789			interconnect-names = "dma-mem", "read-0-hp", "write-0",
1790					     "read-1", "read-1-hp", "write-1",
1791					     "read-2", "read-2-hp", "write-2",
1792					     "read-3", "read-3-hp", "write-3";
1793		};
1794	};
1795
1796	pcie@14100000 {
1797		compatible = "nvidia,tegra194-pcie";
1798		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1799		reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
1800		      <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
1801		      <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1802		      <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1803		reg-names = "appl", "config", "atu_dma", "dbi";
1804
1805		status = "disabled";
1806
1807		#address-cells = <3>;
1808		#size-cells = <2>;
1809		device_type = "pci";
1810		num-lanes = <1>;
1811		num-viewport = <8>;
1812		linux,pci-domain = <1>;
1813
1814		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1815		clock-names = "core";
1816
1817		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1818			 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1819		reset-names = "apb", "core";
1820
1821		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1822			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1823		interrupt-names = "intr", "msi";
1824
1825		#interrupt-cells = <1>;
1826		interrupt-map-mask = <0 0 0 0>;
1827		interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1828
1829		nvidia,bpmp = <&bpmp 1>;
1830
1831		nvidia,aspm-cmrt-us = <60>;
1832		nvidia,aspm-pwr-on-t-us = <20>;
1833		nvidia,aspm-l0s-entrance-latency-us = <3>;
1834
1835		bus-range = <0x0 0xff>;
1836
1837		ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1838			 <0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1839			 <0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1840
1841		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
1842				<&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
1843		interconnect-names = "dma-mem", "write";
1844		iommus = <&smmu TEGRA194_SID_PCIE1>;
1845		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
1846		iommu-map-mask = <0x0>;
1847		dma-coherent;
1848	};
1849
1850	pcie@14120000 {
1851		compatible = "nvidia,tegra194-pcie";
1852		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1853		reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
1854		      <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
1855		      <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1856		      <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1857		reg-names = "appl", "config", "atu_dma", "dbi";
1858
1859		status = "disabled";
1860
1861		#address-cells = <3>;
1862		#size-cells = <2>;
1863		device_type = "pci";
1864		num-lanes = <1>;
1865		num-viewport = <8>;
1866		linux,pci-domain = <2>;
1867
1868		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1869		clock-names = "core";
1870
1871		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1872			 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1873		reset-names = "apb", "core";
1874
1875		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1876			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1877		interrupt-names = "intr", "msi";
1878
1879		#interrupt-cells = <1>;
1880		interrupt-map-mask = <0 0 0 0>;
1881		interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1882
1883		nvidia,bpmp = <&bpmp 2>;
1884
1885		nvidia,aspm-cmrt-us = <60>;
1886		nvidia,aspm-pwr-on-t-us = <20>;
1887		nvidia,aspm-l0s-entrance-latency-us = <3>;
1888
1889		bus-range = <0x0 0xff>;
1890
1891		ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1892			 <0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1893			 <0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1894
1895		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
1896				<&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
1897		interconnect-names = "dma-mem", "write";
1898		iommus = <&smmu TEGRA194_SID_PCIE2>;
1899		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
1900		iommu-map-mask = <0x0>;
1901		dma-coherent;
1902	};
1903
1904	pcie@14140000 {
1905		compatible = "nvidia,tegra194-pcie";
1906		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1907		reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
1908		      <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
1909		      <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1910		      <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1911		reg-names = "appl", "config", "atu_dma", "dbi";
1912
1913		status = "disabled";
1914
1915		#address-cells = <3>;
1916		#size-cells = <2>;
1917		device_type = "pci";
1918		num-lanes = <1>;
1919		num-viewport = <8>;
1920		linux,pci-domain = <3>;
1921
1922		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1923		clock-names = "core";
1924
1925		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1926			 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1927		reset-names = "apb", "core";
1928
1929		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1930			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1931		interrupt-names = "intr", "msi";
1932
1933		#interrupt-cells = <1>;
1934		interrupt-map-mask = <0 0 0 0>;
1935		interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1936
1937		nvidia,bpmp = <&bpmp 3>;
1938
1939		nvidia,aspm-cmrt-us = <60>;
1940		nvidia,aspm-pwr-on-t-us = <20>;
1941		nvidia,aspm-l0s-entrance-latency-us = <3>;
1942
1943		bus-range = <0x0 0xff>;
1944
1945		ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1946			 <0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
1947			 <0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1948
1949		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
1950				<&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
1951		interconnect-names = "dma-mem", "write";
1952		iommus = <&smmu TEGRA194_SID_PCIE3>;
1953		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
1954		iommu-map-mask = <0x0>;
1955		dma-coherent;
1956	};
1957
1958	pcie@14160000 {
1959		compatible = "nvidia,tegra194-pcie";
1960		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1961		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
1962		      <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
1963		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1964		      <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1965		reg-names = "appl", "config", "atu_dma", "dbi";
1966
1967		status = "disabled";
1968
1969		#address-cells = <3>;
1970		#size-cells = <2>;
1971		device_type = "pci";
1972		num-lanes = <4>;
1973		num-viewport = <8>;
1974		linux,pci-domain = <4>;
1975
1976		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1977		clock-names = "core";
1978
1979		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1980			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1981		reset-names = "apb", "core";
1982
1983		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1984			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1985		interrupt-names = "intr", "msi";
1986
1987		#interrupt-cells = <1>;
1988		interrupt-map-mask = <0 0 0 0>;
1989		interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1990
1991		nvidia,bpmp = <&bpmp 4>;
1992
1993		nvidia,aspm-cmrt-us = <60>;
1994		nvidia,aspm-pwr-on-t-us = <20>;
1995		nvidia,aspm-l0s-entrance-latency-us = <3>;
1996
1997		bus-range = <0x0 0xff>;
1998
1999		ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2000			 <0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2001			 <0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2002
2003		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2004				<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2005		interconnect-names = "dma-mem", "write";
2006		iommus = <&smmu TEGRA194_SID_PCIE4>;
2007		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2008		iommu-map-mask = <0x0>;
2009		dma-coherent;
2010	};
2011
2012	pcie@14180000 {
2013		compatible = "nvidia,tegra194-pcie";
2014		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2015		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2016		      <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2017		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2018		      <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2019		reg-names = "appl", "config", "atu_dma", "dbi";
2020
2021		status = "disabled";
2022
2023		#address-cells = <3>;
2024		#size-cells = <2>;
2025		device_type = "pci";
2026		num-lanes = <8>;
2027		num-viewport = <8>;
2028		linux,pci-domain = <0>;
2029
2030		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2031		clock-names = "core";
2032
2033		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2034			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2035		reset-names = "apb", "core";
2036
2037		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2038			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2039		interrupt-names = "intr", "msi";
2040
2041		#interrupt-cells = <1>;
2042		interrupt-map-mask = <0 0 0 0>;
2043		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2044
2045		nvidia,bpmp = <&bpmp 0>;
2046
2047		nvidia,aspm-cmrt-us = <60>;
2048		nvidia,aspm-pwr-on-t-us = <20>;
2049		nvidia,aspm-l0s-entrance-latency-us = <3>;
2050
2051		bus-range = <0x0 0xff>;
2052
2053		ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2054			 <0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2055			 <0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2056
2057		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2058				<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2059		interconnect-names = "dma-mem", "write";
2060		iommus = <&smmu TEGRA194_SID_PCIE0>;
2061		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2062		iommu-map-mask = <0x0>;
2063		dma-coherent;
2064	};
2065
2066	pcie@141a0000 {
2067		compatible = "nvidia,tegra194-pcie";
2068		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2069		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2070		      <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2071		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2072		      <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2073		reg-names = "appl", "config", "atu_dma", "dbi";
2074
2075		status = "disabled";
2076
2077		#address-cells = <3>;
2078		#size-cells = <2>;
2079		device_type = "pci";
2080		num-lanes = <8>;
2081		num-viewport = <8>;
2082		linux,pci-domain = <5>;
2083
2084		pinctrl-names = "default";
2085		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2086
2087		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
2088			 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
2089		clock-names = "core", "core_m";
2090
2091		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2092			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2093		reset-names = "apb", "core";
2094
2095		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2096			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2097		interrupt-names = "intr", "msi";
2098
2099		nvidia,bpmp = <&bpmp 5>;
2100
2101		#interrupt-cells = <1>;
2102		interrupt-map-mask = <0 0 0 0>;
2103		interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2104
2105		nvidia,aspm-cmrt-us = <60>;
2106		nvidia,aspm-pwr-on-t-us = <20>;
2107		nvidia,aspm-l0s-entrance-latency-us = <3>;
2108
2109		bus-range = <0x0 0xff>;
2110
2111		ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2112			 <0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2113			 <0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2114
2115		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2116				<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2117		interconnect-names = "dma-mem", "write";
2118		iommus = <&smmu TEGRA194_SID_PCIE5>;
2119		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2120		iommu-map-mask = <0x0>;
2121		dma-coherent;
2122	};
2123
2124	pcie_ep@14160000 {
2125		compatible = "nvidia,tegra194-pcie-ep";
2126		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2127		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2128		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2129		      <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2130		      <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2131		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2132
2133		status = "disabled";
2134
2135		num-lanes = <4>;
2136		num-ib-windows = <2>;
2137		num-ob-windows = <8>;
2138
2139		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2140		clock-names = "core";
2141
2142		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2143			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2144		reset-names = "apb", "core";
2145
2146		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2147		interrupt-names = "intr";
2148
2149		nvidia,bpmp = <&bpmp 4>;
2150
2151		nvidia,aspm-cmrt-us = <60>;
2152		nvidia,aspm-pwr-on-t-us = <20>;
2153		nvidia,aspm-l0s-entrance-latency-us = <3>;
2154
2155		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2156				<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2157		interconnect-names = "dma-mem", "write";
2158		iommus = <&smmu TEGRA194_SID_PCIE4>;
2159		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2160		iommu-map-mask = <0x0>;
2161		dma-coherent;
2162	};
2163
2164	pcie_ep@14180000 {
2165		compatible = "nvidia,tegra194-pcie-ep";
2166		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2167		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2168		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2169		      <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2170		      <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2171		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2172
2173		status = "disabled";
2174
2175		num-lanes = <8>;
2176		num-ib-windows = <2>;
2177		num-ob-windows = <8>;
2178
2179		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2180		clock-names = "core";
2181
2182		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2183			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2184		reset-names = "apb", "core";
2185
2186		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2187		interrupt-names = "intr";
2188
2189		nvidia,bpmp = <&bpmp 0>;
2190
2191		nvidia,aspm-cmrt-us = <60>;
2192		nvidia,aspm-pwr-on-t-us = <20>;
2193		nvidia,aspm-l0s-entrance-latency-us = <3>;
2194
2195		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2196				<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2197		interconnect-names = "dma-mem", "write";
2198		iommus = <&smmu TEGRA194_SID_PCIE0>;
2199		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2200		iommu-map-mask = <0x0>;
2201		dma-coherent;
2202	};
2203
2204	pcie_ep@141a0000 {
2205		compatible = "nvidia,tegra194-pcie-ep";
2206		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2207		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2208		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2209		      <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2210		      <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2211		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2212
2213		status = "disabled";
2214
2215		num-lanes = <8>;
2216		num-ib-windows = <2>;
2217		num-ob-windows = <8>;
2218
2219		pinctrl-names = "default";
2220		pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2221
2222		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2223		clock-names = "core";
2224
2225		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2226			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2227		reset-names = "apb", "core";
2228
2229		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2230		interrupt-names = "intr";
2231
2232		nvidia,bpmp = <&bpmp 5>;
2233
2234		nvidia,aspm-cmrt-us = <60>;
2235		nvidia,aspm-pwr-on-t-us = <20>;
2236		nvidia,aspm-l0s-entrance-latency-us = <3>;
2237
2238		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2239				<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2240		interconnect-names = "dma-mem", "write";
2241		iommus = <&smmu TEGRA194_SID_PCIE5>;
2242		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2243		iommu-map-mask = <0x0>;
2244		dma-coherent;
2245	};
2246
2247	sram@40000000 {
2248		compatible = "nvidia,tegra194-sysram", "mmio-sram";
2249		reg = <0x0 0x40000000 0x0 0x50000>;
2250		#address-cells = <1>;
2251		#size-cells = <1>;
2252		ranges = <0x0 0x0 0x40000000 0x50000>;
2253
2254		cpu_bpmp_tx: sram@4e000 {
2255			reg = <0x4e000 0x1000>;
2256			label = "cpu-bpmp-tx";
2257			pool;
2258		};
2259
2260		cpu_bpmp_rx: sram@4f000 {
2261			reg = <0x4f000 0x1000>;
2262			label = "cpu-bpmp-rx";
2263			pool;
2264		};
2265	};
2266
2267	bpmp: bpmp {
2268		compatible = "nvidia,tegra186-bpmp";
2269		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2270				    TEGRA_HSP_DB_MASTER_BPMP>;
2271		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2272		#clock-cells = <1>;
2273		#reset-cells = <1>;
2274		#power-domain-cells = <1>;
2275		interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2276				<&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2277				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2278				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2279		interconnect-names = "read", "write", "dma-mem", "dma-write";
2280		iommus = <&smmu TEGRA194_SID_BPMP>;
2281
2282		bpmp_i2c: i2c {
2283			compatible = "nvidia,tegra186-bpmp-i2c";
2284			nvidia,bpmp-bus-id = <5>;
2285			#address-cells = <1>;
2286			#size-cells = <0>;
2287		};
2288
2289		bpmp_thermal: thermal {
2290			compatible = "nvidia,tegra186-bpmp-thermal";
2291			#thermal-sensor-cells = <1>;
2292		};
2293	};
2294
2295	cpus {
2296		compatible = "nvidia,tegra194-ccplex";
2297		nvidia,bpmp = <&bpmp>;
2298		#address-cells = <1>;
2299		#size-cells = <0>;
2300
2301		cpu0_0: cpu@0 {
2302			compatible = "nvidia,tegra194-carmel";
2303			device_type = "cpu";
2304			reg = <0x000>;
2305			enable-method = "psci";
2306			i-cache-size = <131072>;
2307			i-cache-line-size = <64>;
2308			i-cache-sets = <512>;
2309			d-cache-size = <65536>;
2310			d-cache-line-size = <64>;
2311			d-cache-sets = <256>;
2312			next-level-cache = <&l2c_0>;
2313		};
2314
2315		cpu0_1: cpu@1 {
2316			compatible = "nvidia,tegra194-carmel";
2317			device_type = "cpu";
2318			reg = <0x001>;
2319			enable-method = "psci";
2320			i-cache-size = <131072>;
2321			i-cache-line-size = <64>;
2322			i-cache-sets = <512>;
2323			d-cache-size = <65536>;
2324			d-cache-line-size = <64>;
2325			d-cache-sets = <256>;
2326			next-level-cache = <&l2c_0>;
2327		};
2328
2329		cpu1_0: cpu@100 {
2330			compatible = "nvidia,tegra194-carmel";
2331			device_type = "cpu";
2332			reg = <0x100>;
2333			enable-method = "psci";
2334			i-cache-size = <131072>;
2335			i-cache-line-size = <64>;
2336			i-cache-sets = <512>;
2337			d-cache-size = <65536>;
2338			d-cache-line-size = <64>;
2339			d-cache-sets = <256>;
2340			next-level-cache = <&l2c_1>;
2341		};
2342
2343		cpu1_1: cpu@101 {
2344			compatible = "nvidia,tegra194-carmel";
2345			device_type = "cpu";
2346			reg = <0x101>;
2347			enable-method = "psci";
2348			i-cache-size = <131072>;
2349			i-cache-line-size = <64>;
2350			i-cache-sets = <512>;
2351			d-cache-size = <65536>;
2352			d-cache-line-size = <64>;
2353			d-cache-sets = <256>;
2354			next-level-cache = <&l2c_1>;
2355		};
2356
2357		cpu2_0: cpu@200 {
2358			compatible = "nvidia,tegra194-carmel";
2359			device_type = "cpu";
2360			reg = <0x200>;
2361			enable-method = "psci";
2362			i-cache-size = <131072>;
2363			i-cache-line-size = <64>;
2364			i-cache-sets = <512>;
2365			d-cache-size = <65536>;
2366			d-cache-line-size = <64>;
2367			d-cache-sets = <256>;
2368			next-level-cache = <&l2c_2>;
2369		};
2370
2371		cpu2_1: cpu@201 {
2372			compatible = "nvidia,tegra194-carmel";
2373			device_type = "cpu";
2374			reg = <0x201>;
2375			enable-method = "psci";
2376			i-cache-size = <131072>;
2377			i-cache-line-size = <64>;
2378			i-cache-sets = <512>;
2379			d-cache-size = <65536>;
2380			d-cache-line-size = <64>;
2381			d-cache-sets = <256>;
2382			next-level-cache = <&l2c_2>;
2383		};
2384
2385		cpu3_0: cpu@300 {
2386			compatible = "nvidia,tegra194-carmel";
2387			device_type = "cpu";
2388			reg = <0x300>;
2389			enable-method = "psci";
2390			i-cache-size = <131072>;
2391			i-cache-line-size = <64>;
2392			i-cache-sets = <512>;
2393			d-cache-size = <65536>;
2394			d-cache-line-size = <64>;
2395			d-cache-sets = <256>;
2396			next-level-cache = <&l2c_3>;
2397		};
2398
2399		cpu3_1: cpu@301 {
2400			compatible = "nvidia,tegra194-carmel";
2401			device_type = "cpu";
2402			reg = <0x301>;
2403			enable-method = "psci";
2404			i-cache-size = <131072>;
2405			i-cache-line-size = <64>;
2406			i-cache-sets = <512>;
2407			d-cache-size = <65536>;
2408			d-cache-line-size = <64>;
2409			d-cache-sets = <256>;
2410			next-level-cache = <&l2c_3>;
2411		};
2412
2413		cpu-map {
2414			cluster0 {
2415				core0 {
2416					cpu = <&cpu0_0>;
2417				};
2418
2419				core1 {
2420					cpu = <&cpu0_1>;
2421				};
2422			};
2423
2424			cluster1 {
2425				core0 {
2426					cpu = <&cpu1_0>;
2427				};
2428
2429				core1 {
2430					cpu = <&cpu1_1>;
2431				};
2432			};
2433
2434			cluster2 {
2435				core0 {
2436					cpu = <&cpu2_0>;
2437				};
2438
2439				core1 {
2440					cpu = <&cpu2_1>;
2441				};
2442			};
2443
2444			cluster3 {
2445				core0 {
2446					cpu = <&cpu3_0>;
2447				};
2448
2449				core1 {
2450					cpu = <&cpu3_1>;
2451				};
2452			};
2453		};
2454
2455		l2c_0: l2-cache0 {
2456			cache-size = <2097152>;
2457			cache-line-size = <64>;
2458			cache-sets = <2048>;
2459			next-level-cache = <&l3c>;
2460		};
2461
2462		l2c_1: l2-cache1 {
2463			cache-size = <2097152>;
2464			cache-line-size = <64>;
2465			cache-sets = <2048>;
2466			next-level-cache = <&l3c>;
2467		};
2468
2469		l2c_2: l2-cache2 {
2470			cache-size = <2097152>;
2471			cache-line-size = <64>;
2472			cache-sets = <2048>;
2473			next-level-cache = <&l3c>;
2474		};
2475
2476		l2c_3: l2-cache3 {
2477			cache-size = <2097152>;
2478			cache-line-size = <64>;
2479			cache-sets = <2048>;
2480			next-level-cache = <&l3c>;
2481		};
2482
2483		l3c: l3-cache {
2484			cache-size = <4194304>;
2485			cache-line-size = <64>;
2486			cache-sets = <4096>;
2487		};
2488	};
2489
2490	pmu {
2491		compatible = "arm,armv8-pmuv3";
2492		interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2493			     <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
2494			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
2495			     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
2496			     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
2497			     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
2498			     <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
2499			     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
2500		interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
2501				      &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
2502	};
2503
2504	psci {
2505		compatible = "arm,psci-1.0";
2506		status = "okay";
2507		method = "smc";
2508	};
2509
2510	sound {
2511		status = "disabled";
2512
2513		clocks = <&bpmp TEGRA194_CLK_PLLA>,
2514			 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2515		clock-names = "pll_a", "plla_out0";
2516		assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
2517				  <&bpmp TEGRA194_CLK_PLLA_OUT0>,
2518				  <&bpmp TEGRA194_CLK_AUD_MCLK>;
2519		assigned-clock-parents = <0>,
2520					 <&bpmp TEGRA194_CLK_PLLA>,
2521					 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2522		/*
2523		 * PLLA supports dynamic ramp. Below initial rate is chosen
2524		 * for this to work and oscillate between base rates required
2525		 * for 8x and 11.025x sample rate streams.
2526		 */
2527		assigned-clock-rates = <258000000>;
2528
2529		interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
2530				<&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
2531		interconnect-names = "dma-mem", "write";
2532		iommus = <&smmu TEGRA194_SID_APE>;
2533	};
2534
2535	tcu: tcu {
2536		compatible = "nvidia,tegra194-tcu";
2537		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
2538		         <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
2539		mbox-names = "rx", "tx";
2540	};
2541
2542	thermal-zones {
2543		cpu {
2544			thermal-sensors = <&{/bpmp/thermal}
2545					   TEGRA194_BPMP_THERMAL_ZONE_CPU>;
2546			status = "disabled";
2547		};
2548
2549		gpu {
2550			thermal-sensors = <&{/bpmp/thermal}
2551					   TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2552			status = "disabled";
2553		};
2554
2555		aux {
2556			thermal-sensors = <&{/bpmp/thermal}
2557					   TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2558			status = "disabled";
2559		};
2560
2561		pllx {
2562			thermal-sensors = <&{/bpmp/thermal}
2563					   TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2564			status = "disabled";
2565		};
2566
2567		ao {
2568			thermal-sensors = <&{/bpmp/thermal}
2569					   TEGRA194_BPMP_THERMAL_ZONE_AO>;
2570			status = "disabled";
2571		};
2572
2573		tj {
2574			thermal-sensors = <&{/bpmp/thermal}
2575					   TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2576			status = "disabled";
2577		};
2578	};
2579
2580	timer {
2581		compatible = "arm,armv8-timer";
2582		interrupts = <GIC_PPI 13
2583				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2584			     <GIC_PPI 14
2585				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2586			     <GIC_PPI 11
2587				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2588			     <GIC_PPI 10
2589				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2590		interrupt-parent = <&gic>;
2591		always-on;
2592	};
2593};
2594