1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113 #dma-cells = <1>; 114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115 dma-coherent; 116 dma-channel-mask = <0xfffffffe>; 117 status = "okay"; 118 }; 119 120 aconnect@2900000 { 121 compatible = "nvidia,tegra186-aconnect", 122 "nvidia,tegra210-aconnect"; 123 clocks = <&bpmp TEGRA186_CLK_APE>, 124 <&bpmp TEGRA186_CLK_APB2APE>; 125 clock-names = "ape", "apb2ape"; 126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0x02900000 0x0 0x02900000 0x200000>; 130 status = "disabled"; 131 132 tegra_ahub: ahub@2900800 { 133 compatible = "nvidia,tegra186-ahub"; 134 reg = <0x02900800 0x800>; 135 clocks = <&bpmp TEGRA186_CLK_AHUB>; 136 clock-names = "ahub"; 137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 ranges = <0x02900800 0x02900800 0x11800>; 142 status = "disabled"; 143 144 tegra_i2s1: i2s@2901000 { 145 compatible = "nvidia,tegra186-i2s", 146 "nvidia,tegra210-i2s"; 147 reg = <0x2901000 0x100>; 148 clocks = <&bpmp TEGRA186_CLK_I2S1>, 149 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 150 clock-names = "i2s", "sync_input"; 151 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 152 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 153 assigned-clock-rates = <1536000>; 154 sound-name-prefix = "I2S1"; 155 status = "disabled"; 156 }; 157 158 tegra_i2s2: i2s@2901100 { 159 compatible = "nvidia,tegra186-i2s", 160 "nvidia,tegra210-i2s"; 161 reg = <0x2901100 0x100>; 162 clocks = <&bpmp TEGRA186_CLK_I2S2>, 163 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 164 clock-names = "i2s", "sync_input"; 165 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 166 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 167 assigned-clock-rates = <1536000>; 168 sound-name-prefix = "I2S2"; 169 status = "disabled"; 170 }; 171 172 tegra_i2s3: i2s@2901200 { 173 compatible = "nvidia,tegra186-i2s", 174 "nvidia,tegra210-i2s"; 175 reg = <0x2901200 0x100>; 176 clocks = <&bpmp TEGRA186_CLK_I2S3>, 177 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 178 clock-names = "i2s", "sync_input"; 179 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 180 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 181 assigned-clock-rates = <1536000>; 182 sound-name-prefix = "I2S3"; 183 status = "disabled"; 184 }; 185 186 tegra_i2s4: i2s@2901300 { 187 compatible = "nvidia,tegra186-i2s", 188 "nvidia,tegra210-i2s"; 189 reg = <0x2901300 0x100>; 190 clocks = <&bpmp TEGRA186_CLK_I2S4>, 191 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 192 clock-names = "i2s", "sync_input"; 193 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 194 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 195 assigned-clock-rates = <1536000>; 196 sound-name-prefix = "I2S4"; 197 status = "disabled"; 198 }; 199 200 tegra_i2s5: i2s@2901400 { 201 compatible = "nvidia,tegra186-i2s", 202 "nvidia,tegra210-i2s"; 203 reg = <0x2901400 0x100>; 204 clocks = <&bpmp TEGRA186_CLK_I2S5>, 205 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 206 clock-names = "i2s", "sync_input"; 207 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 208 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 209 assigned-clock-rates = <1536000>; 210 sound-name-prefix = "I2S5"; 211 status = "disabled"; 212 }; 213 214 tegra_i2s6: i2s@2901500 { 215 compatible = "nvidia,tegra186-i2s", 216 "nvidia,tegra210-i2s"; 217 reg = <0x2901500 0x100>; 218 clocks = <&bpmp TEGRA186_CLK_I2S6>, 219 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 220 clock-names = "i2s", "sync_input"; 221 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 222 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 223 assigned-clock-rates = <1536000>; 224 sound-name-prefix = "I2S6"; 225 status = "disabled"; 226 }; 227 228 tegra_sfc1: sfc@2902000 { 229 compatible = "nvidia,tegra186-sfc", 230 "nvidia,tegra210-sfc"; 231 reg = <0x2902000 0x200>; 232 sound-name-prefix = "SFC1"; 233 status = "disabled"; 234 }; 235 236 tegra_sfc2: sfc@2902200 { 237 compatible = "nvidia,tegra186-sfc", 238 "nvidia,tegra210-sfc"; 239 reg = <0x2902200 0x200>; 240 sound-name-prefix = "SFC2"; 241 status = "disabled"; 242 }; 243 244 tegra_sfc3: sfc@2902400 { 245 compatible = "nvidia,tegra186-sfc", 246 "nvidia,tegra210-sfc"; 247 reg = <0x2902400 0x200>; 248 sound-name-prefix = "SFC3"; 249 status = "disabled"; 250 }; 251 252 tegra_sfc4: sfc@2902600 { 253 compatible = "nvidia,tegra186-sfc", 254 "nvidia,tegra210-sfc"; 255 reg = <0x2902600 0x200>; 256 sound-name-prefix = "SFC4"; 257 status = "disabled"; 258 }; 259 260 tegra_amx1: amx@2903000 { 261 compatible = "nvidia,tegra186-amx", 262 "nvidia,tegra210-amx"; 263 reg = <0x2903000 0x100>; 264 sound-name-prefix = "AMX1"; 265 status = "disabled"; 266 }; 267 268 tegra_amx2: amx@2903100 { 269 compatible = "nvidia,tegra186-amx", 270 "nvidia,tegra210-amx"; 271 reg = <0x2903100 0x100>; 272 sound-name-prefix = "AMX2"; 273 status = "disabled"; 274 }; 275 276 tegra_amx3: amx@2903200 { 277 compatible = "nvidia,tegra186-amx", 278 "nvidia,tegra210-amx"; 279 reg = <0x2903200 0x100>; 280 sound-name-prefix = "AMX3"; 281 status = "disabled"; 282 }; 283 284 tegra_amx4: amx@2903300 { 285 compatible = "nvidia,tegra186-amx", 286 "nvidia,tegra210-amx"; 287 reg = <0x2903300 0x100>; 288 sound-name-prefix = "AMX4"; 289 status = "disabled"; 290 }; 291 292 tegra_adx1: adx@2903800 { 293 compatible = "nvidia,tegra186-adx", 294 "nvidia,tegra210-adx"; 295 reg = <0x2903800 0x100>; 296 sound-name-prefix = "ADX1"; 297 status = "disabled"; 298 }; 299 300 tegra_adx2: adx@2903900 { 301 compatible = "nvidia,tegra186-adx", 302 "nvidia,tegra210-adx"; 303 reg = <0x2903900 0x100>; 304 sound-name-prefix = "ADX2"; 305 status = "disabled"; 306 }; 307 308 tegra_adx3: adx@2903a00 { 309 compatible = "nvidia,tegra186-adx", 310 "nvidia,tegra210-adx"; 311 reg = <0x2903a00 0x100>; 312 sound-name-prefix = "ADX3"; 313 status = "disabled"; 314 }; 315 316 tegra_adx4: adx@2903b00 { 317 compatible = "nvidia,tegra186-adx", 318 "nvidia,tegra210-adx"; 319 reg = <0x2903b00 0x100>; 320 sound-name-prefix = "ADX4"; 321 status = "disabled"; 322 }; 323 324 tegra_dmic1: dmic@2904000 { 325 compatible = "nvidia,tegra210-dmic"; 326 reg = <0x2904000 0x100>; 327 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 328 clock-names = "dmic"; 329 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 330 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 331 assigned-clock-rates = <3072000>; 332 sound-name-prefix = "DMIC1"; 333 status = "disabled"; 334 }; 335 336 tegra_dmic2: dmic@2904100 { 337 compatible = "nvidia,tegra210-dmic"; 338 reg = <0x2904100 0x100>; 339 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 340 clock-names = "dmic"; 341 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 342 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 343 assigned-clock-rates = <3072000>; 344 sound-name-prefix = "DMIC2"; 345 status = "disabled"; 346 }; 347 348 tegra_dmic3: dmic@2904200 { 349 compatible = "nvidia,tegra210-dmic"; 350 reg = <0x2904200 0x100>; 351 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 352 clock-names = "dmic"; 353 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 354 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 355 assigned-clock-rates = <3072000>; 356 sound-name-prefix = "DMIC3"; 357 status = "disabled"; 358 }; 359 360 tegra_dmic4: dmic@2904300 { 361 compatible = "nvidia,tegra210-dmic"; 362 reg = <0x2904300 0x100>; 363 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 364 clock-names = "dmic"; 365 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 366 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 367 assigned-clock-rates = <3072000>; 368 sound-name-prefix = "DMIC4"; 369 status = "disabled"; 370 }; 371 372 tegra_dspk1: dspk@2905000 { 373 compatible = "nvidia,tegra186-dspk"; 374 reg = <0x2905000 0x100>; 375 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 376 clock-names = "dspk"; 377 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 378 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 379 assigned-clock-rates = <12288000>; 380 sound-name-prefix = "DSPK1"; 381 status = "disabled"; 382 }; 383 384 tegra_dspk2: dspk@2905100 { 385 compatible = "nvidia,tegra186-dspk"; 386 reg = <0x2905100 0x100>; 387 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 388 clock-names = "dspk"; 389 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 390 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 391 assigned-clock-rates = <12288000>; 392 sound-name-prefix = "DSPK2"; 393 status = "disabled"; 394 }; 395 396 tegra_ope1: processing-engine@2908000 { 397 compatible = "nvidia,tegra186-ope", 398 "nvidia,tegra210-ope"; 399 reg = <0x2908000 0x100>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges; 403 sound-name-prefix = "OPE1"; 404 status = "disabled"; 405 406 equalizer@2908100 { 407 compatible = "nvidia,tegra186-peq", 408 "nvidia,tegra210-peq"; 409 reg = <0x2908100 0x100>; 410 }; 411 412 dynamic-range-compressor@2908200 { 413 compatible = "nvidia,tegra186-mbdrc", 414 "nvidia,tegra210-mbdrc"; 415 reg = <0x2908200 0x200>; 416 }; 417 }; 418 419 tegra_mvc1: mvc@290a000 { 420 compatible = "nvidia,tegra186-mvc", 421 "nvidia,tegra210-mvc"; 422 reg = <0x290a000 0x200>; 423 sound-name-prefix = "MVC1"; 424 status = "disabled"; 425 }; 426 427 tegra_mvc2: mvc@290a200 { 428 compatible = "nvidia,tegra186-mvc", 429 "nvidia,tegra210-mvc"; 430 reg = <0x290a200 0x200>; 431 sound-name-prefix = "MVC2"; 432 status = "disabled"; 433 }; 434 435 tegra_amixer: amixer@290bb00 { 436 compatible = "nvidia,tegra186-amixer", 437 "nvidia,tegra210-amixer"; 438 reg = <0x290bb00 0x800>; 439 sound-name-prefix = "MIXER1"; 440 status = "disabled"; 441 }; 442 443 tegra_admaif: admaif@290f000 { 444 compatible = "nvidia,tegra186-admaif"; 445 reg = <0x0290f000 0x1000>; 446 dmas = <&adma 1>, <&adma 1>, 447 <&adma 2>, <&adma 2>, 448 <&adma 3>, <&adma 3>, 449 <&adma 4>, <&adma 4>, 450 <&adma 5>, <&adma 5>, 451 <&adma 6>, <&adma 6>, 452 <&adma 7>, <&adma 7>, 453 <&adma 8>, <&adma 8>, 454 <&adma 9>, <&adma 9>, 455 <&adma 10>, <&adma 10>, 456 <&adma 11>, <&adma 11>, 457 <&adma 12>, <&adma 12>, 458 <&adma 13>, <&adma 13>, 459 <&adma 14>, <&adma 14>, 460 <&adma 15>, <&adma 15>, 461 <&adma 16>, <&adma 16>, 462 <&adma 17>, <&adma 17>, 463 <&adma 18>, <&adma 18>, 464 <&adma 19>, <&adma 19>, 465 <&adma 20>, <&adma 20>; 466 dma-names = "rx1", "tx1", 467 "rx2", "tx2", 468 "rx3", "tx3", 469 "rx4", "tx4", 470 "rx5", "tx5", 471 "rx6", "tx6", 472 "rx7", "tx7", 473 "rx8", "tx8", 474 "rx9", "tx9", 475 "rx10", "tx10", 476 "rx11", "tx11", 477 "rx12", "tx12", 478 "rx13", "tx13", 479 "rx14", "tx14", 480 "rx15", "tx15", 481 "rx16", "tx16", 482 "rx17", "tx17", 483 "rx18", "tx18", 484 "rx19", "tx19", 485 "rx20", "tx20"; 486 status = "disabled"; 487 }; 488 489 tegra_asrc: asrc@2910000 { 490 compatible = "nvidia,tegra186-asrc"; 491 reg = <0x2910000 0x2000>; 492 sound-name-prefix = "ASRC1"; 493 status = "disabled"; 494 }; 495 }; 496 497 adma: dma-controller@2930000 { 498 compatible = "nvidia,tegra186-adma"; 499 reg = <0x02930000 0x20000>; 500 interrupt-parent = <&agic>; 501 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 533 #dma-cells = <1>; 534 clocks = <&bpmp TEGRA186_CLK_AHUB>; 535 clock-names = "d_audio"; 536 status = "disabled"; 537 }; 538 539 agic: interrupt-controller@2a40000 { 540 compatible = "nvidia,tegra186-agic", 541 "nvidia,tegra210-agic"; 542 #interrupt-cells = <3>; 543 interrupt-controller; 544 reg = <0x02a41000 0x1000>, 545 <0x02a42000 0x2000>; 546 interrupts = <GIC_SPI 145 547 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 548 clocks = <&bpmp TEGRA186_CLK_APE>; 549 clock-names = "clk"; 550 status = "disabled"; 551 }; 552 }; 553 554 mc: memory-controller@2c00000 { 555 compatible = "nvidia,tegra186-mc"; 556 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 557 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 558 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 559 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 560 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 561 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 562 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 563 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 564 status = "disabled"; 565 566 #interconnect-cells = <1>; 567 #address-cells = <2>; 568 #size-cells = <2>; 569 570 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 571 572 /* 573 * Memory clients have access to all 40 bits that the memory 574 * controller can address. 575 */ 576 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 577 578 emc: external-memory-controller@2c60000 { 579 compatible = "nvidia,tegra186-emc"; 580 reg = <0x0 0x02c60000 0x0 0x50000>; 581 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&bpmp TEGRA186_CLK_EMC>; 583 clock-names = "emc"; 584 585 #interconnect-cells = <0>; 586 587 nvidia,bpmp = <&bpmp>; 588 }; 589 }; 590 591 timer@3010000 { 592 compatible = "nvidia,tegra186-timer"; 593 reg = <0x0 0x03010000 0x0 0x000e0000>; 594 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 604 status = "okay"; 605 }; 606 607 uarta: serial@3100000 { 608 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 609 reg = <0x0 0x03100000 0x0 0x40>; 610 reg-shift = <2>; 611 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&bpmp TEGRA186_CLK_UARTA>; 613 resets = <&bpmp TEGRA186_RESET_UARTA>; 614 status = "disabled"; 615 }; 616 617 uartb: serial@3110000 { 618 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 619 reg = <0x0 0x03110000 0x0 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA186_CLK_UARTB>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA186_RESET_UARTB>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@3130000 { 630 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 631 reg = <0x0 0x03130000 0x0 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA186_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&bpmp TEGRA186_RESET_UARTD>; 637 reset-names = "serial"; 638 status = "disabled"; 639 }; 640 641 uarte: serial@3140000 { 642 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643 reg = <0x0 0x03140000 0x0 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA186_CLK_UARTE>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA186_RESET_UARTE>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartf: serial@3150000 { 654 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655 reg = <0x0 0x03150000 0x0 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA186_CLK_UARTF>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA186_RESET_UARTF>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 gen1_i2c: i2c@3160000 { 666 compatible = "nvidia,tegra186-i2c"; 667 reg = <0x0 0x03160000 0x0 0x10000>; 668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&bpmp TEGRA186_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&bpmp TEGRA186_RESET_I2C1>; 674 reset-names = "i2c"; 675 dmas = <&gpcdma 21>, <&gpcdma 21>; 676 dma-names = "rx", "tx"; 677 status = "disabled"; 678 }; 679 680 cam_i2c: i2c@3180000 { 681 compatible = "nvidia,tegra186-i2c"; 682 reg = <0x0 0x03180000 0x0 0x10000>; 683 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 clocks = <&bpmp TEGRA186_CLK_I2C3>; 687 clock-names = "div-clk"; 688 resets = <&bpmp TEGRA186_RESET_I2C3>; 689 reset-names = "i2c"; 690 dmas = <&gpcdma 23>, <&gpcdma 23>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 /* shares pads with dpaux1 */ 696 dp_aux_ch1_i2c: i2c@3190000 { 697 compatible = "nvidia,tegra186-i2c"; 698 reg = <0x0 0x03190000 0x0 0x10000>; 699 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 clocks = <&bpmp TEGRA186_CLK_I2C4>; 703 clock-names = "div-clk"; 704 resets = <&bpmp TEGRA186_RESET_I2C4>; 705 reset-names = "i2c"; 706 pinctrl-names = "default", "idle"; 707 pinctrl-0 = <&state_dpaux1_i2c>; 708 pinctrl-1 = <&state_dpaux1_off>; 709 dmas = <&gpcdma 26>, <&gpcdma 26>; 710 dma-names = "rx", "tx"; 711 status = "disabled"; 712 }; 713 714 /* controlled by BPMP, should not be enabled */ 715 pwr_i2c: i2c@31a0000 { 716 compatible = "nvidia,tegra186-i2c"; 717 reg = <0x0 0x031a0000 0x0 0x10000>; 718 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 clocks = <&bpmp TEGRA186_CLK_I2C5>; 722 clock-names = "div-clk"; 723 resets = <&bpmp TEGRA186_RESET_I2C5>; 724 reset-names = "i2c"; 725 status = "disabled"; 726 }; 727 728 /* shares pads with dpaux0 */ 729 dp_aux_ch0_i2c: i2c@31b0000 { 730 compatible = "nvidia,tegra186-i2c"; 731 reg = <0x0 0x031b0000 0x0 0x10000>; 732 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 clocks = <&bpmp TEGRA186_CLK_I2C6>; 736 clock-names = "div-clk"; 737 resets = <&bpmp TEGRA186_RESET_I2C6>; 738 reset-names = "i2c"; 739 pinctrl-names = "default", "idle"; 740 pinctrl-0 = <&state_dpaux_i2c>; 741 pinctrl-1 = <&state_dpaux_off>; 742 dmas = <&gpcdma 30>, <&gpcdma 30>; 743 dma-names = "rx", "tx"; 744 status = "disabled"; 745 }; 746 747 gen7_i2c: i2c@31c0000 { 748 compatible = "nvidia,tegra186-i2c"; 749 reg = <0x0 0x031c0000 0x0 0x10000>; 750 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 clocks = <&bpmp TEGRA186_CLK_I2C7>; 754 clock-names = "div-clk"; 755 resets = <&bpmp TEGRA186_RESET_I2C7>; 756 reset-names = "i2c"; 757 dmas = <&gpcdma 27>, <&gpcdma 27>; 758 dma-names = "rx", "tx"; 759 status = "disabled"; 760 }; 761 762 gen9_i2c: i2c@31e0000 { 763 compatible = "nvidia,tegra186-i2c"; 764 reg = <0x0 0x031e0000 0x0 0x10000>; 765 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 clocks = <&bpmp TEGRA186_CLK_I2C9>; 769 clock-names = "div-clk"; 770 resets = <&bpmp TEGRA186_RESET_I2C9>; 771 reset-names = "i2c"; 772 dmas = <&gpcdma 31>, <&gpcdma 31>; 773 dma-names = "rx", "tx"; 774 status = "disabled"; 775 }; 776 777 pwm1: pwm@3280000 { 778 compatible = "nvidia,tegra186-pwm"; 779 reg = <0x0 0x3280000 0x0 0x10000>; 780 clocks = <&bpmp TEGRA186_CLK_PWM1>; 781 resets = <&bpmp TEGRA186_RESET_PWM1>; 782 reset-names = "pwm"; 783 status = "disabled"; 784 #pwm-cells = <2>; 785 }; 786 787 pwm2: pwm@3290000 { 788 compatible = "nvidia,tegra186-pwm"; 789 reg = <0x0 0x3290000 0x0 0x10000>; 790 clocks = <&bpmp TEGRA186_CLK_PWM2>; 791 resets = <&bpmp TEGRA186_RESET_PWM2>; 792 reset-names = "pwm"; 793 status = "disabled"; 794 #pwm-cells = <2>; 795 }; 796 797 pwm3: pwm@32a0000 { 798 compatible = "nvidia,tegra186-pwm"; 799 reg = <0x0 0x32a0000 0x0 0x10000>; 800 clocks = <&bpmp TEGRA186_CLK_PWM3>; 801 resets = <&bpmp TEGRA186_RESET_PWM3>; 802 reset-names = "pwm"; 803 status = "disabled"; 804 #pwm-cells = <2>; 805 }; 806 807 pwm5: pwm@32c0000 { 808 compatible = "nvidia,tegra186-pwm"; 809 reg = <0x0 0x32c0000 0x0 0x10000>; 810 clocks = <&bpmp TEGRA186_CLK_PWM5>; 811 resets = <&bpmp TEGRA186_RESET_PWM5>; 812 reset-names = "pwm"; 813 status = "disabled"; 814 #pwm-cells = <2>; 815 }; 816 817 pwm6: pwm@32d0000 { 818 compatible = "nvidia,tegra186-pwm"; 819 reg = <0x0 0x32d0000 0x0 0x10000>; 820 clocks = <&bpmp TEGRA186_CLK_PWM6>; 821 resets = <&bpmp TEGRA186_RESET_PWM6>; 822 reset-names = "pwm"; 823 status = "disabled"; 824 #pwm-cells = <2>; 825 }; 826 827 pwm7: pwm@32e0000 { 828 compatible = "nvidia,tegra186-pwm"; 829 reg = <0x0 0x32e0000 0x0 0x10000>; 830 clocks = <&bpmp TEGRA186_CLK_PWM7>; 831 resets = <&bpmp TEGRA186_RESET_PWM7>; 832 reset-names = "pwm"; 833 status = "disabled"; 834 #pwm-cells = <2>; 835 }; 836 837 pwm8: pwm@32f0000 { 838 compatible = "nvidia,tegra186-pwm"; 839 reg = <0x0 0x32f0000 0x0 0x10000>; 840 clocks = <&bpmp TEGRA186_CLK_PWM8>; 841 resets = <&bpmp TEGRA186_RESET_PWM8>; 842 reset-names = "pwm"; 843 status = "disabled"; 844 #pwm-cells = <2>; 845 }; 846 847 sdmmc1: mmc@3400000 { 848 compatible = "nvidia,tegra186-sdhci"; 849 reg = <0x0 0x03400000 0x0 0x10000>; 850 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 852 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 853 clock-names = "sdhci", "tmclk"; 854 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 855 reset-names = "sdhci"; 856 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 857 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 858 interconnect-names = "dma-mem", "write"; 859 iommus = <&smmu TEGRA186_SID_SDMMC1>; 860 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 861 pinctrl-0 = <&sdmmc1_3v3>; 862 pinctrl-1 = <&sdmmc1_1v8>; 863 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 864 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 865 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 866 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 867 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 868 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 869 nvidia,default-tap = <0x5>; 870 nvidia,default-trim = <0xb>; 871 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 872 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 873 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 874 status = "disabled"; 875 }; 876 877 sdmmc2: mmc@3420000 { 878 compatible = "nvidia,tegra186-sdhci"; 879 reg = <0x0 0x03420000 0x0 0x10000>; 880 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 882 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 883 clock-names = "sdhci", "tmclk"; 884 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 885 reset-names = "sdhci"; 886 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 887 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 888 interconnect-names = "dma-mem", "write"; 889 iommus = <&smmu TEGRA186_SID_SDMMC2>; 890 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 891 pinctrl-0 = <&sdmmc2_3v3>; 892 pinctrl-1 = <&sdmmc2_1v8>; 893 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 894 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 895 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 896 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 897 nvidia,default-tap = <0x5>; 898 nvidia,default-trim = <0xb>; 899 status = "disabled"; 900 }; 901 902 sdmmc3: mmc@3440000 { 903 compatible = "nvidia,tegra186-sdhci"; 904 reg = <0x0 0x03440000 0x0 0x10000>; 905 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 907 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 908 clock-names = "sdhci", "tmclk"; 909 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 910 reset-names = "sdhci"; 911 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 912 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 913 interconnect-names = "dma-mem", "write"; 914 iommus = <&smmu TEGRA186_SID_SDMMC3>; 915 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 916 pinctrl-0 = <&sdmmc3_3v3>; 917 pinctrl-1 = <&sdmmc3_1v8>; 918 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 919 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 920 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 921 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 922 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 923 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 924 nvidia,default-tap = <0x5>; 925 nvidia,default-trim = <0xb>; 926 status = "disabled"; 927 }; 928 929 sdmmc4: mmc@3460000 { 930 compatible = "nvidia,tegra186-sdhci"; 931 reg = <0x0 0x03460000 0x0 0x10000>; 932 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 934 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 935 clock-names = "sdhci", "tmclk"; 936 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 937 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 938 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 939 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 940 reset-names = "sdhci"; 941 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 942 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 943 interconnect-names = "dma-mem", "write"; 944 iommus = <&smmu TEGRA186_SID_SDMMC4>; 945 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 946 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 947 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 948 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 949 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 950 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 951 nvidia,default-tap = <0x9>; 952 nvidia,default-trim = <0x5>; 953 nvidia,dqs-trim = <63>; 954 mmc-hs400-1_8v; 955 supports-cqe; 956 status = "disabled"; 957 }; 958 959 sata@3507000 { 960 compatible = "nvidia,tegra186-ahci"; 961 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 962 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 963 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 964 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 965 966 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 967 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 968 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 969 interconnect-names = "dma-mem", "write"; 970 iommus = <&smmu TEGRA186_SID_SATA>; 971 972 clocks = <&bpmp TEGRA186_CLK_SATA>, 973 <&bpmp TEGRA186_CLK_SATA_OOB>; 974 clock-names = "sata", "sata-oob"; 975 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 976 <&bpmp TEGRA186_CLK_SATA_OOB>; 977 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 978 <&bpmp TEGRA186_CLK_PLLP>; 979 assigned-clock-rates = <102000000>, 980 <204000000>; 981 resets = <&bpmp TEGRA186_RESET_SATA>, 982 <&bpmp TEGRA186_RESET_SATACOLD>; 983 reset-names = "sata", "sata-cold"; 984 status = "disabled"; 985 }; 986 987 hda@3510000 { 988 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 989 reg = <0x0 0x03510000 0x0 0x10000>; 990 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&bpmp TEGRA186_CLK_HDA>, 992 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 993 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 994 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 995 resets = <&bpmp TEGRA186_RESET_HDA>, 996 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 997 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 998 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 999 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1000 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1001 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1002 interconnect-names = "dma-mem", "write"; 1003 iommus = <&smmu TEGRA186_SID_HDA>; 1004 status = "disabled"; 1005 }; 1006 1007 padctl: padctl@3520000 { 1008 compatible = "nvidia,tegra186-xusb-padctl"; 1009 reg = <0x0 0x03520000 0x0 0x1000>, 1010 <0x0 0x03540000 0x0 0x1000>; 1011 reg-names = "padctl", "ao"; 1012 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1013 1014 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1015 reset-names = "padctl"; 1016 1017 status = "disabled"; 1018 1019 pads { 1020 usb2 { 1021 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1022 clock-names = "trk"; 1023 status = "disabled"; 1024 1025 lanes { 1026 usb2-0 { 1027 status = "disabled"; 1028 #phy-cells = <0>; 1029 }; 1030 1031 usb2-1 { 1032 status = "disabled"; 1033 #phy-cells = <0>; 1034 }; 1035 1036 usb2-2 { 1037 status = "disabled"; 1038 #phy-cells = <0>; 1039 }; 1040 }; 1041 }; 1042 1043 hsic { 1044 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1045 clock-names = "trk"; 1046 status = "disabled"; 1047 1048 lanes { 1049 hsic-0 { 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 }; 1054 }; 1055 1056 usb3 { 1057 status = "disabled"; 1058 1059 lanes { 1060 usb3-0 { 1061 status = "disabled"; 1062 #phy-cells = <0>; 1063 }; 1064 1065 usb3-1 { 1066 status = "disabled"; 1067 #phy-cells = <0>; 1068 }; 1069 1070 usb3-2 { 1071 status = "disabled"; 1072 #phy-cells = <0>; 1073 }; 1074 }; 1075 }; 1076 }; 1077 1078 ports { 1079 usb2-0 { 1080 status = "disabled"; 1081 }; 1082 1083 usb2-1 { 1084 status = "disabled"; 1085 }; 1086 1087 usb2-2 { 1088 status = "disabled"; 1089 }; 1090 1091 hsic-0 { 1092 status = "disabled"; 1093 }; 1094 1095 usb3-0 { 1096 status = "disabled"; 1097 }; 1098 1099 usb3-1 { 1100 status = "disabled"; 1101 }; 1102 1103 usb3-2 { 1104 status = "disabled"; 1105 }; 1106 }; 1107 }; 1108 1109 usb@3530000 { 1110 compatible = "nvidia,tegra186-xusb"; 1111 reg = <0x0 0x03530000 0x0 0x8000>, 1112 <0x0 0x03538000 0x0 0x1000>; 1113 reg-names = "hcd", "fpci"; 1114 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1117 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1118 <&bpmp TEGRA186_CLK_XUSB_SS>, 1119 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1120 <&bpmp TEGRA186_CLK_CLK_M>, 1121 <&bpmp TEGRA186_CLK_XUSB_FS>, 1122 <&bpmp TEGRA186_CLK_PLLU>, 1123 <&bpmp TEGRA186_CLK_CLK_M>, 1124 <&bpmp TEGRA186_CLK_PLLE>; 1125 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1126 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1127 "pll_u_480m", "clk_m", "pll_e"; 1128 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1129 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1130 power-domain-names = "xusb_host", "xusb_ss"; 1131 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1132 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1133 interconnect-names = "dma-mem", "write"; 1134 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 1139 nvidia,xusb-padctl = <&padctl>; 1140 }; 1141 1142 usb@3550000 { 1143 compatible = "nvidia,tegra186-xudc"; 1144 reg = <0x0 0x03550000 0x0 0x8000>, 1145 <0x0 0x03558000 0x0 0x1000>; 1146 reg-names = "base", "fpci"; 1147 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1149 <&bpmp TEGRA186_CLK_XUSB_SS>, 1150 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1151 <&bpmp TEGRA186_CLK_XUSB_FS>; 1152 clock-names = "dev", "ss", "ss_src", "fs_src"; 1153 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1154 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1155 interconnect-names = "dma-mem", "write"; 1156 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1157 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1158 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1159 power-domain-names = "dev", "ss"; 1160 nvidia,xusb-padctl = <&padctl>; 1161 status = "disabled"; 1162 }; 1163 1164 fuse@3820000 { 1165 compatible = "nvidia,tegra186-efuse"; 1166 reg = <0x0 0x03820000 0x0 0x10000>; 1167 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1168 clock-names = "fuse"; 1169 }; 1170 1171 gic: interrupt-controller@3881000 { 1172 compatible = "arm,gic-400"; 1173 #interrupt-cells = <3>; 1174 interrupt-controller; 1175 reg = <0x0 0x03881000 0x0 0x1000>, 1176 <0x0 0x03882000 0x0 0x2000>, 1177 <0x0 0x03884000 0x0 0x2000>, 1178 <0x0 0x03886000 0x0 0x2000>; 1179 interrupts = <GIC_PPI 9 1180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1181 interrupt-parent = <&gic>; 1182 }; 1183 1184 cec@3960000 { 1185 compatible = "nvidia,tegra186-cec"; 1186 reg = <0x0 0x03960000 0x0 0x10000>; 1187 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&bpmp TEGRA186_CLK_CEC>; 1189 clock-names = "cec"; 1190 status = "disabled"; 1191 }; 1192 1193 hsp_top0: hsp@3c00000 { 1194 compatible = "nvidia,tegra186-hsp"; 1195 reg = <0x0 0x03c00000 0x0 0xa0000>; 1196 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1197 interrupt-names = "doorbell"; 1198 #mbox-cells = <2>; 1199 status = "disabled"; 1200 }; 1201 1202 gen2_i2c: i2c@c240000 { 1203 compatible = "nvidia,tegra186-i2c"; 1204 reg = <0x0 0x0c240000 0x0 0x10000>; 1205 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1209 clock-names = "div-clk"; 1210 resets = <&bpmp TEGRA186_RESET_I2C2>; 1211 reset-names = "i2c"; 1212 dmas = <&gpcdma 22>, <&gpcdma 22>; 1213 dma-names = "rx", "tx"; 1214 status = "disabled"; 1215 }; 1216 1217 gen8_i2c: i2c@c250000 { 1218 compatible = "nvidia,tegra186-i2c"; 1219 reg = <0x0 0x0c250000 0x0 0x10000>; 1220 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1224 clock-names = "div-clk"; 1225 resets = <&bpmp TEGRA186_RESET_I2C8>; 1226 reset-names = "i2c"; 1227 dmas = <&gpcdma 0>, <&gpcdma 0>; 1228 dma-names = "rx", "tx"; 1229 status = "disabled"; 1230 }; 1231 1232 uartc: serial@c280000 { 1233 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1234 reg = <0x0 0x0c280000 0x0 0x40>; 1235 reg-shift = <2>; 1236 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1238 clock-names = "serial"; 1239 resets = <&bpmp TEGRA186_RESET_UARTC>; 1240 reset-names = "serial"; 1241 status = "disabled"; 1242 }; 1243 1244 uartg: serial@c290000 { 1245 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1246 reg = <0x0 0x0c290000 0x0 0x40>; 1247 reg-shift = <2>; 1248 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1250 clock-names = "serial"; 1251 resets = <&bpmp TEGRA186_RESET_UARTG>; 1252 reset-names = "serial"; 1253 status = "disabled"; 1254 }; 1255 1256 rtc: rtc@c2a0000 { 1257 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1258 reg = <0 0x0c2a0000 0 0x10000>; 1259 interrupt-parent = <&pmc>; 1260 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1262 clock-names = "rtc"; 1263 status = "disabled"; 1264 }; 1265 1266 gpio_aon: gpio@c2f0000 { 1267 compatible = "nvidia,tegra186-gpio-aon"; 1268 reg-names = "security", "gpio"; 1269 reg = <0x0 0xc2f0000 0x0 0x1000>, 1270 <0x0 0xc2f1000 0x0 0x1000>; 1271 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1272 gpio-controller; 1273 #gpio-cells = <2>; 1274 interrupt-controller; 1275 #interrupt-cells = <2>; 1276 }; 1277 1278 pwm4: pwm@c340000 { 1279 compatible = "nvidia,tegra186-pwm"; 1280 reg = <0x0 0xc340000 0x0 0x10000>; 1281 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1282 resets = <&bpmp TEGRA186_RESET_PWM4>; 1283 reset-names = "pwm"; 1284 status = "disabled"; 1285 #pwm-cells = <2>; 1286 }; 1287 1288 pmc: pmc@c360000 { 1289 compatible = "nvidia,tegra186-pmc"; 1290 reg = <0 0x0c360000 0 0x10000>, 1291 <0 0x0c370000 0 0x10000>, 1292 <0 0x0c380000 0 0x10000>, 1293 <0 0x0c390000 0 0x10000>; 1294 reg-names = "pmc", "wake", "aotag", "scratch"; 1295 1296 #interrupt-cells = <2>; 1297 interrupt-controller; 1298 1299 sdmmc1_1v8: sdmmc1-1v8 { 1300 pins = "sdmmc1-hv"; 1301 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1302 }; 1303 1304 sdmmc1_3v3: sdmmc1-3v3 { 1305 pins = "sdmmc1-hv"; 1306 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1307 }; 1308 1309 sdmmc2_1v8: sdmmc2-1v8 { 1310 pins = "sdmmc2-hv"; 1311 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1312 }; 1313 1314 sdmmc2_3v3: sdmmc2-3v3 { 1315 pins = "sdmmc2-hv"; 1316 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1317 }; 1318 1319 sdmmc3_1v8: sdmmc3-1v8 { 1320 pins = "sdmmc3-hv"; 1321 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1322 }; 1323 1324 sdmmc3_3v3: sdmmc3-3v3 { 1325 pins = "sdmmc3-hv"; 1326 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1327 }; 1328 }; 1329 1330 ccplex@e000000 { 1331 compatible = "nvidia,tegra186-ccplex-cluster"; 1332 reg = <0x0 0x0e000000 0x0 0x400000>; 1333 1334 nvidia,bpmp = <&bpmp>; 1335 }; 1336 1337 pcie@10003000 { 1338 compatible = "nvidia,tegra186-pcie"; 1339 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1340 device_type = "pci"; 1341 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1342 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1343 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1344 reg-names = "pads", "afi", "cs"; 1345 1346 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1347 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1348 interrupt-names = "intr", "msi"; 1349 1350 #interrupt-cells = <1>; 1351 interrupt-map-mask = <0 0 0 0>; 1352 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1353 1354 bus-range = <0x00 0xff>; 1355 #address-cells = <3>; 1356 #size-cells = <2>; 1357 1358 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1359 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1360 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1361 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1362 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1363 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1364 1365 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1366 <&bpmp TEGRA186_CLK_AFI>, 1367 <&bpmp TEGRA186_CLK_PLLE>; 1368 clock-names = "pex", "afi", "pll_e"; 1369 1370 resets = <&bpmp TEGRA186_RESET_PCIE>, 1371 <&bpmp TEGRA186_RESET_AFI>, 1372 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1373 reset-names = "pex", "afi", "pcie_x"; 1374 1375 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1376 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1377 interconnect-names = "dma-mem", "write"; 1378 1379 iommus = <&smmu TEGRA186_SID_AFI>; 1380 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1381 iommu-map-mask = <0x0>; 1382 1383 status = "disabled"; 1384 1385 pci@1,0 { 1386 device_type = "pci"; 1387 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1388 reg = <0x000800 0 0 0 0>; 1389 status = "disabled"; 1390 1391 #address-cells = <3>; 1392 #size-cells = <2>; 1393 ranges; 1394 1395 nvidia,num-lanes = <2>; 1396 }; 1397 1398 pci@2,0 { 1399 device_type = "pci"; 1400 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1401 reg = <0x001000 0 0 0 0>; 1402 status = "disabled"; 1403 1404 #address-cells = <3>; 1405 #size-cells = <2>; 1406 ranges; 1407 1408 nvidia,num-lanes = <1>; 1409 }; 1410 1411 pci@3,0 { 1412 device_type = "pci"; 1413 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1414 reg = <0x001800 0 0 0 0>; 1415 status = "disabled"; 1416 1417 #address-cells = <3>; 1418 #size-cells = <2>; 1419 ranges; 1420 1421 nvidia,num-lanes = <1>; 1422 }; 1423 }; 1424 1425 smmu: iommu@12000000 { 1426 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1427 reg = <0 0x12000000 0 0x800000>; 1428 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1493 stream-match-mask = <0x7f80>; 1494 #global-interrupts = <1>; 1495 #iommu-cells = <1>; 1496 1497 nvidia,memory-controller = <&mc>; 1498 }; 1499 1500 host1x@13e00000 { 1501 compatible = "nvidia,tegra186-host1x"; 1502 reg = <0x0 0x13e00000 0x0 0x10000>, 1503 <0x0 0x13e10000 0x0 0x10000>; 1504 reg-names = "hypervisor", "vm"; 1505 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1507 interrupt-names = "syncpt", "host1x"; 1508 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1509 clock-names = "host1x"; 1510 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1511 reset-names = "host1x"; 1512 1513 #address-cells = <1>; 1514 #size-cells = <1>; 1515 1516 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1517 1518 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1519 interconnect-names = "dma-mem"; 1520 1521 iommus = <&smmu TEGRA186_SID_HOST1X>; 1522 1523 /* Context isolation domains */ 1524 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1525 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1526 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1527 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1528 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1529 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1530 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1531 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1532 1533 dpaux1: dpaux@15040000 { 1534 compatible = "nvidia,tegra186-dpaux"; 1535 reg = <0x15040000 0x10000>; 1536 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1537 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1538 <&bpmp TEGRA186_CLK_PLLDP>; 1539 clock-names = "dpaux", "parent"; 1540 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1541 reset-names = "dpaux"; 1542 status = "disabled"; 1543 1544 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1545 1546 state_dpaux1_aux: pinmux-aux { 1547 groups = "dpaux-io"; 1548 function = "aux"; 1549 }; 1550 1551 state_dpaux1_i2c: pinmux-i2c { 1552 groups = "dpaux-io"; 1553 function = "i2c"; 1554 }; 1555 1556 state_dpaux1_off: pinmux-off { 1557 groups = "dpaux-io"; 1558 function = "off"; 1559 }; 1560 1561 i2c-bus { 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 }; 1565 }; 1566 1567 display-hub@15200000 { 1568 compatible = "nvidia,tegra186-display"; 1569 reg = <0x15200000 0x00040000>; 1570 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1571 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1572 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1573 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1574 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1575 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1576 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1577 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1578 "wgrp3", "wgrp4", "wgrp5"; 1579 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1580 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1581 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1582 clock-names = "disp", "dsc", "hub"; 1583 status = "disabled"; 1584 1585 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1586 1587 #address-cells = <1>; 1588 #size-cells = <1>; 1589 1590 ranges = <0x15200000 0x15200000 0x40000>; 1591 1592 display@15200000 { 1593 compatible = "nvidia,tegra186-dc"; 1594 reg = <0x15200000 0x10000>; 1595 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1596 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1597 clock-names = "dc"; 1598 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1599 reset-names = "dc"; 1600 1601 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1602 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1603 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1604 interconnect-names = "dma-mem", "read-1"; 1605 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1606 1607 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1608 nvidia,head = <0>; 1609 }; 1610 1611 display@15210000 { 1612 compatible = "nvidia,tegra186-dc"; 1613 reg = <0x15210000 0x10000>; 1614 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1615 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1616 clock-names = "dc"; 1617 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1618 reset-names = "dc"; 1619 1620 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1621 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1622 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1623 interconnect-names = "dma-mem", "read-1"; 1624 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1625 1626 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1627 nvidia,head = <1>; 1628 }; 1629 1630 display@15220000 { 1631 compatible = "nvidia,tegra186-dc"; 1632 reg = <0x15220000 0x10000>; 1633 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1635 clock-names = "dc"; 1636 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1637 reset-names = "dc"; 1638 1639 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1640 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1641 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1642 interconnect-names = "dma-mem", "read-1"; 1643 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1644 1645 nvidia,outputs = <&sor0 &sor1>; 1646 nvidia,head = <2>; 1647 }; 1648 }; 1649 1650 dsia: dsi@15300000 { 1651 compatible = "nvidia,tegra186-dsi"; 1652 reg = <0x15300000 0x10000>; 1653 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1654 clocks = <&bpmp TEGRA186_CLK_DSI>, 1655 <&bpmp TEGRA186_CLK_DSIA_LP>, 1656 <&bpmp TEGRA186_CLK_PLLD>; 1657 clock-names = "dsi", "lp", "parent"; 1658 resets = <&bpmp TEGRA186_RESET_DSI>; 1659 reset-names = "dsi"; 1660 status = "disabled"; 1661 1662 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1663 }; 1664 1665 vic@15340000 { 1666 compatible = "nvidia,tegra186-vic"; 1667 reg = <0x15340000 0x40000>; 1668 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1669 clocks = <&bpmp TEGRA186_CLK_VIC>; 1670 clock-names = "vic"; 1671 resets = <&bpmp TEGRA186_RESET_VIC>; 1672 reset-names = "vic"; 1673 1674 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1675 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1676 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1677 interconnect-names = "dma-mem", "write"; 1678 iommus = <&smmu TEGRA186_SID_VIC>; 1679 }; 1680 1681 nvjpg@15380000 { 1682 compatible = "nvidia,tegra186-nvjpg"; 1683 reg = <0x15380000 0x40000>; 1684 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1685 clock-names = "nvjpg"; 1686 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1687 reset-names = "nvjpg"; 1688 1689 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1690 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1691 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1692 interconnect-names = "dma-mem", "write"; 1693 iommus = <&smmu TEGRA186_SID_NVJPG>; 1694 }; 1695 1696 dsib: dsi@15400000 { 1697 compatible = "nvidia,tegra186-dsi"; 1698 reg = <0x15400000 0x10000>; 1699 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1700 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1701 <&bpmp TEGRA186_CLK_DSIB_LP>, 1702 <&bpmp TEGRA186_CLK_PLLD>; 1703 clock-names = "dsi", "lp", "parent"; 1704 resets = <&bpmp TEGRA186_RESET_DSIB>; 1705 reset-names = "dsi"; 1706 status = "disabled"; 1707 1708 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1709 }; 1710 1711 nvdec@15480000 { 1712 compatible = "nvidia,tegra186-nvdec"; 1713 reg = <0x15480000 0x40000>; 1714 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1715 clock-names = "nvdec"; 1716 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1717 reset-names = "nvdec"; 1718 1719 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1720 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1721 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1722 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1723 interconnect-names = "dma-mem", "read-1", "write"; 1724 iommus = <&smmu TEGRA186_SID_NVDEC>; 1725 }; 1726 1727 nvenc@154c0000 { 1728 compatible = "nvidia,tegra186-nvenc"; 1729 reg = <0x154c0000 0x40000>; 1730 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1731 clock-names = "nvenc"; 1732 resets = <&bpmp TEGRA186_RESET_NVENC>; 1733 reset-names = "nvenc"; 1734 1735 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1736 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1737 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1738 interconnect-names = "dma-mem", "write"; 1739 iommus = <&smmu TEGRA186_SID_NVENC>; 1740 }; 1741 1742 sor0: sor@15540000 { 1743 compatible = "nvidia,tegra186-sor"; 1744 reg = <0x15540000 0x10000>; 1745 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1746 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1747 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1748 <&bpmp TEGRA186_CLK_PLLD2>, 1749 <&bpmp TEGRA186_CLK_PLLDP>, 1750 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1751 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1752 clock-names = "sor", "out", "parent", "dp", "safe", 1753 "pad"; 1754 resets = <&bpmp TEGRA186_RESET_SOR0>; 1755 reset-names = "sor"; 1756 pinctrl-0 = <&state_dpaux_aux>; 1757 pinctrl-1 = <&state_dpaux_i2c>; 1758 pinctrl-2 = <&state_dpaux_off>; 1759 pinctrl-names = "aux", "i2c", "off"; 1760 status = "disabled"; 1761 1762 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1763 nvidia,interface = <0>; 1764 }; 1765 1766 sor1: sor@15580000 { 1767 compatible = "nvidia,tegra186-sor"; 1768 reg = <0x15580000 0x10000>; 1769 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1770 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1771 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1772 <&bpmp TEGRA186_CLK_PLLD3>, 1773 <&bpmp TEGRA186_CLK_PLLDP>, 1774 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1775 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1776 clock-names = "sor", "out", "parent", "dp", "safe", 1777 "pad"; 1778 resets = <&bpmp TEGRA186_RESET_SOR1>; 1779 reset-names = "sor"; 1780 pinctrl-0 = <&state_dpaux1_aux>; 1781 pinctrl-1 = <&state_dpaux1_i2c>; 1782 pinctrl-2 = <&state_dpaux1_off>; 1783 pinctrl-names = "aux", "i2c", "off"; 1784 status = "disabled"; 1785 1786 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1787 nvidia,interface = <1>; 1788 }; 1789 1790 dpaux: dpaux@155c0000 { 1791 compatible = "nvidia,tegra186-dpaux"; 1792 reg = <0x155c0000 0x10000>; 1793 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1794 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1795 <&bpmp TEGRA186_CLK_PLLDP>; 1796 clock-names = "dpaux", "parent"; 1797 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1798 reset-names = "dpaux"; 1799 status = "disabled"; 1800 1801 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1802 1803 state_dpaux_aux: pinmux-aux { 1804 groups = "dpaux-io"; 1805 function = "aux"; 1806 }; 1807 1808 state_dpaux_i2c: pinmux-i2c { 1809 groups = "dpaux-io"; 1810 function = "i2c"; 1811 }; 1812 1813 state_dpaux_off: pinmux-off { 1814 groups = "dpaux-io"; 1815 function = "off"; 1816 }; 1817 1818 i2c-bus { 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 }; 1822 }; 1823 1824 padctl@15880000 { 1825 compatible = "nvidia,tegra186-dsi-padctl"; 1826 reg = <0x15880000 0x10000>; 1827 resets = <&bpmp TEGRA186_RESET_DSI>; 1828 reset-names = "dsi"; 1829 status = "disabled"; 1830 }; 1831 1832 dsic: dsi@15900000 { 1833 compatible = "nvidia,tegra186-dsi"; 1834 reg = <0x15900000 0x10000>; 1835 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1836 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1837 <&bpmp TEGRA186_CLK_DSIC_LP>, 1838 <&bpmp TEGRA186_CLK_PLLD>; 1839 clock-names = "dsi", "lp", "parent"; 1840 resets = <&bpmp TEGRA186_RESET_DSIC>; 1841 reset-names = "dsi"; 1842 status = "disabled"; 1843 1844 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1845 }; 1846 1847 dsid: dsi@15940000 { 1848 compatible = "nvidia,tegra186-dsi"; 1849 reg = <0x15940000 0x10000>; 1850 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1851 clocks = <&bpmp TEGRA186_CLK_DSID>, 1852 <&bpmp TEGRA186_CLK_DSID_LP>, 1853 <&bpmp TEGRA186_CLK_PLLD>; 1854 clock-names = "dsi", "lp", "parent"; 1855 resets = <&bpmp TEGRA186_RESET_DSID>; 1856 reset-names = "dsi"; 1857 status = "disabled"; 1858 1859 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1860 }; 1861 }; 1862 1863 gpu@17000000 { 1864 compatible = "nvidia,gp10b"; 1865 reg = <0x0 0x17000000 0x0 0x1000000>, 1866 <0x0 0x18000000 0x0 0x1000000>; 1867 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1869 interrupt-names = "stall", "nonstall"; 1870 1871 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1872 <&bpmp TEGRA186_CLK_GPU>; 1873 clock-names = "gpu", "pwr"; 1874 resets = <&bpmp TEGRA186_RESET_GPU>; 1875 reset-names = "gpu"; 1876 status = "disabled"; 1877 1878 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1879 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1880 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1881 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1882 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1883 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1884 }; 1885 1886 sram@30000000 { 1887 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1888 reg = <0x0 0x30000000 0x0 0x50000>; 1889 #address-cells = <1>; 1890 #size-cells = <1>; 1891 ranges = <0x0 0x0 0x30000000 0x50000>; 1892 no-memory-wc; 1893 1894 cpu_bpmp_tx: sram@4e000 { 1895 reg = <0x4e000 0x1000>; 1896 label = "cpu-bpmp-tx"; 1897 pool; 1898 }; 1899 1900 cpu_bpmp_rx: sram@4f000 { 1901 reg = <0x4f000 0x1000>; 1902 label = "cpu-bpmp-rx"; 1903 pool; 1904 }; 1905 }; 1906 1907 bpmp: bpmp { 1908 compatible = "nvidia,tegra186-bpmp"; 1909 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1910 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1911 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1912 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1913 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1914 iommus = <&smmu TEGRA186_SID_BPMP>; 1915 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1916 TEGRA_HSP_DB_MASTER_BPMP>; 1917 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1918 #clock-cells = <1>; 1919 #reset-cells = <1>; 1920 #power-domain-cells = <1>; 1921 1922 bpmp_i2c: i2c { 1923 compatible = "nvidia,tegra186-bpmp-i2c"; 1924 nvidia,bpmp-bus-id = <5>; 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 status = "disabled"; 1928 }; 1929 1930 bpmp_thermal: thermal { 1931 compatible = "nvidia,tegra186-bpmp-thermal"; 1932 #thermal-sensor-cells = <1>; 1933 }; 1934 }; 1935 1936 cpus { 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 1940 denver_0: cpu@0 { 1941 compatible = "nvidia,tegra186-denver"; 1942 device_type = "cpu"; 1943 i-cache-size = <0x20000>; 1944 i-cache-line-size = <64>; 1945 i-cache-sets = <512>; 1946 d-cache-size = <0x10000>; 1947 d-cache-line-size = <64>; 1948 d-cache-sets = <256>; 1949 next-level-cache = <&L2_DENVER>; 1950 reg = <0x000>; 1951 }; 1952 1953 denver_1: cpu@1 { 1954 compatible = "nvidia,tegra186-denver"; 1955 device_type = "cpu"; 1956 i-cache-size = <0x20000>; 1957 i-cache-line-size = <64>; 1958 i-cache-sets = <512>; 1959 d-cache-size = <0x10000>; 1960 d-cache-line-size = <64>; 1961 d-cache-sets = <256>; 1962 next-level-cache = <&L2_DENVER>; 1963 reg = <0x001>; 1964 }; 1965 1966 ca57_0: cpu@2 { 1967 compatible = "arm,cortex-a57"; 1968 device_type = "cpu"; 1969 i-cache-size = <0xC000>; 1970 i-cache-line-size = <64>; 1971 i-cache-sets = <256>; 1972 d-cache-size = <0x8000>; 1973 d-cache-line-size = <64>; 1974 d-cache-sets = <256>; 1975 next-level-cache = <&L2_A57>; 1976 reg = <0x100>; 1977 }; 1978 1979 ca57_1: cpu@3 { 1980 compatible = "arm,cortex-a57"; 1981 device_type = "cpu"; 1982 i-cache-size = <0xC000>; 1983 i-cache-line-size = <64>; 1984 i-cache-sets = <256>; 1985 d-cache-size = <0x8000>; 1986 d-cache-line-size = <64>; 1987 d-cache-sets = <256>; 1988 next-level-cache = <&L2_A57>; 1989 reg = <0x101>; 1990 }; 1991 1992 ca57_2: cpu@4 { 1993 compatible = "arm,cortex-a57"; 1994 device_type = "cpu"; 1995 i-cache-size = <0xC000>; 1996 i-cache-line-size = <64>; 1997 i-cache-sets = <256>; 1998 d-cache-size = <0x8000>; 1999 d-cache-line-size = <64>; 2000 d-cache-sets = <256>; 2001 next-level-cache = <&L2_A57>; 2002 reg = <0x102>; 2003 }; 2004 2005 ca57_3: cpu@5 { 2006 compatible = "arm,cortex-a57"; 2007 device_type = "cpu"; 2008 i-cache-size = <0xC000>; 2009 i-cache-line-size = <64>; 2010 i-cache-sets = <256>; 2011 d-cache-size = <0x8000>; 2012 d-cache-line-size = <64>; 2013 d-cache-sets = <256>; 2014 next-level-cache = <&L2_A57>; 2015 reg = <0x103>; 2016 }; 2017 2018 L2_DENVER: l2-cache0 { 2019 compatible = "cache"; 2020 cache-unified; 2021 cache-level = <2>; 2022 cache-size = <0x200000>; 2023 cache-line-size = <64>; 2024 cache-sets = <2048>; 2025 }; 2026 2027 L2_A57: l2-cache1 { 2028 compatible = "cache"; 2029 cache-unified; 2030 cache-level = <2>; 2031 cache-size = <0x200000>; 2032 cache-line-size = <64>; 2033 cache-sets = <2048>; 2034 }; 2035 }; 2036 2037 pmu-a57 { 2038 compatible = "arm,cortex-a57-pmu"; 2039 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2043 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2044 }; 2045 2046 pmu-denver { 2047 compatible = "nvidia,denver-pmu"; 2048 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2050 interrupt-affinity = <&denver_0 &denver_1>; 2051 }; 2052 2053 sound { 2054 status = "disabled"; 2055 2056 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2057 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2058 clock-names = "pll_a", "plla_out0"; 2059 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2060 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2061 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2062 assigned-clock-parents = <0>, 2063 <&bpmp TEGRA186_CLK_PLLA>, 2064 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2065 /* 2066 * PLLA supports dynamic ramp. Below initial rate is chosen 2067 * for this to work and oscillate between base rates required 2068 * for 8x and 11.025x sample rate streams. 2069 */ 2070 assigned-clock-rates = <258000000>; 2071 2072 iommus = <&smmu TEGRA186_SID_APE>; 2073 }; 2074 2075 thermal-zones { 2076 /* Cortex-A57 cluster */ 2077 cpu-thermal { 2078 polling-delay = <0>; 2079 polling-delay-passive = <1000>; 2080 2081 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2082 2083 trips { 2084 critical { 2085 temperature = <101000>; 2086 hysteresis = <0>; 2087 type = "critical"; 2088 }; 2089 }; 2090 2091 cooling-maps { 2092 }; 2093 }; 2094 2095 /* Denver cluster */ 2096 aux-thermal { 2097 polling-delay = <0>; 2098 polling-delay-passive = <1000>; 2099 2100 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2101 2102 trips { 2103 critical { 2104 temperature = <101000>; 2105 hysteresis = <0>; 2106 type = "critical"; 2107 }; 2108 }; 2109 2110 cooling-maps { 2111 }; 2112 }; 2113 2114 gpu-thermal { 2115 polling-delay = <0>; 2116 polling-delay-passive = <1000>; 2117 2118 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2119 2120 trips { 2121 critical { 2122 temperature = <101000>; 2123 hysteresis = <0>; 2124 type = "critical"; 2125 }; 2126 }; 2127 2128 cooling-maps { 2129 }; 2130 }; 2131 2132 pll-thermal { 2133 polling-delay = <0>; 2134 polling-delay-passive = <1000>; 2135 2136 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2137 2138 trips { 2139 critical { 2140 temperature = <101000>; 2141 hysteresis = <0>; 2142 type = "critical"; 2143 }; 2144 }; 2145 2146 cooling-maps { 2147 }; 2148 }; 2149 2150 ao-thermal { 2151 polling-delay = <0>; 2152 polling-delay-passive = <1000>; 2153 2154 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2155 2156 trips { 2157 critical { 2158 temperature = <101000>; 2159 hysteresis = <0>; 2160 type = "critical"; 2161 }; 2162 }; 2163 2164 cooling-maps { 2165 }; 2166 }; 2167 }; 2168 2169 timer { 2170 compatible = "arm,armv8-timer"; 2171 interrupts = <GIC_PPI 13 2172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2173 <GIC_PPI 14 2174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2175 <GIC_PPI 11 2176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2177 <GIC_PPI 10 2178 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2179 interrupt-parent = <&gic>; 2180 always-on; 2181 }; 2182}; 2183