1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra186-clock.h>
3#include <dt-bindings/gpio/tegra186-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/memory/tegra186-mc.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8#include <dt-bindings/power/tegra186-powergate.h>
9#include <dt-bindings/reset/tegra186-reset.h>
10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12/ {
13	compatible = "nvidia,tegra186";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	misc@100000 {
19		compatible = "nvidia,tegra186-misc";
20		reg = <0x0 0x00100000 0x0 0xf000>,
21		      <0x0 0x0010f000 0x0 0x1000>;
22	};
23
24	gpio: gpio@2200000 {
25		compatible = "nvidia,tegra186-gpio";
26		reg-names = "security", "gpio";
27		reg = <0x0 0x2200000 0x0 0x10000>,
28		      <0x0 0x2210000 0x0 0x10000>;
29		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
30			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35		#interrupt-cells = <2>;
36		interrupt-controller;
37		#gpio-cells = <2>;
38		gpio-controller;
39	};
40
41	ethernet@2490000 {
42		compatible = "nvidia,tegra186-eqos",
43			     "snps,dwc-qos-ethernet-4.10";
44		reg = <0x0 0x02490000 0x0 0x10000>;
45		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57			 <&bpmp TEGRA186_CLK_EQOS_RX>,
58			 <&bpmp TEGRA186_CLK_EQOS_TX>,
59			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61		resets = <&bpmp TEGRA186_RESET_EQOS>;
62		reset-names = "eqos";
63		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65		interconnect-names = "dma-mem", "write";
66		iommus = <&smmu TEGRA186_SID_EQOS>;
67		status = "disabled";
68
69		snps,write-requests = <1>;
70		snps,read-requests = <3>;
71		snps,burst-map = <0x7>;
72		snps,txpbl = <32>;
73		snps,rxpbl = <8>;
74	};
75
76	aconnect {
77		compatible = "nvidia,tegra186-aconnect",
78			     "nvidia,tegra210-aconnect";
79		clocks = <&bpmp TEGRA186_CLK_APE>,
80			 <&bpmp TEGRA186_CLK_APB2APE>;
81		clock-names = "ape", "apb2ape";
82		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
83		#address-cells = <1>;
84		#size-cells = <1>;
85		ranges = <0x02900000 0x0 0x02900000 0x200000>;
86		status = "disabled";
87
88		adma: dma-controller@2930000 {
89			compatible = "nvidia,tegra186-adma";
90			reg = <0x02930000 0x20000>;
91			interrupt-parent = <&agic>;
92			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
94				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
95				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
96				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
98				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
99				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
108				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
109				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
110				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
111				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
112				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
113				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
114				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
115				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
116				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
117				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
118				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
119				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
120				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
121				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
122				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
123				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
124			#dma-cells = <1>;
125			clocks = <&bpmp TEGRA186_CLK_AHUB>;
126			clock-names = "d_audio";
127			status = "disabled";
128		};
129
130		agic: interrupt-controller@2a40000 {
131			compatible = "nvidia,tegra186-agic",
132				     "nvidia,tegra210-agic";
133			#interrupt-cells = <3>;
134			interrupt-controller;
135			reg = <0x02a41000 0x1000>,
136			      <0x02a42000 0x2000>;
137			interrupts = <GIC_SPI 145
138				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
139			clocks = <&bpmp TEGRA186_CLK_APE>;
140			clock-names = "clk";
141			status = "disabled";
142		};
143
144		tegra_ahub: ahub@2900800 {
145			compatible = "nvidia,tegra186-ahub";
146			reg = <0x02900800 0x800>;
147			clocks = <&bpmp TEGRA186_CLK_AHUB>;
148			clock-names = "ahub";
149			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
151			#address-cells = <1>;
152			#size-cells = <1>;
153			ranges = <0x02900800 0x02900800 0x11800>;
154			status = "disabled";
155
156			tegra_admaif: admaif@290f000 {
157				compatible = "nvidia,tegra186-admaif";
158				reg = <0x0290f000 0x1000>;
159				dmas = <&adma 1>, <&adma 1>,
160				       <&adma 2>, <&adma 2>,
161				       <&adma 3>, <&adma 3>,
162				       <&adma 4>, <&adma 4>,
163				       <&adma 5>, <&adma 5>,
164				       <&adma 6>, <&adma 6>,
165				       <&adma 7>, <&adma 7>,
166				       <&adma 8>, <&adma 8>,
167				       <&adma 9>, <&adma 9>,
168				       <&adma 10>, <&adma 10>,
169				       <&adma 11>, <&adma 11>,
170				       <&adma 12>, <&adma 12>,
171				       <&adma 13>, <&adma 13>,
172				       <&adma 14>, <&adma 14>,
173				       <&adma 15>, <&adma 15>,
174				       <&adma 16>, <&adma 16>,
175				       <&adma 17>, <&adma 17>,
176				       <&adma 18>, <&adma 18>,
177				       <&adma 19>, <&adma 19>,
178				       <&adma 20>, <&adma 20>;
179				dma-names = "rx1", "tx1",
180					    "rx2", "tx2",
181					    "rx3", "tx3",
182					    "rx4", "tx4",
183					    "rx5", "tx5",
184					    "rx6", "tx6",
185					    "rx7", "tx7",
186					    "rx8", "tx8",
187					    "rx9", "tx9",
188					    "rx10", "tx10",
189					    "rx11", "tx11",
190					    "rx12", "tx12",
191					    "rx13", "tx13",
192					    "rx14", "tx14",
193					    "rx15", "tx15",
194					    "rx16", "tx16",
195					    "rx17", "tx17",
196					    "rx18", "tx18",
197					    "rx19", "tx19",
198					    "rx20", "tx20";
199				status = "disabled";
200			};
201
202			tegra_i2s1: i2s@2901000 {
203				compatible = "nvidia,tegra186-i2s",
204					     "nvidia,tegra210-i2s";
205				reg = <0x2901000 0x100>;
206				clocks = <&bpmp TEGRA186_CLK_I2S1>,
207					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
208				clock-names = "i2s", "sync_input";
209				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211				assigned-clock-rates = <1536000>;
212				sound-name-prefix = "I2S1";
213				status = "disabled";
214			};
215
216			tegra_i2s2: i2s@2901100 {
217				compatible = "nvidia,tegra186-i2s",
218					     "nvidia,tegra210-i2s";
219				reg = <0x2901100 0x100>;
220				clocks = <&bpmp TEGRA186_CLK_I2S2>,
221					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
222				clock-names = "i2s", "sync_input";
223				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225				assigned-clock-rates = <1536000>;
226				sound-name-prefix = "I2S2";
227				status = "disabled";
228			};
229
230			tegra_i2s3: i2s@2901200 {
231				compatible = "nvidia,tegra186-i2s",
232					     "nvidia,tegra210-i2s";
233				reg = <0x2901200 0x100>;
234				clocks = <&bpmp TEGRA186_CLK_I2S3>,
235					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
236				clock-names = "i2s", "sync_input";
237				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
239				assigned-clock-rates = <1536000>;
240				sound-name-prefix = "I2S3";
241				status = "disabled";
242			};
243
244			tegra_i2s4: i2s@2901300 {
245				compatible = "nvidia,tegra186-i2s",
246					     "nvidia,tegra210-i2s";
247				reg = <0x2901300 0x100>;
248				clocks = <&bpmp TEGRA186_CLK_I2S4>,
249					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
250				clock-names = "i2s", "sync_input";
251				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
252				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253				assigned-clock-rates = <1536000>;
254				sound-name-prefix = "I2S4";
255				status = "disabled";
256			};
257
258			tegra_i2s5: i2s@2901400 {
259				compatible = "nvidia,tegra186-i2s",
260					     "nvidia,tegra210-i2s";
261				reg = <0x2901400 0x100>;
262				clocks = <&bpmp TEGRA186_CLK_I2S5>,
263					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
264				clock-names = "i2s", "sync_input";
265				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
266				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267				assigned-clock-rates = <1536000>;
268				sound-name-prefix = "I2S5";
269				status = "disabled";
270			};
271
272			tegra_i2s6: i2s@2901500 {
273				compatible = "nvidia,tegra186-i2s",
274					     "nvidia,tegra210-i2s";
275				reg = <0x2901500 0x100>;
276				clocks = <&bpmp TEGRA186_CLK_I2S6>,
277					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
278				clock-names = "i2s", "sync_input";
279				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
280				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281				assigned-clock-rates = <1536000>;
282				sound-name-prefix = "I2S6";
283				status = "disabled";
284			};
285
286			tegra_dmic1: dmic@2904000 {
287				compatible = "nvidia,tegra210-dmic";
288				reg = <0x2904000 0x100>;
289				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
290				clock-names = "dmic";
291				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
292				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
293				assigned-clock-rates = <3072000>;
294				sound-name-prefix = "DMIC1";
295				status = "disabled";
296			};
297
298			tegra_dmic2: dmic@2904100 {
299				compatible = "nvidia,tegra210-dmic";
300				reg = <0x2904100 0x100>;
301				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
302				clock-names = "dmic";
303				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
304				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
305				assigned-clock-rates = <3072000>;
306				sound-name-prefix = "DMIC2";
307				status = "disabled";
308			};
309
310			tegra_dmic3: dmic@2904200 {
311				compatible = "nvidia,tegra210-dmic";
312				reg = <0x2904200 0x100>;
313				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
314				clock-names = "dmic";
315				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
316				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
317				assigned-clock-rates = <3072000>;
318				sound-name-prefix = "DMIC3";
319				status = "disabled";
320			};
321
322			tegra_dmic4: dmic@2904300 {
323				compatible = "nvidia,tegra210-dmic";
324				reg = <0x2904300 0x100>;
325				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
326				clock-names = "dmic";
327				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
328				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
329				assigned-clock-rates = <3072000>;
330				sound-name-prefix = "DMIC4";
331				status = "disabled";
332			};
333
334			tegra_dspk1: dspk@2905000 {
335				compatible = "nvidia,tegra186-dspk";
336				reg = <0x2905000 0x100>;
337				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
338				clock-names = "dspk";
339				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
340				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
341				assigned-clock-rates = <12288000>;
342				sound-name-prefix = "DSPK1";
343				status = "disabled";
344			};
345
346			tegra_dspk2: dspk@2905100 {
347				compatible = "nvidia,tegra186-dspk";
348				reg = <0x2905100 0x100>;
349				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
350				clock-names = "dspk";
351				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
352				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
353				assigned-clock-rates = <12288000>;
354				sound-name-prefix = "DSPK2";
355				status = "disabled";
356			};
357		};
358	};
359
360	mc: memory-controller@2c00000 {
361		compatible = "nvidia,tegra186-mc";
362		reg = <0x0 0x02c00000 0x0 0xb0000>;
363		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
364		status = "disabled";
365
366		#interconnect-cells = <1>;
367		#address-cells = <2>;
368		#size-cells = <2>;
369
370		ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
371
372		/*
373		 * Memory clients have access to all 40 bits that the memory
374		 * controller can address.
375		 */
376		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
377
378		emc: external-memory-controller@2c60000 {
379			compatible = "nvidia,tegra186-emc";
380			reg = <0x0 0x02c60000 0x0 0x50000>;
381			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
382			clocks = <&bpmp TEGRA186_CLK_EMC>;
383			clock-names = "emc";
384
385			#interconnect-cells = <0>;
386
387			nvidia,bpmp = <&bpmp>;
388		};
389	};
390
391	uarta: serial@3100000 {
392		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
393		reg = <0x0 0x03100000 0x0 0x40>;
394		reg-shift = <2>;
395		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
396		clocks = <&bpmp TEGRA186_CLK_UARTA>;
397		clock-names = "serial";
398		resets = <&bpmp TEGRA186_RESET_UARTA>;
399		reset-names = "serial";
400		status = "disabled";
401	};
402
403	uartb: serial@3110000 {
404		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
405		reg = <0x0 0x03110000 0x0 0x40>;
406		reg-shift = <2>;
407		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
408		clocks = <&bpmp TEGRA186_CLK_UARTB>;
409		clock-names = "serial";
410		resets = <&bpmp TEGRA186_RESET_UARTB>;
411		reset-names = "serial";
412		status = "disabled";
413	};
414
415	uartd: serial@3130000 {
416		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
417		reg = <0x0 0x03130000 0x0 0x40>;
418		reg-shift = <2>;
419		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
420		clocks = <&bpmp TEGRA186_CLK_UARTD>;
421		clock-names = "serial";
422		resets = <&bpmp TEGRA186_RESET_UARTD>;
423		reset-names = "serial";
424		status = "disabled";
425	};
426
427	uarte: serial@3140000 {
428		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
429		reg = <0x0 0x03140000 0x0 0x40>;
430		reg-shift = <2>;
431		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
432		clocks = <&bpmp TEGRA186_CLK_UARTE>;
433		clock-names = "serial";
434		resets = <&bpmp TEGRA186_RESET_UARTE>;
435		reset-names = "serial";
436		status = "disabled";
437	};
438
439	uartf: serial@3150000 {
440		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
441		reg = <0x0 0x03150000 0x0 0x40>;
442		reg-shift = <2>;
443		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
444		clocks = <&bpmp TEGRA186_CLK_UARTF>;
445		clock-names = "serial";
446		resets = <&bpmp TEGRA186_RESET_UARTF>;
447		reset-names = "serial";
448		status = "disabled";
449	};
450
451	gen1_i2c: i2c@3160000 {
452		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
453		reg = <0x0 0x03160000 0x0 0x10000>;
454		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
455		#address-cells = <1>;
456		#size-cells = <0>;
457		clocks = <&bpmp TEGRA186_CLK_I2C1>;
458		clock-names = "div-clk";
459		resets = <&bpmp TEGRA186_RESET_I2C1>;
460		reset-names = "i2c";
461		status = "disabled";
462	};
463
464	cam_i2c: i2c@3180000 {
465		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
466		reg = <0x0 0x03180000 0x0 0x10000>;
467		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
468		#address-cells = <1>;
469		#size-cells = <0>;
470		clocks = <&bpmp TEGRA186_CLK_I2C3>;
471		clock-names = "div-clk";
472		resets = <&bpmp TEGRA186_RESET_I2C3>;
473		reset-names = "i2c";
474		status = "disabled";
475	};
476
477	/* shares pads with dpaux1 */
478	dp_aux_ch1_i2c: i2c@3190000 {
479		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
480		reg = <0x0 0x03190000 0x0 0x10000>;
481		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
482		#address-cells = <1>;
483		#size-cells = <0>;
484		clocks = <&bpmp TEGRA186_CLK_I2C4>;
485		clock-names = "div-clk";
486		resets = <&bpmp TEGRA186_RESET_I2C4>;
487		reset-names = "i2c";
488		pinctrl-names = "default", "idle";
489		pinctrl-0 = <&state_dpaux1_i2c>;
490		pinctrl-1 = <&state_dpaux1_off>;
491		status = "disabled";
492	};
493
494	/* controlled by BPMP, should not be enabled */
495	pwr_i2c: i2c@31a0000 {
496		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
497		reg = <0x0 0x031a0000 0x0 0x10000>;
498		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
499		#address-cells = <1>;
500		#size-cells = <0>;
501		clocks = <&bpmp TEGRA186_CLK_I2C5>;
502		clock-names = "div-clk";
503		resets = <&bpmp TEGRA186_RESET_I2C5>;
504		reset-names = "i2c";
505		status = "disabled";
506	};
507
508	/* shares pads with dpaux0 */
509	dp_aux_ch0_i2c: i2c@31b0000 {
510		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
511		reg = <0x0 0x031b0000 0x0 0x10000>;
512		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
513		#address-cells = <1>;
514		#size-cells = <0>;
515		clocks = <&bpmp TEGRA186_CLK_I2C6>;
516		clock-names = "div-clk";
517		resets = <&bpmp TEGRA186_RESET_I2C6>;
518		reset-names = "i2c";
519		pinctrl-names = "default", "idle";
520		pinctrl-0 = <&state_dpaux_i2c>;
521		pinctrl-1 = <&state_dpaux_off>;
522		status = "disabled";
523	};
524
525	gen7_i2c: i2c@31c0000 {
526		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
527		reg = <0x0 0x031c0000 0x0 0x10000>;
528		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
529		#address-cells = <1>;
530		#size-cells = <0>;
531		clocks = <&bpmp TEGRA186_CLK_I2C7>;
532		clock-names = "div-clk";
533		resets = <&bpmp TEGRA186_RESET_I2C7>;
534		reset-names = "i2c";
535		status = "disabled";
536	};
537
538	gen9_i2c: i2c@31e0000 {
539		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
540		reg = <0x0 0x031e0000 0x0 0x10000>;
541		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
542		#address-cells = <1>;
543		#size-cells = <0>;
544		clocks = <&bpmp TEGRA186_CLK_I2C9>;
545		clock-names = "div-clk";
546		resets = <&bpmp TEGRA186_RESET_I2C9>;
547		reset-names = "i2c";
548		status = "disabled";
549	};
550
551	sdmmc1: mmc@3400000 {
552		compatible = "nvidia,tegra186-sdhci";
553		reg = <0x0 0x03400000 0x0 0x10000>;
554		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
555		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
556			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
557		clock-names = "sdhci", "tmclk";
558		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
559		reset-names = "sdhci";
560		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
561				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
562		interconnect-names = "dma-mem", "write";
563		iommus = <&smmu TEGRA186_SID_SDMMC1>;
564		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
565		pinctrl-0 = <&sdmmc1_3v3>;
566		pinctrl-1 = <&sdmmc1_1v8>;
567		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
568		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
569		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
570		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
571		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
572		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
573		nvidia,default-tap = <0x5>;
574		nvidia,default-trim = <0xb>;
575		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
576				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
577		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
578		status = "disabled";
579	};
580
581	sdmmc2: mmc@3420000 {
582		compatible = "nvidia,tegra186-sdhci";
583		reg = <0x0 0x03420000 0x0 0x10000>;
584		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
585		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
586			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
587		clock-names = "sdhci", "tmclk";
588		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
589		reset-names = "sdhci";
590		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
591				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
592		interconnect-names = "dma-mem", "write";
593		iommus = <&smmu TEGRA186_SID_SDMMC2>;
594		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
595		pinctrl-0 = <&sdmmc2_3v3>;
596		pinctrl-1 = <&sdmmc2_1v8>;
597		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
598		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
599		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
600		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
601		nvidia,default-tap = <0x5>;
602		nvidia,default-trim = <0xb>;
603		status = "disabled";
604	};
605
606	sdmmc3: mmc@3440000 {
607		compatible = "nvidia,tegra186-sdhci";
608		reg = <0x0 0x03440000 0x0 0x10000>;
609		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
610		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
611			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
612		clock-names = "sdhci", "tmclk";
613		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
614		reset-names = "sdhci";
615		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
616				<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
617		interconnect-names = "dma-mem", "write";
618		iommus = <&smmu TEGRA186_SID_SDMMC3>;
619		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
620		pinctrl-0 = <&sdmmc3_3v3>;
621		pinctrl-1 = <&sdmmc3_1v8>;
622		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
623		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
624		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
625		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
626		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
627		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
628		nvidia,default-tap = <0x5>;
629		nvidia,default-trim = <0xb>;
630		status = "disabled";
631	};
632
633	sdmmc4: mmc@3460000 {
634		compatible = "nvidia,tegra186-sdhci";
635		reg = <0x0 0x03460000 0x0 0x10000>;
636		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
637		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
638			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
639		clock-names = "sdhci", "tmclk";
640		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
641				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
642		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
643		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
644		reset-names = "sdhci";
645		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
646				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
647		interconnect-names = "dma-mem", "write";
648		iommus = <&smmu TEGRA186_SID_SDMMC4>;
649		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
650		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
651		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
652		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
653		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
654		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
655		nvidia,default-tap = <0x9>;
656		nvidia,default-trim = <0x5>;
657		nvidia,dqs-trim = <63>;
658		mmc-hs400-1_8v;
659		supports-cqe;
660		status = "disabled";
661	};
662
663	hda@3510000 {
664		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
665		reg = <0x0 0x03510000 0x0 0x10000>;
666		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
667		clocks = <&bpmp TEGRA186_CLK_HDA>,
668			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
669			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
670		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
671		resets = <&bpmp TEGRA186_RESET_HDA>,
672			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
673			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
674		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
675		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
676		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
677				<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
678		interconnect-names = "dma-mem", "write";
679		iommus = <&smmu TEGRA186_SID_HDA>;
680		status = "disabled";
681	};
682
683	padctl: padctl@3520000 {
684		compatible = "nvidia,tegra186-xusb-padctl";
685		reg = <0x0 0x03520000 0x0 0x1000>,
686		      <0x0 0x03540000 0x0 0x1000>;
687		reg-names = "padctl", "ao";
688
689		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
690		reset-names = "padctl";
691
692		status = "disabled";
693
694		pads {
695			usb2 {
696				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
697				clock-names = "trk";
698				status = "disabled";
699
700				lanes {
701					usb2-0 {
702						status = "disabled";
703						#phy-cells = <0>;
704					};
705
706					usb2-1 {
707						status = "disabled";
708						#phy-cells = <0>;
709					};
710
711					usb2-2 {
712						status = "disabled";
713						#phy-cells = <0>;
714					};
715				};
716			};
717
718			hsic {
719				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
720				clock-names = "trk";
721				status = "disabled";
722
723				lanes {
724					hsic-0 {
725						status = "disabled";
726						#phy-cells = <0>;
727					};
728				};
729			};
730
731			usb3 {
732				status = "disabled";
733
734				lanes {
735					usb3-0 {
736						status = "disabled";
737						#phy-cells = <0>;
738					};
739
740					usb3-1 {
741						status = "disabled";
742						#phy-cells = <0>;
743					};
744
745					usb3-2 {
746						status = "disabled";
747						#phy-cells = <0>;
748					};
749				};
750			};
751		};
752
753		ports {
754			usb2-0 {
755				status = "disabled";
756			};
757
758			usb2-1 {
759				status = "disabled";
760			};
761
762			usb2-2 {
763				status = "disabled";
764			};
765
766			hsic-0 {
767				status = "disabled";
768			};
769
770			usb3-0 {
771				status = "disabled";
772			};
773
774			usb3-1 {
775				status = "disabled";
776			};
777
778			usb3-2 {
779				status = "disabled";
780			};
781		};
782	};
783
784	usb@3530000 {
785		compatible = "nvidia,tegra186-xusb";
786		reg = <0x0 0x03530000 0x0 0x8000>,
787		      <0x0 0x03538000 0x0 0x1000>;
788		reg-names = "hcd", "fpci";
789		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
790			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
791		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
792			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
793			 <&bpmp TEGRA186_CLK_XUSB_SS>,
794			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
795			 <&bpmp TEGRA186_CLK_CLK_M>,
796			 <&bpmp TEGRA186_CLK_XUSB_FS>,
797			 <&bpmp TEGRA186_CLK_PLLU>,
798			 <&bpmp TEGRA186_CLK_CLK_M>,
799			 <&bpmp TEGRA186_CLK_PLLE>;
800		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
801			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
802			      "pll_u_480m", "clk_m", "pll_e";
803		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
804				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
805		power-domain-names = "xusb_host", "xusb_ss";
806		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
807				<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
808		interconnect-names = "dma-mem", "write";
809		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
810		#address-cells = <1>;
811		#size-cells = <0>;
812		status = "disabled";
813
814		nvidia,xusb-padctl = <&padctl>;
815	};
816
817	usb@3550000 {
818		compatible = "nvidia,tegra186-xudc";
819		reg = <0x0 0x03550000 0x0 0x8000>,
820		      <0x0 0x03558000 0x0 0x1000>;
821		reg-names = "base", "fpci";
822		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
823		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
824			 <&bpmp TEGRA186_CLK_XUSB_SS>,
825			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
826			 <&bpmp TEGRA186_CLK_XUSB_FS>;
827		clock-names = "dev", "ss", "ss_src", "fs_src";
828		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
829		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
830				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
831		power-domain-names = "dev", "ss";
832		nvidia,xusb-padctl = <&padctl>;
833		status = "disabled";
834	};
835
836	fuse@3820000 {
837		compatible = "nvidia,tegra186-efuse";
838		reg = <0x0 0x03820000 0x0 0x10000>;
839		clocks = <&bpmp TEGRA186_CLK_FUSE>;
840		clock-names = "fuse";
841	};
842
843	gic: interrupt-controller@3881000 {
844		compatible = "arm,gic-400";
845		#interrupt-cells = <3>;
846		interrupt-controller;
847		reg = <0x0 0x03881000 0x0 0x1000>,
848		      <0x0 0x03882000 0x0 0x2000>;
849		interrupts = <GIC_PPI 9
850			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
851		interrupt-parent = <&gic>;
852	};
853
854	cec@3960000 {
855		compatible = "nvidia,tegra186-cec";
856		reg = <0x0 0x03960000 0x0 0x10000>;
857		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
858		clocks = <&bpmp TEGRA186_CLK_CEC>;
859		clock-names = "cec";
860		status = "disabled";
861	};
862
863	hsp_top0: hsp@3c00000 {
864		compatible = "nvidia,tegra186-hsp";
865		reg = <0x0 0x03c00000 0x0 0xa0000>;
866		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
867		interrupt-names = "doorbell";
868		#mbox-cells = <2>;
869		status = "disabled";
870	};
871
872	gen2_i2c: i2c@c240000 {
873		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
874		reg = <0x0 0x0c240000 0x0 0x10000>;
875		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
876		#address-cells = <1>;
877		#size-cells = <0>;
878		clocks = <&bpmp TEGRA186_CLK_I2C2>;
879		clock-names = "div-clk";
880		resets = <&bpmp TEGRA186_RESET_I2C2>;
881		reset-names = "i2c";
882		status = "disabled";
883	};
884
885	gen8_i2c: i2c@c250000 {
886		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
887		reg = <0x0 0x0c250000 0x0 0x10000>;
888		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
889		#address-cells = <1>;
890		#size-cells = <0>;
891		clocks = <&bpmp TEGRA186_CLK_I2C8>;
892		clock-names = "div-clk";
893		resets = <&bpmp TEGRA186_RESET_I2C8>;
894		reset-names = "i2c";
895		status = "disabled";
896	};
897
898	uartc: serial@c280000 {
899		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
900		reg = <0x0 0x0c280000 0x0 0x40>;
901		reg-shift = <2>;
902		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
903		clocks = <&bpmp TEGRA186_CLK_UARTC>;
904		clock-names = "serial";
905		resets = <&bpmp TEGRA186_RESET_UARTC>;
906		reset-names = "serial";
907		status = "disabled";
908	};
909
910	uartg: serial@c290000 {
911		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
912		reg = <0x0 0x0c290000 0x0 0x40>;
913		reg-shift = <2>;
914		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
915		clocks = <&bpmp TEGRA186_CLK_UARTG>;
916		clock-names = "serial";
917		resets = <&bpmp TEGRA186_RESET_UARTG>;
918		reset-names = "serial";
919		status = "disabled";
920	};
921
922	rtc: rtc@c2a0000 {
923		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
924		reg = <0 0x0c2a0000 0 0x10000>;
925		interrupt-parent = <&pmc>;
926		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
927		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
928		clock-names = "rtc";
929		status = "disabled";
930	};
931
932	gpio_aon: gpio@c2f0000 {
933		compatible = "nvidia,tegra186-gpio-aon";
934		reg-names = "security", "gpio";
935		reg = <0x0 0xc2f0000 0x0 0x1000>,
936		      <0x0 0xc2f1000 0x0 0x1000>;
937		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
938		gpio-controller;
939		#gpio-cells = <2>;
940		interrupt-controller;
941		#interrupt-cells = <2>;
942	};
943
944	pmc: pmc@c360000 {
945		compatible = "nvidia,tegra186-pmc";
946		reg = <0 0x0c360000 0 0x10000>,
947		      <0 0x0c370000 0 0x10000>,
948		      <0 0x0c380000 0 0x10000>,
949		      <0 0x0c390000 0 0x10000>;
950		reg-names = "pmc", "wake", "aotag", "scratch";
951
952		#interrupt-cells = <2>;
953		interrupt-controller;
954
955		sdmmc1_3v3: sdmmc1-3v3 {
956			pins = "sdmmc1-hv";
957			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
958		};
959
960		sdmmc1_1v8: sdmmc1-1v8 {
961			pins = "sdmmc1-hv";
962			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
963		};
964
965		sdmmc2_3v3: sdmmc2-3v3 {
966			pins = "sdmmc2-hv";
967			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
968		};
969
970		sdmmc2_1v8: sdmmc2-1v8 {
971			pins = "sdmmc2-hv";
972			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
973		};
974
975		sdmmc3_3v3: sdmmc3-3v3 {
976			pins = "sdmmc3-hv";
977			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
978		};
979
980		sdmmc3_1v8: sdmmc3-1v8 {
981			pins = "sdmmc3-hv";
982			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
983		};
984	};
985
986	ccplex@e000000 {
987		compatible = "nvidia,tegra186-ccplex-cluster";
988		reg = <0x0 0x0e000000 0x0 0x3fffff>;
989
990		nvidia,bpmp = <&bpmp>;
991	};
992
993	pcie@10003000 {
994		compatible = "nvidia,tegra186-pcie";
995		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
996		device_type = "pci";
997		reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
998		      <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
999		      <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1000		reg-names = "pads", "afi", "cs";
1001
1002		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1003			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1004		interrupt-names = "intr", "msi";
1005
1006		#interrupt-cells = <1>;
1007		interrupt-map-mask = <0 0 0 0>;
1008		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1009
1010		bus-range = <0x00 0xff>;
1011		#address-cells = <3>;
1012		#size-cells = <2>;
1013
1014		ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1015			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1016			 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1017			 <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1018			 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1019			 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1020
1021		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1022			 <&bpmp TEGRA186_CLK_AFI>,
1023			 <&bpmp TEGRA186_CLK_PLLE>;
1024		clock-names = "pex", "afi", "pll_e";
1025
1026		resets = <&bpmp TEGRA186_RESET_PCIE>,
1027			 <&bpmp TEGRA186_RESET_AFI>,
1028			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1029		reset-names = "pex", "afi", "pcie_x";
1030
1031		interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1032				<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1033		interconnect-names = "dma-mem", "write";
1034
1035		iommus = <&smmu TEGRA186_SID_AFI>;
1036		iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1037		iommu-map-mask = <0x0>;
1038
1039		status = "disabled";
1040
1041		pci@1,0 {
1042			device_type = "pci";
1043			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1044			reg = <0x000800 0 0 0 0>;
1045			status = "disabled";
1046
1047			#address-cells = <3>;
1048			#size-cells = <2>;
1049			ranges;
1050
1051			nvidia,num-lanes = <2>;
1052		};
1053
1054		pci@2,0 {
1055			device_type = "pci";
1056			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1057			reg = <0x001000 0 0 0 0>;
1058			status = "disabled";
1059
1060			#address-cells = <3>;
1061			#size-cells = <2>;
1062			ranges;
1063
1064			nvidia,num-lanes = <1>;
1065		};
1066
1067		pci@3,0 {
1068			device_type = "pci";
1069			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1070			reg = <0x001800 0 0 0 0>;
1071			status = "disabled";
1072
1073			#address-cells = <3>;
1074			#size-cells = <2>;
1075			ranges;
1076
1077			nvidia,num-lanes = <1>;
1078		};
1079	};
1080
1081	smmu: iommu@12000000 {
1082		compatible = "arm,mmu-500";
1083		reg = <0 0x12000000 0 0x800000>;
1084		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1085			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1086			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1087			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1088			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1089			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1090			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1091			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1092			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1093			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1094			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1095			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1096			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1097			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1098			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1099			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1100			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1101			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1102			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1103			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1104			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1105			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1106			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1107			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1108			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1109			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1110			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1111			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1112			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1113			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1114			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1115			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1116			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1117			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1118			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1119			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1120			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1121			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1122			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1123			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1124			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1125			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1126			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1127			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1128			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1129			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1130			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1131			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1132			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1133			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1134			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1135			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1136			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1137			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1138			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1139			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1140			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1141			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1142			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1143			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1144			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1145			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1146			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1147			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1148			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1149		stream-match-mask = <0x7f80>;
1150		#global-interrupts = <1>;
1151		#iommu-cells = <1>;
1152	};
1153
1154	host1x@13e00000 {
1155		compatible = "nvidia,tegra186-host1x";
1156		reg = <0x0 0x13e00000 0x0 0x10000>,
1157		      <0x0 0x13e10000 0x0 0x10000>;
1158		reg-names = "hypervisor", "vm";
1159		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1160		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1161		interrupt-names = "syncpt", "host1x";
1162		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1163		clock-names = "host1x";
1164		resets = <&bpmp TEGRA186_RESET_HOST1X>;
1165		reset-names = "host1x";
1166
1167		#address-cells = <1>;
1168		#size-cells = <1>;
1169
1170		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1171
1172		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1173		interconnect-names = "dma-mem";
1174
1175		iommus = <&smmu TEGRA186_SID_HOST1X>;
1176
1177		dpaux1: dpaux@15040000 {
1178			compatible = "nvidia,tegra186-dpaux";
1179			reg = <0x15040000 0x10000>;
1180			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1181			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1182				 <&bpmp TEGRA186_CLK_PLLDP>;
1183			clock-names = "dpaux", "parent";
1184			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1185			reset-names = "dpaux";
1186			status = "disabled";
1187
1188			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1189
1190			state_dpaux1_aux: pinmux-aux {
1191				groups = "dpaux-io";
1192				function = "aux";
1193			};
1194
1195			state_dpaux1_i2c: pinmux-i2c {
1196				groups = "dpaux-io";
1197				function = "i2c";
1198			};
1199
1200			state_dpaux1_off: pinmux-off {
1201				groups = "dpaux-io";
1202				function = "off";
1203			};
1204
1205			i2c-bus {
1206				#address-cells = <1>;
1207				#size-cells = <0>;
1208			};
1209		};
1210
1211		display-hub@15200000 {
1212			compatible = "nvidia,tegra186-display";
1213			reg = <0x15200000 0x00040000>;
1214			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1215				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1216				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1217				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1218				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1219				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1220				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1221			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1222				      "wgrp3", "wgrp4", "wgrp5";
1223			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1224				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1225				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1226			clock-names = "disp", "dsc", "hub";
1227			status = "disabled";
1228
1229			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1230
1231			#address-cells = <1>;
1232			#size-cells = <1>;
1233
1234			ranges = <0x15200000 0x15200000 0x40000>;
1235
1236			display@15200000 {
1237				compatible = "nvidia,tegra186-dc";
1238				reg = <0x15200000 0x10000>;
1239				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1240				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1241				clock-names = "dc";
1242				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1243				reset-names = "dc";
1244
1245				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1246				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1247						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1248				interconnect-names = "dma-mem", "read-1";
1249				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1250
1251				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1252				nvidia,head = <0>;
1253			};
1254
1255			display@15210000 {
1256				compatible = "nvidia,tegra186-dc";
1257				reg = <0x15210000 0x10000>;
1258				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1259				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1260				clock-names = "dc";
1261				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1262				reset-names = "dc";
1263
1264				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1265				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1266						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1267				interconnect-names = "dma-mem", "read-1";
1268				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1269
1270				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1271				nvidia,head = <1>;
1272			};
1273
1274			display@15220000 {
1275				compatible = "nvidia,tegra186-dc";
1276				reg = <0x15220000 0x10000>;
1277				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1278				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1279				clock-names = "dc";
1280				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1281				reset-names = "dc";
1282
1283				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1284				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1285						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1286				interconnect-names = "dma-mem", "read-1";
1287				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1288
1289				nvidia,outputs = <&sor0 &sor1>;
1290				nvidia,head = <2>;
1291			};
1292		};
1293
1294		dsia: dsi@15300000 {
1295			compatible = "nvidia,tegra186-dsi";
1296			reg = <0x15300000 0x10000>;
1297			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1298			clocks = <&bpmp TEGRA186_CLK_DSI>,
1299				 <&bpmp TEGRA186_CLK_DSIA_LP>,
1300				 <&bpmp TEGRA186_CLK_PLLD>;
1301			clock-names = "dsi", "lp", "parent";
1302			resets = <&bpmp TEGRA186_RESET_DSI>;
1303			reset-names = "dsi";
1304			status = "disabled";
1305
1306			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1307		};
1308
1309		vic@15340000 {
1310			compatible = "nvidia,tegra186-vic";
1311			reg = <0x15340000 0x40000>;
1312			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1313			clocks = <&bpmp TEGRA186_CLK_VIC>;
1314			clock-names = "vic";
1315			resets = <&bpmp TEGRA186_RESET_VIC>;
1316			reset-names = "vic";
1317
1318			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1319			interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1320					<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1321			interconnect-names = "dma-mem", "write";
1322			iommus = <&smmu TEGRA186_SID_VIC>;
1323		};
1324
1325		dsib: dsi@15400000 {
1326			compatible = "nvidia,tegra186-dsi";
1327			reg = <0x15400000 0x10000>;
1328			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1329			clocks = <&bpmp TEGRA186_CLK_DSIB>,
1330				 <&bpmp TEGRA186_CLK_DSIB_LP>,
1331				 <&bpmp TEGRA186_CLK_PLLD>;
1332			clock-names = "dsi", "lp", "parent";
1333			resets = <&bpmp TEGRA186_RESET_DSIB>;
1334			reset-names = "dsi";
1335			status = "disabled";
1336
1337			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1338		};
1339
1340		sor0: sor@15540000 {
1341			compatible = "nvidia,tegra186-sor";
1342			reg = <0x15540000 0x10000>;
1343			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1344			clocks = <&bpmp TEGRA186_CLK_SOR0>,
1345				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1346				 <&bpmp TEGRA186_CLK_PLLD2>,
1347				 <&bpmp TEGRA186_CLK_PLLDP>,
1348				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1349				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1350			clock-names = "sor", "out", "parent", "dp", "safe",
1351				      "pad";
1352			resets = <&bpmp TEGRA186_RESET_SOR0>;
1353			reset-names = "sor";
1354			pinctrl-0 = <&state_dpaux_aux>;
1355			pinctrl-1 = <&state_dpaux_i2c>;
1356			pinctrl-2 = <&state_dpaux_off>;
1357			pinctrl-names = "aux", "i2c", "off";
1358			status = "disabled";
1359
1360			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1361			nvidia,interface = <0>;
1362		};
1363
1364		sor1: sor@15580000 {
1365			compatible = "nvidia,tegra186-sor";
1366			reg = <0x15580000 0x10000>;
1367			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1368			clocks = <&bpmp TEGRA186_CLK_SOR1>,
1369				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1370				 <&bpmp TEGRA186_CLK_PLLD3>,
1371				 <&bpmp TEGRA186_CLK_PLLDP>,
1372				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1373				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1374			clock-names = "sor", "out", "parent", "dp", "safe",
1375				      "pad";
1376			resets = <&bpmp TEGRA186_RESET_SOR1>;
1377			reset-names = "sor";
1378			pinctrl-0 = <&state_dpaux1_aux>;
1379			pinctrl-1 = <&state_dpaux1_i2c>;
1380			pinctrl-2 = <&state_dpaux1_off>;
1381			pinctrl-names = "aux", "i2c", "off";
1382			status = "disabled";
1383
1384			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1385			nvidia,interface = <1>;
1386		};
1387
1388		dpaux: dpaux@155c0000 {
1389			compatible = "nvidia,tegra186-dpaux";
1390			reg = <0x155c0000 0x10000>;
1391			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1392			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1393				 <&bpmp TEGRA186_CLK_PLLDP>;
1394			clock-names = "dpaux", "parent";
1395			resets = <&bpmp TEGRA186_RESET_DPAUX>;
1396			reset-names = "dpaux";
1397			status = "disabled";
1398
1399			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1400
1401			state_dpaux_aux: pinmux-aux {
1402				groups = "dpaux-io";
1403				function = "aux";
1404			};
1405
1406			state_dpaux_i2c: pinmux-i2c {
1407				groups = "dpaux-io";
1408				function = "i2c";
1409			};
1410
1411			state_dpaux_off: pinmux-off {
1412				groups = "dpaux-io";
1413				function = "off";
1414			};
1415
1416			i2c-bus {
1417				#address-cells = <1>;
1418				#size-cells = <0>;
1419			};
1420		};
1421
1422		padctl@15880000 {
1423			compatible = "nvidia,tegra186-dsi-padctl";
1424			reg = <0x15880000 0x10000>;
1425			resets = <&bpmp TEGRA186_RESET_DSI>;
1426			reset-names = "dsi";
1427			status = "disabled";
1428		};
1429
1430		dsic: dsi@15900000 {
1431			compatible = "nvidia,tegra186-dsi";
1432			reg = <0x15900000 0x10000>;
1433			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1434			clocks = <&bpmp TEGRA186_CLK_DSIC>,
1435				 <&bpmp TEGRA186_CLK_DSIC_LP>,
1436				 <&bpmp TEGRA186_CLK_PLLD>;
1437			clock-names = "dsi", "lp", "parent";
1438			resets = <&bpmp TEGRA186_RESET_DSIC>;
1439			reset-names = "dsi";
1440			status = "disabled";
1441
1442			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1443		};
1444
1445		dsid: dsi@15940000 {
1446			compatible = "nvidia,tegra186-dsi";
1447			reg = <0x15940000 0x10000>;
1448			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1449			clocks = <&bpmp TEGRA186_CLK_DSID>,
1450				 <&bpmp TEGRA186_CLK_DSID_LP>,
1451				 <&bpmp TEGRA186_CLK_PLLD>;
1452			clock-names = "dsi", "lp", "parent";
1453			resets = <&bpmp TEGRA186_RESET_DSID>;
1454			reset-names = "dsi";
1455			status = "disabled";
1456
1457			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1458		};
1459	};
1460
1461	gpu@17000000 {
1462		compatible = "nvidia,gp10b";
1463		reg = <0x0 0x17000000 0x0 0x1000000>,
1464		      <0x0 0x18000000 0x0 0x1000000>;
1465		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1466			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1467		interrupt-names = "stall", "nonstall";
1468
1469		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1470			 <&bpmp TEGRA186_CLK_GPU>;
1471		clock-names = "gpu", "pwr";
1472		resets = <&bpmp TEGRA186_RESET_GPU>;
1473		reset-names = "gpu";
1474		status = "disabled";
1475
1476		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1477		interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1478				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1479				<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1480				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1481		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1482	};
1483
1484	sram@30000000 {
1485		compatible = "nvidia,tegra186-sysram", "mmio-sram";
1486		reg = <0x0 0x30000000 0x0 0x50000>;
1487		#address-cells = <1>;
1488		#size-cells = <1>;
1489		ranges = <0x0 0x0 0x30000000 0x50000>;
1490
1491		cpu_bpmp_tx: sram@4e000 {
1492			reg = <0x4e000 0x1000>;
1493			label = "cpu-bpmp-tx";
1494			pool;
1495		};
1496
1497		cpu_bpmp_rx: sram@4f000 {
1498			reg = <0x4f000 0x1000>;
1499			label = "cpu-bpmp-rx";
1500			pool;
1501		};
1502	};
1503
1504	bpmp: bpmp {
1505		compatible = "nvidia,tegra186-bpmp";
1506		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1507				<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1508				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1509				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1510		interconnect-names = "read", "write", "dma-mem", "dma-write";
1511		iommus = <&smmu TEGRA186_SID_BPMP>;
1512		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1513				    TEGRA_HSP_DB_MASTER_BPMP>;
1514		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1515		#clock-cells = <1>;
1516		#reset-cells = <1>;
1517		#power-domain-cells = <1>;
1518
1519		bpmp_i2c: i2c {
1520			compatible = "nvidia,tegra186-bpmp-i2c";
1521			nvidia,bpmp-bus-id = <5>;
1522			#address-cells = <1>;
1523			#size-cells = <0>;
1524			status = "disabled";
1525		};
1526
1527		bpmp_thermal: thermal {
1528			compatible = "nvidia,tegra186-bpmp-thermal";
1529			#thermal-sensor-cells = <1>;
1530		};
1531	};
1532
1533	cpus {
1534		#address-cells = <1>;
1535		#size-cells = <0>;
1536
1537		cpu@0 {
1538			compatible = "nvidia,tegra186-denver";
1539			device_type = "cpu";
1540			i-cache-size = <0x20000>;
1541			i-cache-line-size = <64>;
1542			i-cache-sets = <512>;
1543			d-cache-size = <0x10000>;
1544			d-cache-line-size = <64>;
1545			d-cache-sets = <256>;
1546			next-level-cache = <&L2_DENVER>;
1547			reg = <0x000>;
1548		};
1549
1550		cpu@1 {
1551			compatible = "nvidia,tegra186-denver";
1552			device_type = "cpu";
1553			i-cache-size = <0x20000>;
1554			i-cache-line-size = <64>;
1555			i-cache-sets = <512>;
1556			d-cache-size = <0x10000>;
1557			d-cache-line-size = <64>;
1558			d-cache-sets = <256>;
1559			next-level-cache = <&L2_DENVER>;
1560			reg = <0x001>;
1561		};
1562
1563		cpu@2 {
1564			compatible = "arm,cortex-a57";
1565			device_type = "cpu";
1566			i-cache-size = <0xC000>;
1567			i-cache-line-size = <64>;
1568			i-cache-sets = <256>;
1569			d-cache-size = <0x8000>;
1570			d-cache-line-size = <64>;
1571			d-cache-sets = <256>;
1572			next-level-cache = <&L2_A57>;
1573			reg = <0x100>;
1574		};
1575
1576		cpu@3 {
1577			compatible = "arm,cortex-a57";
1578			device_type = "cpu";
1579			i-cache-size = <0xC000>;
1580			i-cache-line-size = <64>;
1581			i-cache-sets = <256>;
1582			d-cache-size = <0x8000>;
1583			d-cache-line-size = <64>;
1584			d-cache-sets = <256>;
1585			next-level-cache = <&L2_A57>;
1586			reg = <0x101>;
1587		};
1588
1589		cpu@4 {
1590			compatible = "arm,cortex-a57";
1591			device_type = "cpu";
1592			i-cache-size = <0xC000>;
1593			i-cache-line-size = <64>;
1594			i-cache-sets = <256>;
1595			d-cache-size = <0x8000>;
1596			d-cache-line-size = <64>;
1597			d-cache-sets = <256>;
1598			next-level-cache = <&L2_A57>;
1599			reg = <0x102>;
1600		};
1601
1602		cpu@5 {
1603			compatible = "arm,cortex-a57";
1604			device_type = "cpu";
1605			i-cache-size = <0xC000>;
1606			i-cache-line-size = <64>;
1607			i-cache-sets = <256>;
1608			d-cache-size = <0x8000>;
1609			d-cache-line-size = <64>;
1610			d-cache-sets = <256>;
1611			next-level-cache = <&L2_A57>;
1612			reg = <0x103>;
1613		};
1614
1615		L2_DENVER: l2-cache0 {
1616			compatible = "cache";
1617			cache-unified;
1618			cache-level = <2>;
1619			cache-size = <0x200000>;
1620			cache-line-size = <64>;
1621			cache-sets = <2048>;
1622		};
1623
1624		L2_A57: l2-cache1 {
1625			compatible = "cache";
1626			cache-unified;
1627			cache-level = <2>;
1628			cache-size = <0x200000>;
1629			cache-line-size = <64>;
1630			cache-sets = <2048>;
1631		};
1632	};
1633
1634	thermal-zones {
1635		a57 {
1636			polling-delay = <0>;
1637			polling-delay-passive = <1000>;
1638
1639			thermal-sensors =
1640				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1641
1642			trips {
1643				critical {
1644					temperature = <101000>;
1645					hysteresis = <0>;
1646					type = "critical";
1647				};
1648			};
1649
1650			cooling-maps {
1651			};
1652		};
1653
1654		denver {
1655			polling-delay = <0>;
1656			polling-delay-passive = <1000>;
1657
1658			thermal-sensors =
1659				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1660
1661			trips {
1662				critical {
1663					temperature = <101000>;
1664					hysteresis = <0>;
1665					type = "critical";
1666				};
1667			};
1668
1669			cooling-maps {
1670			};
1671		};
1672
1673		gpu {
1674			polling-delay = <0>;
1675			polling-delay-passive = <1000>;
1676
1677			thermal-sensors =
1678				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1679
1680			trips {
1681				critical {
1682					temperature = <101000>;
1683					hysteresis = <0>;
1684					type = "critical";
1685				};
1686			};
1687
1688			cooling-maps {
1689			};
1690		};
1691
1692		pll {
1693			polling-delay = <0>;
1694			polling-delay-passive = <1000>;
1695
1696			thermal-sensors =
1697				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1698
1699			trips {
1700				critical {
1701					temperature = <101000>;
1702					hysteresis = <0>;
1703					type = "critical";
1704				};
1705			};
1706
1707			cooling-maps {
1708			};
1709		};
1710
1711		always_on {
1712			polling-delay = <0>;
1713			polling-delay-passive = <1000>;
1714
1715			thermal-sensors =
1716				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1717
1718			trips {
1719				critical {
1720					temperature = <101000>;
1721					hysteresis = <0>;
1722					type = "critical";
1723				};
1724			};
1725
1726			cooling-maps {
1727			};
1728		};
1729	};
1730
1731	timer {
1732		compatible = "arm,armv8-timer";
1733		interrupts = <GIC_PPI 13
1734				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1735			     <GIC_PPI 14
1736				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1737			     <GIC_PPI 11
1738				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1739			     <GIC_PPI 10
1740				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1741		interrupt-parent = <&gic>;
1742		always-on;
1743	};
1744};
1745