1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113 #dma-cells = <1>; 114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115 dma-coherent; 116 dma-channel-mask = <0xfffffffe>; 117 status = "okay"; 118 }; 119 120 aconnect@2900000 { 121 compatible = "nvidia,tegra186-aconnect", 122 "nvidia,tegra210-aconnect"; 123 clocks = <&bpmp TEGRA186_CLK_APE>, 124 <&bpmp TEGRA186_CLK_APB2APE>; 125 clock-names = "ape", "apb2ape"; 126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0x02900000 0x0 0x02900000 0x200000>; 130 status = "disabled"; 131 132 adma: dma-controller@2930000 { 133 compatible = "nvidia,tegra186-adma"; 134 reg = <0x02930000 0x20000>; 135 interrupt-parent = <&agic>; 136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 168 #dma-cells = <1>; 169 clocks = <&bpmp TEGRA186_CLK_AHUB>; 170 clock-names = "d_audio"; 171 status = "disabled"; 172 }; 173 174 agic: interrupt-controller@2a40000 { 175 compatible = "nvidia,tegra186-agic", 176 "nvidia,tegra210-agic"; 177 #interrupt-cells = <3>; 178 interrupt-controller; 179 reg = <0x02a41000 0x1000>, 180 <0x02a42000 0x2000>; 181 interrupts = <GIC_SPI 145 182 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 183 clocks = <&bpmp TEGRA186_CLK_APE>; 184 clock-names = "clk"; 185 status = "disabled"; 186 }; 187 188 tegra_ahub: ahub@2900800 { 189 compatible = "nvidia,tegra186-ahub"; 190 reg = <0x02900800 0x800>; 191 clocks = <&bpmp TEGRA186_CLK_AHUB>; 192 clock-names = "ahub"; 193 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 194 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0x02900800 0x02900800 0x11800>; 198 status = "disabled"; 199 200 tegra_admaif: admaif@290f000 { 201 compatible = "nvidia,tegra186-admaif"; 202 reg = <0x0290f000 0x1000>; 203 dmas = <&adma 1>, <&adma 1>, 204 <&adma 2>, <&adma 2>, 205 <&adma 3>, <&adma 3>, 206 <&adma 4>, <&adma 4>, 207 <&adma 5>, <&adma 5>, 208 <&adma 6>, <&adma 6>, 209 <&adma 7>, <&adma 7>, 210 <&adma 8>, <&adma 8>, 211 <&adma 9>, <&adma 9>, 212 <&adma 10>, <&adma 10>, 213 <&adma 11>, <&adma 11>, 214 <&adma 12>, <&adma 12>, 215 <&adma 13>, <&adma 13>, 216 <&adma 14>, <&adma 14>, 217 <&adma 15>, <&adma 15>, 218 <&adma 16>, <&adma 16>, 219 <&adma 17>, <&adma 17>, 220 <&adma 18>, <&adma 18>, 221 <&adma 19>, <&adma 19>, 222 <&adma 20>, <&adma 20>; 223 dma-names = "rx1", "tx1", 224 "rx2", "tx2", 225 "rx3", "tx3", 226 "rx4", "tx4", 227 "rx5", "tx5", 228 "rx6", "tx6", 229 "rx7", "tx7", 230 "rx8", "tx8", 231 "rx9", "tx9", 232 "rx10", "tx10", 233 "rx11", "tx11", 234 "rx12", "tx12", 235 "rx13", "tx13", 236 "rx14", "tx14", 237 "rx15", "tx15", 238 "rx16", "tx16", 239 "rx17", "tx17", 240 "rx18", "tx18", 241 "rx19", "tx19", 242 "rx20", "tx20"; 243 status = "disabled"; 244 }; 245 246 tegra_i2s1: i2s@2901000 { 247 compatible = "nvidia,tegra186-i2s", 248 "nvidia,tegra210-i2s"; 249 reg = <0x2901000 0x100>; 250 clocks = <&bpmp TEGRA186_CLK_I2S1>, 251 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 252 clock-names = "i2s", "sync_input"; 253 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 254 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 255 assigned-clock-rates = <1536000>; 256 sound-name-prefix = "I2S1"; 257 status = "disabled"; 258 }; 259 260 tegra_i2s2: i2s@2901100 { 261 compatible = "nvidia,tegra186-i2s", 262 "nvidia,tegra210-i2s"; 263 reg = <0x2901100 0x100>; 264 clocks = <&bpmp TEGRA186_CLK_I2S2>, 265 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 266 clock-names = "i2s", "sync_input"; 267 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 268 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 269 assigned-clock-rates = <1536000>; 270 sound-name-prefix = "I2S2"; 271 status = "disabled"; 272 }; 273 274 tegra_i2s3: i2s@2901200 { 275 compatible = "nvidia,tegra186-i2s", 276 "nvidia,tegra210-i2s"; 277 reg = <0x2901200 0x100>; 278 clocks = <&bpmp TEGRA186_CLK_I2S3>, 279 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 280 clock-names = "i2s", "sync_input"; 281 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 282 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 283 assigned-clock-rates = <1536000>; 284 sound-name-prefix = "I2S3"; 285 status = "disabled"; 286 }; 287 288 tegra_i2s4: i2s@2901300 { 289 compatible = "nvidia,tegra186-i2s", 290 "nvidia,tegra210-i2s"; 291 reg = <0x2901300 0x100>; 292 clocks = <&bpmp TEGRA186_CLK_I2S4>, 293 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 294 clock-names = "i2s", "sync_input"; 295 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 296 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 297 assigned-clock-rates = <1536000>; 298 sound-name-prefix = "I2S4"; 299 status = "disabled"; 300 }; 301 302 tegra_i2s5: i2s@2901400 { 303 compatible = "nvidia,tegra186-i2s", 304 "nvidia,tegra210-i2s"; 305 reg = <0x2901400 0x100>; 306 clocks = <&bpmp TEGRA186_CLK_I2S5>, 307 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 308 clock-names = "i2s", "sync_input"; 309 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 310 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 311 assigned-clock-rates = <1536000>; 312 sound-name-prefix = "I2S5"; 313 status = "disabled"; 314 }; 315 316 tegra_i2s6: i2s@2901500 { 317 compatible = "nvidia,tegra186-i2s", 318 "nvidia,tegra210-i2s"; 319 reg = <0x2901500 0x100>; 320 clocks = <&bpmp TEGRA186_CLK_I2S6>, 321 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 322 clock-names = "i2s", "sync_input"; 323 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 324 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 325 assigned-clock-rates = <1536000>; 326 sound-name-prefix = "I2S6"; 327 status = "disabled"; 328 }; 329 330 tegra_dmic1: dmic@2904000 { 331 compatible = "nvidia,tegra210-dmic"; 332 reg = <0x2904000 0x100>; 333 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334 clock-names = "dmic"; 335 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 336 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 337 assigned-clock-rates = <3072000>; 338 sound-name-prefix = "DMIC1"; 339 status = "disabled"; 340 }; 341 342 tegra_dmic2: dmic@2904100 { 343 compatible = "nvidia,tegra210-dmic"; 344 reg = <0x2904100 0x100>; 345 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346 clock-names = "dmic"; 347 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 348 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 349 assigned-clock-rates = <3072000>; 350 sound-name-prefix = "DMIC2"; 351 status = "disabled"; 352 }; 353 354 tegra_dmic3: dmic@2904200 { 355 compatible = "nvidia,tegra210-dmic"; 356 reg = <0x2904200 0x100>; 357 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358 clock-names = "dmic"; 359 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 360 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 361 assigned-clock-rates = <3072000>; 362 sound-name-prefix = "DMIC3"; 363 status = "disabled"; 364 }; 365 366 tegra_dmic4: dmic@2904300 { 367 compatible = "nvidia,tegra210-dmic"; 368 reg = <0x2904300 0x100>; 369 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370 clock-names = "dmic"; 371 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 372 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 373 assigned-clock-rates = <3072000>; 374 sound-name-prefix = "DMIC4"; 375 status = "disabled"; 376 }; 377 378 tegra_dspk1: dspk@2905000 { 379 compatible = "nvidia,tegra186-dspk"; 380 reg = <0x2905000 0x100>; 381 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382 clock-names = "dspk"; 383 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 384 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 385 assigned-clock-rates = <12288000>; 386 sound-name-prefix = "DSPK1"; 387 status = "disabled"; 388 }; 389 390 tegra_dspk2: dspk@2905100 { 391 compatible = "nvidia,tegra186-dspk"; 392 reg = <0x2905100 0x100>; 393 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394 clock-names = "dspk"; 395 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 396 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 397 assigned-clock-rates = <12288000>; 398 sound-name-prefix = "DSPK2"; 399 status = "disabled"; 400 }; 401 402 tegra_sfc1: sfc@2902000 { 403 compatible = "nvidia,tegra186-sfc", 404 "nvidia,tegra210-sfc"; 405 reg = <0x2902000 0x200>; 406 sound-name-prefix = "SFC1"; 407 status = "disabled"; 408 }; 409 410 tegra_sfc2: sfc@2902200 { 411 compatible = "nvidia,tegra186-sfc", 412 "nvidia,tegra210-sfc"; 413 reg = <0x2902200 0x200>; 414 sound-name-prefix = "SFC2"; 415 status = "disabled"; 416 }; 417 418 tegra_sfc3: sfc@2902400 { 419 compatible = "nvidia,tegra186-sfc", 420 "nvidia,tegra210-sfc"; 421 reg = <0x2902400 0x200>; 422 sound-name-prefix = "SFC3"; 423 status = "disabled"; 424 }; 425 426 tegra_sfc4: sfc@2902600 { 427 compatible = "nvidia,tegra186-sfc", 428 "nvidia,tegra210-sfc"; 429 reg = <0x2902600 0x200>; 430 sound-name-prefix = "SFC4"; 431 status = "disabled"; 432 }; 433 434 tegra_mvc1: mvc@290a000 { 435 compatible = "nvidia,tegra186-mvc", 436 "nvidia,tegra210-mvc"; 437 reg = <0x290a000 0x200>; 438 sound-name-prefix = "MVC1"; 439 status = "disabled"; 440 }; 441 442 tegra_mvc2: mvc@290a200 { 443 compatible = "nvidia,tegra186-mvc", 444 "nvidia,tegra210-mvc"; 445 reg = <0x290a200 0x200>; 446 sound-name-prefix = "MVC2"; 447 status = "disabled"; 448 }; 449 450 tegra_amx1: amx@2903000 { 451 compatible = "nvidia,tegra186-amx", 452 "nvidia,tegra210-amx"; 453 reg = <0x2903000 0x100>; 454 sound-name-prefix = "AMX1"; 455 status = "disabled"; 456 }; 457 458 tegra_amx2: amx@2903100 { 459 compatible = "nvidia,tegra186-amx", 460 "nvidia,tegra210-amx"; 461 reg = <0x2903100 0x100>; 462 sound-name-prefix = "AMX2"; 463 status = "disabled"; 464 }; 465 466 tegra_amx3: amx@2903200 { 467 compatible = "nvidia,tegra186-amx", 468 "nvidia,tegra210-amx"; 469 reg = <0x2903200 0x100>; 470 sound-name-prefix = "AMX3"; 471 status = "disabled"; 472 }; 473 474 tegra_amx4: amx@2903300 { 475 compatible = "nvidia,tegra186-amx", 476 "nvidia,tegra210-amx"; 477 reg = <0x2903300 0x100>; 478 sound-name-prefix = "AMX4"; 479 status = "disabled"; 480 }; 481 482 tegra_adx1: adx@2903800 { 483 compatible = "nvidia,tegra186-adx", 484 "nvidia,tegra210-adx"; 485 reg = <0x2903800 0x100>; 486 sound-name-prefix = "ADX1"; 487 status = "disabled"; 488 }; 489 490 tegra_adx2: adx@2903900 { 491 compatible = "nvidia,tegra186-adx", 492 "nvidia,tegra210-adx"; 493 reg = <0x2903900 0x100>; 494 sound-name-prefix = "ADX2"; 495 status = "disabled"; 496 }; 497 498 tegra_adx3: adx@2903a00 { 499 compatible = "nvidia,tegra186-adx", 500 "nvidia,tegra210-adx"; 501 reg = <0x2903a00 0x100>; 502 sound-name-prefix = "ADX3"; 503 status = "disabled"; 504 }; 505 506 tegra_adx4: adx@2903b00 { 507 compatible = "nvidia,tegra186-adx", 508 "nvidia,tegra210-adx"; 509 reg = <0x2903b00 0x100>; 510 sound-name-prefix = "ADX4"; 511 status = "disabled"; 512 }; 513 514 tegra_ope1: processing-engine@2908000 { 515 compatible = "nvidia,tegra186-ope", 516 "nvidia,tegra210-ope"; 517 reg = <0x2908000 0x100>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges; 521 sound-name-prefix = "OPE1"; 522 status = "disabled"; 523 524 equalizer@2908100 { 525 compatible = "nvidia,tegra186-peq", 526 "nvidia,tegra210-peq"; 527 reg = <0x2908100 0x100>; 528 }; 529 530 dynamic-range-compressor@2908200 { 531 compatible = "nvidia,tegra186-mbdrc", 532 "nvidia,tegra210-mbdrc"; 533 reg = <0x2908200 0x200>; 534 }; 535 }; 536 537 tegra_amixer: amixer@290bb00 { 538 compatible = "nvidia,tegra186-amixer", 539 "nvidia,tegra210-amixer"; 540 reg = <0x290bb00 0x800>; 541 sound-name-prefix = "MIXER1"; 542 status = "disabled"; 543 }; 544 545 tegra_asrc: asrc@2910000 { 546 compatible = "nvidia,tegra186-asrc"; 547 reg = <0x2910000 0x2000>; 548 sound-name-prefix = "ASRC1"; 549 status = "disabled"; 550 }; 551 }; 552 }; 553 554 mc: memory-controller@2c00000 { 555 compatible = "nvidia,tegra186-mc"; 556 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 557 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 558 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 559 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 560 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 561 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 562 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 563 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 564 status = "disabled"; 565 566 #interconnect-cells = <1>; 567 #address-cells = <2>; 568 #size-cells = <2>; 569 570 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 571 572 /* 573 * Memory clients have access to all 40 bits that the memory 574 * controller can address. 575 */ 576 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 577 578 emc: external-memory-controller@2c60000 { 579 compatible = "nvidia,tegra186-emc"; 580 reg = <0x0 0x02c60000 0x0 0x50000>; 581 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&bpmp TEGRA186_CLK_EMC>; 583 clock-names = "emc"; 584 585 #interconnect-cells = <0>; 586 587 nvidia,bpmp = <&bpmp>; 588 }; 589 }; 590 591 timer@3010000 { 592 compatible = "nvidia,tegra186-timer"; 593 reg = <0x0 0x03010000 0x0 0x000e0000>; 594 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 604 status = "okay"; 605 }; 606 607 uarta: serial@3100000 { 608 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 609 reg = <0x0 0x03100000 0x0 0x40>; 610 reg-shift = <2>; 611 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&bpmp TEGRA186_CLK_UARTA>; 613 clock-names = "serial"; 614 resets = <&bpmp TEGRA186_RESET_UARTA>; 615 reset-names = "serial"; 616 status = "disabled"; 617 }; 618 619 uartb: serial@3110000 { 620 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 621 reg = <0x0 0x03110000 0x0 0x40>; 622 reg-shift = <2>; 623 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&bpmp TEGRA186_CLK_UARTB>; 625 clock-names = "serial"; 626 resets = <&bpmp TEGRA186_RESET_UARTB>; 627 reset-names = "serial"; 628 status = "disabled"; 629 }; 630 631 uartd: serial@3130000 { 632 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 633 reg = <0x0 0x03130000 0x0 0x40>; 634 reg-shift = <2>; 635 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&bpmp TEGRA186_CLK_UARTD>; 637 clock-names = "serial"; 638 resets = <&bpmp TEGRA186_RESET_UARTD>; 639 reset-names = "serial"; 640 status = "disabled"; 641 }; 642 643 uarte: serial@3140000 { 644 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 645 reg = <0x0 0x03140000 0x0 0x40>; 646 reg-shift = <2>; 647 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&bpmp TEGRA186_CLK_UARTE>; 649 clock-names = "serial"; 650 resets = <&bpmp TEGRA186_RESET_UARTE>; 651 reset-names = "serial"; 652 status = "disabled"; 653 }; 654 655 uartf: serial@3150000 { 656 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 657 reg = <0x0 0x03150000 0x0 0x40>; 658 reg-shift = <2>; 659 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&bpmp TEGRA186_CLK_UARTF>; 661 clock-names = "serial"; 662 resets = <&bpmp TEGRA186_RESET_UARTF>; 663 reset-names = "serial"; 664 status = "disabled"; 665 }; 666 667 gen1_i2c: i2c@3160000 { 668 compatible = "nvidia,tegra186-i2c"; 669 reg = <0x0 0x03160000 0x0 0x10000>; 670 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&bpmp TEGRA186_CLK_I2C1>; 674 clock-names = "div-clk"; 675 resets = <&bpmp TEGRA186_RESET_I2C1>; 676 reset-names = "i2c"; 677 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 678 dma-coherent; 679 dmas = <&gpcdma 21>, <&gpcdma 21>; 680 dma-names = "rx", "tx"; 681 status = "disabled"; 682 }; 683 684 cam_i2c: i2c@3180000 { 685 compatible = "nvidia,tegra186-i2c"; 686 reg = <0x0 0x03180000 0x0 0x10000>; 687 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 clocks = <&bpmp TEGRA186_CLK_I2C3>; 691 clock-names = "div-clk"; 692 resets = <&bpmp TEGRA186_RESET_I2C3>; 693 reset-names = "i2c"; 694 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 695 dma-coherent; 696 dmas = <&gpcdma 23>, <&gpcdma 23>; 697 dma-names = "rx", "tx"; 698 status = "disabled"; 699 }; 700 701 /* shares pads with dpaux1 */ 702 dp_aux_ch1_i2c: i2c@3190000 { 703 compatible = "nvidia,tegra186-i2c"; 704 reg = <0x0 0x03190000 0x0 0x10000>; 705 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 clocks = <&bpmp TEGRA186_CLK_I2C4>; 709 clock-names = "div-clk"; 710 resets = <&bpmp TEGRA186_RESET_I2C4>; 711 reset-names = "i2c"; 712 pinctrl-names = "default", "idle"; 713 pinctrl-0 = <&state_dpaux1_i2c>; 714 pinctrl-1 = <&state_dpaux1_off>; 715 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 716 dma-coherent; 717 dmas = <&gpcdma 26>, <&gpcdma 26>; 718 dma-names = "rx", "tx"; 719 status = "disabled"; 720 }; 721 722 /* controlled by BPMP, should not be enabled */ 723 pwr_i2c: i2c@31a0000 { 724 compatible = "nvidia,tegra186-i2c"; 725 reg = <0x0 0x031a0000 0x0 0x10000>; 726 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&bpmp TEGRA186_CLK_I2C5>; 730 clock-names = "div-clk"; 731 resets = <&bpmp TEGRA186_RESET_I2C5>; 732 reset-names = "i2c"; 733 status = "disabled"; 734 }; 735 736 /* shares pads with dpaux0 */ 737 dp_aux_ch0_i2c: i2c@31b0000 { 738 compatible = "nvidia,tegra186-i2c"; 739 reg = <0x0 0x031b0000 0x0 0x10000>; 740 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 clocks = <&bpmp TEGRA186_CLK_I2C6>; 744 clock-names = "div-clk"; 745 resets = <&bpmp TEGRA186_RESET_I2C6>; 746 reset-names = "i2c"; 747 pinctrl-names = "default", "idle"; 748 pinctrl-0 = <&state_dpaux_i2c>; 749 pinctrl-1 = <&state_dpaux_off>; 750 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 751 dma-coherent; 752 dmas = <&gpcdma 30>, <&gpcdma 30>; 753 dma-names = "rx", "tx"; 754 status = "disabled"; 755 }; 756 757 gen7_i2c: i2c@31c0000 { 758 compatible = "nvidia,tegra186-i2c"; 759 reg = <0x0 0x031c0000 0x0 0x10000>; 760 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 clocks = <&bpmp TEGRA186_CLK_I2C7>; 764 clock-names = "div-clk"; 765 resets = <&bpmp TEGRA186_RESET_I2C7>; 766 reset-names = "i2c"; 767 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 768 dma-coherent; 769 dmas = <&gpcdma 27>, <&gpcdma 27>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 gen9_i2c: i2c@31e0000 { 775 compatible = "nvidia,tegra186-i2c"; 776 reg = <0x0 0x031e0000 0x0 0x10000>; 777 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 clocks = <&bpmp TEGRA186_CLK_I2C9>; 781 clock-names = "div-clk"; 782 resets = <&bpmp TEGRA186_RESET_I2C9>; 783 reset-names = "i2c"; 784 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 785 dma-coherent; 786 dmas = <&gpcdma 31>, <&gpcdma 31>; 787 dma-names = "rx", "tx"; 788 status = "disabled"; 789 }; 790 791 pwm1: pwm@3280000 { 792 compatible = "nvidia,tegra186-pwm"; 793 reg = <0x0 0x3280000 0x0 0x10000>; 794 clocks = <&bpmp TEGRA186_CLK_PWM1>; 795 resets = <&bpmp TEGRA186_RESET_PWM1>; 796 reset-names = "pwm"; 797 status = "disabled"; 798 #pwm-cells = <2>; 799 }; 800 801 pwm2: pwm@3290000 { 802 compatible = "nvidia,tegra186-pwm"; 803 reg = <0x0 0x3290000 0x0 0x10000>; 804 clocks = <&bpmp TEGRA186_CLK_PWM2>; 805 resets = <&bpmp TEGRA186_RESET_PWM2>; 806 reset-names = "pwm"; 807 status = "disabled"; 808 #pwm-cells = <2>; 809 }; 810 811 pwm3: pwm@32a0000 { 812 compatible = "nvidia,tegra186-pwm"; 813 reg = <0x0 0x32a0000 0x0 0x10000>; 814 clocks = <&bpmp TEGRA186_CLK_PWM3>; 815 resets = <&bpmp TEGRA186_RESET_PWM3>; 816 reset-names = "pwm"; 817 status = "disabled"; 818 #pwm-cells = <2>; 819 }; 820 821 pwm5: pwm@32c0000 { 822 compatible = "nvidia,tegra186-pwm"; 823 reg = <0x0 0x32c0000 0x0 0x10000>; 824 clocks = <&bpmp TEGRA186_CLK_PWM5>; 825 resets = <&bpmp TEGRA186_RESET_PWM5>; 826 reset-names = "pwm"; 827 status = "disabled"; 828 #pwm-cells = <2>; 829 }; 830 831 pwm6: pwm@32d0000 { 832 compatible = "nvidia,tegra186-pwm"; 833 reg = <0x0 0x32d0000 0x0 0x10000>; 834 clocks = <&bpmp TEGRA186_CLK_PWM6>; 835 resets = <&bpmp TEGRA186_RESET_PWM6>; 836 reset-names = "pwm"; 837 status = "disabled"; 838 #pwm-cells = <2>; 839 }; 840 841 pwm7: pwm@32e0000 { 842 compatible = "nvidia,tegra186-pwm"; 843 reg = <0x0 0x32e0000 0x0 0x10000>; 844 clocks = <&bpmp TEGRA186_CLK_PWM7>; 845 resets = <&bpmp TEGRA186_RESET_PWM7>; 846 reset-names = "pwm"; 847 status = "disabled"; 848 #pwm-cells = <2>; 849 }; 850 851 pwm8: pwm@32f0000 { 852 compatible = "nvidia,tegra186-pwm"; 853 reg = <0x0 0x32f0000 0x0 0x10000>; 854 clocks = <&bpmp TEGRA186_CLK_PWM8>; 855 resets = <&bpmp TEGRA186_RESET_PWM8>; 856 reset-names = "pwm"; 857 status = "disabled"; 858 #pwm-cells = <2>; 859 }; 860 861 sdmmc1: mmc@3400000 { 862 compatible = "nvidia,tegra186-sdhci"; 863 reg = <0x0 0x03400000 0x0 0x10000>; 864 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 866 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 867 clock-names = "sdhci", "tmclk"; 868 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 869 reset-names = "sdhci"; 870 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 871 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 872 interconnect-names = "dma-mem", "write"; 873 iommus = <&smmu TEGRA186_SID_SDMMC1>; 874 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 875 pinctrl-0 = <&sdmmc1_3v3>; 876 pinctrl-1 = <&sdmmc1_1v8>; 877 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 878 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 879 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 880 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 881 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 882 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 883 nvidia,default-tap = <0x5>; 884 nvidia,default-trim = <0xb>; 885 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 886 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 887 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 888 status = "disabled"; 889 }; 890 891 sdmmc2: mmc@3420000 { 892 compatible = "nvidia,tegra186-sdhci"; 893 reg = <0x0 0x03420000 0x0 0x10000>; 894 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 896 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 897 clock-names = "sdhci", "tmclk"; 898 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 899 reset-names = "sdhci"; 900 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 901 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 902 interconnect-names = "dma-mem", "write"; 903 iommus = <&smmu TEGRA186_SID_SDMMC2>; 904 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 905 pinctrl-0 = <&sdmmc2_3v3>; 906 pinctrl-1 = <&sdmmc2_1v8>; 907 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 908 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 909 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 910 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 911 nvidia,default-tap = <0x5>; 912 nvidia,default-trim = <0xb>; 913 status = "disabled"; 914 }; 915 916 sdmmc3: mmc@3440000 { 917 compatible = "nvidia,tegra186-sdhci"; 918 reg = <0x0 0x03440000 0x0 0x10000>; 919 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 921 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 922 clock-names = "sdhci", "tmclk"; 923 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 924 reset-names = "sdhci"; 925 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 926 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 927 interconnect-names = "dma-mem", "write"; 928 iommus = <&smmu TEGRA186_SID_SDMMC3>; 929 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 930 pinctrl-0 = <&sdmmc3_3v3>; 931 pinctrl-1 = <&sdmmc3_1v8>; 932 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 933 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 934 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 935 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 936 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 937 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 938 nvidia,default-tap = <0x5>; 939 nvidia,default-trim = <0xb>; 940 status = "disabled"; 941 }; 942 943 sdmmc4: mmc@3460000 { 944 compatible = "nvidia,tegra186-sdhci"; 945 reg = <0x0 0x03460000 0x0 0x10000>; 946 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 948 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 949 clock-names = "sdhci", "tmclk"; 950 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 951 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 952 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 953 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 954 reset-names = "sdhci"; 955 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 956 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 957 interconnect-names = "dma-mem", "write"; 958 iommus = <&smmu TEGRA186_SID_SDMMC4>; 959 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 960 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 961 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 962 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 963 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 964 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 965 nvidia,default-tap = <0x9>; 966 nvidia,default-trim = <0x5>; 967 nvidia,dqs-trim = <63>; 968 mmc-hs400-1_8v; 969 supports-cqe; 970 status = "disabled"; 971 }; 972 973 hda@3510000 { 974 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 975 reg = <0x0 0x03510000 0x0 0x10000>; 976 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&bpmp TEGRA186_CLK_HDA>, 978 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 979 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 980 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 981 resets = <&bpmp TEGRA186_RESET_HDA>, 982 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 983 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 984 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 985 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 986 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 987 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 988 interconnect-names = "dma-mem", "write"; 989 iommus = <&smmu TEGRA186_SID_HDA>; 990 status = "disabled"; 991 }; 992 993 padctl: padctl@3520000 { 994 compatible = "nvidia,tegra186-xusb-padctl"; 995 reg = <0x0 0x03520000 0x0 0x1000>, 996 <0x0 0x03540000 0x0 0x1000>; 997 reg-names = "padctl", "ao"; 998 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 999 1000 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1001 reset-names = "padctl"; 1002 1003 status = "disabled"; 1004 1005 pads { 1006 usb2 { 1007 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1008 clock-names = "trk"; 1009 status = "disabled"; 1010 1011 lanes { 1012 usb2-0 { 1013 status = "disabled"; 1014 #phy-cells = <0>; 1015 }; 1016 1017 usb2-1 { 1018 status = "disabled"; 1019 #phy-cells = <0>; 1020 }; 1021 1022 usb2-2 { 1023 status = "disabled"; 1024 #phy-cells = <0>; 1025 }; 1026 }; 1027 }; 1028 1029 hsic { 1030 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1031 clock-names = "trk"; 1032 status = "disabled"; 1033 1034 lanes { 1035 hsic-0 { 1036 status = "disabled"; 1037 #phy-cells = <0>; 1038 }; 1039 }; 1040 }; 1041 1042 usb3 { 1043 status = "disabled"; 1044 1045 lanes { 1046 usb3-0 { 1047 status = "disabled"; 1048 #phy-cells = <0>; 1049 }; 1050 1051 usb3-1 { 1052 status = "disabled"; 1053 #phy-cells = <0>; 1054 }; 1055 1056 usb3-2 { 1057 status = "disabled"; 1058 #phy-cells = <0>; 1059 }; 1060 }; 1061 }; 1062 }; 1063 1064 ports { 1065 usb2-0 { 1066 status = "disabled"; 1067 }; 1068 1069 usb2-1 { 1070 status = "disabled"; 1071 }; 1072 1073 usb2-2 { 1074 status = "disabled"; 1075 }; 1076 1077 hsic-0 { 1078 status = "disabled"; 1079 }; 1080 1081 usb3-0 { 1082 status = "disabled"; 1083 }; 1084 1085 usb3-1 { 1086 status = "disabled"; 1087 }; 1088 1089 usb3-2 { 1090 status = "disabled"; 1091 }; 1092 }; 1093 }; 1094 1095 usb@3530000 { 1096 compatible = "nvidia,tegra186-xusb"; 1097 reg = <0x0 0x03530000 0x0 0x8000>, 1098 <0x0 0x03538000 0x0 0x1000>; 1099 reg-names = "hcd", "fpci"; 1100 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1103 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1104 <&bpmp TEGRA186_CLK_XUSB_SS>, 1105 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1106 <&bpmp TEGRA186_CLK_CLK_M>, 1107 <&bpmp TEGRA186_CLK_XUSB_FS>, 1108 <&bpmp TEGRA186_CLK_PLLU>, 1109 <&bpmp TEGRA186_CLK_CLK_M>, 1110 <&bpmp TEGRA186_CLK_PLLE>; 1111 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1112 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1113 "pll_u_480m", "clk_m", "pll_e"; 1114 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1115 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1116 power-domain-names = "xusb_host", "xusb_ss"; 1117 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1118 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1119 interconnect-names = "dma-mem", "write"; 1120 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 1125 nvidia,xusb-padctl = <&padctl>; 1126 }; 1127 1128 usb@3550000 { 1129 compatible = "nvidia,tegra186-xudc"; 1130 reg = <0x0 0x03550000 0x0 0x8000>, 1131 <0x0 0x03558000 0x0 0x1000>; 1132 reg-names = "base", "fpci"; 1133 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1135 <&bpmp TEGRA186_CLK_XUSB_SS>, 1136 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1137 <&bpmp TEGRA186_CLK_XUSB_FS>; 1138 clock-names = "dev", "ss", "ss_src", "fs_src"; 1139 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1140 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1141 interconnect-names = "dma-mem", "write"; 1142 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1143 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1144 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1145 power-domain-names = "dev", "ss"; 1146 nvidia,xusb-padctl = <&padctl>; 1147 status = "disabled"; 1148 }; 1149 1150 fuse@3820000 { 1151 compatible = "nvidia,tegra186-efuse"; 1152 reg = <0x0 0x03820000 0x0 0x10000>; 1153 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1154 clock-names = "fuse"; 1155 }; 1156 1157 gic: interrupt-controller@3881000 { 1158 compatible = "arm,gic-400"; 1159 #interrupt-cells = <3>; 1160 interrupt-controller; 1161 reg = <0x0 0x03881000 0x0 0x1000>, 1162 <0x0 0x03882000 0x0 0x2000>, 1163 <0x0 0x03884000 0x0 0x2000>, 1164 <0x0 0x03886000 0x0 0x2000>; 1165 interrupts = <GIC_PPI 9 1166 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1167 interrupt-parent = <&gic>; 1168 }; 1169 1170 cec@3960000 { 1171 compatible = "nvidia,tegra186-cec"; 1172 reg = <0x0 0x03960000 0x0 0x10000>; 1173 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&bpmp TEGRA186_CLK_CEC>; 1175 clock-names = "cec"; 1176 status = "disabled"; 1177 }; 1178 1179 hsp_top0: hsp@3c00000 { 1180 compatible = "nvidia,tegra186-hsp"; 1181 reg = <0x0 0x03c00000 0x0 0xa0000>; 1182 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1183 interrupt-names = "doorbell"; 1184 #mbox-cells = <2>; 1185 status = "disabled"; 1186 }; 1187 1188 gen2_i2c: i2c@c240000 { 1189 compatible = "nvidia,tegra186-i2c"; 1190 reg = <0x0 0x0c240000 0x0 0x10000>; 1191 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1195 clock-names = "div-clk"; 1196 resets = <&bpmp TEGRA186_RESET_I2C2>; 1197 reset-names = "i2c"; 1198 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1199 dma-coherent; 1200 dmas = <&gpcdma 22>, <&gpcdma 22>; 1201 dma-names = "rx", "tx"; 1202 status = "disabled"; 1203 }; 1204 1205 gen8_i2c: i2c@c250000 { 1206 compatible = "nvidia,tegra186-i2c"; 1207 reg = <0x0 0x0c250000 0x0 0x10000>; 1208 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1212 clock-names = "div-clk"; 1213 resets = <&bpmp TEGRA186_RESET_I2C8>; 1214 reset-names = "i2c"; 1215 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1216 dma-coherent; 1217 dmas = <&gpcdma 0>, <&gpcdma 0>; 1218 dma-names = "rx", "tx"; 1219 status = "disabled"; 1220 }; 1221 1222 uartc: serial@c280000 { 1223 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1224 reg = <0x0 0x0c280000 0x0 0x40>; 1225 reg-shift = <2>; 1226 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1228 clock-names = "serial"; 1229 resets = <&bpmp TEGRA186_RESET_UARTC>; 1230 reset-names = "serial"; 1231 status = "disabled"; 1232 }; 1233 1234 uartg: serial@c290000 { 1235 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1236 reg = <0x0 0x0c290000 0x0 0x40>; 1237 reg-shift = <2>; 1238 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1240 clock-names = "serial"; 1241 resets = <&bpmp TEGRA186_RESET_UARTG>; 1242 reset-names = "serial"; 1243 status = "disabled"; 1244 }; 1245 1246 rtc: rtc@c2a0000 { 1247 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1248 reg = <0 0x0c2a0000 0 0x10000>; 1249 interrupt-parent = <&pmc>; 1250 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1252 clock-names = "rtc"; 1253 status = "disabled"; 1254 }; 1255 1256 gpio_aon: gpio@c2f0000 { 1257 compatible = "nvidia,tegra186-gpio-aon"; 1258 reg-names = "security", "gpio"; 1259 reg = <0x0 0xc2f0000 0x0 0x1000>, 1260 <0x0 0xc2f1000 0x0 0x1000>; 1261 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1262 gpio-controller; 1263 #gpio-cells = <2>; 1264 interrupt-controller; 1265 #interrupt-cells = <2>; 1266 }; 1267 1268 pwm4: pwm@c340000 { 1269 compatible = "nvidia,tegra186-pwm"; 1270 reg = <0x0 0xc340000 0x0 0x10000>; 1271 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1272 resets = <&bpmp TEGRA186_RESET_PWM4>; 1273 reset-names = "pwm"; 1274 status = "disabled"; 1275 #pwm-cells = <2>; 1276 }; 1277 1278 pmc: pmc@c360000 { 1279 compatible = "nvidia,tegra186-pmc"; 1280 reg = <0 0x0c360000 0 0x10000>, 1281 <0 0x0c370000 0 0x10000>, 1282 <0 0x0c380000 0 0x10000>, 1283 <0 0x0c390000 0 0x10000>; 1284 reg-names = "pmc", "wake", "aotag", "scratch"; 1285 1286 #interrupt-cells = <2>; 1287 interrupt-controller; 1288 1289 sdmmc1_3v3: sdmmc1-3v3 { 1290 pins = "sdmmc1-hv"; 1291 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1292 }; 1293 1294 sdmmc1_1v8: sdmmc1-1v8 { 1295 pins = "sdmmc1-hv"; 1296 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1297 }; 1298 1299 sdmmc2_3v3: sdmmc2-3v3 { 1300 pins = "sdmmc2-hv"; 1301 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1302 }; 1303 1304 sdmmc2_1v8: sdmmc2-1v8 { 1305 pins = "sdmmc2-hv"; 1306 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1307 }; 1308 1309 sdmmc3_3v3: sdmmc3-3v3 { 1310 pins = "sdmmc3-hv"; 1311 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1312 }; 1313 1314 sdmmc3_1v8: sdmmc3-1v8 { 1315 pins = "sdmmc3-hv"; 1316 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1317 }; 1318 }; 1319 1320 ccplex@e000000 { 1321 compatible = "nvidia,tegra186-ccplex-cluster"; 1322 reg = <0x0 0x0e000000 0x0 0x400000>; 1323 1324 nvidia,bpmp = <&bpmp>; 1325 }; 1326 1327 pcie@10003000 { 1328 compatible = "nvidia,tegra186-pcie"; 1329 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1330 device_type = "pci"; 1331 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1332 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1333 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1334 reg-names = "pads", "afi", "cs"; 1335 1336 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1337 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1338 interrupt-names = "intr", "msi"; 1339 1340 #interrupt-cells = <1>; 1341 interrupt-map-mask = <0 0 0 0>; 1342 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1343 1344 bus-range = <0x00 0xff>; 1345 #address-cells = <3>; 1346 #size-cells = <2>; 1347 1348 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1349 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1350 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1351 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1352 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1353 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1354 1355 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1356 <&bpmp TEGRA186_CLK_AFI>, 1357 <&bpmp TEGRA186_CLK_PLLE>; 1358 clock-names = "pex", "afi", "pll_e"; 1359 1360 resets = <&bpmp TEGRA186_RESET_PCIE>, 1361 <&bpmp TEGRA186_RESET_AFI>, 1362 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1363 reset-names = "pex", "afi", "pcie_x"; 1364 1365 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1366 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1367 interconnect-names = "dma-mem", "write"; 1368 1369 iommus = <&smmu TEGRA186_SID_AFI>; 1370 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1371 iommu-map-mask = <0x0>; 1372 1373 status = "disabled"; 1374 1375 pci@1,0 { 1376 device_type = "pci"; 1377 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1378 reg = <0x000800 0 0 0 0>; 1379 status = "disabled"; 1380 1381 #address-cells = <3>; 1382 #size-cells = <2>; 1383 ranges; 1384 1385 nvidia,num-lanes = <2>; 1386 }; 1387 1388 pci@2,0 { 1389 device_type = "pci"; 1390 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1391 reg = <0x001000 0 0 0 0>; 1392 status = "disabled"; 1393 1394 #address-cells = <3>; 1395 #size-cells = <2>; 1396 ranges; 1397 1398 nvidia,num-lanes = <1>; 1399 }; 1400 1401 pci@3,0 { 1402 device_type = "pci"; 1403 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1404 reg = <0x001800 0 0 0 0>; 1405 status = "disabled"; 1406 1407 #address-cells = <3>; 1408 #size-cells = <2>; 1409 ranges; 1410 1411 nvidia,num-lanes = <1>; 1412 }; 1413 }; 1414 1415 smmu: iommu@12000000 { 1416 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1417 reg = <0 0x12000000 0 0x800000>; 1418 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1483 stream-match-mask = <0x7f80>; 1484 #global-interrupts = <1>; 1485 #iommu-cells = <1>; 1486 1487 nvidia,memory-controller = <&mc>; 1488 }; 1489 1490 host1x@13e00000 { 1491 compatible = "nvidia,tegra186-host1x"; 1492 reg = <0x0 0x13e00000 0x0 0x10000>, 1493 <0x0 0x13e10000 0x0 0x10000>; 1494 reg-names = "hypervisor", "vm"; 1495 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1497 interrupt-names = "syncpt", "host1x"; 1498 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1499 clock-names = "host1x"; 1500 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1501 reset-names = "host1x"; 1502 1503 #address-cells = <1>; 1504 #size-cells = <1>; 1505 1506 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1507 1508 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1509 interconnect-names = "dma-mem"; 1510 1511 iommus = <&smmu TEGRA186_SID_HOST1X>; 1512 1513 /* Context isolation domains */ 1514 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1515 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1516 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1517 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1518 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1519 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1520 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1521 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1522 1523 dpaux1: dpaux@15040000 { 1524 compatible = "nvidia,tegra186-dpaux"; 1525 reg = <0x15040000 0x10000>; 1526 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1527 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1528 <&bpmp TEGRA186_CLK_PLLDP>; 1529 clock-names = "dpaux", "parent"; 1530 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1531 reset-names = "dpaux"; 1532 status = "disabled"; 1533 1534 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1535 1536 state_dpaux1_aux: pinmux-aux { 1537 groups = "dpaux-io"; 1538 function = "aux"; 1539 }; 1540 1541 state_dpaux1_i2c: pinmux-i2c { 1542 groups = "dpaux-io"; 1543 function = "i2c"; 1544 }; 1545 1546 state_dpaux1_off: pinmux-off { 1547 groups = "dpaux-io"; 1548 function = "off"; 1549 }; 1550 1551 i2c-bus { 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 }; 1555 }; 1556 1557 display-hub@15200000 { 1558 compatible = "nvidia,tegra186-display"; 1559 reg = <0x15200000 0x00040000>; 1560 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1561 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1562 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1563 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1564 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1565 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1566 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1567 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1568 "wgrp3", "wgrp4", "wgrp5"; 1569 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1570 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1571 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1572 clock-names = "disp", "dsc", "hub"; 1573 status = "disabled"; 1574 1575 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1576 1577 #address-cells = <1>; 1578 #size-cells = <1>; 1579 1580 ranges = <0x15200000 0x15200000 0x40000>; 1581 1582 display@15200000 { 1583 compatible = "nvidia,tegra186-dc"; 1584 reg = <0x15200000 0x10000>; 1585 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1586 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1587 clock-names = "dc"; 1588 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1589 reset-names = "dc"; 1590 1591 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1592 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1593 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1594 interconnect-names = "dma-mem", "read-1"; 1595 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1596 1597 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1598 nvidia,head = <0>; 1599 }; 1600 1601 display@15210000 { 1602 compatible = "nvidia,tegra186-dc"; 1603 reg = <0x15210000 0x10000>; 1604 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1606 clock-names = "dc"; 1607 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1608 reset-names = "dc"; 1609 1610 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1611 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1612 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1613 interconnect-names = "dma-mem", "read-1"; 1614 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1615 1616 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1617 nvidia,head = <1>; 1618 }; 1619 1620 display@15220000 { 1621 compatible = "nvidia,tegra186-dc"; 1622 reg = <0x15220000 0x10000>; 1623 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1624 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1625 clock-names = "dc"; 1626 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1627 reset-names = "dc"; 1628 1629 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1630 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1631 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1632 interconnect-names = "dma-mem", "read-1"; 1633 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1634 1635 nvidia,outputs = <&sor0 &sor1>; 1636 nvidia,head = <2>; 1637 }; 1638 }; 1639 1640 dsia: dsi@15300000 { 1641 compatible = "nvidia,tegra186-dsi"; 1642 reg = <0x15300000 0x10000>; 1643 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1644 clocks = <&bpmp TEGRA186_CLK_DSI>, 1645 <&bpmp TEGRA186_CLK_DSIA_LP>, 1646 <&bpmp TEGRA186_CLK_PLLD>; 1647 clock-names = "dsi", "lp", "parent"; 1648 resets = <&bpmp TEGRA186_RESET_DSI>; 1649 reset-names = "dsi"; 1650 status = "disabled"; 1651 1652 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1653 }; 1654 1655 vic@15340000 { 1656 compatible = "nvidia,tegra186-vic"; 1657 reg = <0x15340000 0x40000>; 1658 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&bpmp TEGRA186_CLK_VIC>; 1660 clock-names = "vic"; 1661 resets = <&bpmp TEGRA186_RESET_VIC>; 1662 reset-names = "vic"; 1663 1664 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1665 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1666 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1667 interconnect-names = "dma-mem", "write"; 1668 iommus = <&smmu TEGRA186_SID_VIC>; 1669 }; 1670 1671 nvjpg@15380000 { 1672 compatible = "nvidia,tegra186-nvjpg"; 1673 reg = <0x15380000 0x40000>; 1674 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1675 clock-names = "nvjpg"; 1676 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1677 reset-names = "nvjpg"; 1678 1679 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1680 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1681 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1682 interconnect-names = "dma-mem", "write"; 1683 iommus = <&smmu TEGRA186_SID_NVJPG>; 1684 }; 1685 1686 dsib: dsi@15400000 { 1687 compatible = "nvidia,tegra186-dsi"; 1688 reg = <0x15400000 0x10000>; 1689 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1690 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1691 <&bpmp TEGRA186_CLK_DSIB_LP>, 1692 <&bpmp TEGRA186_CLK_PLLD>; 1693 clock-names = "dsi", "lp", "parent"; 1694 resets = <&bpmp TEGRA186_RESET_DSIB>; 1695 reset-names = "dsi"; 1696 status = "disabled"; 1697 1698 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1699 }; 1700 1701 nvdec@15480000 { 1702 compatible = "nvidia,tegra186-nvdec"; 1703 reg = <0x15480000 0x40000>; 1704 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1705 clock-names = "nvdec"; 1706 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1707 reset-names = "nvdec"; 1708 1709 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1710 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1711 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1712 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1713 interconnect-names = "dma-mem", "read-1", "write"; 1714 iommus = <&smmu TEGRA186_SID_NVDEC>; 1715 }; 1716 1717 nvenc@154c0000 { 1718 compatible = "nvidia,tegra186-nvenc"; 1719 reg = <0x154c0000 0x40000>; 1720 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1721 clock-names = "nvenc"; 1722 resets = <&bpmp TEGRA186_RESET_NVENC>; 1723 reset-names = "nvenc"; 1724 1725 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1726 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1727 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1728 interconnect-names = "dma-mem", "write"; 1729 iommus = <&smmu TEGRA186_SID_NVENC>; 1730 }; 1731 1732 sor0: sor@15540000 { 1733 compatible = "nvidia,tegra186-sor"; 1734 reg = <0x15540000 0x10000>; 1735 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1736 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1737 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1738 <&bpmp TEGRA186_CLK_PLLD2>, 1739 <&bpmp TEGRA186_CLK_PLLDP>, 1740 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1741 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1742 clock-names = "sor", "out", "parent", "dp", "safe", 1743 "pad"; 1744 resets = <&bpmp TEGRA186_RESET_SOR0>; 1745 reset-names = "sor"; 1746 pinctrl-0 = <&state_dpaux_aux>; 1747 pinctrl-1 = <&state_dpaux_i2c>; 1748 pinctrl-2 = <&state_dpaux_off>; 1749 pinctrl-names = "aux", "i2c", "off"; 1750 status = "disabled"; 1751 1752 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1753 nvidia,interface = <0>; 1754 }; 1755 1756 sor1: sor@15580000 { 1757 compatible = "nvidia,tegra186-sor"; 1758 reg = <0x15580000 0x10000>; 1759 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1760 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1761 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1762 <&bpmp TEGRA186_CLK_PLLD3>, 1763 <&bpmp TEGRA186_CLK_PLLDP>, 1764 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1765 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1766 clock-names = "sor", "out", "parent", "dp", "safe", 1767 "pad"; 1768 resets = <&bpmp TEGRA186_RESET_SOR1>; 1769 reset-names = "sor"; 1770 pinctrl-0 = <&state_dpaux1_aux>; 1771 pinctrl-1 = <&state_dpaux1_i2c>; 1772 pinctrl-2 = <&state_dpaux1_off>; 1773 pinctrl-names = "aux", "i2c", "off"; 1774 status = "disabled"; 1775 1776 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1777 nvidia,interface = <1>; 1778 }; 1779 1780 dpaux: dpaux@155c0000 { 1781 compatible = "nvidia,tegra186-dpaux"; 1782 reg = <0x155c0000 0x10000>; 1783 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1784 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1785 <&bpmp TEGRA186_CLK_PLLDP>; 1786 clock-names = "dpaux", "parent"; 1787 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1788 reset-names = "dpaux"; 1789 status = "disabled"; 1790 1791 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1792 1793 state_dpaux_aux: pinmux-aux { 1794 groups = "dpaux-io"; 1795 function = "aux"; 1796 }; 1797 1798 state_dpaux_i2c: pinmux-i2c { 1799 groups = "dpaux-io"; 1800 function = "i2c"; 1801 }; 1802 1803 state_dpaux_off: pinmux-off { 1804 groups = "dpaux-io"; 1805 function = "off"; 1806 }; 1807 1808 i2c-bus { 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 }; 1812 }; 1813 1814 padctl@15880000 { 1815 compatible = "nvidia,tegra186-dsi-padctl"; 1816 reg = <0x15880000 0x10000>; 1817 resets = <&bpmp TEGRA186_RESET_DSI>; 1818 reset-names = "dsi"; 1819 status = "disabled"; 1820 }; 1821 1822 dsic: dsi@15900000 { 1823 compatible = "nvidia,tegra186-dsi"; 1824 reg = <0x15900000 0x10000>; 1825 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1826 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1827 <&bpmp TEGRA186_CLK_DSIC_LP>, 1828 <&bpmp TEGRA186_CLK_PLLD>; 1829 clock-names = "dsi", "lp", "parent"; 1830 resets = <&bpmp TEGRA186_RESET_DSIC>; 1831 reset-names = "dsi"; 1832 status = "disabled"; 1833 1834 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1835 }; 1836 1837 dsid: dsi@15940000 { 1838 compatible = "nvidia,tegra186-dsi"; 1839 reg = <0x15940000 0x10000>; 1840 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1841 clocks = <&bpmp TEGRA186_CLK_DSID>, 1842 <&bpmp TEGRA186_CLK_DSID_LP>, 1843 <&bpmp TEGRA186_CLK_PLLD>; 1844 clock-names = "dsi", "lp", "parent"; 1845 resets = <&bpmp TEGRA186_RESET_DSID>; 1846 reset-names = "dsi"; 1847 status = "disabled"; 1848 1849 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1850 }; 1851 }; 1852 1853 gpu@17000000 { 1854 compatible = "nvidia,gp10b"; 1855 reg = <0x0 0x17000000 0x0 0x1000000>, 1856 <0x0 0x18000000 0x0 0x1000000>; 1857 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1859 interrupt-names = "stall", "nonstall"; 1860 1861 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1862 <&bpmp TEGRA186_CLK_GPU>; 1863 clock-names = "gpu", "pwr"; 1864 resets = <&bpmp TEGRA186_RESET_GPU>; 1865 reset-names = "gpu"; 1866 status = "disabled"; 1867 1868 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1869 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1870 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1871 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1872 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1873 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1874 }; 1875 1876 sram@30000000 { 1877 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1878 reg = <0x0 0x30000000 0x0 0x50000>; 1879 #address-cells = <1>; 1880 #size-cells = <1>; 1881 ranges = <0x0 0x0 0x30000000 0x50000>; 1882 no-memory-wc; 1883 1884 cpu_bpmp_tx: sram@4e000 { 1885 reg = <0x4e000 0x1000>; 1886 label = "cpu-bpmp-tx"; 1887 pool; 1888 }; 1889 1890 cpu_bpmp_rx: sram@4f000 { 1891 reg = <0x4f000 0x1000>; 1892 label = "cpu-bpmp-rx"; 1893 pool; 1894 }; 1895 }; 1896 1897 sata@3507000 { 1898 compatible = "nvidia,tegra186-ahci"; 1899 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1900 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1901 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1902 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1903 1904 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1905 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1906 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1907 interconnect-names = "dma-mem", "write"; 1908 iommus = <&smmu TEGRA186_SID_SATA>; 1909 1910 clocks = <&bpmp TEGRA186_CLK_SATA>, 1911 <&bpmp TEGRA186_CLK_SATA_OOB>; 1912 clock-names = "sata", "sata-oob"; 1913 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1914 <&bpmp TEGRA186_CLK_SATA_OOB>; 1915 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1916 <&bpmp TEGRA186_CLK_PLLP>; 1917 assigned-clock-rates = <102000000>, 1918 <204000000>; 1919 resets = <&bpmp TEGRA186_RESET_SATA>, 1920 <&bpmp TEGRA186_RESET_SATACOLD>; 1921 reset-names = "sata", "sata-cold"; 1922 status = "disabled"; 1923 }; 1924 1925 bpmp: bpmp { 1926 compatible = "nvidia,tegra186-bpmp"; 1927 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1928 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1929 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1930 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1931 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1932 iommus = <&smmu TEGRA186_SID_BPMP>; 1933 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1934 TEGRA_HSP_DB_MASTER_BPMP>; 1935 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1936 #clock-cells = <1>; 1937 #reset-cells = <1>; 1938 #power-domain-cells = <1>; 1939 1940 bpmp_i2c: i2c { 1941 compatible = "nvidia,tegra186-bpmp-i2c"; 1942 nvidia,bpmp-bus-id = <5>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 status = "disabled"; 1946 }; 1947 1948 bpmp_thermal: thermal { 1949 compatible = "nvidia,tegra186-bpmp-thermal"; 1950 #thermal-sensor-cells = <1>; 1951 }; 1952 }; 1953 1954 cpus { 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 1958 denver_0: cpu@0 { 1959 compatible = "nvidia,tegra186-denver"; 1960 device_type = "cpu"; 1961 i-cache-size = <0x20000>; 1962 i-cache-line-size = <64>; 1963 i-cache-sets = <512>; 1964 d-cache-size = <0x10000>; 1965 d-cache-line-size = <64>; 1966 d-cache-sets = <256>; 1967 next-level-cache = <&L2_DENVER>; 1968 reg = <0x000>; 1969 }; 1970 1971 denver_1: cpu@1 { 1972 compatible = "nvidia,tegra186-denver"; 1973 device_type = "cpu"; 1974 i-cache-size = <0x20000>; 1975 i-cache-line-size = <64>; 1976 i-cache-sets = <512>; 1977 d-cache-size = <0x10000>; 1978 d-cache-line-size = <64>; 1979 d-cache-sets = <256>; 1980 next-level-cache = <&L2_DENVER>; 1981 reg = <0x001>; 1982 }; 1983 1984 ca57_0: cpu@2 { 1985 compatible = "arm,cortex-a57"; 1986 device_type = "cpu"; 1987 i-cache-size = <0xC000>; 1988 i-cache-line-size = <64>; 1989 i-cache-sets = <256>; 1990 d-cache-size = <0x8000>; 1991 d-cache-line-size = <64>; 1992 d-cache-sets = <256>; 1993 next-level-cache = <&L2_A57>; 1994 reg = <0x100>; 1995 }; 1996 1997 ca57_1: cpu@3 { 1998 compatible = "arm,cortex-a57"; 1999 device_type = "cpu"; 2000 i-cache-size = <0xC000>; 2001 i-cache-line-size = <64>; 2002 i-cache-sets = <256>; 2003 d-cache-size = <0x8000>; 2004 d-cache-line-size = <64>; 2005 d-cache-sets = <256>; 2006 next-level-cache = <&L2_A57>; 2007 reg = <0x101>; 2008 }; 2009 2010 ca57_2: cpu@4 { 2011 compatible = "arm,cortex-a57"; 2012 device_type = "cpu"; 2013 i-cache-size = <0xC000>; 2014 i-cache-line-size = <64>; 2015 i-cache-sets = <256>; 2016 d-cache-size = <0x8000>; 2017 d-cache-line-size = <64>; 2018 d-cache-sets = <256>; 2019 next-level-cache = <&L2_A57>; 2020 reg = <0x102>; 2021 }; 2022 2023 ca57_3: cpu@5 { 2024 compatible = "arm,cortex-a57"; 2025 device_type = "cpu"; 2026 i-cache-size = <0xC000>; 2027 i-cache-line-size = <64>; 2028 i-cache-sets = <256>; 2029 d-cache-size = <0x8000>; 2030 d-cache-line-size = <64>; 2031 d-cache-sets = <256>; 2032 next-level-cache = <&L2_A57>; 2033 reg = <0x103>; 2034 }; 2035 2036 L2_DENVER: l2-cache0 { 2037 compatible = "cache"; 2038 cache-unified; 2039 cache-level = <2>; 2040 cache-size = <0x200000>; 2041 cache-line-size = <64>; 2042 cache-sets = <2048>; 2043 }; 2044 2045 L2_A57: l2-cache1 { 2046 compatible = "cache"; 2047 cache-unified; 2048 cache-level = <2>; 2049 cache-size = <0x200000>; 2050 cache-line-size = <64>; 2051 cache-sets = <2048>; 2052 }; 2053 }; 2054 2055 pmu_denver { 2056 compatible = "nvidia,denver-pmu"; 2057 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2059 interrupt-affinity = <&denver_0 &denver_1>; 2060 }; 2061 2062 pmu_a57 { 2063 compatible = "arm,cortex-a57-pmu"; 2064 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2068 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2069 }; 2070 2071 sound { 2072 status = "disabled"; 2073 2074 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2075 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2076 clock-names = "pll_a", "plla_out0"; 2077 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2078 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2079 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2080 assigned-clock-parents = <0>, 2081 <&bpmp TEGRA186_CLK_PLLA>, 2082 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2083 /* 2084 * PLLA supports dynamic ramp. Below initial rate is chosen 2085 * for this to work and oscillate between base rates required 2086 * for 8x and 11.025x sample rate streams. 2087 */ 2088 assigned-clock-rates = <258000000>; 2089 2090 iommus = <&smmu TEGRA186_SID_APE>; 2091 }; 2092 2093 thermal-zones { 2094 /* Cortex-A57 cluster */ 2095 cpu-thermal { 2096 polling-delay = <0>; 2097 polling-delay-passive = <1000>; 2098 2099 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2100 2101 trips { 2102 critical { 2103 temperature = <101000>; 2104 hysteresis = <0>; 2105 type = "critical"; 2106 }; 2107 }; 2108 2109 cooling-maps { 2110 }; 2111 }; 2112 2113 /* Denver cluster */ 2114 aux-thermal { 2115 polling-delay = <0>; 2116 polling-delay-passive = <1000>; 2117 2118 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2119 2120 trips { 2121 critical { 2122 temperature = <101000>; 2123 hysteresis = <0>; 2124 type = "critical"; 2125 }; 2126 }; 2127 2128 cooling-maps { 2129 }; 2130 }; 2131 2132 gpu-thermal { 2133 polling-delay = <0>; 2134 polling-delay-passive = <1000>; 2135 2136 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2137 2138 trips { 2139 critical { 2140 temperature = <101000>; 2141 hysteresis = <0>; 2142 type = "critical"; 2143 }; 2144 }; 2145 2146 cooling-maps { 2147 }; 2148 }; 2149 2150 pll-thermal { 2151 polling-delay = <0>; 2152 polling-delay-passive = <1000>; 2153 2154 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2155 2156 trips { 2157 critical { 2158 temperature = <101000>; 2159 hysteresis = <0>; 2160 type = "critical"; 2161 }; 2162 }; 2163 2164 cooling-maps { 2165 }; 2166 }; 2167 2168 ao-thermal { 2169 polling-delay = <0>; 2170 polling-delay-passive = <1000>; 2171 2172 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2173 2174 trips { 2175 critical { 2176 temperature = <101000>; 2177 hysteresis = <0>; 2178 type = "critical"; 2179 }; 2180 }; 2181 2182 cooling-maps { 2183 }; 2184 }; 2185 }; 2186 2187 timer { 2188 compatible = "arm,armv8-timer"; 2189 interrupts = <GIC_PPI 13 2190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2191 <GIC_PPI 14 2192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2193 <GIC_PPI 11 2194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2195 <GIC_PPI 10 2196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2197 interrupt-parent = <&gic>; 2198 always-on; 2199 }; 2200}; 2201