1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112 #dma-cells = <1>; 113 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114 dma-coherent; 115 status = "okay"; 116 }; 117 118 aconnect@2900000 { 119 compatible = "nvidia,tegra186-aconnect", 120 "nvidia,tegra210-aconnect"; 121 clocks = <&bpmp TEGRA186_CLK_APE>, 122 <&bpmp TEGRA186_CLK_APB2APE>; 123 clock-names = "ape", "apb2ape"; 124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x02900000 0x0 0x02900000 0x200000>; 128 status = "disabled"; 129 130 adma: dma-controller@2930000 { 131 compatible = "nvidia,tegra186-adma"; 132 reg = <0x02930000 0x20000>; 133 interrupt-parent = <&agic>; 134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&bpmp TEGRA186_CLK_AHUB>; 168 clock-names = "d_audio"; 169 status = "disabled"; 170 }; 171 172 agic: interrupt-controller@2a40000 { 173 compatible = "nvidia,tegra186-agic", 174 "nvidia,tegra210-agic"; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 reg = <0x02a41000 0x1000>, 178 <0x02a42000 0x2000>; 179 interrupts = <GIC_SPI 145 180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 181 clocks = <&bpmp TEGRA186_CLK_APE>; 182 clock-names = "clk"; 183 status = "disabled"; 184 }; 185 186 tegra_ahub: ahub@2900800 { 187 compatible = "nvidia,tegra186-ahub"; 188 reg = <0x02900800 0x800>; 189 clocks = <&bpmp TEGRA186_CLK_AHUB>; 190 clock-names = "ahub"; 191 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges = <0x02900800 0x02900800 0x11800>; 196 status = "disabled"; 197 198 tegra_admaif: admaif@290f000 { 199 compatible = "nvidia,tegra186-admaif"; 200 reg = <0x0290f000 0x1000>; 201 dmas = <&adma 1>, <&adma 1>, 202 <&adma 2>, <&adma 2>, 203 <&adma 3>, <&adma 3>, 204 <&adma 4>, <&adma 4>, 205 <&adma 5>, <&adma 5>, 206 <&adma 6>, <&adma 6>, 207 <&adma 7>, <&adma 7>, 208 <&adma 8>, <&adma 8>, 209 <&adma 9>, <&adma 9>, 210 <&adma 10>, <&adma 10>, 211 <&adma 11>, <&adma 11>, 212 <&adma 12>, <&adma 12>, 213 <&adma 13>, <&adma 13>, 214 <&adma 14>, <&adma 14>, 215 <&adma 15>, <&adma 15>, 216 <&adma 16>, <&adma 16>, 217 <&adma 17>, <&adma 17>, 218 <&adma 18>, <&adma 18>, 219 <&adma 19>, <&adma 19>, 220 <&adma 20>, <&adma 20>; 221 dma-names = "rx1", "tx1", 222 "rx2", "tx2", 223 "rx3", "tx3", 224 "rx4", "tx4", 225 "rx5", "tx5", 226 "rx6", "tx6", 227 "rx7", "tx7", 228 "rx8", "tx8", 229 "rx9", "tx9", 230 "rx10", "tx10", 231 "rx11", "tx11", 232 "rx12", "tx12", 233 "rx13", "tx13", 234 "rx14", "tx14", 235 "rx15", "tx15", 236 "rx16", "tx16", 237 "rx17", "tx17", 238 "rx18", "tx18", 239 "rx19", "tx19", 240 "rx20", "tx20"; 241 status = "disabled"; 242 }; 243 244 tegra_i2s1: i2s@2901000 { 245 compatible = "nvidia,tegra186-i2s", 246 "nvidia,tegra210-i2s"; 247 reg = <0x2901000 0x100>; 248 clocks = <&bpmp TEGRA186_CLK_I2S1>, 249 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250 clock-names = "i2s", "sync_input"; 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253 assigned-clock-rates = <1536000>; 254 sound-name-prefix = "I2S1"; 255 status = "disabled"; 256 }; 257 258 tegra_i2s2: i2s@2901100 { 259 compatible = "nvidia,tegra186-i2s", 260 "nvidia,tegra210-i2s"; 261 reg = <0x2901100 0x100>; 262 clocks = <&bpmp TEGRA186_CLK_I2S2>, 263 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264 clock-names = "i2s", "sync_input"; 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267 assigned-clock-rates = <1536000>; 268 sound-name-prefix = "I2S2"; 269 status = "disabled"; 270 }; 271 272 tegra_i2s3: i2s@2901200 { 273 compatible = "nvidia,tegra186-i2s", 274 "nvidia,tegra210-i2s"; 275 reg = <0x2901200 0x100>; 276 clocks = <&bpmp TEGRA186_CLK_I2S3>, 277 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278 clock-names = "i2s", "sync_input"; 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281 assigned-clock-rates = <1536000>; 282 sound-name-prefix = "I2S3"; 283 status = "disabled"; 284 }; 285 286 tegra_i2s4: i2s@2901300 { 287 compatible = "nvidia,tegra186-i2s", 288 "nvidia,tegra210-i2s"; 289 reg = <0x2901300 0x100>; 290 clocks = <&bpmp TEGRA186_CLK_I2S4>, 291 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292 clock-names = "i2s", "sync_input"; 293 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295 assigned-clock-rates = <1536000>; 296 sound-name-prefix = "I2S4"; 297 status = "disabled"; 298 }; 299 300 tegra_i2s5: i2s@2901400 { 301 compatible = "nvidia,tegra186-i2s", 302 "nvidia,tegra210-i2s"; 303 reg = <0x2901400 0x100>; 304 clocks = <&bpmp TEGRA186_CLK_I2S5>, 305 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306 clock-names = "i2s", "sync_input"; 307 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309 assigned-clock-rates = <1536000>; 310 sound-name-prefix = "I2S5"; 311 status = "disabled"; 312 }; 313 314 tegra_i2s6: i2s@2901500 { 315 compatible = "nvidia,tegra186-i2s", 316 "nvidia,tegra210-i2s"; 317 reg = <0x2901500 0x100>; 318 clocks = <&bpmp TEGRA186_CLK_I2S6>, 319 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320 clock-names = "i2s", "sync_input"; 321 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323 assigned-clock-rates = <1536000>; 324 sound-name-prefix = "I2S6"; 325 status = "disabled"; 326 }; 327 328 tegra_dmic1: dmic@2904000 { 329 compatible = "nvidia,tegra210-dmic"; 330 reg = <0x2904000 0x100>; 331 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC1"; 337 status = "disabled"; 338 }; 339 340 tegra_dmic2: dmic@2904100 { 341 compatible = "nvidia,tegra210-dmic"; 342 reg = <0x2904100 0x100>; 343 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344 clock-names = "dmic"; 345 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347 assigned-clock-rates = <3072000>; 348 sound-name-prefix = "DMIC2"; 349 status = "disabled"; 350 }; 351 352 tegra_dmic3: dmic@2904200 { 353 compatible = "nvidia,tegra210-dmic"; 354 reg = <0x2904200 0x100>; 355 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356 clock-names = "dmic"; 357 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359 assigned-clock-rates = <3072000>; 360 sound-name-prefix = "DMIC3"; 361 status = "disabled"; 362 }; 363 364 tegra_dmic4: dmic@2904300 { 365 compatible = "nvidia,tegra210-dmic"; 366 reg = <0x2904300 0x100>; 367 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368 clock-names = "dmic"; 369 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371 assigned-clock-rates = <3072000>; 372 sound-name-prefix = "DMIC4"; 373 status = "disabled"; 374 }; 375 376 tegra_dspk1: dspk@2905000 { 377 compatible = "nvidia,tegra186-dspk"; 378 reg = <0x2905000 0x100>; 379 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380 clock-names = "dspk"; 381 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383 assigned-clock-rates = <12288000>; 384 sound-name-prefix = "DSPK1"; 385 status = "disabled"; 386 }; 387 388 tegra_dspk2: dspk@2905100 { 389 compatible = "nvidia,tegra186-dspk"; 390 reg = <0x2905100 0x100>; 391 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392 clock-names = "dspk"; 393 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395 assigned-clock-rates = <12288000>; 396 sound-name-prefix = "DSPK2"; 397 status = "disabled"; 398 }; 399 400 tegra_sfc1: sfc@2902000 { 401 compatible = "nvidia,tegra186-sfc", 402 "nvidia,tegra210-sfc"; 403 reg = <0x2902000 0x200>; 404 sound-name-prefix = "SFC1"; 405 status = "disabled"; 406 }; 407 408 tegra_sfc2: sfc@2902200 { 409 compatible = "nvidia,tegra186-sfc", 410 "nvidia,tegra210-sfc"; 411 reg = <0x2902200 0x200>; 412 sound-name-prefix = "SFC2"; 413 status = "disabled"; 414 }; 415 416 tegra_sfc3: sfc@2902400 { 417 compatible = "nvidia,tegra186-sfc", 418 "nvidia,tegra210-sfc"; 419 reg = <0x2902400 0x200>; 420 sound-name-prefix = "SFC3"; 421 status = "disabled"; 422 }; 423 424 tegra_sfc4: sfc@2902600 { 425 compatible = "nvidia,tegra186-sfc", 426 "nvidia,tegra210-sfc"; 427 reg = <0x2902600 0x200>; 428 sound-name-prefix = "SFC4"; 429 status = "disabled"; 430 }; 431 432 tegra_mvc1: mvc@290a000 { 433 compatible = "nvidia,tegra186-mvc", 434 "nvidia,tegra210-mvc"; 435 reg = <0x290a000 0x200>; 436 sound-name-prefix = "MVC1"; 437 status = "disabled"; 438 }; 439 440 tegra_mvc2: mvc@290a200 { 441 compatible = "nvidia,tegra186-mvc", 442 "nvidia,tegra210-mvc"; 443 reg = <0x290a200 0x200>; 444 sound-name-prefix = "MVC2"; 445 status = "disabled"; 446 }; 447 448 tegra_amx1: amx@2903000 { 449 compatible = "nvidia,tegra186-amx", 450 "nvidia,tegra210-amx"; 451 reg = <0x2903000 0x100>; 452 sound-name-prefix = "AMX1"; 453 status = "disabled"; 454 }; 455 456 tegra_amx2: amx@2903100 { 457 compatible = "nvidia,tegra186-amx", 458 "nvidia,tegra210-amx"; 459 reg = <0x2903100 0x100>; 460 sound-name-prefix = "AMX2"; 461 status = "disabled"; 462 }; 463 464 tegra_amx3: amx@2903200 { 465 compatible = "nvidia,tegra186-amx", 466 "nvidia,tegra210-amx"; 467 reg = <0x2903200 0x100>; 468 sound-name-prefix = "AMX3"; 469 status = "disabled"; 470 }; 471 472 tegra_amx4: amx@2903300 { 473 compatible = "nvidia,tegra186-amx", 474 "nvidia,tegra210-amx"; 475 reg = <0x2903300 0x100>; 476 sound-name-prefix = "AMX4"; 477 status = "disabled"; 478 }; 479 480 tegra_adx1: adx@2903800 { 481 compatible = "nvidia,tegra186-adx", 482 "nvidia,tegra210-adx"; 483 reg = <0x2903800 0x100>; 484 sound-name-prefix = "ADX1"; 485 status = "disabled"; 486 }; 487 488 tegra_adx2: adx@2903900 { 489 compatible = "nvidia,tegra186-adx", 490 "nvidia,tegra210-adx"; 491 reg = <0x2903900 0x100>; 492 sound-name-prefix = "ADX2"; 493 status = "disabled"; 494 }; 495 496 tegra_adx3: adx@2903a00 { 497 compatible = "nvidia,tegra186-adx", 498 "nvidia,tegra210-adx"; 499 reg = <0x2903a00 0x100>; 500 sound-name-prefix = "ADX3"; 501 status = "disabled"; 502 }; 503 504 tegra_adx4: adx@2903b00 { 505 compatible = "nvidia,tegra186-adx", 506 "nvidia,tegra210-adx"; 507 reg = <0x2903b00 0x100>; 508 sound-name-prefix = "ADX4"; 509 status = "disabled"; 510 }; 511 512 tegra_amixer: amixer@290bb00 { 513 compatible = "nvidia,tegra186-amixer", 514 "nvidia,tegra210-amixer"; 515 reg = <0x290bb00 0x800>; 516 sound-name-prefix = "MIXER1"; 517 status = "disabled"; 518 }; 519 }; 520 }; 521 522 mc: memory-controller@2c00000 { 523 compatible = "nvidia,tegra186-mc"; 524 reg = <0x0 0x02c00000 0x0 0xb0000>; 525 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 526 status = "disabled"; 527 528 #interconnect-cells = <1>; 529 #address-cells = <2>; 530 #size-cells = <2>; 531 532 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 533 534 /* 535 * Memory clients have access to all 40 bits that the memory 536 * controller can address. 537 */ 538 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 539 540 emc: external-memory-controller@2c60000 { 541 compatible = "nvidia,tegra186-emc"; 542 reg = <0x0 0x02c60000 0x0 0x50000>; 543 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&bpmp TEGRA186_CLK_EMC>; 545 clock-names = "emc"; 546 547 #interconnect-cells = <0>; 548 549 nvidia,bpmp = <&bpmp>; 550 }; 551 }; 552 553 timer@3010000 { 554 compatible = "nvidia,tegra186-timer"; 555 reg = <0x0 0x03010000 0x0 0x000e0000>; 556 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 566 status = "disabled"; 567 }; 568 569 uarta: serial@3100000 { 570 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 571 reg = <0x0 0x03100000 0x0 0x40>; 572 reg-shift = <2>; 573 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&bpmp TEGRA186_CLK_UARTA>; 575 clock-names = "serial"; 576 resets = <&bpmp TEGRA186_RESET_UARTA>; 577 reset-names = "serial"; 578 status = "disabled"; 579 }; 580 581 uartb: serial@3110000 { 582 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 583 reg = <0x0 0x03110000 0x0 0x40>; 584 reg-shift = <2>; 585 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&bpmp TEGRA186_CLK_UARTB>; 587 clock-names = "serial"; 588 resets = <&bpmp TEGRA186_RESET_UARTB>; 589 reset-names = "serial"; 590 status = "disabled"; 591 }; 592 593 uartd: serial@3130000 { 594 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 595 reg = <0x0 0x03130000 0x0 0x40>; 596 reg-shift = <2>; 597 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&bpmp TEGRA186_CLK_UARTD>; 599 clock-names = "serial"; 600 resets = <&bpmp TEGRA186_RESET_UARTD>; 601 reset-names = "serial"; 602 status = "disabled"; 603 }; 604 605 uarte: serial@3140000 { 606 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 607 reg = <0x0 0x03140000 0x0 0x40>; 608 reg-shift = <2>; 609 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA186_CLK_UARTE>; 611 clock-names = "serial"; 612 resets = <&bpmp TEGRA186_RESET_UARTE>; 613 reset-names = "serial"; 614 status = "disabled"; 615 }; 616 617 uartf: serial@3150000 { 618 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 619 reg = <0x0 0x03150000 0x0 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA186_CLK_UARTF>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA186_RESET_UARTF>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 gen1_i2c: i2c@3160000 { 630 compatible = "nvidia,tegra186-i2c"; 631 reg = <0x0 0x03160000 0x0 0x10000>; 632 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 clocks = <&bpmp TEGRA186_CLK_I2C1>; 636 clock-names = "div-clk"; 637 resets = <&bpmp TEGRA186_RESET_I2C1>; 638 reset-names = "i2c"; 639 status = "disabled"; 640 }; 641 642 cam_i2c: i2c@3180000 { 643 compatible = "nvidia,tegra186-i2c"; 644 reg = <0x0 0x03180000 0x0 0x10000>; 645 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 clocks = <&bpmp TEGRA186_CLK_I2C3>; 649 clock-names = "div-clk"; 650 resets = <&bpmp TEGRA186_RESET_I2C3>; 651 reset-names = "i2c"; 652 status = "disabled"; 653 }; 654 655 /* shares pads with dpaux1 */ 656 dp_aux_ch1_i2c: i2c@3190000 { 657 compatible = "nvidia,tegra186-i2c"; 658 reg = <0x0 0x03190000 0x0 0x10000>; 659 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 clocks = <&bpmp TEGRA186_CLK_I2C4>; 663 clock-names = "div-clk"; 664 resets = <&bpmp TEGRA186_RESET_I2C4>; 665 reset-names = "i2c"; 666 pinctrl-names = "default", "idle"; 667 pinctrl-0 = <&state_dpaux1_i2c>; 668 pinctrl-1 = <&state_dpaux1_off>; 669 status = "disabled"; 670 }; 671 672 /* controlled by BPMP, should not be enabled */ 673 pwr_i2c: i2c@31a0000 { 674 compatible = "nvidia,tegra186-i2c"; 675 reg = <0x0 0x031a0000 0x0 0x10000>; 676 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&bpmp TEGRA186_CLK_I2C5>; 680 clock-names = "div-clk"; 681 resets = <&bpmp TEGRA186_RESET_I2C5>; 682 reset-names = "i2c"; 683 status = "disabled"; 684 }; 685 686 /* shares pads with dpaux0 */ 687 dp_aux_ch0_i2c: i2c@31b0000 { 688 compatible = "nvidia,tegra186-i2c"; 689 reg = <0x0 0x031b0000 0x0 0x10000>; 690 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 clocks = <&bpmp TEGRA186_CLK_I2C6>; 694 clock-names = "div-clk"; 695 resets = <&bpmp TEGRA186_RESET_I2C6>; 696 reset-names = "i2c"; 697 pinctrl-names = "default", "idle"; 698 pinctrl-0 = <&state_dpaux_i2c>; 699 pinctrl-1 = <&state_dpaux_off>; 700 status = "disabled"; 701 }; 702 703 gen7_i2c: i2c@31c0000 { 704 compatible = "nvidia,tegra186-i2c"; 705 reg = <0x0 0x031c0000 0x0 0x10000>; 706 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&bpmp TEGRA186_CLK_I2C7>; 710 clock-names = "div-clk"; 711 resets = <&bpmp TEGRA186_RESET_I2C7>; 712 reset-names = "i2c"; 713 status = "disabled"; 714 }; 715 716 gen9_i2c: i2c@31e0000 { 717 compatible = "nvidia,tegra186-i2c"; 718 reg = <0x0 0x031e0000 0x0 0x10000>; 719 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 clocks = <&bpmp TEGRA186_CLK_I2C9>; 723 clock-names = "div-clk"; 724 resets = <&bpmp TEGRA186_RESET_I2C9>; 725 reset-names = "i2c"; 726 status = "disabled"; 727 }; 728 729 pwm1: pwm@3280000 { 730 compatible = "nvidia,tegra186-pwm"; 731 reg = <0x0 0x3280000 0x0 0x10000>; 732 clocks = <&bpmp TEGRA186_CLK_PWM1>; 733 clock-names = "pwm"; 734 resets = <&bpmp TEGRA186_RESET_PWM1>; 735 reset-names = "pwm"; 736 status = "disabled"; 737 #pwm-cells = <2>; 738 }; 739 740 pwm2: pwm@3290000 { 741 compatible = "nvidia,tegra186-pwm"; 742 reg = <0x0 0x3290000 0x0 0x10000>; 743 clocks = <&bpmp TEGRA186_CLK_PWM2>; 744 clock-names = "pwm"; 745 resets = <&bpmp TEGRA186_RESET_PWM2>; 746 reset-names = "pwm"; 747 status = "disabled"; 748 #pwm-cells = <2>; 749 }; 750 751 pwm3: pwm@32a0000 { 752 compatible = "nvidia,tegra186-pwm"; 753 reg = <0x0 0x32a0000 0x0 0x10000>; 754 clocks = <&bpmp TEGRA186_CLK_PWM3>; 755 clock-names = "pwm"; 756 resets = <&bpmp TEGRA186_RESET_PWM3>; 757 reset-names = "pwm"; 758 status = "disabled"; 759 #pwm-cells = <2>; 760 }; 761 762 pwm5: pwm@32c0000 { 763 compatible = "nvidia,tegra186-pwm"; 764 reg = <0x0 0x32c0000 0x0 0x10000>; 765 clocks = <&bpmp TEGRA186_CLK_PWM5>; 766 clock-names = "pwm"; 767 resets = <&bpmp TEGRA186_RESET_PWM5>; 768 reset-names = "pwm"; 769 status = "disabled"; 770 #pwm-cells = <2>; 771 }; 772 773 pwm6: pwm@32d0000 { 774 compatible = "nvidia,tegra186-pwm"; 775 reg = <0x0 0x32d0000 0x0 0x10000>; 776 clocks = <&bpmp TEGRA186_CLK_PWM6>; 777 clock-names = "pwm"; 778 resets = <&bpmp TEGRA186_RESET_PWM6>; 779 reset-names = "pwm"; 780 status = "disabled"; 781 #pwm-cells = <2>; 782 }; 783 784 pwm7: pwm@32e0000 { 785 compatible = "nvidia,tegra186-pwm"; 786 reg = <0x0 0x32e0000 0x0 0x10000>; 787 clocks = <&bpmp TEGRA186_CLK_PWM7>; 788 clock-names = "pwm"; 789 resets = <&bpmp TEGRA186_RESET_PWM7>; 790 reset-names = "pwm"; 791 status = "disabled"; 792 #pwm-cells = <2>; 793 }; 794 795 pwm8: pwm@32f0000 { 796 compatible = "nvidia,tegra186-pwm"; 797 reg = <0x0 0x32f0000 0x0 0x10000>; 798 clocks = <&bpmp TEGRA186_CLK_PWM8>; 799 clock-names = "pwm"; 800 resets = <&bpmp TEGRA186_RESET_PWM8>; 801 reset-names = "pwm"; 802 status = "disabled"; 803 #pwm-cells = <2>; 804 }; 805 806 sdmmc1: mmc@3400000 { 807 compatible = "nvidia,tegra186-sdhci"; 808 reg = <0x0 0x03400000 0x0 0x10000>; 809 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 811 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 812 clock-names = "sdhci", "tmclk"; 813 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 814 reset-names = "sdhci"; 815 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 816 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 817 interconnect-names = "dma-mem", "write"; 818 iommus = <&smmu TEGRA186_SID_SDMMC1>; 819 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 820 pinctrl-0 = <&sdmmc1_3v3>; 821 pinctrl-1 = <&sdmmc1_1v8>; 822 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 823 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 824 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 825 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 826 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 827 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 828 nvidia,default-tap = <0x5>; 829 nvidia,default-trim = <0xb>; 830 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 831 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 832 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 833 status = "disabled"; 834 }; 835 836 sdmmc2: mmc@3420000 { 837 compatible = "nvidia,tegra186-sdhci"; 838 reg = <0x0 0x03420000 0x0 0x10000>; 839 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 841 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 842 clock-names = "sdhci", "tmclk"; 843 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 844 reset-names = "sdhci"; 845 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 846 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 847 interconnect-names = "dma-mem", "write"; 848 iommus = <&smmu TEGRA186_SID_SDMMC2>; 849 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 850 pinctrl-0 = <&sdmmc2_3v3>; 851 pinctrl-1 = <&sdmmc2_1v8>; 852 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 853 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 854 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 855 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 856 nvidia,default-tap = <0x5>; 857 nvidia,default-trim = <0xb>; 858 status = "disabled"; 859 }; 860 861 sdmmc3: mmc@3440000 { 862 compatible = "nvidia,tegra186-sdhci"; 863 reg = <0x0 0x03440000 0x0 0x10000>; 864 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 866 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 867 clock-names = "sdhci", "tmclk"; 868 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 869 reset-names = "sdhci"; 870 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 871 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 872 interconnect-names = "dma-mem", "write"; 873 iommus = <&smmu TEGRA186_SID_SDMMC3>; 874 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 875 pinctrl-0 = <&sdmmc3_3v3>; 876 pinctrl-1 = <&sdmmc3_1v8>; 877 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 878 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 879 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 880 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 881 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 882 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 883 nvidia,default-tap = <0x5>; 884 nvidia,default-trim = <0xb>; 885 status = "disabled"; 886 }; 887 888 sdmmc4: mmc@3460000 { 889 compatible = "nvidia,tegra186-sdhci"; 890 reg = <0x0 0x03460000 0x0 0x10000>; 891 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 893 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 894 clock-names = "sdhci", "tmclk"; 895 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 896 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 897 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 898 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 899 reset-names = "sdhci"; 900 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 901 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 902 interconnect-names = "dma-mem", "write"; 903 iommus = <&smmu TEGRA186_SID_SDMMC4>; 904 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 905 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 906 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 907 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 908 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 909 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 910 nvidia,default-tap = <0x9>; 911 nvidia,default-trim = <0x5>; 912 nvidia,dqs-trim = <63>; 913 mmc-hs400-1_8v; 914 supports-cqe; 915 status = "disabled"; 916 }; 917 918 hda@3510000 { 919 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 920 reg = <0x0 0x03510000 0x0 0x10000>; 921 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&bpmp TEGRA186_CLK_HDA>, 923 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 924 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 925 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 926 resets = <&bpmp TEGRA186_RESET_HDA>, 927 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 928 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 929 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 930 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 931 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 932 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 933 interconnect-names = "dma-mem", "write"; 934 iommus = <&smmu TEGRA186_SID_HDA>; 935 status = "disabled"; 936 }; 937 938 padctl: padctl@3520000 { 939 compatible = "nvidia,tegra186-xusb-padctl"; 940 reg = <0x0 0x03520000 0x0 0x1000>, 941 <0x0 0x03540000 0x0 0x1000>; 942 reg-names = "padctl", "ao"; 943 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 944 945 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 946 reset-names = "padctl"; 947 948 status = "disabled"; 949 950 pads { 951 usb2 { 952 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 953 clock-names = "trk"; 954 status = "disabled"; 955 956 lanes { 957 usb2-0 { 958 status = "disabled"; 959 #phy-cells = <0>; 960 }; 961 962 usb2-1 { 963 status = "disabled"; 964 #phy-cells = <0>; 965 }; 966 967 usb2-2 { 968 status = "disabled"; 969 #phy-cells = <0>; 970 }; 971 }; 972 }; 973 974 hsic { 975 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 976 clock-names = "trk"; 977 status = "disabled"; 978 979 lanes { 980 hsic-0 { 981 status = "disabled"; 982 #phy-cells = <0>; 983 }; 984 }; 985 }; 986 987 usb3 { 988 status = "disabled"; 989 990 lanes { 991 usb3-0 { 992 status = "disabled"; 993 #phy-cells = <0>; 994 }; 995 996 usb3-1 { 997 status = "disabled"; 998 #phy-cells = <0>; 999 }; 1000 1001 usb3-2 { 1002 status = "disabled"; 1003 #phy-cells = <0>; 1004 }; 1005 }; 1006 }; 1007 }; 1008 1009 ports { 1010 usb2-0 { 1011 status = "disabled"; 1012 }; 1013 1014 usb2-1 { 1015 status = "disabled"; 1016 }; 1017 1018 usb2-2 { 1019 status = "disabled"; 1020 }; 1021 1022 hsic-0 { 1023 status = "disabled"; 1024 }; 1025 1026 usb3-0 { 1027 status = "disabled"; 1028 }; 1029 1030 usb3-1 { 1031 status = "disabled"; 1032 }; 1033 1034 usb3-2 { 1035 status = "disabled"; 1036 }; 1037 }; 1038 }; 1039 1040 usb@3530000 { 1041 compatible = "nvidia,tegra186-xusb"; 1042 reg = <0x0 0x03530000 0x0 0x8000>, 1043 <0x0 0x03538000 0x0 0x1000>; 1044 reg-names = "hcd", "fpci"; 1045 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1048 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1049 <&bpmp TEGRA186_CLK_XUSB_SS>, 1050 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1051 <&bpmp TEGRA186_CLK_CLK_M>, 1052 <&bpmp TEGRA186_CLK_XUSB_FS>, 1053 <&bpmp TEGRA186_CLK_PLLU>, 1054 <&bpmp TEGRA186_CLK_CLK_M>, 1055 <&bpmp TEGRA186_CLK_PLLE>; 1056 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1057 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1058 "pll_u_480m", "clk_m", "pll_e"; 1059 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1060 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1061 power-domain-names = "xusb_host", "xusb_ss"; 1062 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1063 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1064 interconnect-names = "dma-mem", "write"; 1065 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 1070 nvidia,xusb-padctl = <&padctl>; 1071 }; 1072 1073 usb@3550000 { 1074 compatible = "nvidia,tegra186-xudc"; 1075 reg = <0x0 0x03550000 0x0 0x8000>, 1076 <0x0 0x03558000 0x0 0x1000>; 1077 reg-names = "base", "fpci"; 1078 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1080 <&bpmp TEGRA186_CLK_XUSB_SS>, 1081 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1082 <&bpmp TEGRA186_CLK_XUSB_FS>; 1083 clock-names = "dev", "ss", "ss_src", "fs_src"; 1084 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1085 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1086 interconnect-names = "dma-mem", "write"; 1087 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1088 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1089 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1090 power-domain-names = "dev", "ss"; 1091 nvidia,xusb-padctl = <&padctl>; 1092 status = "disabled"; 1093 }; 1094 1095 fuse@3820000 { 1096 compatible = "nvidia,tegra186-efuse"; 1097 reg = <0x0 0x03820000 0x0 0x10000>; 1098 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1099 clock-names = "fuse"; 1100 }; 1101 1102 gic: interrupt-controller@3881000 { 1103 compatible = "arm,gic-400"; 1104 #interrupt-cells = <3>; 1105 interrupt-controller; 1106 reg = <0x0 0x03881000 0x0 0x1000>, 1107 <0x0 0x03882000 0x0 0x2000>, 1108 <0x0 0x03884000 0x0 0x2000>, 1109 <0x0 0x03886000 0x0 0x2000>; 1110 interrupts = <GIC_PPI 9 1111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1112 interrupt-parent = <&gic>; 1113 }; 1114 1115 cec@3960000 { 1116 compatible = "nvidia,tegra186-cec"; 1117 reg = <0x0 0x03960000 0x0 0x10000>; 1118 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&bpmp TEGRA186_CLK_CEC>; 1120 clock-names = "cec"; 1121 status = "disabled"; 1122 }; 1123 1124 hsp_top0: hsp@3c00000 { 1125 compatible = "nvidia,tegra186-hsp"; 1126 reg = <0x0 0x03c00000 0x0 0xa0000>; 1127 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1128 interrupt-names = "doorbell"; 1129 #mbox-cells = <2>; 1130 status = "disabled"; 1131 }; 1132 1133 gen2_i2c: i2c@c240000 { 1134 compatible = "nvidia,tegra186-i2c"; 1135 reg = <0x0 0x0c240000 0x0 0x10000>; 1136 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1140 clock-names = "div-clk"; 1141 resets = <&bpmp TEGRA186_RESET_I2C2>; 1142 reset-names = "i2c"; 1143 status = "disabled"; 1144 }; 1145 1146 gen8_i2c: i2c@c250000 { 1147 compatible = "nvidia,tegra186-i2c"; 1148 reg = <0x0 0x0c250000 0x0 0x10000>; 1149 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1153 clock-names = "div-clk"; 1154 resets = <&bpmp TEGRA186_RESET_I2C8>; 1155 reset-names = "i2c"; 1156 status = "disabled"; 1157 }; 1158 1159 uartc: serial@c280000 { 1160 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1161 reg = <0x0 0x0c280000 0x0 0x40>; 1162 reg-shift = <2>; 1163 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1165 clock-names = "serial"; 1166 resets = <&bpmp TEGRA186_RESET_UARTC>; 1167 reset-names = "serial"; 1168 status = "disabled"; 1169 }; 1170 1171 uartg: serial@c290000 { 1172 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1173 reg = <0x0 0x0c290000 0x0 0x40>; 1174 reg-shift = <2>; 1175 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1177 clock-names = "serial"; 1178 resets = <&bpmp TEGRA186_RESET_UARTG>; 1179 reset-names = "serial"; 1180 status = "disabled"; 1181 }; 1182 1183 rtc: rtc@c2a0000 { 1184 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1185 reg = <0 0x0c2a0000 0 0x10000>; 1186 interrupt-parent = <&pmc>; 1187 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1189 clock-names = "rtc"; 1190 status = "disabled"; 1191 }; 1192 1193 gpio_aon: gpio@c2f0000 { 1194 compatible = "nvidia,tegra186-gpio-aon"; 1195 reg-names = "security", "gpio"; 1196 reg = <0x0 0xc2f0000 0x0 0x1000>, 1197 <0x0 0xc2f1000 0x0 0x1000>; 1198 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1199 gpio-controller; 1200 #gpio-cells = <2>; 1201 interrupt-controller; 1202 #interrupt-cells = <2>; 1203 }; 1204 1205 pwm4: pwm@c340000 { 1206 compatible = "nvidia,tegra186-pwm"; 1207 reg = <0x0 0xc340000 0x0 0x10000>; 1208 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1209 clock-names = "pwm"; 1210 resets = <&bpmp TEGRA186_RESET_PWM4>; 1211 reset-names = "pwm"; 1212 status = "disabled"; 1213 #pwm-cells = <2>; 1214 }; 1215 1216 pmc: pmc@c360000 { 1217 compatible = "nvidia,tegra186-pmc"; 1218 reg = <0 0x0c360000 0 0x10000>, 1219 <0 0x0c370000 0 0x10000>, 1220 <0 0x0c380000 0 0x10000>, 1221 <0 0x0c390000 0 0x10000>; 1222 reg-names = "pmc", "wake", "aotag", "scratch"; 1223 1224 #interrupt-cells = <2>; 1225 interrupt-controller; 1226 1227 sdmmc1_3v3: sdmmc1-3v3 { 1228 pins = "sdmmc1-hv"; 1229 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1230 }; 1231 1232 sdmmc1_1v8: sdmmc1-1v8 { 1233 pins = "sdmmc1-hv"; 1234 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1235 }; 1236 1237 sdmmc2_3v3: sdmmc2-3v3 { 1238 pins = "sdmmc2-hv"; 1239 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1240 }; 1241 1242 sdmmc2_1v8: sdmmc2-1v8 { 1243 pins = "sdmmc2-hv"; 1244 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1245 }; 1246 1247 sdmmc3_3v3: sdmmc3-3v3 { 1248 pins = "sdmmc3-hv"; 1249 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1250 }; 1251 1252 sdmmc3_1v8: sdmmc3-1v8 { 1253 pins = "sdmmc3-hv"; 1254 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1255 }; 1256 }; 1257 1258 ccplex@e000000 { 1259 compatible = "nvidia,tegra186-ccplex-cluster"; 1260 reg = <0x0 0x0e000000 0x0 0x400000>; 1261 1262 nvidia,bpmp = <&bpmp>; 1263 }; 1264 1265 pcie@10003000 { 1266 compatible = "nvidia,tegra186-pcie"; 1267 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1268 device_type = "pci"; 1269 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1270 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1271 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1272 reg-names = "pads", "afi", "cs"; 1273 1274 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1275 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1276 interrupt-names = "intr", "msi"; 1277 1278 #interrupt-cells = <1>; 1279 interrupt-map-mask = <0 0 0 0>; 1280 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1281 1282 bus-range = <0x00 0xff>; 1283 #address-cells = <3>; 1284 #size-cells = <2>; 1285 1286 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1287 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1288 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1289 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1290 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1291 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1292 1293 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1294 <&bpmp TEGRA186_CLK_AFI>, 1295 <&bpmp TEGRA186_CLK_PLLE>; 1296 clock-names = "pex", "afi", "pll_e"; 1297 1298 resets = <&bpmp TEGRA186_RESET_PCIE>, 1299 <&bpmp TEGRA186_RESET_AFI>, 1300 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1301 reset-names = "pex", "afi", "pcie_x"; 1302 1303 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1304 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1305 interconnect-names = "dma-mem", "write"; 1306 1307 iommus = <&smmu TEGRA186_SID_AFI>; 1308 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1309 iommu-map-mask = <0x0>; 1310 1311 status = "disabled"; 1312 1313 pci@1,0 { 1314 device_type = "pci"; 1315 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1316 reg = <0x000800 0 0 0 0>; 1317 status = "disabled"; 1318 1319 #address-cells = <3>; 1320 #size-cells = <2>; 1321 ranges; 1322 1323 nvidia,num-lanes = <2>; 1324 }; 1325 1326 pci@2,0 { 1327 device_type = "pci"; 1328 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1329 reg = <0x001000 0 0 0 0>; 1330 status = "disabled"; 1331 1332 #address-cells = <3>; 1333 #size-cells = <2>; 1334 ranges; 1335 1336 nvidia,num-lanes = <1>; 1337 }; 1338 1339 pci@3,0 { 1340 device_type = "pci"; 1341 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1342 reg = <0x001800 0 0 0 0>; 1343 status = "disabled"; 1344 1345 #address-cells = <3>; 1346 #size-cells = <2>; 1347 ranges; 1348 1349 nvidia,num-lanes = <1>; 1350 }; 1351 }; 1352 1353 smmu: iommu@12000000 { 1354 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1355 reg = <0 0x12000000 0 0x800000>; 1356 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1421 stream-match-mask = <0x7f80>; 1422 #global-interrupts = <1>; 1423 #iommu-cells = <1>; 1424 1425 nvidia,memory-controller = <&mc>; 1426 }; 1427 1428 host1x@13e00000 { 1429 compatible = "nvidia,tegra186-host1x"; 1430 reg = <0x0 0x13e00000 0x0 0x10000>, 1431 <0x0 0x13e10000 0x0 0x10000>; 1432 reg-names = "hypervisor", "vm"; 1433 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1435 interrupt-names = "syncpt", "host1x"; 1436 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1437 clock-names = "host1x"; 1438 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1439 reset-names = "host1x"; 1440 1441 #address-cells = <1>; 1442 #size-cells = <1>; 1443 1444 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1445 1446 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1447 interconnect-names = "dma-mem"; 1448 1449 iommus = <&smmu TEGRA186_SID_HOST1X>; 1450 1451 dpaux1: dpaux@15040000 { 1452 compatible = "nvidia,tegra186-dpaux"; 1453 reg = <0x15040000 0x10000>; 1454 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1456 <&bpmp TEGRA186_CLK_PLLDP>; 1457 clock-names = "dpaux", "parent"; 1458 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1459 reset-names = "dpaux"; 1460 status = "disabled"; 1461 1462 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1463 1464 state_dpaux1_aux: pinmux-aux { 1465 groups = "dpaux-io"; 1466 function = "aux"; 1467 }; 1468 1469 state_dpaux1_i2c: pinmux-i2c { 1470 groups = "dpaux-io"; 1471 function = "i2c"; 1472 }; 1473 1474 state_dpaux1_off: pinmux-off { 1475 groups = "dpaux-io"; 1476 function = "off"; 1477 }; 1478 1479 i2c-bus { 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 }; 1483 }; 1484 1485 display-hub@15200000 { 1486 compatible = "nvidia,tegra186-display"; 1487 reg = <0x15200000 0x00040000>; 1488 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1489 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1490 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1491 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1492 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1493 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1494 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1495 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1496 "wgrp3", "wgrp4", "wgrp5"; 1497 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1498 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1499 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1500 clock-names = "disp", "dsc", "hub"; 1501 status = "disabled"; 1502 1503 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1504 1505 #address-cells = <1>; 1506 #size-cells = <1>; 1507 1508 ranges = <0x15200000 0x15200000 0x40000>; 1509 1510 display@15200000 { 1511 compatible = "nvidia,tegra186-dc"; 1512 reg = <0x15200000 0x10000>; 1513 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1515 clock-names = "dc"; 1516 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1517 reset-names = "dc"; 1518 1519 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1520 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1521 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1522 interconnect-names = "dma-mem", "read-1"; 1523 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1524 1525 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1526 nvidia,head = <0>; 1527 }; 1528 1529 display@15210000 { 1530 compatible = "nvidia,tegra186-dc"; 1531 reg = <0x15210000 0x10000>; 1532 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1534 clock-names = "dc"; 1535 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1536 reset-names = "dc"; 1537 1538 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1539 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1540 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1541 interconnect-names = "dma-mem", "read-1"; 1542 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1543 1544 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1545 nvidia,head = <1>; 1546 }; 1547 1548 display@15220000 { 1549 compatible = "nvidia,tegra186-dc"; 1550 reg = <0x15220000 0x10000>; 1551 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1552 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1553 clock-names = "dc"; 1554 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1555 reset-names = "dc"; 1556 1557 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1558 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1559 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1560 interconnect-names = "dma-mem", "read-1"; 1561 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1562 1563 nvidia,outputs = <&sor0 &sor1>; 1564 nvidia,head = <2>; 1565 }; 1566 }; 1567 1568 dsia: dsi@15300000 { 1569 compatible = "nvidia,tegra186-dsi"; 1570 reg = <0x15300000 0x10000>; 1571 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1572 clocks = <&bpmp TEGRA186_CLK_DSI>, 1573 <&bpmp TEGRA186_CLK_DSIA_LP>, 1574 <&bpmp TEGRA186_CLK_PLLD>; 1575 clock-names = "dsi", "lp", "parent"; 1576 resets = <&bpmp TEGRA186_RESET_DSI>; 1577 reset-names = "dsi"; 1578 status = "disabled"; 1579 1580 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1581 }; 1582 1583 vic@15340000 { 1584 compatible = "nvidia,tegra186-vic"; 1585 reg = <0x15340000 0x40000>; 1586 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1587 clocks = <&bpmp TEGRA186_CLK_VIC>; 1588 clock-names = "vic"; 1589 resets = <&bpmp TEGRA186_RESET_VIC>; 1590 reset-names = "vic"; 1591 1592 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1593 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1594 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1595 interconnect-names = "dma-mem", "write"; 1596 iommus = <&smmu TEGRA186_SID_VIC>; 1597 }; 1598 1599 nvjpg@15380000 { 1600 compatible = "nvidia,tegra186-nvjpg"; 1601 reg = <0x15380000 0x40000>; 1602 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1603 clock-names = "nvjpg"; 1604 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1605 reset-names = "nvjpg"; 1606 1607 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1608 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1609 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1610 interconnect-names = "dma-mem", "write"; 1611 iommus = <&smmu TEGRA186_SID_NVJPG>; 1612 }; 1613 1614 dsib: dsi@15400000 { 1615 compatible = "nvidia,tegra186-dsi"; 1616 reg = <0x15400000 0x10000>; 1617 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1619 <&bpmp TEGRA186_CLK_DSIB_LP>, 1620 <&bpmp TEGRA186_CLK_PLLD>; 1621 clock-names = "dsi", "lp", "parent"; 1622 resets = <&bpmp TEGRA186_RESET_DSIB>; 1623 reset-names = "dsi"; 1624 status = "disabled"; 1625 1626 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1627 }; 1628 1629 nvdec@15480000 { 1630 compatible = "nvidia,tegra186-nvdec"; 1631 reg = <0x15480000 0x40000>; 1632 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1633 clock-names = "nvdec"; 1634 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1635 reset-names = "nvdec"; 1636 1637 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1638 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1639 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1640 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1641 interconnect-names = "dma-mem", "read-1", "write"; 1642 iommus = <&smmu TEGRA186_SID_NVDEC>; 1643 }; 1644 1645 nvenc@154c0000 { 1646 compatible = "nvidia,tegra186-nvenc"; 1647 reg = <0x154c0000 0x40000>; 1648 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1649 clock-names = "nvenc"; 1650 resets = <&bpmp TEGRA186_RESET_NVENC>; 1651 reset-names = "nvenc"; 1652 1653 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1654 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1655 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1656 interconnect-names = "dma-mem", "write"; 1657 iommus = <&smmu TEGRA186_SID_NVENC>; 1658 }; 1659 1660 sor0: sor@15540000 { 1661 compatible = "nvidia,tegra186-sor"; 1662 reg = <0x15540000 0x10000>; 1663 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1664 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1665 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1666 <&bpmp TEGRA186_CLK_PLLD2>, 1667 <&bpmp TEGRA186_CLK_PLLDP>, 1668 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1669 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1670 clock-names = "sor", "out", "parent", "dp", "safe", 1671 "pad"; 1672 resets = <&bpmp TEGRA186_RESET_SOR0>; 1673 reset-names = "sor"; 1674 pinctrl-0 = <&state_dpaux_aux>; 1675 pinctrl-1 = <&state_dpaux_i2c>; 1676 pinctrl-2 = <&state_dpaux_off>; 1677 pinctrl-names = "aux", "i2c", "off"; 1678 status = "disabled"; 1679 1680 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1681 nvidia,interface = <0>; 1682 }; 1683 1684 sor1: sor@15580000 { 1685 compatible = "nvidia,tegra186-sor"; 1686 reg = <0x15580000 0x10000>; 1687 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1688 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1689 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1690 <&bpmp TEGRA186_CLK_PLLD3>, 1691 <&bpmp TEGRA186_CLK_PLLDP>, 1692 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1693 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1694 clock-names = "sor", "out", "parent", "dp", "safe", 1695 "pad"; 1696 resets = <&bpmp TEGRA186_RESET_SOR1>; 1697 reset-names = "sor"; 1698 pinctrl-0 = <&state_dpaux1_aux>; 1699 pinctrl-1 = <&state_dpaux1_i2c>; 1700 pinctrl-2 = <&state_dpaux1_off>; 1701 pinctrl-names = "aux", "i2c", "off"; 1702 status = "disabled"; 1703 1704 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1705 nvidia,interface = <1>; 1706 }; 1707 1708 dpaux: dpaux@155c0000 { 1709 compatible = "nvidia,tegra186-dpaux"; 1710 reg = <0x155c0000 0x10000>; 1711 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1712 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1713 <&bpmp TEGRA186_CLK_PLLDP>; 1714 clock-names = "dpaux", "parent"; 1715 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1716 reset-names = "dpaux"; 1717 status = "disabled"; 1718 1719 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1720 1721 state_dpaux_aux: pinmux-aux { 1722 groups = "dpaux-io"; 1723 function = "aux"; 1724 }; 1725 1726 state_dpaux_i2c: pinmux-i2c { 1727 groups = "dpaux-io"; 1728 function = "i2c"; 1729 }; 1730 1731 state_dpaux_off: pinmux-off { 1732 groups = "dpaux-io"; 1733 function = "off"; 1734 }; 1735 1736 i2c-bus { 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 }; 1740 }; 1741 1742 padctl@15880000 { 1743 compatible = "nvidia,tegra186-dsi-padctl"; 1744 reg = <0x15880000 0x10000>; 1745 resets = <&bpmp TEGRA186_RESET_DSI>; 1746 reset-names = "dsi"; 1747 status = "disabled"; 1748 }; 1749 1750 dsic: dsi@15900000 { 1751 compatible = "nvidia,tegra186-dsi"; 1752 reg = <0x15900000 0x10000>; 1753 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1754 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1755 <&bpmp TEGRA186_CLK_DSIC_LP>, 1756 <&bpmp TEGRA186_CLK_PLLD>; 1757 clock-names = "dsi", "lp", "parent"; 1758 resets = <&bpmp TEGRA186_RESET_DSIC>; 1759 reset-names = "dsi"; 1760 status = "disabled"; 1761 1762 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1763 }; 1764 1765 dsid: dsi@15940000 { 1766 compatible = "nvidia,tegra186-dsi"; 1767 reg = <0x15940000 0x10000>; 1768 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1769 clocks = <&bpmp TEGRA186_CLK_DSID>, 1770 <&bpmp TEGRA186_CLK_DSID_LP>, 1771 <&bpmp TEGRA186_CLK_PLLD>; 1772 clock-names = "dsi", "lp", "parent"; 1773 resets = <&bpmp TEGRA186_RESET_DSID>; 1774 reset-names = "dsi"; 1775 status = "disabled"; 1776 1777 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1778 }; 1779 }; 1780 1781 gpu@17000000 { 1782 compatible = "nvidia,gp10b"; 1783 reg = <0x0 0x17000000 0x0 0x1000000>, 1784 <0x0 0x18000000 0x0 0x1000000>; 1785 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1787 interrupt-names = "stall", "nonstall"; 1788 1789 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1790 <&bpmp TEGRA186_CLK_GPU>; 1791 clock-names = "gpu", "pwr"; 1792 resets = <&bpmp TEGRA186_RESET_GPU>; 1793 reset-names = "gpu"; 1794 status = "disabled"; 1795 1796 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1797 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1798 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1799 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1800 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1801 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1802 }; 1803 1804 sram@30000000 { 1805 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1806 reg = <0x0 0x30000000 0x0 0x50000>; 1807 #address-cells = <1>; 1808 #size-cells = <1>; 1809 ranges = <0x0 0x0 0x30000000 0x50000>; 1810 1811 cpu_bpmp_tx: sram@4e000 { 1812 reg = <0x4e000 0x1000>; 1813 label = "cpu-bpmp-tx"; 1814 pool; 1815 }; 1816 1817 cpu_bpmp_rx: sram@4f000 { 1818 reg = <0x4f000 0x1000>; 1819 label = "cpu-bpmp-rx"; 1820 pool; 1821 }; 1822 }; 1823 1824 sata@3507000 { 1825 compatible = "nvidia,tegra186-ahci"; 1826 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1827 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1828 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1829 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1830 1831 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1832 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1833 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1834 interconnect-names = "dma-mem", "write"; 1835 iommus = <&smmu TEGRA186_SID_SATA>; 1836 1837 clocks = <&bpmp TEGRA186_CLK_SATA>, 1838 <&bpmp TEGRA186_CLK_SATA_OOB>; 1839 clock-names = "sata", "sata-oob"; 1840 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1841 <&bpmp TEGRA186_CLK_SATA_OOB>; 1842 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1843 <&bpmp TEGRA186_CLK_PLLP>; 1844 assigned-clock-rates = <102000000>, 1845 <204000000>; 1846 resets = <&bpmp TEGRA186_RESET_SATA>, 1847 <&bpmp TEGRA186_RESET_SATACOLD>; 1848 reset-names = "sata", "sata-cold"; 1849 status = "disabled"; 1850 }; 1851 1852 bpmp: bpmp { 1853 compatible = "nvidia,tegra186-bpmp"; 1854 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1855 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1856 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1857 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1858 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1859 iommus = <&smmu TEGRA186_SID_BPMP>; 1860 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1861 TEGRA_HSP_DB_MASTER_BPMP>; 1862 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1863 #clock-cells = <1>; 1864 #reset-cells = <1>; 1865 #power-domain-cells = <1>; 1866 1867 bpmp_i2c: i2c { 1868 compatible = "nvidia,tegra186-bpmp-i2c"; 1869 nvidia,bpmp-bus-id = <5>; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 status = "disabled"; 1873 }; 1874 1875 bpmp_thermal: thermal { 1876 compatible = "nvidia,tegra186-bpmp-thermal"; 1877 #thermal-sensor-cells = <1>; 1878 }; 1879 }; 1880 1881 cpus { 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 1885 denver_0: cpu@0 { 1886 compatible = "nvidia,tegra186-denver"; 1887 device_type = "cpu"; 1888 i-cache-size = <0x20000>; 1889 i-cache-line-size = <64>; 1890 i-cache-sets = <512>; 1891 d-cache-size = <0x10000>; 1892 d-cache-line-size = <64>; 1893 d-cache-sets = <256>; 1894 next-level-cache = <&L2_DENVER>; 1895 reg = <0x000>; 1896 }; 1897 1898 denver_1: cpu@1 { 1899 compatible = "nvidia,tegra186-denver"; 1900 device_type = "cpu"; 1901 i-cache-size = <0x20000>; 1902 i-cache-line-size = <64>; 1903 i-cache-sets = <512>; 1904 d-cache-size = <0x10000>; 1905 d-cache-line-size = <64>; 1906 d-cache-sets = <256>; 1907 next-level-cache = <&L2_DENVER>; 1908 reg = <0x001>; 1909 }; 1910 1911 ca57_0: cpu@2 { 1912 compatible = "arm,cortex-a57"; 1913 device_type = "cpu"; 1914 i-cache-size = <0xC000>; 1915 i-cache-line-size = <64>; 1916 i-cache-sets = <256>; 1917 d-cache-size = <0x8000>; 1918 d-cache-line-size = <64>; 1919 d-cache-sets = <256>; 1920 next-level-cache = <&L2_A57>; 1921 reg = <0x100>; 1922 }; 1923 1924 ca57_1: cpu@3 { 1925 compatible = "arm,cortex-a57"; 1926 device_type = "cpu"; 1927 i-cache-size = <0xC000>; 1928 i-cache-line-size = <64>; 1929 i-cache-sets = <256>; 1930 d-cache-size = <0x8000>; 1931 d-cache-line-size = <64>; 1932 d-cache-sets = <256>; 1933 next-level-cache = <&L2_A57>; 1934 reg = <0x101>; 1935 }; 1936 1937 ca57_2: cpu@4 { 1938 compatible = "arm,cortex-a57"; 1939 device_type = "cpu"; 1940 i-cache-size = <0xC000>; 1941 i-cache-line-size = <64>; 1942 i-cache-sets = <256>; 1943 d-cache-size = <0x8000>; 1944 d-cache-line-size = <64>; 1945 d-cache-sets = <256>; 1946 next-level-cache = <&L2_A57>; 1947 reg = <0x102>; 1948 }; 1949 1950 ca57_3: cpu@5 { 1951 compatible = "arm,cortex-a57"; 1952 device_type = "cpu"; 1953 i-cache-size = <0xC000>; 1954 i-cache-line-size = <64>; 1955 i-cache-sets = <256>; 1956 d-cache-size = <0x8000>; 1957 d-cache-line-size = <64>; 1958 d-cache-sets = <256>; 1959 next-level-cache = <&L2_A57>; 1960 reg = <0x103>; 1961 }; 1962 1963 L2_DENVER: l2-cache0 { 1964 compatible = "cache"; 1965 cache-unified; 1966 cache-level = <2>; 1967 cache-size = <0x200000>; 1968 cache-line-size = <64>; 1969 cache-sets = <2048>; 1970 }; 1971 1972 L2_A57: l2-cache1 { 1973 compatible = "cache"; 1974 cache-unified; 1975 cache-level = <2>; 1976 cache-size = <0x200000>; 1977 cache-line-size = <64>; 1978 cache-sets = <2048>; 1979 }; 1980 }; 1981 1982 pmu_denver { 1983 compatible = "nvidia,denver-pmu"; 1984 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1986 interrupt-affinity = <&denver_0 &denver_1>; 1987 }; 1988 1989 pmu_a57 { 1990 compatible = "arm,cortex-a57-pmu"; 1991 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1995 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 1996 }; 1997 1998 sound { 1999 status = "disabled"; 2000 2001 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2002 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2003 clock-names = "pll_a", "plla_out0"; 2004 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2005 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2006 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2007 assigned-clock-parents = <0>, 2008 <&bpmp TEGRA186_CLK_PLLA>, 2009 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2010 /* 2011 * PLLA supports dynamic ramp. Below initial rate is chosen 2012 * for this to work and oscillate between base rates required 2013 * for 8x and 11.025x sample rate streams. 2014 */ 2015 assigned-clock-rates = <258000000>; 2016 2017 iommus = <&smmu TEGRA186_SID_APE>; 2018 }; 2019 2020 thermal-zones { 2021 /* Cortex-A57 cluster */ 2022 cpu-thermal { 2023 polling-delay = <0>; 2024 polling-delay-passive = <1000>; 2025 2026 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2027 2028 trips { 2029 critical { 2030 temperature = <101000>; 2031 hysteresis = <0>; 2032 type = "critical"; 2033 }; 2034 }; 2035 2036 cooling-maps { 2037 }; 2038 }; 2039 2040 /* Denver cluster */ 2041 aux-thermal { 2042 polling-delay = <0>; 2043 polling-delay-passive = <1000>; 2044 2045 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2046 2047 trips { 2048 critical { 2049 temperature = <101000>; 2050 hysteresis = <0>; 2051 type = "critical"; 2052 }; 2053 }; 2054 2055 cooling-maps { 2056 }; 2057 }; 2058 2059 gpu-thermal { 2060 polling-delay = <0>; 2061 polling-delay-passive = <1000>; 2062 2063 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2064 2065 trips { 2066 critical { 2067 temperature = <101000>; 2068 hysteresis = <0>; 2069 type = "critical"; 2070 }; 2071 }; 2072 2073 cooling-maps { 2074 }; 2075 }; 2076 2077 pll-thermal { 2078 polling-delay = <0>; 2079 polling-delay-passive = <1000>; 2080 2081 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2082 2083 trips { 2084 critical { 2085 temperature = <101000>; 2086 hysteresis = <0>; 2087 type = "critical"; 2088 }; 2089 }; 2090 2091 cooling-maps { 2092 }; 2093 }; 2094 2095 ao-thermal { 2096 polling-delay = <0>; 2097 polling-delay-passive = <1000>; 2098 2099 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2100 2101 trips { 2102 critical { 2103 temperature = <101000>; 2104 hysteresis = <0>; 2105 type = "critical"; 2106 }; 2107 }; 2108 2109 cooling-maps { 2110 }; 2111 }; 2112 }; 2113 2114 timer { 2115 compatible = "arm,armv8-timer"; 2116 interrupts = <GIC_PPI 13 2117 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2118 <GIC_PPI 14 2119 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2120 <GIC_PPI 11 2121 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2122 <GIC_PPI 10 2123 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2124 interrupt-parent = <&gic>; 2125 always-on; 2126 }; 2127}; 2128