1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 iommus = <&smmu TEGRA186_SID_EQOS>; 64 status = "disabled"; 65 66 snps,write-requests = <1>; 67 snps,read-requests = <3>; 68 snps,burst-map = <0x7>; 69 snps,txpbl = <32>; 70 snps,rxpbl = <8>; 71 }; 72 73 aconnect { 74 compatible = "nvidia,tegra186-aconnect", 75 "nvidia,tegra210-aconnect"; 76 clocks = <&bpmp TEGRA186_CLK_APE>, 77 <&bpmp TEGRA186_CLK_APB2APE>; 78 clock-names = "ape", "apb2ape"; 79 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges = <0x02900000 0x0 0x02900000 0x200000>; 83 status = "disabled"; 84 85 dma-controller@2930000 { 86 compatible = "nvidia,tegra186-adma"; 87 reg = <0x02930000 0x20000>; 88 interrupt-parent = <&agic>; 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 121 #dma-cells = <1>; 122 clocks = <&bpmp TEGRA186_CLK_AHUB>; 123 clock-names = "d_audio"; 124 status = "disabled"; 125 }; 126 127 agic: interrupt-controller@2a40000 { 128 compatible = "nvidia,tegra186-agic", 129 "nvidia,tegra210-agic"; 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 reg = <0x02a41000 0x1000>, 133 <0x02a42000 0x2000>; 134 interrupts = <GIC_SPI 145 135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 136 clocks = <&bpmp TEGRA186_CLK_APE>; 137 clock-names = "clk"; 138 status = "disabled"; 139 }; 140 }; 141 142 memory-controller@2c00000 { 143 compatible = "nvidia,tegra186-mc"; 144 reg = <0x0 0x02c00000 0x0 0xb0000>; 145 status = "disabled"; 146 }; 147 148 uarta: serial@3100000 { 149 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 150 reg = <0x0 0x03100000 0x0 0x40>; 151 reg-shift = <2>; 152 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&bpmp TEGRA186_CLK_UARTA>; 154 clock-names = "serial"; 155 resets = <&bpmp TEGRA186_RESET_UARTA>; 156 reset-names = "serial"; 157 status = "disabled"; 158 }; 159 160 uartb: serial@3110000 { 161 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 162 reg = <0x0 0x03110000 0x0 0x40>; 163 reg-shift = <2>; 164 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&bpmp TEGRA186_CLK_UARTB>; 166 clock-names = "serial"; 167 resets = <&bpmp TEGRA186_RESET_UARTB>; 168 reset-names = "serial"; 169 status = "disabled"; 170 }; 171 172 uartd: serial@3130000 { 173 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 174 reg = <0x0 0x03130000 0x0 0x40>; 175 reg-shift = <2>; 176 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&bpmp TEGRA186_CLK_UARTD>; 178 clock-names = "serial"; 179 resets = <&bpmp TEGRA186_RESET_UARTD>; 180 reset-names = "serial"; 181 status = "disabled"; 182 }; 183 184 uarte: serial@3140000 { 185 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 186 reg = <0x0 0x03140000 0x0 0x40>; 187 reg-shift = <2>; 188 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&bpmp TEGRA186_CLK_UARTE>; 190 clock-names = "serial"; 191 resets = <&bpmp TEGRA186_RESET_UARTE>; 192 reset-names = "serial"; 193 status = "disabled"; 194 }; 195 196 uartf: serial@3150000 { 197 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 198 reg = <0x0 0x03150000 0x0 0x40>; 199 reg-shift = <2>; 200 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&bpmp TEGRA186_CLK_UARTF>; 202 clock-names = "serial"; 203 resets = <&bpmp TEGRA186_RESET_UARTF>; 204 reset-names = "serial"; 205 status = "disabled"; 206 }; 207 208 gen1_i2c: i2c@3160000 { 209 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 210 reg = <0x0 0x03160000 0x0 0x10000>; 211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 clocks = <&bpmp TEGRA186_CLK_I2C1>; 215 clock-names = "div-clk"; 216 resets = <&bpmp TEGRA186_RESET_I2C1>; 217 reset-names = "i2c"; 218 status = "disabled"; 219 }; 220 221 cam_i2c: i2c@3180000 { 222 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 223 reg = <0x0 0x03180000 0x0 0x10000>; 224 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 clocks = <&bpmp TEGRA186_CLK_I2C3>; 228 clock-names = "div-clk"; 229 resets = <&bpmp TEGRA186_RESET_I2C3>; 230 reset-names = "i2c"; 231 status = "disabled"; 232 }; 233 234 /* shares pads with dpaux1 */ 235 dp_aux_ch1_i2c: i2c@3190000 { 236 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 237 reg = <0x0 0x03190000 0x0 0x10000>; 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 clocks = <&bpmp TEGRA186_CLK_I2C4>; 242 clock-names = "div-clk"; 243 resets = <&bpmp TEGRA186_RESET_I2C4>; 244 reset-names = "i2c"; 245 pinctrl-names = "default", "idle"; 246 pinctrl-0 = <&state_dpaux1_i2c>; 247 pinctrl-1 = <&state_dpaux1_off>; 248 status = "disabled"; 249 }; 250 251 /* controlled by BPMP, should not be enabled */ 252 pwr_i2c: i2c@31a0000 { 253 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 254 reg = <0x0 0x031a0000 0x0 0x10000>; 255 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clocks = <&bpmp TEGRA186_CLK_I2C5>; 259 clock-names = "div-clk"; 260 resets = <&bpmp TEGRA186_RESET_I2C5>; 261 reset-names = "i2c"; 262 status = "disabled"; 263 }; 264 265 /* shares pads with dpaux0 */ 266 dp_aux_ch0_i2c: i2c@31b0000 { 267 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 268 reg = <0x0 0x031b0000 0x0 0x10000>; 269 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 clocks = <&bpmp TEGRA186_CLK_I2C6>; 273 clock-names = "div-clk"; 274 resets = <&bpmp TEGRA186_RESET_I2C6>; 275 reset-names = "i2c"; 276 pinctrl-names = "default", "idle"; 277 pinctrl-0 = <&state_dpaux_i2c>; 278 pinctrl-1 = <&state_dpaux_off>; 279 status = "disabled"; 280 }; 281 282 gen7_i2c: i2c@31c0000 { 283 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 284 reg = <0x0 0x031c0000 0x0 0x10000>; 285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clocks = <&bpmp TEGRA186_CLK_I2C7>; 289 clock-names = "div-clk"; 290 resets = <&bpmp TEGRA186_RESET_I2C7>; 291 reset-names = "i2c"; 292 status = "disabled"; 293 }; 294 295 gen9_i2c: i2c@31e0000 { 296 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 297 reg = <0x0 0x031e0000 0x0 0x10000>; 298 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clocks = <&bpmp TEGRA186_CLK_I2C9>; 302 clock-names = "div-clk"; 303 resets = <&bpmp TEGRA186_RESET_I2C9>; 304 reset-names = "i2c"; 305 status = "disabled"; 306 }; 307 308 sdmmc1: sdhci@3400000 { 309 compatible = "nvidia,tegra186-sdhci"; 310 reg = <0x0 0x03400000 0x0 0x10000>; 311 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 313 clock-names = "sdhci"; 314 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 315 reset-names = "sdhci"; 316 iommus = <&smmu TEGRA186_SID_SDMMC1>; 317 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 318 pinctrl-0 = <&sdmmc1_3v3>; 319 pinctrl-1 = <&sdmmc1_1v8>; 320 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 321 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 322 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 323 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 324 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 325 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 326 nvidia,default-tap = <0x5>; 327 nvidia,default-trim = <0xb>; 328 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 329 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 330 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 331 status = "disabled"; 332 }; 333 334 sdmmc2: sdhci@3420000 { 335 compatible = "nvidia,tegra186-sdhci"; 336 reg = <0x0 0x03420000 0x0 0x10000>; 337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 339 clock-names = "sdhci"; 340 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 341 reset-names = "sdhci"; 342 iommus = <&smmu TEGRA186_SID_SDMMC2>; 343 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 344 pinctrl-0 = <&sdmmc2_3v3>; 345 pinctrl-1 = <&sdmmc2_1v8>; 346 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 347 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 348 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 349 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 350 nvidia,default-tap = <0x5>; 351 nvidia,default-trim = <0xb>; 352 status = "disabled"; 353 }; 354 355 sdmmc3: sdhci@3440000 { 356 compatible = "nvidia,tegra186-sdhci"; 357 reg = <0x0 0x03440000 0x0 0x10000>; 358 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 360 clock-names = "sdhci"; 361 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 362 reset-names = "sdhci"; 363 iommus = <&smmu TEGRA186_SID_SDMMC3>; 364 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 365 pinctrl-0 = <&sdmmc3_3v3>; 366 pinctrl-1 = <&sdmmc3_1v8>; 367 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 368 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 369 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 370 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 371 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 372 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 373 nvidia,default-tap = <0x5>; 374 nvidia,default-trim = <0xb>; 375 status = "disabled"; 376 }; 377 378 sdmmc4: sdhci@3460000 { 379 compatible = "nvidia,tegra186-sdhci"; 380 reg = <0x0 0x03460000 0x0 0x10000>; 381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 383 clock-names = "sdhci"; 384 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 385 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 386 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 387 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 388 reset-names = "sdhci"; 389 iommus = <&smmu TEGRA186_SID_SDMMC4>; 390 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 391 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 392 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 393 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 394 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 395 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 396 nvidia,default-tap = <0x9>; 397 nvidia,default-trim = <0x5>; 398 nvidia,dqs-trim = <63>; 399 mmc-hs400-1_8v; 400 supports-cqe; 401 status = "disabled"; 402 }; 403 404 hda@3510000 { 405 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 406 reg = <0x0 0x03510000 0x0 0x10000>; 407 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&bpmp TEGRA186_CLK_HDA>, 409 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 410 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 411 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 412 resets = <&bpmp TEGRA186_RESET_HDA>, 413 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 414 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 415 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 416 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 417 iommus = <&smmu TEGRA186_SID_HDA>; 418 status = "disabled"; 419 }; 420 421 padctl: padctl@3520000 { 422 compatible = "nvidia,tegra186-xusb-padctl"; 423 reg = <0x0 0x03520000 0x0 0x1000>, 424 <0x0 0x03540000 0x0 0x1000>; 425 reg-names = "padctl", "ao"; 426 427 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 428 reset-names = "padctl"; 429 430 status = "disabled"; 431 432 pads { 433 usb2 { 434 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 435 clock-names = "trk"; 436 status = "disabled"; 437 438 lanes { 439 usb2-0 { 440 status = "disabled"; 441 #phy-cells = <0>; 442 }; 443 444 usb2-1 { 445 status = "disabled"; 446 #phy-cells = <0>; 447 }; 448 449 usb2-2 { 450 status = "disabled"; 451 #phy-cells = <0>; 452 }; 453 }; 454 }; 455 456 hsic { 457 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 458 clock-names = "trk"; 459 status = "disabled"; 460 461 lanes { 462 hsic-0 { 463 status = "disabled"; 464 #phy-cells = <0>; 465 }; 466 }; 467 }; 468 469 usb3 { 470 status = "disabled"; 471 472 lanes { 473 usb3-0 { 474 status = "disabled"; 475 #phy-cells = <0>; 476 }; 477 478 usb3-1 { 479 status = "disabled"; 480 #phy-cells = <0>; 481 }; 482 483 usb3-2 { 484 status = "disabled"; 485 #phy-cells = <0>; 486 }; 487 }; 488 }; 489 }; 490 491 ports { 492 usb2-0 { 493 status = "disabled"; 494 }; 495 496 usb2-1 { 497 status = "disabled"; 498 }; 499 500 usb2-2 { 501 status = "disabled"; 502 }; 503 504 hsic-0 { 505 status = "disabled"; 506 }; 507 508 usb3-0 { 509 status = "disabled"; 510 }; 511 512 usb3-1 { 513 status = "disabled"; 514 }; 515 516 usb3-2 { 517 status = "disabled"; 518 }; 519 }; 520 }; 521 522 usb@3530000 { 523 compatible = "nvidia,tegra186-xusb"; 524 reg = <0x0 0x03530000 0x0 0x8000>, 525 <0x0 0x03538000 0x0 0x1000>; 526 reg-names = "hcd", "fpci"; 527 528 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 531 532 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 533 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 534 <&bpmp TEGRA186_CLK_XUSB_SS>, 535 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 536 <&bpmp TEGRA186_CLK_CLK_M>, 537 <&bpmp TEGRA186_CLK_XUSB_FS>, 538 <&bpmp TEGRA186_CLK_PLLU>, 539 <&bpmp TEGRA186_CLK_CLK_M>, 540 <&bpmp TEGRA186_CLK_PLLE>; 541 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 542 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 543 "pll_u_480m", "clk_m", "pll_e"; 544 545 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 546 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 547 power-domain-names = "xusb_host", "xusb_ss"; 548 nvidia,xusb-padctl = <&padctl>; 549 550 status = "disabled"; 551 552 #address-cells = <1>; 553 #size-cells = <0>; 554 }; 555 556 fuse@3820000 { 557 compatible = "nvidia,tegra186-efuse"; 558 reg = <0x0 0x03820000 0x0 0x10000>; 559 clocks = <&bpmp TEGRA186_CLK_FUSE>; 560 clock-names = "fuse"; 561 }; 562 563 gic: interrupt-controller@3881000 { 564 compatible = "arm,gic-400"; 565 #interrupt-cells = <3>; 566 interrupt-controller; 567 reg = <0x0 0x03881000 0x0 0x1000>, 568 <0x0 0x03882000 0x0 0x2000>; 569 interrupts = <GIC_PPI 9 570 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 571 interrupt-parent = <&gic>; 572 }; 573 574 cec@3960000 { 575 compatible = "nvidia,tegra186-cec"; 576 reg = <0x0 0x03960000 0x0 0x10000>; 577 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&bpmp TEGRA186_CLK_CEC>; 579 clock-names = "cec"; 580 status = "disabled"; 581 }; 582 583 hsp_top0: hsp@3c00000 { 584 compatible = "nvidia,tegra186-hsp"; 585 reg = <0x0 0x03c00000 0x0 0xa0000>; 586 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "doorbell"; 588 #mbox-cells = <2>; 589 status = "disabled"; 590 }; 591 592 gen2_i2c: i2c@c240000 { 593 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 594 reg = <0x0 0x0c240000 0x0 0x10000>; 595 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 clocks = <&bpmp TEGRA186_CLK_I2C2>; 599 clock-names = "div-clk"; 600 resets = <&bpmp TEGRA186_RESET_I2C2>; 601 reset-names = "i2c"; 602 status = "disabled"; 603 }; 604 605 gen8_i2c: i2c@c250000 { 606 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 607 reg = <0x0 0x0c250000 0x0 0x10000>; 608 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clocks = <&bpmp TEGRA186_CLK_I2C8>; 612 clock-names = "div-clk"; 613 resets = <&bpmp TEGRA186_RESET_I2C8>; 614 reset-names = "i2c"; 615 status = "disabled"; 616 }; 617 618 uartc: serial@c280000 { 619 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 620 reg = <0x0 0x0c280000 0x0 0x40>; 621 reg-shift = <2>; 622 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&bpmp TEGRA186_CLK_UARTC>; 624 clock-names = "serial"; 625 resets = <&bpmp TEGRA186_RESET_UARTC>; 626 reset-names = "serial"; 627 status = "disabled"; 628 }; 629 630 uartg: serial@c290000 { 631 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 632 reg = <0x0 0x0c290000 0x0 0x40>; 633 reg-shift = <2>; 634 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&bpmp TEGRA186_CLK_UARTG>; 636 clock-names = "serial"; 637 resets = <&bpmp TEGRA186_RESET_UARTG>; 638 reset-names = "serial"; 639 status = "disabled"; 640 }; 641 642 rtc: rtc@c2a0000 { 643 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 644 reg = <0 0x0c2a0000 0 0x10000>; 645 interrupt-parent = <&pmc>; 646 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 648 clock-names = "rtc"; 649 status = "disabled"; 650 }; 651 652 gpio_aon: gpio@c2f0000 { 653 compatible = "nvidia,tegra186-gpio-aon"; 654 reg-names = "security", "gpio"; 655 reg = <0x0 0xc2f0000 0x0 0x1000>, 656 <0x0 0xc2f1000 0x0 0x1000>; 657 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 658 gpio-controller; 659 #gpio-cells = <2>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 }; 663 664 pmc: pmc@c360000 { 665 compatible = "nvidia,tegra186-pmc"; 666 reg = <0 0x0c360000 0 0x10000>, 667 <0 0x0c370000 0 0x10000>, 668 <0 0x0c380000 0 0x10000>, 669 <0 0x0c390000 0 0x10000>; 670 reg-names = "pmc", "wake", "aotag", "scratch"; 671 672 #interrupt-cells = <2>; 673 interrupt-controller; 674 675 sdmmc1_3v3: sdmmc1-3v3 { 676 pins = "sdmmc1-hv"; 677 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 678 }; 679 680 sdmmc1_1v8: sdmmc1-1v8 { 681 pins = "sdmmc1-hv"; 682 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 683 }; 684 685 sdmmc2_3v3: sdmmc2-3v3 { 686 pins = "sdmmc2-hv"; 687 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 688 }; 689 690 sdmmc2_1v8: sdmmc2-1v8 { 691 pins = "sdmmc2-hv"; 692 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 693 }; 694 695 sdmmc3_3v3: sdmmc3-3v3 { 696 pins = "sdmmc3-hv"; 697 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 698 }; 699 700 sdmmc3_1v8: sdmmc3-1v8 { 701 pins = "sdmmc3-hv"; 702 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 703 }; 704 }; 705 706 ccplex@e000000 { 707 compatible = "nvidia,tegra186-ccplex-cluster"; 708 reg = <0x0 0x0e000000 0x0 0x3fffff>; 709 710 nvidia,bpmp = <&bpmp>; 711 }; 712 713 pcie@10003000 { 714 compatible = "nvidia,tegra186-pcie"; 715 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 716 device_type = "pci"; 717 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 718 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 719 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 720 reg-names = "pads", "afi", "cs"; 721 722 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 723 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 724 interrupt-names = "intr", "msi"; 725 726 #interrupt-cells = <1>; 727 interrupt-map-mask = <0 0 0 0>; 728 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 729 730 bus-range = <0x00 0xff>; 731 #address-cells = <3>; 732 #size-cells = <2>; 733 734 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 735 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 736 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 737 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 738 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 739 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 740 741 clocks = <&bpmp TEGRA186_CLK_AFI>, 742 <&bpmp TEGRA186_CLK_PCIE>, 743 <&bpmp TEGRA186_CLK_PLLE>; 744 clock-names = "afi", "pex", "pll_e"; 745 746 resets = <&bpmp TEGRA186_RESET_AFI>, 747 <&bpmp TEGRA186_RESET_PCIE>, 748 <&bpmp TEGRA186_RESET_PCIEXCLK>; 749 reset-names = "afi", "pex", "pcie_x"; 750 751 iommus = <&smmu TEGRA186_SID_AFI>; 752 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 753 iommu-map-mask = <0x0>; 754 755 status = "disabled"; 756 757 pci@1,0 { 758 device_type = "pci"; 759 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 760 reg = <0x000800 0 0 0 0>; 761 status = "disabled"; 762 763 #address-cells = <3>; 764 #size-cells = <2>; 765 ranges; 766 767 nvidia,num-lanes = <2>; 768 }; 769 770 pci@2,0 { 771 device_type = "pci"; 772 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 773 reg = <0x001000 0 0 0 0>; 774 status = "disabled"; 775 776 #address-cells = <3>; 777 #size-cells = <2>; 778 ranges; 779 780 nvidia,num-lanes = <1>; 781 }; 782 783 pci@3,0 { 784 device_type = "pci"; 785 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 786 reg = <0x001800 0 0 0 0>; 787 status = "disabled"; 788 789 #address-cells = <3>; 790 #size-cells = <2>; 791 ranges; 792 793 nvidia,num-lanes = <1>; 794 }; 795 }; 796 797 smmu: iommu@12000000 { 798 compatible = "arm,mmu-500"; 799 reg = <0 0x12000000 0 0x800000>; 800 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 865 stream-match-mask = <0x7f80>; 866 #global-interrupts = <1>; 867 #iommu-cells = <1>; 868 }; 869 870 host1x@13e00000 { 871 compatible = "nvidia,tegra186-host1x", "simple-bus"; 872 reg = <0x0 0x13e00000 0x0 0x10000>, 873 <0x0 0x13e10000 0x0 0x10000>; 874 reg-names = "hypervisor", "vm"; 875 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 878 clock-names = "host1x"; 879 resets = <&bpmp TEGRA186_RESET_HOST1X>; 880 reset-names = "host1x"; 881 882 #address-cells = <1>; 883 #size-cells = <1>; 884 885 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 886 iommus = <&smmu TEGRA186_SID_HOST1X>; 887 888 dpaux1: dpaux@15040000 { 889 compatible = "nvidia,tegra186-dpaux"; 890 reg = <0x15040000 0x10000>; 891 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 893 <&bpmp TEGRA186_CLK_PLLDP>; 894 clock-names = "dpaux", "parent"; 895 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 896 reset-names = "dpaux"; 897 status = "disabled"; 898 899 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 900 901 state_dpaux1_aux: pinmux-aux { 902 groups = "dpaux-io"; 903 function = "aux"; 904 }; 905 906 state_dpaux1_i2c: pinmux-i2c { 907 groups = "dpaux-io"; 908 function = "i2c"; 909 }; 910 911 state_dpaux1_off: pinmux-off { 912 groups = "dpaux-io"; 913 function = "off"; 914 }; 915 916 i2c-bus { 917 #address-cells = <1>; 918 #size-cells = <0>; 919 }; 920 }; 921 922 display-hub@15200000 { 923 compatible = "nvidia,tegra186-display", "simple-bus"; 924 reg = <0x15200000 0x00040000>; 925 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 926 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 927 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 928 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 929 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 930 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 931 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 932 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 933 "wgrp3", "wgrp4", "wgrp5"; 934 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 935 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 936 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 937 clock-names = "disp", "dsc", "hub"; 938 status = "disabled"; 939 940 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 941 942 #address-cells = <1>; 943 #size-cells = <1>; 944 945 ranges = <0x15200000 0x15200000 0x40000>; 946 947 display@15200000 { 948 compatible = "nvidia,tegra186-dc"; 949 reg = <0x15200000 0x10000>; 950 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 952 clock-names = "dc"; 953 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 954 reset-names = "dc"; 955 956 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 957 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 958 959 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 960 nvidia,head = <0>; 961 }; 962 963 display@15210000 { 964 compatible = "nvidia,tegra186-dc"; 965 reg = <0x15210000 0x10000>; 966 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 968 clock-names = "dc"; 969 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 970 reset-names = "dc"; 971 972 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 973 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 974 975 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 976 nvidia,head = <1>; 977 }; 978 979 display@15220000 { 980 compatible = "nvidia,tegra186-dc"; 981 reg = <0x15220000 0x10000>; 982 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 984 clock-names = "dc"; 985 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 986 reset-names = "dc"; 987 988 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 989 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 990 991 nvidia,outputs = <&sor0 &sor1>; 992 nvidia,head = <2>; 993 }; 994 }; 995 996 dsia: dsi@15300000 { 997 compatible = "nvidia,tegra186-dsi"; 998 reg = <0x15300000 0x10000>; 999 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&bpmp TEGRA186_CLK_DSI>, 1001 <&bpmp TEGRA186_CLK_DSIA_LP>, 1002 <&bpmp TEGRA186_CLK_PLLD>; 1003 clock-names = "dsi", "lp", "parent"; 1004 resets = <&bpmp TEGRA186_RESET_DSI>; 1005 reset-names = "dsi"; 1006 status = "disabled"; 1007 1008 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1009 }; 1010 1011 vic@15340000 { 1012 compatible = "nvidia,tegra186-vic"; 1013 reg = <0x15340000 0x40000>; 1014 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&bpmp TEGRA186_CLK_VIC>; 1016 clock-names = "vic"; 1017 resets = <&bpmp TEGRA186_RESET_VIC>; 1018 reset-names = "vic"; 1019 1020 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1021 }; 1022 1023 dsib: dsi@15400000 { 1024 compatible = "nvidia,tegra186-dsi"; 1025 reg = <0x15400000 0x10000>; 1026 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1028 <&bpmp TEGRA186_CLK_DSIB_LP>, 1029 <&bpmp TEGRA186_CLK_PLLD>; 1030 clock-names = "dsi", "lp", "parent"; 1031 resets = <&bpmp TEGRA186_RESET_DSIB>; 1032 reset-names = "dsi"; 1033 status = "disabled"; 1034 1035 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1036 }; 1037 1038 sor0: sor@15540000 { 1039 compatible = "nvidia,tegra186-sor"; 1040 reg = <0x15540000 0x10000>; 1041 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1043 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1044 <&bpmp TEGRA186_CLK_PLLD2>, 1045 <&bpmp TEGRA186_CLK_PLLDP>, 1046 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1047 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1048 clock-names = "sor", "out", "parent", "dp", "safe", 1049 "pad"; 1050 resets = <&bpmp TEGRA186_RESET_SOR0>; 1051 reset-names = "sor"; 1052 pinctrl-0 = <&state_dpaux_aux>; 1053 pinctrl-1 = <&state_dpaux_i2c>; 1054 pinctrl-2 = <&state_dpaux_off>; 1055 pinctrl-names = "aux", "i2c", "off"; 1056 status = "disabled"; 1057 1058 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1059 nvidia,interface = <0>; 1060 }; 1061 1062 sor1: sor@15580000 { 1063 compatible = "nvidia,tegra186-sor1"; 1064 reg = <0x15580000 0x10000>; 1065 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1067 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1068 <&bpmp TEGRA186_CLK_PLLD3>, 1069 <&bpmp TEGRA186_CLK_PLLDP>, 1070 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1071 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1072 clock-names = "sor", "out", "parent", "dp", "safe", 1073 "pad"; 1074 resets = <&bpmp TEGRA186_RESET_SOR1>; 1075 reset-names = "sor"; 1076 pinctrl-0 = <&state_dpaux1_aux>; 1077 pinctrl-1 = <&state_dpaux1_i2c>; 1078 pinctrl-2 = <&state_dpaux1_off>; 1079 pinctrl-names = "aux", "i2c", "off"; 1080 status = "disabled"; 1081 1082 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1083 nvidia,interface = <1>; 1084 }; 1085 1086 dpaux: dpaux@155c0000 { 1087 compatible = "nvidia,tegra186-dpaux"; 1088 reg = <0x155c0000 0x10000>; 1089 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1091 <&bpmp TEGRA186_CLK_PLLDP>; 1092 clock-names = "dpaux", "parent"; 1093 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1094 reset-names = "dpaux"; 1095 status = "disabled"; 1096 1097 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1098 1099 state_dpaux_aux: pinmux-aux { 1100 groups = "dpaux-io"; 1101 function = "aux"; 1102 }; 1103 1104 state_dpaux_i2c: pinmux-i2c { 1105 groups = "dpaux-io"; 1106 function = "i2c"; 1107 }; 1108 1109 state_dpaux_off: pinmux-off { 1110 groups = "dpaux-io"; 1111 function = "off"; 1112 }; 1113 1114 i2c-bus { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 }; 1118 }; 1119 1120 padctl@15880000 { 1121 compatible = "nvidia,tegra186-dsi-padctl"; 1122 reg = <0x15880000 0x10000>; 1123 resets = <&bpmp TEGRA186_RESET_DSI>; 1124 reset-names = "dsi"; 1125 status = "disabled"; 1126 }; 1127 1128 dsic: dsi@15900000 { 1129 compatible = "nvidia,tegra186-dsi"; 1130 reg = <0x15900000 0x10000>; 1131 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1133 <&bpmp TEGRA186_CLK_DSIC_LP>, 1134 <&bpmp TEGRA186_CLK_PLLD>; 1135 clock-names = "dsi", "lp", "parent"; 1136 resets = <&bpmp TEGRA186_RESET_DSIC>; 1137 reset-names = "dsi"; 1138 status = "disabled"; 1139 1140 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1141 }; 1142 1143 dsid: dsi@15940000 { 1144 compatible = "nvidia,tegra186-dsi"; 1145 reg = <0x15940000 0x10000>; 1146 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&bpmp TEGRA186_CLK_DSID>, 1148 <&bpmp TEGRA186_CLK_DSID_LP>, 1149 <&bpmp TEGRA186_CLK_PLLD>; 1150 clock-names = "dsi", "lp", "parent"; 1151 resets = <&bpmp TEGRA186_RESET_DSID>; 1152 reset-names = "dsi"; 1153 status = "disabled"; 1154 1155 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1156 }; 1157 }; 1158 1159 gpu@17000000 { 1160 compatible = "nvidia,gp10b"; 1161 reg = <0x0 0x17000000 0x0 0x1000000>, 1162 <0x0 0x18000000 0x0 0x1000000>; 1163 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1164 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "stall", "nonstall"; 1166 1167 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1168 <&bpmp TEGRA186_CLK_GPU>; 1169 clock-names = "gpu", "pwr"; 1170 resets = <&bpmp TEGRA186_RESET_GPU>; 1171 reset-names = "gpu"; 1172 status = "disabled"; 1173 1174 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1175 }; 1176 1177 sysram@30000000 { 1178 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1179 reg = <0x0 0x30000000 0x0 0x50000>; 1180 #address-cells = <2>; 1181 #size-cells = <2>; 1182 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 1183 1184 cpu_bpmp_tx: shmem@4e000 { 1185 compatible = "nvidia,tegra186-bpmp-shmem"; 1186 reg = <0x0 0x4e000 0x0 0x1000>; 1187 label = "cpu-bpmp-tx"; 1188 pool; 1189 }; 1190 1191 cpu_bpmp_rx: shmem@4f000 { 1192 compatible = "nvidia,tegra186-bpmp-shmem"; 1193 reg = <0x0 0x4f000 0x0 0x1000>; 1194 label = "cpu-bpmp-rx"; 1195 pool; 1196 }; 1197 }; 1198 1199 bpmp: bpmp { 1200 compatible = "nvidia,tegra186-bpmp"; 1201 iommus = <&smmu TEGRA186_SID_BPMP>; 1202 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1203 TEGRA_HSP_DB_MASTER_BPMP>; 1204 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1205 #clock-cells = <1>; 1206 #reset-cells = <1>; 1207 #power-domain-cells = <1>; 1208 1209 bpmp_i2c: i2c { 1210 compatible = "nvidia,tegra186-bpmp-i2c"; 1211 nvidia,bpmp-bus-id = <5>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 bpmp_thermal: thermal { 1218 compatible = "nvidia,tegra186-bpmp-thermal"; 1219 #thermal-sensor-cells = <1>; 1220 }; 1221 }; 1222 1223 cpus { 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 1227 cpu@0 { 1228 compatible = "nvidia,tegra186-denver"; 1229 device_type = "cpu"; 1230 i-cache-size = <0x20000>; 1231 i-cache-line-size = <64>; 1232 i-cache-sets = <512>; 1233 d-cache-size = <0x10000>; 1234 d-cache-line-size = <64>; 1235 d-cache-sets = <256>; 1236 next-level-cache = <&L2_DENVER>; 1237 reg = <0x000>; 1238 }; 1239 1240 cpu@1 { 1241 compatible = "nvidia,tegra186-denver"; 1242 device_type = "cpu"; 1243 i-cache-size = <0x20000>; 1244 i-cache-line-size = <64>; 1245 i-cache-sets = <512>; 1246 d-cache-size = <0x10000>; 1247 d-cache-line-size = <64>; 1248 d-cache-sets = <256>; 1249 next-level-cache = <&L2_DENVER>; 1250 reg = <0x001>; 1251 }; 1252 1253 cpu@2 { 1254 compatible = "arm,cortex-a57"; 1255 device_type = "cpu"; 1256 i-cache-size = <0xC000>; 1257 i-cache-line-size = <64>; 1258 i-cache-sets = <256>; 1259 d-cache-size = <0x8000>; 1260 d-cache-line-size = <64>; 1261 d-cache-sets = <256>; 1262 next-level-cache = <&L2_A57>; 1263 reg = <0x100>; 1264 }; 1265 1266 cpu@3 { 1267 compatible = "arm,cortex-a57"; 1268 device_type = "cpu"; 1269 i-cache-size = <0xC000>; 1270 i-cache-line-size = <64>; 1271 i-cache-sets = <256>; 1272 d-cache-size = <0x8000>; 1273 d-cache-line-size = <64>; 1274 d-cache-sets = <256>; 1275 next-level-cache = <&L2_A57>; 1276 reg = <0x101>; 1277 }; 1278 1279 cpu@4 { 1280 compatible = "arm,cortex-a57"; 1281 device_type = "cpu"; 1282 i-cache-size = <0xC000>; 1283 i-cache-line-size = <64>; 1284 i-cache-sets = <256>; 1285 d-cache-size = <0x8000>; 1286 d-cache-line-size = <64>; 1287 d-cache-sets = <256>; 1288 next-level-cache = <&L2_A57>; 1289 reg = <0x102>; 1290 }; 1291 1292 cpu@5 { 1293 compatible = "arm,cortex-a57"; 1294 device_type = "cpu"; 1295 i-cache-size = <0xC000>; 1296 i-cache-line-size = <64>; 1297 i-cache-sets = <256>; 1298 d-cache-size = <0x8000>; 1299 d-cache-line-size = <64>; 1300 d-cache-sets = <256>; 1301 next-level-cache = <&L2_A57>; 1302 reg = <0x103>; 1303 }; 1304 1305 L2_DENVER: l2-cache0 { 1306 compatible = "cache"; 1307 cache-unified; 1308 cache-level = <2>; 1309 cache-size = <0x200000>; 1310 cache-line-size = <64>; 1311 cache-sets = <2048>; 1312 }; 1313 1314 L2_A57: l2-cache1 { 1315 compatible = "cache"; 1316 cache-unified; 1317 cache-level = <2>; 1318 cache-size = <0x200000>; 1319 cache-line-size = <64>; 1320 cache-sets = <2048>; 1321 }; 1322 }; 1323 1324 thermal-zones { 1325 a57 { 1326 polling-delay = <0>; 1327 polling-delay-passive = <1000>; 1328 1329 thermal-sensors = 1330 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1331 1332 trips { 1333 critical { 1334 temperature = <101000>; 1335 hysteresis = <0>; 1336 type = "critical"; 1337 }; 1338 }; 1339 1340 cooling-maps { 1341 }; 1342 }; 1343 1344 denver { 1345 polling-delay = <0>; 1346 polling-delay-passive = <1000>; 1347 1348 thermal-sensors = 1349 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1350 1351 trips { 1352 critical { 1353 temperature = <101000>; 1354 hysteresis = <0>; 1355 type = "critical"; 1356 }; 1357 }; 1358 1359 cooling-maps { 1360 }; 1361 }; 1362 1363 gpu { 1364 polling-delay = <0>; 1365 polling-delay-passive = <1000>; 1366 1367 thermal-sensors = 1368 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1369 1370 trips { 1371 critical { 1372 temperature = <101000>; 1373 hysteresis = <0>; 1374 type = "critical"; 1375 }; 1376 }; 1377 1378 cooling-maps { 1379 }; 1380 }; 1381 1382 pll { 1383 polling-delay = <0>; 1384 polling-delay-passive = <1000>; 1385 1386 thermal-sensors = 1387 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1388 1389 trips { 1390 critical { 1391 temperature = <101000>; 1392 hysteresis = <0>; 1393 type = "critical"; 1394 }; 1395 }; 1396 1397 cooling-maps { 1398 }; 1399 }; 1400 1401 always_on { 1402 polling-delay = <0>; 1403 polling-delay-passive = <1000>; 1404 1405 thermal-sensors = 1406 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1407 1408 trips { 1409 critical { 1410 temperature = <101000>; 1411 hysteresis = <0>; 1412 type = "critical"; 1413 }; 1414 }; 1415 1416 cooling-maps { 1417 }; 1418 }; 1419 }; 1420 1421 timer { 1422 compatible = "arm,armv8-timer"; 1423 interrupts = <GIC_PPI 13 1424 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1425 <GIC_PPI 14 1426 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1427 <GIC_PPI 11 1428 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1429 <GIC_PPI 10 1430 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1431 interrupt-parent = <&gic>; 1432 always-on; 1433 }; 1434}; 1435