1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 aconnect@2900000 { 77 compatible = "nvidia,tegra186-aconnect", 78 "nvidia,tegra210-aconnect"; 79 clocks = <&bpmp TEGRA186_CLK_APE>, 80 <&bpmp TEGRA186_CLK_APB2APE>; 81 clock-names = "ape", "apb2ape"; 82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x02900000 0x0 0x02900000 0x200000>; 86 status = "disabled"; 87 88 adma: dma-controller@2930000 { 89 compatible = "nvidia,tegra186-adma"; 90 reg = <0x02930000 0x20000>; 91 interrupt-parent = <&agic>; 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 124 #dma-cells = <1>; 125 clocks = <&bpmp TEGRA186_CLK_AHUB>; 126 clock-names = "d_audio"; 127 status = "disabled"; 128 }; 129 130 agic: interrupt-controller@2a40000 { 131 compatible = "nvidia,tegra186-agic", 132 "nvidia,tegra210-agic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0x02a41000 0x1000>, 136 <0x02a42000 0x2000>; 137 interrupts = <GIC_SPI 145 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA186_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 144 tegra_ahub: ahub@2900800 { 145 compatible = "nvidia,tegra186-ahub"; 146 reg = <0x02900800 0x800>; 147 clocks = <&bpmp TEGRA186_CLK_AHUB>; 148 clock-names = "ahub"; 149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0x02900800 0x02900800 0x11800>; 154 status = "disabled"; 155 156 tegra_admaif: admaif@290f000 { 157 compatible = "nvidia,tegra186-admaif"; 158 reg = <0x0290f000 0x1000>; 159 dmas = <&adma 1>, <&adma 1>, 160 <&adma 2>, <&adma 2>, 161 <&adma 3>, <&adma 3>, 162 <&adma 4>, <&adma 4>, 163 <&adma 5>, <&adma 5>, 164 <&adma 6>, <&adma 6>, 165 <&adma 7>, <&adma 7>, 166 <&adma 8>, <&adma 8>, 167 <&adma 9>, <&adma 9>, 168 <&adma 10>, <&adma 10>, 169 <&adma 11>, <&adma 11>, 170 <&adma 12>, <&adma 12>, 171 <&adma 13>, <&adma 13>, 172 <&adma 14>, <&adma 14>, 173 <&adma 15>, <&adma 15>, 174 <&adma 16>, <&adma 16>, 175 <&adma 17>, <&adma 17>, 176 <&adma 18>, <&adma 18>, 177 <&adma 19>, <&adma 19>, 178 <&adma 20>, <&adma 20>; 179 dma-names = "rx1", "tx1", 180 "rx2", "tx2", 181 "rx3", "tx3", 182 "rx4", "tx4", 183 "rx5", "tx5", 184 "rx6", "tx6", 185 "rx7", "tx7", 186 "rx8", "tx8", 187 "rx9", "tx9", 188 "rx10", "tx10", 189 "rx11", "tx11", 190 "rx12", "tx12", 191 "rx13", "tx13", 192 "rx14", "tx14", 193 "rx15", "tx15", 194 "rx16", "tx16", 195 "rx17", "tx17", 196 "rx18", "tx18", 197 "rx19", "tx19", 198 "rx20", "tx20"; 199 status = "disabled"; 200 }; 201 202 tegra_i2s1: i2s@2901000 { 203 compatible = "nvidia,tegra186-i2s", 204 "nvidia,tegra210-i2s"; 205 reg = <0x2901000 0x100>; 206 clocks = <&bpmp TEGRA186_CLK_I2S1>, 207 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 208 clock-names = "i2s", "sync_input"; 209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 211 assigned-clock-rates = <1536000>; 212 sound-name-prefix = "I2S1"; 213 status = "disabled"; 214 }; 215 216 tegra_i2s2: i2s@2901100 { 217 compatible = "nvidia,tegra186-i2s", 218 "nvidia,tegra210-i2s"; 219 reg = <0x2901100 0x100>; 220 clocks = <&bpmp TEGRA186_CLK_I2S2>, 221 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 222 clock-names = "i2s", "sync_input"; 223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 225 assigned-clock-rates = <1536000>; 226 sound-name-prefix = "I2S2"; 227 status = "disabled"; 228 }; 229 230 tegra_i2s3: i2s@2901200 { 231 compatible = "nvidia,tegra186-i2s", 232 "nvidia,tegra210-i2s"; 233 reg = <0x2901200 0x100>; 234 clocks = <&bpmp TEGRA186_CLK_I2S3>, 235 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 236 clock-names = "i2s", "sync_input"; 237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 239 assigned-clock-rates = <1536000>; 240 sound-name-prefix = "I2S3"; 241 status = "disabled"; 242 }; 243 244 tegra_i2s4: i2s@2901300 { 245 compatible = "nvidia,tegra186-i2s", 246 "nvidia,tegra210-i2s"; 247 reg = <0x2901300 0x100>; 248 clocks = <&bpmp TEGRA186_CLK_I2S4>, 249 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 250 clock-names = "i2s", "sync_input"; 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253 assigned-clock-rates = <1536000>; 254 sound-name-prefix = "I2S4"; 255 status = "disabled"; 256 }; 257 258 tegra_i2s5: i2s@2901400 { 259 compatible = "nvidia,tegra186-i2s", 260 "nvidia,tegra210-i2s"; 261 reg = <0x2901400 0x100>; 262 clocks = <&bpmp TEGRA186_CLK_I2S5>, 263 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 264 clock-names = "i2s", "sync_input"; 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267 assigned-clock-rates = <1536000>; 268 sound-name-prefix = "I2S5"; 269 status = "disabled"; 270 }; 271 272 tegra_i2s6: i2s@2901500 { 273 compatible = "nvidia,tegra186-i2s", 274 "nvidia,tegra210-i2s"; 275 reg = <0x2901500 0x100>; 276 clocks = <&bpmp TEGRA186_CLK_I2S6>, 277 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 278 clock-names = "i2s", "sync_input"; 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281 assigned-clock-rates = <1536000>; 282 sound-name-prefix = "I2S6"; 283 status = "disabled"; 284 }; 285 286 tegra_dmic1: dmic@2904000 { 287 compatible = "nvidia,tegra210-dmic"; 288 reg = <0x2904000 0x100>; 289 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 290 clock-names = "dmic"; 291 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 292 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 293 assigned-clock-rates = <3072000>; 294 sound-name-prefix = "DMIC1"; 295 status = "disabled"; 296 }; 297 298 tegra_dmic2: dmic@2904100 { 299 compatible = "nvidia,tegra210-dmic"; 300 reg = <0x2904100 0x100>; 301 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 302 clock-names = "dmic"; 303 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 304 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 305 assigned-clock-rates = <3072000>; 306 sound-name-prefix = "DMIC2"; 307 status = "disabled"; 308 }; 309 310 tegra_dmic3: dmic@2904200 { 311 compatible = "nvidia,tegra210-dmic"; 312 reg = <0x2904200 0x100>; 313 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 314 clock-names = "dmic"; 315 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 316 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 317 assigned-clock-rates = <3072000>; 318 sound-name-prefix = "DMIC3"; 319 status = "disabled"; 320 }; 321 322 tegra_dmic4: dmic@2904300 { 323 compatible = "nvidia,tegra210-dmic"; 324 reg = <0x2904300 0x100>; 325 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 326 clock-names = "dmic"; 327 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 328 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 329 assigned-clock-rates = <3072000>; 330 sound-name-prefix = "DMIC4"; 331 status = "disabled"; 332 }; 333 334 tegra_dspk1: dspk@2905000 { 335 compatible = "nvidia,tegra186-dspk"; 336 reg = <0x2905000 0x100>; 337 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 338 clock-names = "dspk"; 339 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 340 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 341 assigned-clock-rates = <12288000>; 342 sound-name-prefix = "DSPK1"; 343 status = "disabled"; 344 }; 345 346 tegra_dspk2: dspk@2905100 { 347 compatible = "nvidia,tegra186-dspk"; 348 reg = <0x2905100 0x100>; 349 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 350 clock-names = "dspk"; 351 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 353 assigned-clock-rates = <12288000>; 354 sound-name-prefix = "DSPK2"; 355 status = "disabled"; 356 }; 357 }; 358 }; 359 360 mc: memory-controller@2c00000 { 361 compatible = "nvidia,tegra186-mc"; 362 reg = <0x0 0x02c00000 0x0 0xb0000>; 363 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 364 status = "disabled"; 365 366 #interconnect-cells = <1>; 367 #address-cells = <2>; 368 #size-cells = <2>; 369 370 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 371 372 /* 373 * Memory clients have access to all 40 bits that the memory 374 * controller can address. 375 */ 376 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 377 378 emc: external-memory-controller@2c60000 { 379 compatible = "nvidia,tegra186-emc"; 380 reg = <0x0 0x02c60000 0x0 0x50000>; 381 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&bpmp TEGRA186_CLK_EMC>; 383 clock-names = "emc"; 384 385 #interconnect-cells = <0>; 386 387 nvidia,bpmp = <&bpmp>; 388 }; 389 }; 390 391 uarta: serial@3100000 { 392 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 393 reg = <0x0 0x03100000 0x0 0x40>; 394 reg-shift = <2>; 395 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&bpmp TEGRA186_CLK_UARTA>; 397 clock-names = "serial"; 398 resets = <&bpmp TEGRA186_RESET_UARTA>; 399 reset-names = "serial"; 400 status = "disabled"; 401 }; 402 403 uartb: serial@3110000 { 404 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 405 reg = <0x0 0x03110000 0x0 0x40>; 406 reg-shift = <2>; 407 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&bpmp TEGRA186_CLK_UARTB>; 409 clock-names = "serial"; 410 resets = <&bpmp TEGRA186_RESET_UARTB>; 411 reset-names = "serial"; 412 status = "disabled"; 413 }; 414 415 uartd: serial@3130000 { 416 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 417 reg = <0x0 0x03130000 0x0 0x40>; 418 reg-shift = <2>; 419 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&bpmp TEGRA186_CLK_UARTD>; 421 clock-names = "serial"; 422 resets = <&bpmp TEGRA186_RESET_UARTD>; 423 reset-names = "serial"; 424 status = "disabled"; 425 }; 426 427 uarte: serial@3140000 { 428 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 429 reg = <0x0 0x03140000 0x0 0x40>; 430 reg-shift = <2>; 431 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&bpmp TEGRA186_CLK_UARTE>; 433 clock-names = "serial"; 434 resets = <&bpmp TEGRA186_RESET_UARTE>; 435 reset-names = "serial"; 436 status = "disabled"; 437 }; 438 439 uartf: serial@3150000 { 440 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 441 reg = <0x0 0x03150000 0x0 0x40>; 442 reg-shift = <2>; 443 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&bpmp TEGRA186_CLK_UARTF>; 445 clock-names = "serial"; 446 resets = <&bpmp TEGRA186_RESET_UARTF>; 447 reset-names = "serial"; 448 status = "disabled"; 449 }; 450 451 gen1_i2c: i2c@3160000 { 452 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 453 reg = <0x0 0x03160000 0x0 0x10000>; 454 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&bpmp TEGRA186_CLK_I2C1>; 458 clock-names = "div-clk"; 459 resets = <&bpmp TEGRA186_RESET_I2C1>; 460 reset-names = "i2c"; 461 status = "disabled"; 462 }; 463 464 cam_i2c: i2c@3180000 { 465 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 466 reg = <0x0 0x03180000 0x0 0x10000>; 467 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&bpmp TEGRA186_CLK_I2C3>; 471 clock-names = "div-clk"; 472 resets = <&bpmp TEGRA186_RESET_I2C3>; 473 reset-names = "i2c"; 474 status = "disabled"; 475 }; 476 477 /* shares pads with dpaux1 */ 478 dp_aux_ch1_i2c: i2c@3190000 { 479 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 480 reg = <0x0 0x03190000 0x0 0x10000>; 481 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clocks = <&bpmp TEGRA186_CLK_I2C4>; 485 clock-names = "div-clk"; 486 resets = <&bpmp TEGRA186_RESET_I2C4>; 487 reset-names = "i2c"; 488 pinctrl-names = "default", "idle"; 489 pinctrl-0 = <&state_dpaux1_i2c>; 490 pinctrl-1 = <&state_dpaux1_off>; 491 status = "disabled"; 492 }; 493 494 /* controlled by BPMP, should not be enabled */ 495 pwr_i2c: i2c@31a0000 { 496 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 497 reg = <0x0 0x031a0000 0x0 0x10000>; 498 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&bpmp TEGRA186_CLK_I2C5>; 502 clock-names = "div-clk"; 503 resets = <&bpmp TEGRA186_RESET_I2C5>; 504 reset-names = "i2c"; 505 status = "disabled"; 506 }; 507 508 /* shares pads with dpaux0 */ 509 dp_aux_ch0_i2c: i2c@31b0000 { 510 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 511 reg = <0x0 0x031b0000 0x0 0x10000>; 512 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&bpmp TEGRA186_CLK_I2C6>; 516 clock-names = "div-clk"; 517 resets = <&bpmp TEGRA186_RESET_I2C6>; 518 reset-names = "i2c"; 519 pinctrl-names = "default", "idle"; 520 pinctrl-0 = <&state_dpaux_i2c>; 521 pinctrl-1 = <&state_dpaux_off>; 522 status = "disabled"; 523 }; 524 525 gen7_i2c: i2c@31c0000 { 526 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 527 reg = <0x0 0x031c0000 0x0 0x10000>; 528 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&bpmp TEGRA186_CLK_I2C7>; 532 clock-names = "div-clk"; 533 resets = <&bpmp TEGRA186_RESET_I2C7>; 534 reset-names = "i2c"; 535 status = "disabled"; 536 }; 537 538 gen9_i2c: i2c@31e0000 { 539 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 540 reg = <0x0 0x031e0000 0x0 0x10000>; 541 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 clocks = <&bpmp TEGRA186_CLK_I2C9>; 545 clock-names = "div-clk"; 546 resets = <&bpmp TEGRA186_RESET_I2C9>; 547 reset-names = "i2c"; 548 status = "disabled"; 549 }; 550 551 sdmmc1: mmc@3400000 { 552 compatible = "nvidia,tegra186-sdhci"; 553 reg = <0x0 0x03400000 0x0 0x10000>; 554 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 556 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 557 clock-names = "sdhci", "tmclk"; 558 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 559 reset-names = "sdhci"; 560 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 561 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 562 interconnect-names = "dma-mem", "write"; 563 iommus = <&smmu TEGRA186_SID_SDMMC1>; 564 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 565 pinctrl-0 = <&sdmmc1_3v3>; 566 pinctrl-1 = <&sdmmc1_1v8>; 567 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 568 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 569 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 570 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 571 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 572 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 573 nvidia,default-tap = <0x5>; 574 nvidia,default-trim = <0xb>; 575 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 576 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 577 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 578 status = "disabled"; 579 }; 580 581 sdmmc2: mmc@3420000 { 582 compatible = "nvidia,tegra186-sdhci"; 583 reg = <0x0 0x03420000 0x0 0x10000>; 584 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 586 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 587 clock-names = "sdhci", "tmclk"; 588 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 589 reset-names = "sdhci"; 590 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 591 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 592 interconnect-names = "dma-mem", "write"; 593 iommus = <&smmu TEGRA186_SID_SDMMC2>; 594 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 595 pinctrl-0 = <&sdmmc2_3v3>; 596 pinctrl-1 = <&sdmmc2_1v8>; 597 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 598 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 599 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 600 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 601 nvidia,default-tap = <0x5>; 602 nvidia,default-trim = <0xb>; 603 status = "disabled"; 604 }; 605 606 sdmmc3: mmc@3440000 { 607 compatible = "nvidia,tegra186-sdhci"; 608 reg = <0x0 0x03440000 0x0 0x10000>; 609 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 611 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 612 clock-names = "sdhci", "tmclk"; 613 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 614 reset-names = "sdhci"; 615 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 616 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 617 interconnect-names = "dma-mem", "write"; 618 iommus = <&smmu TEGRA186_SID_SDMMC3>; 619 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 620 pinctrl-0 = <&sdmmc3_3v3>; 621 pinctrl-1 = <&sdmmc3_1v8>; 622 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 623 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 624 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 625 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 626 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 627 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 628 nvidia,default-tap = <0x5>; 629 nvidia,default-trim = <0xb>; 630 status = "disabled"; 631 }; 632 633 sdmmc4: mmc@3460000 { 634 compatible = "nvidia,tegra186-sdhci"; 635 reg = <0x0 0x03460000 0x0 0x10000>; 636 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 638 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 639 clock-names = "sdhci", "tmclk"; 640 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 641 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 642 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 643 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 644 reset-names = "sdhci"; 645 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 646 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 647 interconnect-names = "dma-mem", "write"; 648 iommus = <&smmu TEGRA186_SID_SDMMC4>; 649 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 650 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 651 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 652 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 653 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 654 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 655 nvidia,default-tap = <0x9>; 656 nvidia,default-trim = <0x5>; 657 nvidia,dqs-trim = <63>; 658 mmc-hs400-1_8v; 659 supports-cqe; 660 status = "disabled"; 661 }; 662 663 hda@3510000 { 664 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 665 reg = <0x0 0x03510000 0x0 0x10000>; 666 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&bpmp TEGRA186_CLK_HDA>, 668 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 669 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 670 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 671 resets = <&bpmp TEGRA186_RESET_HDA>, 672 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 673 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 674 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 675 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 676 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 677 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 678 interconnect-names = "dma-mem", "write"; 679 iommus = <&smmu TEGRA186_SID_HDA>; 680 status = "disabled"; 681 }; 682 683 padctl: padctl@3520000 { 684 compatible = "nvidia,tegra186-xusb-padctl"; 685 reg = <0x0 0x03520000 0x0 0x1000>, 686 <0x0 0x03540000 0x0 0x1000>; 687 reg-names = "padctl", "ao"; 688 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 689 690 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 691 reset-names = "padctl"; 692 693 status = "disabled"; 694 695 pads { 696 usb2 { 697 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 698 clock-names = "trk"; 699 status = "disabled"; 700 701 lanes { 702 usb2-0 { 703 status = "disabled"; 704 #phy-cells = <0>; 705 }; 706 707 usb2-1 { 708 status = "disabled"; 709 #phy-cells = <0>; 710 }; 711 712 usb2-2 { 713 status = "disabled"; 714 #phy-cells = <0>; 715 }; 716 }; 717 }; 718 719 hsic { 720 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 721 clock-names = "trk"; 722 status = "disabled"; 723 724 lanes { 725 hsic-0 { 726 status = "disabled"; 727 #phy-cells = <0>; 728 }; 729 }; 730 }; 731 732 usb3 { 733 status = "disabled"; 734 735 lanes { 736 usb3-0 { 737 status = "disabled"; 738 #phy-cells = <0>; 739 }; 740 741 usb3-1 { 742 status = "disabled"; 743 #phy-cells = <0>; 744 }; 745 746 usb3-2 { 747 status = "disabled"; 748 #phy-cells = <0>; 749 }; 750 }; 751 }; 752 }; 753 754 ports { 755 usb2-0 { 756 status = "disabled"; 757 }; 758 759 usb2-1 { 760 status = "disabled"; 761 }; 762 763 usb2-2 { 764 status = "disabled"; 765 }; 766 767 hsic-0 { 768 status = "disabled"; 769 }; 770 771 usb3-0 { 772 status = "disabled"; 773 }; 774 775 usb3-1 { 776 status = "disabled"; 777 }; 778 779 usb3-2 { 780 status = "disabled"; 781 }; 782 }; 783 }; 784 785 usb@3530000 { 786 compatible = "nvidia,tegra186-xusb"; 787 reg = <0x0 0x03530000 0x0 0x8000>, 788 <0x0 0x03538000 0x0 0x1000>; 789 reg-names = "hcd", "fpci"; 790 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 793 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 794 <&bpmp TEGRA186_CLK_XUSB_SS>, 795 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 796 <&bpmp TEGRA186_CLK_CLK_M>, 797 <&bpmp TEGRA186_CLK_XUSB_FS>, 798 <&bpmp TEGRA186_CLK_PLLU>, 799 <&bpmp TEGRA186_CLK_CLK_M>, 800 <&bpmp TEGRA186_CLK_PLLE>; 801 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 802 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 803 "pll_u_480m", "clk_m", "pll_e"; 804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 805 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 806 power-domain-names = "xusb_host", "xusb_ss"; 807 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 808 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 809 interconnect-names = "dma-mem", "write"; 810 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 status = "disabled"; 814 815 nvidia,xusb-padctl = <&padctl>; 816 }; 817 818 usb@3550000 { 819 compatible = "nvidia,tegra186-xudc"; 820 reg = <0x0 0x03550000 0x0 0x8000>, 821 <0x0 0x03558000 0x0 0x1000>; 822 reg-names = "base", "fpci"; 823 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 825 <&bpmp TEGRA186_CLK_XUSB_SS>, 826 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 827 <&bpmp TEGRA186_CLK_XUSB_FS>; 828 clock-names = "dev", "ss", "ss_src", "fs_src"; 829 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 830 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 831 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 832 power-domain-names = "dev", "ss"; 833 nvidia,xusb-padctl = <&padctl>; 834 status = "disabled"; 835 }; 836 837 fuse@3820000 { 838 compatible = "nvidia,tegra186-efuse"; 839 reg = <0x0 0x03820000 0x0 0x10000>; 840 clocks = <&bpmp TEGRA186_CLK_FUSE>; 841 clock-names = "fuse"; 842 }; 843 844 gic: interrupt-controller@3881000 { 845 compatible = "arm,gic-400"; 846 #interrupt-cells = <3>; 847 interrupt-controller; 848 reg = <0x0 0x03881000 0x0 0x1000>, 849 <0x0 0x03882000 0x0 0x2000>, 850 <0x0 0x03884000 0x0 0x2000>, 851 <0x0 0x03886000 0x0 0x2000>; 852 interrupts = <GIC_PPI 9 853 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 854 interrupt-parent = <&gic>; 855 }; 856 857 cec@3960000 { 858 compatible = "nvidia,tegra186-cec"; 859 reg = <0x0 0x03960000 0x0 0x10000>; 860 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&bpmp TEGRA186_CLK_CEC>; 862 clock-names = "cec"; 863 status = "disabled"; 864 }; 865 866 hsp_top0: hsp@3c00000 { 867 compatible = "nvidia,tegra186-hsp"; 868 reg = <0x0 0x03c00000 0x0 0xa0000>; 869 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "doorbell"; 871 #mbox-cells = <2>; 872 status = "disabled"; 873 }; 874 875 gen2_i2c: i2c@c240000 { 876 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 877 reg = <0x0 0x0c240000 0x0 0x10000>; 878 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 clocks = <&bpmp TEGRA186_CLK_I2C2>; 882 clock-names = "div-clk"; 883 resets = <&bpmp TEGRA186_RESET_I2C2>; 884 reset-names = "i2c"; 885 status = "disabled"; 886 }; 887 888 gen8_i2c: i2c@c250000 { 889 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 890 reg = <0x0 0x0c250000 0x0 0x10000>; 891 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 clocks = <&bpmp TEGRA186_CLK_I2C8>; 895 clock-names = "div-clk"; 896 resets = <&bpmp TEGRA186_RESET_I2C8>; 897 reset-names = "i2c"; 898 status = "disabled"; 899 }; 900 901 uartc: serial@c280000 { 902 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 903 reg = <0x0 0x0c280000 0x0 0x40>; 904 reg-shift = <2>; 905 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&bpmp TEGRA186_CLK_UARTC>; 907 clock-names = "serial"; 908 resets = <&bpmp TEGRA186_RESET_UARTC>; 909 reset-names = "serial"; 910 status = "disabled"; 911 }; 912 913 uartg: serial@c290000 { 914 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 915 reg = <0x0 0x0c290000 0x0 0x40>; 916 reg-shift = <2>; 917 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&bpmp TEGRA186_CLK_UARTG>; 919 clock-names = "serial"; 920 resets = <&bpmp TEGRA186_RESET_UARTG>; 921 reset-names = "serial"; 922 status = "disabled"; 923 }; 924 925 rtc: rtc@c2a0000 { 926 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 927 reg = <0 0x0c2a0000 0 0x10000>; 928 interrupt-parent = <&pmc>; 929 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 931 clock-names = "rtc"; 932 status = "disabled"; 933 }; 934 935 gpio_aon: gpio@c2f0000 { 936 compatible = "nvidia,tegra186-gpio-aon"; 937 reg-names = "security", "gpio"; 938 reg = <0x0 0xc2f0000 0x0 0x1000>, 939 <0x0 0xc2f1000 0x0 0x1000>; 940 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 941 gpio-controller; 942 #gpio-cells = <2>; 943 interrupt-controller; 944 #interrupt-cells = <2>; 945 }; 946 947 pmc: pmc@c360000 { 948 compatible = "nvidia,tegra186-pmc"; 949 reg = <0 0x0c360000 0 0x10000>, 950 <0 0x0c370000 0 0x10000>, 951 <0 0x0c380000 0 0x10000>, 952 <0 0x0c390000 0 0x10000>; 953 reg-names = "pmc", "wake", "aotag", "scratch"; 954 955 #interrupt-cells = <2>; 956 interrupt-controller; 957 958 sdmmc1_3v3: sdmmc1-3v3 { 959 pins = "sdmmc1-hv"; 960 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 961 }; 962 963 sdmmc1_1v8: sdmmc1-1v8 { 964 pins = "sdmmc1-hv"; 965 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 966 }; 967 968 sdmmc2_3v3: sdmmc2-3v3 { 969 pins = "sdmmc2-hv"; 970 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 971 }; 972 973 sdmmc2_1v8: sdmmc2-1v8 { 974 pins = "sdmmc2-hv"; 975 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 976 }; 977 978 sdmmc3_3v3: sdmmc3-3v3 { 979 pins = "sdmmc3-hv"; 980 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 981 }; 982 983 sdmmc3_1v8: sdmmc3-1v8 { 984 pins = "sdmmc3-hv"; 985 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 986 }; 987 }; 988 989 ccplex@e000000 { 990 compatible = "nvidia,tegra186-ccplex-cluster"; 991 reg = <0x0 0x0e000000 0x0 0x3fffff>; 992 993 nvidia,bpmp = <&bpmp>; 994 }; 995 996 pcie@10003000 { 997 compatible = "nvidia,tegra186-pcie"; 998 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 999 device_type = "pci"; 1000 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1001 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1002 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1003 reg-names = "pads", "afi", "cs"; 1004 1005 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1006 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1007 interrupt-names = "intr", "msi"; 1008 1009 #interrupt-cells = <1>; 1010 interrupt-map-mask = <0 0 0 0>; 1011 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1012 1013 bus-range = <0x00 0xff>; 1014 #address-cells = <3>; 1015 #size-cells = <2>; 1016 1017 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1018 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1019 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1020 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1021 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1022 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1023 1024 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1025 <&bpmp TEGRA186_CLK_AFI>, 1026 <&bpmp TEGRA186_CLK_PLLE>; 1027 clock-names = "pex", "afi", "pll_e"; 1028 1029 resets = <&bpmp TEGRA186_RESET_PCIE>, 1030 <&bpmp TEGRA186_RESET_AFI>, 1031 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1032 reset-names = "pex", "afi", "pcie_x"; 1033 1034 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1035 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1036 interconnect-names = "dma-mem", "write"; 1037 1038 iommus = <&smmu TEGRA186_SID_AFI>; 1039 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1040 iommu-map-mask = <0x0>; 1041 1042 status = "disabled"; 1043 1044 pci@1,0 { 1045 device_type = "pci"; 1046 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1047 reg = <0x000800 0 0 0 0>; 1048 status = "disabled"; 1049 1050 #address-cells = <3>; 1051 #size-cells = <2>; 1052 ranges; 1053 1054 nvidia,num-lanes = <2>; 1055 }; 1056 1057 pci@2,0 { 1058 device_type = "pci"; 1059 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1060 reg = <0x001000 0 0 0 0>; 1061 status = "disabled"; 1062 1063 #address-cells = <3>; 1064 #size-cells = <2>; 1065 ranges; 1066 1067 nvidia,num-lanes = <1>; 1068 }; 1069 1070 pci@3,0 { 1071 device_type = "pci"; 1072 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1073 reg = <0x001800 0 0 0 0>; 1074 status = "disabled"; 1075 1076 #address-cells = <3>; 1077 #size-cells = <2>; 1078 ranges; 1079 1080 nvidia,num-lanes = <1>; 1081 }; 1082 }; 1083 1084 smmu: iommu@12000000 { 1085 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1086 reg = <0 0x12000000 0 0x800000>; 1087 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1152 stream-match-mask = <0x7f80>; 1153 #global-interrupts = <1>; 1154 #iommu-cells = <1>; 1155 1156 nvidia,memory-controller = <&mc>; 1157 }; 1158 1159 host1x@13e00000 { 1160 compatible = "nvidia,tegra186-host1x"; 1161 reg = <0x0 0x13e00000 0x0 0x10000>, 1162 <0x0 0x13e10000 0x0 0x10000>; 1163 reg-names = "hypervisor", "vm"; 1164 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1166 interrupt-names = "syncpt", "host1x"; 1167 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1168 clock-names = "host1x"; 1169 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1170 reset-names = "host1x"; 1171 1172 #address-cells = <1>; 1173 #size-cells = <1>; 1174 1175 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1176 1177 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1178 interconnect-names = "dma-mem"; 1179 1180 iommus = <&smmu TEGRA186_SID_HOST1X>; 1181 1182 dpaux1: dpaux@15040000 { 1183 compatible = "nvidia,tegra186-dpaux"; 1184 reg = <0x15040000 0x10000>; 1185 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1187 <&bpmp TEGRA186_CLK_PLLDP>; 1188 clock-names = "dpaux", "parent"; 1189 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1190 reset-names = "dpaux"; 1191 status = "disabled"; 1192 1193 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1194 1195 state_dpaux1_aux: pinmux-aux { 1196 groups = "dpaux-io"; 1197 function = "aux"; 1198 }; 1199 1200 state_dpaux1_i2c: pinmux-i2c { 1201 groups = "dpaux-io"; 1202 function = "i2c"; 1203 }; 1204 1205 state_dpaux1_off: pinmux-off { 1206 groups = "dpaux-io"; 1207 function = "off"; 1208 }; 1209 1210 i2c-bus { 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 }; 1214 }; 1215 1216 display-hub@15200000 { 1217 compatible = "nvidia,tegra186-display"; 1218 reg = <0x15200000 0x00040000>; 1219 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1220 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1221 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1222 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1223 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1224 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1225 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1226 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1227 "wgrp3", "wgrp4", "wgrp5"; 1228 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1229 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1230 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1231 clock-names = "disp", "dsc", "hub"; 1232 status = "disabled"; 1233 1234 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1235 1236 #address-cells = <1>; 1237 #size-cells = <1>; 1238 1239 ranges = <0x15200000 0x15200000 0x40000>; 1240 1241 display@15200000 { 1242 compatible = "nvidia,tegra186-dc"; 1243 reg = <0x15200000 0x10000>; 1244 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1246 clock-names = "dc"; 1247 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1248 reset-names = "dc"; 1249 1250 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1251 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1252 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1253 interconnect-names = "dma-mem", "read-1"; 1254 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1255 1256 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1257 nvidia,head = <0>; 1258 }; 1259 1260 display@15210000 { 1261 compatible = "nvidia,tegra186-dc"; 1262 reg = <0x15210000 0x10000>; 1263 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1265 clock-names = "dc"; 1266 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1267 reset-names = "dc"; 1268 1269 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1270 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1271 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1272 interconnect-names = "dma-mem", "read-1"; 1273 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1274 1275 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1276 nvidia,head = <1>; 1277 }; 1278 1279 display@15220000 { 1280 compatible = "nvidia,tegra186-dc"; 1281 reg = <0x15220000 0x10000>; 1282 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1284 clock-names = "dc"; 1285 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1286 reset-names = "dc"; 1287 1288 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1289 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1290 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1291 interconnect-names = "dma-mem", "read-1"; 1292 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1293 1294 nvidia,outputs = <&sor0 &sor1>; 1295 nvidia,head = <2>; 1296 }; 1297 }; 1298 1299 dsia: dsi@15300000 { 1300 compatible = "nvidia,tegra186-dsi"; 1301 reg = <0x15300000 0x10000>; 1302 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&bpmp TEGRA186_CLK_DSI>, 1304 <&bpmp TEGRA186_CLK_DSIA_LP>, 1305 <&bpmp TEGRA186_CLK_PLLD>; 1306 clock-names = "dsi", "lp", "parent"; 1307 resets = <&bpmp TEGRA186_RESET_DSI>; 1308 reset-names = "dsi"; 1309 status = "disabled"; 1310 1311 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1312 }; 1313 1314 vic@15340000 { 1315 compatible = "nvidia,tegra186-vic"; 1316 reg = <0x15340000 0x40000>; 1317 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&bpmp TEGRA186_CLK_VIC>; 1319 clock-names = "vic"; 1320 resets = <&bpmp TEGRA186_RESET_VIC>; 1321 reset-names = "vic"; 1322 1323 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1324 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1325 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1326 interconnect-names = "dma-mem", "write"; 1327 iommus = <&smmu TEGRA186_SID_VIC>; 1328 }; 1329 1330 dsib: dsi@15400000 { 1331 compatible = "nvidia,tegra186-dsi"; 1332 reg = <0x15400000 0x10000>; 1333 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1334 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1335 <&bpmp TEGRA186_CLK_DSIB_LP>, 1336 <&bpmp TEGRA186_CLK_PLLD>; 1337 clock-names = "dsi", "lp", "parent"; 1338 resets = <&bpmp TEGRA186_RESET_DSIB>; 1339 reset-names = "dsi"; 1340 status = "disabled"; 1341 1342 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1343 }; 1344 1345 sor0: sor@15540000 { 1346 compatible = "nvidia,tegra186-sor"; 1347 reg = <0x15540000 0x10000>; 1348 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1350 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1351 <&bpmp TEGRA186_CLK_PLLD2>, 1352 <&bpmp TEGRA186_CLK_PLLDP>, 1353 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1354 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1355 clock-names = "sor", "out", "parent", "dp", "safe", 1356 "pad"; 1357 resets = <&bpmp TEGRA186_RESET_SOR0>; 1358 reset-names = "sor"; 1359 pinctrl-0 = <&state_dpaux_aux>; 1360 pinctrl-1 = <&state_dpaux_i2c>; 1361 pinctrl-2 = <&state_dpaux_off>; 1362 pinctrl-names = "aux", "i2c", "off"; 1363 status = "disabled"; 1364 1365 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1366 nvidia,interface = <0>; 1367 }; 1368 1369 sor1: sor@15580000 { 1370 compatible = "nvidia,tegra186-sor"; 1371 reg = <0x15580000 0x10000>; 1372 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1373 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1374 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1375 <&bpmp TEGRA186_CLK_PLLD3>, 1376 <&bpmp TEGRA186_CLK_PLLDP>, 1377 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1378 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1379 clock-names = "sor", "out", "parent", "dp", "safe", 1380 "pad"; 1381 resets = <&bpmp TEGRA186_RESET_SOR1>; 1382 reset-names = "sor"; 1383 pinctrl-0 = <&state_dpaux1_aux>; 1384 pinctrl-1 = <&state_dpaux1_i2c>; 1385 pinctrl-2 = <&state_dpaux1_off>; 1386 pinctrl-names = "aux", "i2c", "off"; 1387 status = "disabled"; 1388 1389 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1390 nvidia,interface = <1>; 1391 }; 1392 1393 dpaux: dpaux@155c0000 { 1394 compatible = "nvidia,tegra186-dpaux"; 1395 reg = <0x155c0000 0x10000>; 1396 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1398 <&bpmp TEGRA186_CLK_PLLDP>; 1399 clock-names = "dpaux", "parent"; 1400 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1401 reset-names = "dpaux"; 1402 status = "disabled"; 1403 1404 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1405 1406 state_dpaux_aux: pinmux-aux { 1407 groups = "dpaux-io"; 1408 function = "aux"; 1409 }; 1410 1411 state_dpaux_i2c: pinmux-i2c { 1412 groups = "dpaux-io"; 1413 function = "i2c"; 1414 }; 1415 1416 state_dpaux_off: pinmux-off { 1417 groups = "dpaux-io"; 1418 function = "off"; 1419 }; 1420 1421 i2c-bus { 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 }; 1425 }; 1426 1427 padctl@15880000 { 1428 compatible = "nvidia,tegra186-dsi-padctl"; 1429 reg = <0x15880000 0x10000>; 1430 resets = <&bpmp TEGRA186_RESET_DSI>; 1431 reset-names = "dsi"; 1432 status = "disabled"; 1433 }; 1434 1435 dsic: dsi@15900000 { 1436 compatible = "nvidia,tegra186-dsi"; 1437 reg = <0x15900000 0x10000>; 1438 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1439 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1440 <&bpmp TEGRA186_CLK_DSIC_LP>, 1441 <&bpmp TEGRA186_CLK_PLLD>; 1442 clock-names = "dsi", "lp", "parent"; 1443 resets = <&bpmp TEGRA186_RESET_DSIC>; 1444 reset-names = "dsi"; 1445 status = "disabled"; 1446 1447 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1448 }; 1449 1450 dsid: dsi@15940000 { 1451 compatible = "nvidia,tegra186-dsi"; 1452 reg = <0x15940000 0x10000>; 1453 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1454 clocks = <&bpmp TEGRA186_CLK_DSID>, 1455 <&bpmp TEGRA186_CLK_DSID_LP>, 1456 <&bpmp TEGRA186_CLK_PLLD>; 1457 clock-names = "dsi", "lp", "parent"; 1458 resets = <&bpmp TEGRA186_RESET_DSID>; 1459 reset-names = "dsi"; 1460 status = "disabled"; 1461 1462 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1463 }; 1464 }; 1465 1466 gpu@17000000 { 1467 compatible = "nvidia,gp10b"; 1468 reg = <0x0 0x17000000 0x0 0x1000000>, 1469 <0x0 0x18000000 0x0 0x1000000>; 1470 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1472 interrupt-names = "stall", "nonstall"; 1473 1474 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1475 <&bpmp TEGRA186_CLK_GPU>; 1476 clock-names = "gpu", "pwr"; 1477 resets = <&bpmp TEGRA186_RESET_GPU>; 1478 reset-names = "gpu"; 1479 status = "disabled"; 1480 1481 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1482 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1483 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1484 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1485 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1486 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1487 }; 1488 1489 sram@30000000 { 1490 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1491 reg = <0x0 0x30000000 0x0 0x50000>; 1492 #address-cells = <1>; 1493 #size-cells = <1>; 1494 ranges = <0x0 0x0 0x30000000 0x50000>; 1495 1496 cpu_bpmp_tx: sram@4e000 { 1497 reg = <0x4e000 0x1000>; 1498 label = "cpu-bpmp-tx"; 1499 pool; 1500 }; 1501 1502 cpu_bpmp_rx: sram@4f000 { 1503 reg = <0x4f000 0x1000>; 1504 label = "cpu-bpmp-rx"; 1505 pool; 1506 }; 1507 }; 1508 1509 sata@3507000 { 1510 compatible = "nvidia,tegra186-ahci"; 1511 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1512 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1513 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1514 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1515 1516 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1517 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1518 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1519 interconnect-names = "dma-mem", "write"; 1520 iommus = <&smmu TEGRA186_SID_SATA>; 1521 1522 clocks = <&bpmp TEGRA186_CLK_SATA>, 1523 <&bpmp TEGRA186_CLK_SATA_OOB>; 1524 clock-names = "sata", "sata-oob"; 1525 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1526 <&bpmp TEGRA186_CLK_SATA_OOB>; 1527 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1528 <&bpmp TEGRA186_CLK_PLLP>; 1529 assigned-clock-rates = <102000000>, 1530 <204000000>; 1531 resets = <&bpmp TEGRA186_RESET_SATA>, 1532 <&bpmp TEGRA186_RESET_SATACOLD>; 1533 reset-names = "sata", "sata-cold"; 1534 status = "disabled"; 1535 }; 1536 1537 bpmp: bpmp { 1538 compatible = "nvidia,tegra186-bpmp"; 1539 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1540 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1541 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1542 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1543 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1544 iommus = <&smmu TEGRA186_SID_BPMP>; 1545 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1546 TEGRA_HSP_DB_MASTER_BPMP>; 1547 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1548 #clock-cells = <1>; 1549 #reset-cells = <1>; 1550 #power-domain-cells = <1>; 1551 1552 bpmp_i2c: i2c { 1553 compatible = "nvidia,tegra186-bpmp-i2c"; 1554 nvidia,bpmp-bus-id = <5>; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 status = "disabled"; 1558 }; 1559 1560 bpmp_thermal: thermal { 1561 compatible = "nvidia,tegra186-bpmp-thermal"; 1562 #thermal-sensor-cells = <1>; 1563 }; 1564 }; 1565 1566 cpus { 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 1570 denver_0: cpu@0 { 1571 compatible = "nvidia,tegra186-denver"; 1572 device_type = "cpu"; 1573 i-cache-size = <0x20000>; 1574 i-cache-line-size = <64>; 1575 i-cache-sets = <512>; 1576 d-cache-size = <0x10000>; 1577 d-cache-line-size = <64>; 1578 d-cache-sets = <256>; 1579 next-level-cache = <&L2_DENVER>; 1580 reg = <0x000>; 1581 }; 1582 1583 denver_1: cpu@1 { 1584 compatible = "nvidia,tegra186-denver"; 1585 device_type = "cpu"; 1586 i-cache-size = <0x20000>; 1587 i-cache-line-size = <64>; 1588 i-cache-sets = <512>; 1589 d-cache-size = <0x10000>; 1590 d-cache-line-size = <64>; 1591 d-cache-sets = <256>; 1592 next-level-cache = <&L2_DENVER>; 1593 reg = <0x001>; 1594 }; 1595 1596 ca57_0: cpu@2 { 1597 compatible = "arm,cortex-a57"; 1598 device_type = "cpu"; 1599 i-cache-size = <0xC000>; 1600 i-cache-line-size = <64>; 1601 i-cache-sets = <256>; 1602 d-cache-size = <0x8000>; 1603 d-cache-line-size = <64>; 1604 d-cache-sets = <256>; 1605 next-level-cache = <&L2_A57>; 1606 reg = <0x100>; 1607 }; 1608 1609 ca57_1: cpu@3 { 1610 compatible = "arm,cortex-a57"; 1611 device_type = "cpu"; 1612 i-cache-size = <0xC000>; 1613 i-cache-line-size = <64>; 1614 i-cache-sets = <256>; 1615 d-cache-size = <0x8000>; 1616 d-cache-line-size = <64>; 1617 d-cache-sets = <256>; 1618 next-level-cache = <&L2_A57>; 1619 reg = <0x101>; 1620 }; 1621 1622 ca57_2: cpu@4 { 1623 compatible = "arm,cortex-a57"; 1624 device_type = "cpu"; 1625 i-cache-size = <0xC000>; 1626 i-cache-line-size = <64>; 1627 i-cache-sets = <256>; 1628 d-cache-size = <0x8000>; 1629 d-cache-line-size = <64>; 1630 d-cache-sets = <256>; 1631 next-level-cache = <&L2_A57>; 1632 reg = <0x102>; 1633 }; 1634 1635 ca57_3: cpu@5 { 1636 compatible = "arm,cortex-a57"; 1637 device_type = "cpu"; 1638 i-cache-size = <0xC000>; 1639 i-cache-line-size = <64>; 1640 i-cache-sets = <256>; 1641 d-cache-size = <0x8000>; 1642 d-cache-line-size = <64>; 1643 d-cache-sets = <256>; 1644 next-level-cache = <&L2_A57>; 1645 reg = <0x103>; 1646 }; 1647 1648 L2_DENVER: l2-cache0 { 1649 compatible = "cache"; 1650 cache-unified; 1651 cache-level = <2>; 1652 cache-size = <0x200000>; 1653 cache-line-size = <64>; 1654 cache-sets = <2048>; 1655 }; 1656 1657 L2_A57: l2-cache1 { 1658 compatible = "cache"; 1659 cache-unified; 1660 cache-level = <2>; 1661 cache-size = <0x200000>; 1662 cache-line-size = <64>; 1663 cache-sets = <2048>; 1664 }; 1665 }; 1666 1667 pmu_denver { 1668 compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; 1669 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1671 interrupt-affinity = <&denver_0 &denver_1>; 1672 }; 1673 1674 pmu_a57 { 1675 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 1676 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1680 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 1681 }; 1682 1683 sound { 1684 status = "disabled"; 1685 1686 clocks = <&bpmp TEGRA186_CLK_PLLA>, 1687 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1688 clock-names = "pll_a", "plla_out0"; 1689 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 1690 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 1691 <&bpmp TEGRA186_CLK_AUD_MCLK>; 1692 assigned-clock-parents = <0>, 1693 <&bpmp TEGRA186_CLK_PLLA>, 1694 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1695 /* 1696 * PLLA supports dynamic ramp. Below initial rate is chosen 1697 * for this to work and oscillate between base rates required 1698 * for 8x and 11.025x sample rate streams. 1699 */ 1700 assigned-clock-rates = <258000000>; 1701 1702 iommus = <&smmu TEGRA186_SID_APE>; 1703 }; 1704 1705 thermal-zones { 1706 a57 { 1707 polling-delay = <0>; 1708 polling-delay-passive = <1000>; 1709 1710 thermal-sensors = 1711 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1712 1713 trips { 1714 critical { 1715 temperature = <101000>; 1716 hysteresis = <0>; 1717 type = "critical"; 1718 }; 1719 }; 1720 1721 cooling-maps { 1722 }; 1723 }; 1724 1725 denver { 1726 polling-delay = <0>; 1727 polling-delay-passive = <1000>; 1728 1729 thermal-sensors = 1730 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1731 1732 trips { 1733 critical { 1734 temperature = <101000>; 1735 hysteresis = <0>; 1736 type = "critical"; 1737 }; 1738 }; 1739 1740 cooling-maps { 1741 }; 1742 }; 1743 1744 gpu { 1745 polling-delay = <0>; 1746 polling-delay-passive = <1000>; 1747 1748 thermal-sensors = 1749 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1750 1751 trips { 1752 critical { 1753 temperature = <101000>; 1754 hysteresis = <0>; 1755 type = "critical"; 1756 }; 1757 }; 1758 1759 cooling-maps { 1760 }; 1761 }; 1762 1763 pll { 1764 polling-delay = <0>; 1765 polling-delay-passive = <1000>; 1766 1767 thermal-sensors = 1768 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1769 1770 trips { 1771 critical { 1772 temperature = <101000>; 1773 hysteresis = <0>; 1774 type = "critical"; 1775 }; 1776 }; 1777 1778 cooling-maps { 1779 }; 1780 }; 1781 1782 always_on { 1783 polling-delay = <0>; 1784 polling-delay-passive = <1000>; 1785 1786 thermal-sensors = 1787 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1788 1789 trips { 1790 critical { 1791 temperature = <101000>; 1792 hysteresis = <0>; 1793 type = "critical"; 1794 }; 1795 }; 1796 1797 cooling-maps { 1798 }; 1799 }; 1800 }; 1801 1802 timer { 1803 compatible = "arm,armv8-timer"; 1804 interrupts = <GIC_PPI 13 1805 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1806 <GIC_PPI 14 1807 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1808 <GIC_PPI 11 1809 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1810 <GIC_PPI 10 1811 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1812 interrupt-parent = <&gic>; 1813 always-on; 1814 }; 1815}; 1816