1#include <dt-bindings/gpio/tegra186-gpio.h> 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3 4/ { 5 compatible = "nvidia,tegra186"; 6 interrupt-parent = <&gic>; 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 gpio: gpio@2200000 { 11 compatible = "nvidia,tegra186-gpio"; 12 reg-names = "security", "gpio"; 13 reg = <0x0 0x2200000 0x0 0x10000>, 14 <0x0 0x2210000 0x0 0x10000>; 15 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 16 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 17 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 18 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 19 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 20 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 21 #interrupt-cells = <2>; 22 interrupt-controller; 23 #gpio-cells = <2>; 24 gpio-controller; 25 }; 26 27 uarta: serial@3100000 { 28 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 29 reg = <0x0 0x03100000 0x0 0x40>; 30 reg-shift = <2>; 31 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&bpmp 55>; 33 clock-names = "serial"; 34 resets = <&bpmp 47>; 35 reset-names = "serial"; 36 status = "disabled"; 37 }; 38 39 uartb: serial@3110000 { 40 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 41 reg = <0x0 0x03110000 0x0 0x40>; 42 reg-shift = <2>; 43 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 44 clocks = <&bpmp 56>; 45 clock-names = "serial"; 46 resets = <&bpmp 48>; 47 reset-names = "serial"; 48 status = "disabled"; 49 }; 50 51 uartd: serial@3130000 { 52 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 53 reg = <0x0 0x03130000 0x0 0x40>; 54 reg-shift = <2>; 55 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 56 clocks = <&bpmp 77>; 57 clock-names = "serial"; 58 resets = <&bpmp 50>; 59 reset-names = "serial"; 60 status = "disabled"; 61 }; 62 63 uarte: serial@3140000 { 64 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 65 reg = <0x0 0x03140000 0x0 0x40>; 66 reg-shift = <2>; 67 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&bpmp 194>; 69 clock-names = "serial"; 70 resets = <&bpmp 132>; 71 reset-names = "serial"; 72 status = "disabled"; 73 }; 74 75 uartf: serial@3150000 { 76 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 77 reg = <0x0 0x03150000 0x0 0x40>; 78 reg-shift = <2>; 79 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 80 clocks = <&bpmp 195>; 81 clock-names = "serial"; 82 resets = <&bpmp 111>; 83 reset-names = "serial"; 84 status = "disabled"; 85 }; 86 87 gen1_i2c: i2c@3160000 { 88 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 89 reg = <0x0 0x03160000 0x0 0x10000>; 90 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 91 #address-cells = <1>; 92 #size-cells = <0>; 93 clocks = <&bpmp 47>; 94 clock-names = "div-clk"; 95 resets = <&bpmp 19>; 96 reset-names = "i2c"; 97 status = "disabled"; 98 }; 99 100 cam_i2c: i2c@3180000 { 101 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 102 reg = <0x0 0x03180000 0x0 0x10000>; 103 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 clocks = <&bpmp 75>; 107 clock-names = "div-clk"; 108 resets = <&bpmp 21>; 109 reset-names = "i2c"; 110 status = "disabled"; 111 }; 112 113 /* shares pads with dpaux1 */ 114 dp_aux_ch1_i2c: i2c@3190000 { 115 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 116 reg = <0x0 0x03190000 0x0 0x10000>; 117 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 clocks = <&bpmp 86>; 121 clock-names = "div-clk"; 122 resets = <&bpmp 22>; 123 reset-names = "i2c"; 124 status = "disabled"; 125 }; 126 127 /* controlled by BPMP, should not be enabled */ 128 pwr_i2c: i2c@31a0000 { 129 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 130 reg = <0x0 0x031a0000 0x0 0x10000>; 131 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 clocks = <&bpmp 48>; 135 clock-names = "div-clk"; 136 resets = <&bpmp 23>; 137 reset-names = "i2c"; 138 status = "disabled"; 139 }; 140 141 /* shares pads with dpaux0 */ 142 dp_aux_ch0_i2c: i2c@31b0000 { 143 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 144 reg = <0x0 0x031b0000 0x0 0x10000>; 145 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clocks = <&bpmp 125>; 149 clock-names = "div-clk"; 150 resets = <&bpmp 24>; 151 reset-names = "i2c"; 152 status = "disabled"; 153 }; 154 155 gen7_i2c: i2c@31c0000 { 156 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 157 reg = <0x0 0x031c0000 0x0 0x10000>; 158 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 clocks = <&bpmp 182>; 162 clock-names = "div-clk"; 163 resets = <&bpmp 81>; 164 reset-names = "i2c"; 165 status = "disabled"; 166 }; 167 168 gen9_i2c: i2c@31e0000 { 169 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 170 reg = <0x0 0x031e0000 0x0 0x10000>; 171 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 clocks = <&bpmp 183>; 175 clock-names = "div-clk"; 176 resets = <&bpmp 83>; 177 reset-names = "i2c"; 178 status = "disabled"; 179 }; 180 181 sdmmc1: sdhci@3400000 { 182 compatible = "nvidia,tegra186-sdhci"; 183 reg = <0x0 0x03400000 0x0 0x10000>; 184 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&bpmp 52>; 186 clock-names = "sdhci"; 187 resets = <&bpmp 33>; 188 reset-names = "sdhci"; 189 status = "disabled"; 190 }; 191 192 sdmmc2: sdhci@3420000 { 193 compatible = "nvidia,tegra186-sdhci"; 194 reg = <0x0 0x03420000 0x0 0x10000>; 195 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&bpmp 53>; 197 clock-names = "sdhci"; 198 resets = <&bpmp 34>; 199 reset-names = "sdhci"; 200 status = "disabled"; 201 }; 202 203 sdmmc3: sdhci@3440000 { 204 compatible = "nvidia,tegra186-sdhci"; 205 reg = <0x0 0x03440000 0x0 0x10000>; 206 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&bpmp 76>; 208 clock-names = "sdhci"; 209 resets = <&bpmp 35>; 210 reset-names = "sdhci"; 211 status = "disabled"; 212 }; 213 214 sdmmc4: sdhci@3460000 { 215 compatible = "nvidia,tegra186-sdhci"; 216 reg = <0x0 0x03460000 0x0 0x10000>; 217 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&bpmp 54>; 219 clock-names = "sdhci"; 220 resets = <&bpmp 36>; 221 reset-names = "sdhci"; 222 status = "disabled"; 223 }; 224 225 gic: interrupt-controller@3881000 { 226 compatible = "arm,gic-400"; 227 #interrupt-cells = <3>; 228 interrupt-controller; 229 reg = <0x0 0x03881000 0x0 0x1000>, 230 <0x0 0x03882000 0x0 0x2000>; 231 interrupts = <GIC_PPI 9 232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 233 interrupt-parent = <&gic>; 234 }; 235 236 hsp_top0: hsp@3c00000 { 237 compatible = "nvidia,tegra186-hsp"; 238 reg = <0x0 0x03c00000 0x0 0xa0000>; 239 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 240 interrupt-names = "doorbell"; 241 #mbox-cells = <2>; 242 status = "disabled"; 243 }; 244 245 gen2_i2c: i2c@c240000 { 246 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 247 reg = <0x0 0x0c240000 0x0 0x10000>; 248 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 clocks = <&bpmp 218>; 252 clock-names = "div-clk"; 253 resets = <&bpmp 20>; 254 reset-names = "i2c"; 255 status = "disabled"; 256 }; 257 258 gen8_i2c: i2c@c250000 { 259 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 260 reg = <0x0 0x0c250000 0x0 0x10000>; 261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 clocks = <&bpmp 219>; 265 clock-names = "div-clk"; 266 resets = <&bpmp 82>; 267 reset-names = "i2c"; 268 status = "disabled"; 269 }; 270 271 uartc: serial@c280000 { 272 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 273 reg = <0x0 0x0c280000 0x0 0x40>; 274 reg-shift = <2>; 275 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&bpmp 215>; 277 clock-names = "serial"; 278 resets = <&bpmp 49>; 279 reset-names = "serial"; 280 status = "disabled"; 281 }; 282 283 uartg: serial@c290000 { 284 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 285 reg = <0x0 0x0c290000 0x0 0x40>; 286 reg-shift = <2>; 287 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&bpmp 216>; 289 clock-names = "serial"; 290 resets = <&bpmp 112>; 291 reset-names = "serial"; 292 status = "disabled"; 293 }; 294 295 gpio_aon: gpio@c2f0000 { 296 compatible = "nvidia,tegra186-gpio-aon"; 297 reg-names = "security", "gpio"; 298 reg = <0x0 0xc2f0000 0x0 0x1000>, 299 <0x0 0xc2f1000 0x0 0x1000>; 300 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 }; 306 307 sysram@30000000 { 308 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 309 reg = <0x0 0x30000000 0x0 0x50000>; 310 #address-cells = <2>; 311 #size-cells = <2>; 312 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 313 314 cpu_bpmp_tx: shmem@4e000 { 315 compatible = "nvidia,tegra186-bpmp-shmem"; 316 reg = <0x0 0x4e000 0x0 0x1000>; 317 label = "cpu-bpmp-tx"; 318 pool; 319 }; 320 321 cpu_bpmp_rx: shmem@4f000 { 322 compatible = "nvidia,tegra186-bpmp-shmem"; 323 reg = <0x0 0x4f000 0x0 0x1000>; 324 label = "cpu-bpmp-rx"; 325 pool; 326 }; 327 }; 328 329 cpus { 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 cpu@0 { 334 compatible = "nvidia,tegra186-denver", "arm,armv8"; 335 device_type = "cpu"; 336 reg = <0x000>; 337 }; 338 339 cpu@1 { 340 compatible = "nvidia,tegra186-denver", "arm,armv8"; 341 device_type = "cpu"; 342 reg = <0x001>; 343 }; 344 345 cpu@2 { 346 compatible = "arm,cortex-a57", "arm,armv8"; 347 device_type = "cpu"; 348 reg = <0x100>; 349 }; 350 351 cpu@3 { 352 compatible = "arm,cortex-a57", "arm,armv8"; 353 device_type = "cpu"; 354 reg = <0x101>; 355 }; 356 357 cpu@4 { 358 compatible = "arm,cortex-a57", "arm,armv8"; 359 device_type = "cpu"; 360 reg = <0x102>; 361 }; 362 363 cpu@5 { 364 compatible = "arm,cortex-a57", "arm,armv8"; 365 device_type = "cpu"; 366 reg = <0x103>; 367 }; 368 }; 369 370 bpmp: bpmp { 371 compatible = "nvidia,tegra186-bpmp"; 372 mboxes = <&hsp_top0 0 19>; 373 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 377 bpmp_i2c: i2c { 378 compatible = "nvidia,tegra186-bpmp-i2c"; 379 nvidia,bpmp-bus-id = <5>; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 status = "disabled"; 383 }; 384 }; 385 386 timer { 387 compatible = "arm,armv8-timer"; 388 interrupts = <GIC_PPI 13 389 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 390 <GIC_PPI 14 391 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 392 <GIC_PPI 11 393 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 394 <GIC_PPI 10 395 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 396 interrupt-parent = <&gic>; 397 }; 398}; 399