1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 iommus = <&smmu TEGRA186_SID_EQOS>; 64 status = "disabled"; 65 66 snps,write-requests = <1>; 67 snps,read-requests = <3>; 68 snps,burst-map = <0x7>; 69 snps,txpbl = <32>; 70 snps,rxpbl = <8>; 71 }; 72 73 aconnect { 74 compatible = "nvidia,tegra186-aconnect", 75 "nvidia,tegra210-aconnect"; 76 clocks = <&bpmp TEGRA186_CLK_APE>, 77 <&bpmp TEGRA186_CLK_APB2APE>; 78 clock-names = "ape", "apb2ape"; 79 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges = <0x02900000 0x0 0x02900000 0x200000>; 83 status = "disabled"; 84 85 dma-controller@2930000 { 86 compatible = "nvidia,tegra186-adma"; 87 reg = <0x02930000 0x20000>; 88 interrupt-parent = <&agic>; 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 121 #dma-cells = <1>; 122 clocks = <&bpmp TEGRA186_CLK_AHUB>; 123 clock-names = "d_audio"; 124 status = "disabled"; 125 }; 126 127 agic: interrupt-controller@2a40000 { 128 compatible = "nvidia,tegra186-agic", 129 "nvidia,tegra210-agic"; 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 reg = <0x02a41000 0x1000>, 133 <0x02a42000 0x2000>; 134 interrupts = <GIC_SPI 145 135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 136 clocks = <&bpmp TEGRA186_CLK_APE>; 137 clock-names = "clk"; 138 status = "disabled"; 139 }; 140 }; 141 142 memory-controller@2c00000 { 143 compatible = "nvidia,tegra186-mc"; 144 reg = <0x0 0x02c00000 0x0 0xb0000>; 145 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 146 status = "disabled"; 147 148 #address-cells = <2>; 149 #size-cells = <2>; 150 151 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 152 153 /* 154 * Memory clients have access to all 40 bits that the memory 155 * controller can address. 156 */ 157 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 158 159 emc: external-memory-controller@2c60000 { 160 compatible = "nvidia,tegra186-emc"; 161 reg = <0x0 0x02c60000 0x0 0x50000>; 162 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&bpmp TEGRA186_CLK_EMC>; 164 clock-names = "emc"; 165 166 nvidia,bpmp = <&bpmp>; 167 }; 168 }; 169 170 uarta: serial@3100000 { 171 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 172 reg = <0x0 0x03100000 0x0 0x40>; 173 reg-shift = <2>; 174 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&bpmp TEGRA186_CLK_UARTA>; 176 clock-names = "serial"; 177 resets = <&bpmp TEGRA186_RESET_UARTA>; 178 reset-names = "serial"; 179 status = "disabled"; 180 }; 181 182 uartb: serial@3110000 { 183 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 184 reg = <0x0 0x03110000 0x0 0x40>; 185 reg-shift = <2>; 186 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&bpmp TEGRA186_CLK_UARTB>; 188 clock-names = "serial"; 189 resets = <&bpmp TEGRA186_RESET_UARTB>; 190 reset-names = "serial"; 191 status = "disabled"; 192 }; 193 194 uartd: serial@3130000 { 195 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 196 reg = <0x0 0x03130000 0x0 0x40>; 197 reg-shift = <2>; 198 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&bpmp TEGRA186_CLK_UARTD>; 200 clock-names = "serial"; 201 resets = <&bpmp TEGRA186_RESET_UARTD>; 202 reset-names = "serial"; 203 status = "disabled"; 204 }; 205 206 uarte: serial@3140000 { 207 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 208 reg = <0x0 0x03140000 0x0 0x40>; 209 reg-shift = <2>; 210 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&bpmp TEGRA186_CLK_UARTE>; 212 clock-names = "serial"; 213 resets = <&bpmp TEGRA186_RESET_UARTE>; 214 reset-names = "serial"; 215 status = "disabled"; 216 }; 217 218 uartf: serial@3150000 { 219 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 220 reg = <0x0 0x03150000 0x0 0x40>; 221 reg-shift = <2>; 222 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&bpmp TEGRA186_CLK_UARTF>; 224 clock-names = "serial"; 225 resets = <&bpmp TEGRA186_RESET_UARTF>; 226 reset-names = "serial"; 227 status = "disabled"; 228 }; 229 230 gen1_i2c: i2c@3160000 { 231 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 232 reg = <0x0 0x03160000 0x0 0x10000>; 233 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 clocks = <&bpmp TEGRA186_CLK_I2C1>; 237 clock-names = "div-clk"; 238 resets = <&bpmp TEGRA186_RESET_I2C1>; 239 reset-names = "i2c"; 240 status = "disabled"; 241 }; 242 243 cam_i2c: i2c@3180000 { 244 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 245 reg = <0x0 0x03180000 0x0 0x10000>; 246 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 clocks = <&bpmp TEGRA186_CLK_I2C3>; 250 clock-names = "div-clk"; 251 resets = <&bpmp TEGRA186_RESET_I2C3>; 252 reset-names = "i2c"; 253 status = "disabled"; 254 }; 255 256 /* shares pads with dpaux1 */ 257 dp_aux_ch1_i2c: i2c@3190000 { 258 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 259 reg = <0x0 0x03190000 0x0 0x10000>; 260 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 clocks = <&bpmp TEGRA186_CLK_I2C4>; 264 clock-names = "div-clk"; 265 resets = <&bpmp TEGRA186_RESET_I2C4>; 266 reset-names = "i2c"; 267 pinctrl-names = "default", "idle"; 268 pinctrl-0 = <&state_dpaux1_i2c>; 269 pinctrl-1 = <&state_dpaux1_off>; 270 status = "disabled"; 271 }; 272 273 /* controlled by BPMP, should not be enabled */ 274 pwr_i2c: i2c@31a0000 { 275 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 276 reg = <0x0 0x031a0000 0x0 0x10000>; 277 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 clocks = <&bpmp TEGRA186_CLK_I2C5>; 281 clock-names = "div-clk"; 282 resets = <&bpmp TEGRA186_RESET_I2C5>; 283 reset-names = "i2c"; 284 status = "disabled"; 285 }; 286 287 /* shares pads with dpaux0 */ 288 dp_aux_ch0_i2c: i2c@31b0000 { 289 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 290 reg = <0x0 0x031b0000 0x0 0x10000>; 291 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 clocks = <&bpmp TEGRA186_CLK_I2C6>; 295 clock-names = "div-clk"; 296 resets = <&bpmp TEGRA186_RESET_I2C6>; 297 reset-names = "i2c"; 298 pinctrl-names = "default", "idle"; 299 pinctrl-0 = <&state_dpaux_i2c>; 300 pinctrl-1 = <&state_dpaux_off>; 301 status = "disabled"; 302 }; 303 304 gen7_i2c: i2c@31c0000 { 305 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 306 reg = <0x0 0x031c0000 0x0 0x10000>; 307 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clocks = <&bpmp TEGRA186_CLK_I2C7>; 311 clock-names = "div-clk"; 312 resets = <&bpmp TEGRA186_RESET_I2C7>; 313 reset-names = "i2c"; 314 status = "disabled"; 315 }; 316 317 gen9_i2c: i2c@31e0000 { 318 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 319 reg = <0x0 0x031e0000 0x0 0x10000>; 320 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 clocks = <&bpmp TEGRA186_CLK_I2C9>; 324 clock-names = "div-clk"; 325 resets = <&bpmp TEGRA186_RESET_I2C9>; 326 reset-names = "i2c"; 327 status = "disabled"; 328 }; 329 330 sdmmc1: sdhci@3400000 { 331 compatible = "nvidia,tegra186-sdhci"; 332 reg = <0x0 0x03400000 0x0 0x10000>; 333 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 335 clock-names = "sdhci"; 336 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 337 reset-names = "sdhci"; 338 iommus = <&smmu TEGRA186_SID_SDMMC1>; 339 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 340 pinctrl-0 = <&sdmmc1_3v3>; 341 pinctrl-1 = <&sdmmc1_1v8>; 342 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 343 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 344 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 345 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 346 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 347 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 348 nvidia,default-tap = <0x5>; 349 nvidia,default-trim = <0xb>; 350 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 351 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 353 status = "disabled"; 354 }; 355 356 sdmmc2: sdhci@3420000 { 357 compatible = "nvidia,tegra186-sdhci"; 358 reg = <0x0 0x03420000 0x0 0x10000>; 359 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 361 clock-names = "sdhci"; 362 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 363 reset-names = "sdhci"; 364 iommus = <&smmu TEGRA186_SID_SDMMC2>; 365 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 366 pinctrl-0 = <&sdmmc2_3v3>; 367 pinctrl-1 = <&sdmmc2_1v8>; 368 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 369 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 370 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 371 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 372 nvidia,default-tap = <0x5>; 373 nvidia,default-trim = <0xb>; 374 status = "disabled"; 375 }; 376 377 sdmmc3: sdhci@3440000 { 378 compatible = "nvidia,tegra186-sdhci"; 379 reg = <0x0 0x03440000 0x0 0x10000>; 380 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 382 clock-names = "sdhci"; 383 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 384 reset-names = "sdhci"; 385 iommus = <&smmu TEGRA186_SID_SDMMC3>; 386 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 387 pinctrl-0 = <&sdmmc3_3v3>; 388 pinctrl-1 = <&sdmmc3_1v8>; 389 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 390 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 391 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 392 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 393 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 394 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 395 nvidia,default-tap = <0x5>; 396 nvidia,default-trim = <0xb>; 397 status = "disabled"; 398 }; 399 400 sdmmc4: sdhci@3460000 { 401 compatible = "nvidia,tegra186-sdhci"; 402 reg = <0x0 0x03460000 0x0 0x10000>; 403 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 405 clock-names = "sdhci"; 406 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 407 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 408 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 409 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 410 reset-names = "sdhci"; 411 iommus = <&smmu TEGRA186_SID_SDMMC4>; 412 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 413 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 414 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 415 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 416 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 417 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 418 nvidia,default-tap = <0x9>; 419 nvidia,default-trim = <0x5>; 420 nvidia,dqs-trim = <63>; 421 mmc-hs400-1_8v; 422 supports-cqe; 423 status = "disabled"; 424 }; 425 426 hda@3510000 { 427 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 428 reg = <0x0 0x03510000 0x0 0x10000>; 429 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&bpmp TEGRA186_CLK_HDA>, 431 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 432 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 433 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 434 resets = <&bpmp TEGRA186_RESET_HDA>, 435 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 436 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 437 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 438 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 439 iommus = <&smmu TEGRA186_SID_HDA>; 440 status = "disabled"; 441 }; 442 443 padctl: padctl@3520000 { 444 compatible = "nvidia,tegra186-xusb-padctl"; 445 reg = <0x0 0x03520000 0x0 0x1000>, 446 <0x0 0x03540000 0x0 0x1000>; 447 reg-names = "padctl", "ao"; 448 449 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 450 reset-names = "padctl"; 451 452 status = "disabled"; 453 454 pads { 455 usb2 { 456 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 457 clock-names = "trk"; 458 status = "disabled"; 459 460 lanes { 461 usb2-0 { 462 status = "disabled"; 463 #phy-cells = <0>; 464 }; 465 466 usb2-1 { 467 status = "disabled"; 468 #phy-cells = <0>; 469 }; 470 471 usb2-2 { 472 status = "disabled"; 473 #phy-cells = <0>; 474 }; 475 }; 476 }; 477 478 hsic { 479 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 480 clock-names = "trk"; 481 status = "disabled"; 482 483 lanes { 484 hsic-0 { 485 status = "disabled"; 486 #phy-cells = <0>; 487 }; 488 }; 489 }; 490 491 usb3 { 492 status = "disabled"; 493 494 lanes { 495 usb3-0 { 496 status = "disabled"; 497 #phy-cells = <0>; 498 }; 499 500 usb3-1 { 501 status = "disabled"; 502 #phy-cells = <0>; 503 }; 504 505 usb3-2 { 506 status = "disabled"; 507 #phy-cells = <0>; 508 }; 509 }; 510 }; 511 }; 512 513 ports { 514 usb2-0 { 515 status = "disabled"; 516 }; 517 518 usb2-1 { 519 status = "disabled"; 520 }; 521 522 usb2-2 { 523 status = "disabled"; 524 }; 525 526 hsic-0 { 527 status = "disabled"; 528 }; 529 530 usb3-0 { 531 status = "disabled"; 532 }; 533 534 usb3-1 { 535 status = "disabled"; 536 }; 537 538 usb3-2 { 539 status = "disabled"; 540 }; 541 }; 542 }; 543 544 usb@3530000 { 545 compatible = "nvidia,tegra186-xusb"; 546 reg = <0x0 0x03530000 0x0 0x8000>, 547 <0x0 0x03538000 0x0 0x1000>; 548 reg-names = "hcd", "fpci"; 549 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 553 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 554 <&bpmp TEGRA186_CLK_XUSB_SS>, 555 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 556 <&bpmp TEGRA186_CLK_CLK_M>, 557 <&bpmp TEGRA186_CLK_XUSB_FS>, 558 <&bpmp TEGRA186_CLK_PLLU>, 559 <&bpmp TEGRA186_CLK_CLK_M>, 560 <&bpmp TEGRA186_CLK_PLLE>; 561 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 562 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 563 "pll_u_480m", "clk_m", "pll_e"; 564 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 565 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 566 power-domain-names = "xusb_host", "xusb_ss"; 567 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 572 nvidia,xusb-padctl = <&padctl>; 573 }; 574 575 usb@3550000 { 576 compatible = "nvidia,tegra186-xudc"; 577 reg = <0x0 0x03550000 0x0 0x8000>, 578 <0x0 0x03558000 0x0 0x1000>; 579 reg-names = "base", "fpci"; 580 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 582 <&bpmp TEGRA186_CLK_XUSB_SS>, 583 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 584 <&bpmp TEGRA186_CLK_XUSB_FS>; 585 clock-names = "dev", "ss", "ss_src", "fs_src"; 586 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 587 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 588 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 589 power-domain-names = "dev", "ss"; 590 nvidia,xusb-padctl = <&padctl>; 591 status = "disabled"; 592 }; 593 594 fuse@3820000 { 595 compatible = "nvidia,tegra186-efuse"; 596 reg = <0x0 0x03820000 0x0 0x10000>; 597 clocks = <&bpmp TEGRA186_CLK_FUSE>; 598 clock-names = "fuse"; 599 }; 600 601 gic: interrupt-controller@3881000 { 602 compatible = "arm,gic-400"; 603 #interrupt-cells = <3>; 604 interrupt-controller; 605 reg = <0x0 0x03881000 0x0 0x1000>, 606 <0x0 0x03882000 0x0 0x2000>; 607 interrupts = <GIC_PPI 9 608 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 609 interrupt-parent = <&gic>; 610 }; 611 612 cec@3960000 { 613 compatible = "nvidia,tegra186-cec"; 614 reg = <0x0 0x03960000 0x0 0x10000>; 615 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&bpmp TEGRA186_CLK_CEC>; 617 clock-names = "cec"; 618 status = "disabled"; 619 }; 620 621 hsp_top0: hsp@3c00000 { 622 compatible = "nvidia,tegra186-hsp"; 623 reg = <0x0 0x03c00000 0x0 0xa0000>; 624 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 625 interrupt-names = "doorbell"; 626 #mbox-cells = <2>; 627 status = "disabled"; 628 }; 629 630 gen2_i2c: i2c@c240000 { 631 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 632 reg = <0x0 0x0c240000 0x0 0x10000>; 633 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 clocks = <&bpmp TEGRA186_CLK_I2C2>; 637 clock-names = "div-clk"; 638 resets = <&bpmp TEGRA186_RESET_I2C2>; 639 reset-names = "i2c"; 640 status = "disabled"; 641 }; 642 643 gen8_i2c: i2c@c250000 { 644 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 645 reg = <0x0 0x0c250000 0x0 0x10000>; 646 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 clocks = <&bpmp TEGRA186_CLK_I2C8>; 650 clock-names = "div-clk"; 651 resets = <&bpmp TEGRA186_RESET_I2C8>; 652 reset-names = "i2c"; 653 status = "disabled"; 654 }; 655 656 uartc: serial@c280000 { 657 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 658 reg = <0x0 0x0c280000 0x0 0x40>; 659 reg-shift = <2>; 660 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&bpmp TEGRA186_CLK_UARTC>; 662 clock-names = "serial"; 663 resets = <&bpmp TEGRA186_RESET_UARTC>; 664 reset-names = "serial"; 665 status = "disabled"; 666 }; 667 668 uartg: serial@c290000 { 669 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 670 reg = <0x0 0x0c290000 0x0 0x40>; 671 reg-shift = <2>; 672 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&bpmp TEGRA186_CLK_UARTG>; 674 clock-names = "serial"; 675 resets = <&bpmp TEGRA186_RESET_UARTG>; 676 reset-names = "serial"; 677 status = "disabled"; 678 }; 679 680 rtc: rtc@c2a0000 { 681 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 682 reg = <0 0x0c2a0000 0 0x10000>; 683 interrupt-parent = <&pmc>; 684 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 686 clock-names = "rtc"; 687 status = "disabled"; 688 }; 689 690 gpio_aon: gpio@c2f0000 { 691 compatible = "nvidia,tegra186-gpio-aon"; 692 reg-names = "security", "gpio"; 693 reg = <0x0 0xc2f0000 0x0 0x1000>, 694 <0x0 0xc2f1000 0x0 0x1000>; 695 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 696 gpio-controller; 697 #gpio-cells = <2>; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 702 pmc: pmc@c360000 { 703 compatible = "nvidia,tegra186-pmc"; 704 reg = <0 0x0c360000 0 0x10000>, 705 <0 0x0c370000 0 0x10000>, 706 <0 0x0c380000 0 0x10000>, 707 <0 0x0c390000 0 0x10000>; 708 reg-names = "pmc", "wake", "aotag", "scratch"; 709 710 #interrupt-cells = <2>; 711 interrupt-controller; 712 713 sdmmc1_3v3: sdmmc1-3v3 { 714 pins = "sdmmc1-hv"; 715 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 716 }; 717 718 sdmmc1_1v8: sdmmc1-1v8 { 719 pins = "sdmmc1-hv"; 720 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 721 }; 722 723 sdmmc2_3v3: sdmmc2-3v3 { 724 pins = "sdmmc2-hv"; 725 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 726 }; 727 728 sdmmc2_1v8: sdmmc2-1v8 { 729 pins = "sdmmc2-hv"; 730 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 731 }; 732 733 sdmmc3_3v3: sdmmc3-3v3 { 734 pins = "sdmmc3-hv"; 735 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 736 }; 737 738 sdmmc3_1v8: sdmmc3-1v8 { 739 pins = "sdmmc3-hv"; 740 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 741 }; 742 }; 743 744 ccplex@e000000 { 745 compatible = "nvidia,tegra186-ccplex-cluster"; 746 reg = <0x0 0x0e000000 0x0 0x3fffff>; 747 748 nvidia,bpmp = <&bpmp>; 749 }; 750 751 pcie@10003000 { 752 compatible = "nvidia,tegra186-pcie"; 753 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 754 device_type = "pci"; 755 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 756 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 757 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 758 reg-names = "pads", "afi", "cs"; 759 760 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 761 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 762 interrupt-names = "intr", "msi"; 763 764 #interrupt-cells = <1>; 765 interrupt-map-mask = <0 0 0 0>; 766 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 767 768 bus-range = <0x00 0xff>; 769 #address-cells = <3>; 770 #size-cells = <2>; 771 772 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 773 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 774 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 775 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 776 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 777 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 778 779 clocks = <&bpmp TEGRA186_CLK_AFI>, 780 <&bpmp TEGRA186_CLK_PCIE>, 781 <&bpmp TEGRA186_CLK_PLLE>; 782 clock-names = "afi", "pex", "pll_e"; 783 784 resets = <&bpmp TEGRA186_RESET_AFI>, 785 <&bpmp TEGRA186_RESET_PCIE>, 786 <&bpmp TEGRA186_RESET_PCIEXCLK>; 787 reset-names = "afi", "pex", "pcie_x"; 788 789 iommus = <&smmu TEGRA186_SID_AFI>; 790 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 791 iommu-map-mask = <0x0>; 792 793 status = "disabled"; 794 795 pci@1,0 { 796 device_type = "pci"; 797 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 798 reg = <0x000800 0 0 0 0>; 799 status = "disabled"; 800 801 #address-cells = <3>; 802 #size-cells = <2>; 803 ranges; 804 805 nvidia,num-lanes = <2>; 806 }; 807 808 pci@2,0 { 809 device_type = "pci"; 810 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 811 reg = <0x001000 0 0 0 0>; 812 status = "disabled"; 813 814 #address-cells = <3>; 815 #size-cells = <2>; 816 ranges; 817 818 nvidia,num-lanes = <1>; 819 }; 820 821 pci@3,0 { 822 device_type = "pci"; 823 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 824 reg = <0x001800 0 0 0 0>; 825 status = "disabled"; 826 827 #address-cells = <3>; 828 #size-cells = <2>; 829 ranges; 830 831 nvidia,num-lanes = <1>; 832 }; 833 }; 834 835 smmu: iommu@12000000 { 836 compatible = "arm,mmu-500"; 837 reg = <0 0x12000000 0 0x800000>; 838 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 903 stream-match-mask = <0x7f80>; 904 #global-interrupts = <1>; 905 #iommu-cells = <1>; 906 }; 907 908 host1x@13e00000 { 909 compatible = "nvidia,tegra186-host1x", "simple-bus"; 910 reg = <0x0 0x13e00000 0x0 0x10000>, 911 <0x0 0x13e10000 0x0 0x10000>; 912 reg-names = "hypervisor", "vm"; 913 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 916 clock-names = "host1x"; 917 resets = <&bpmp TEGRA186_RESET_HOST1X>; 918 reset-names = "host1x"; 919 920 #address-cells = <1>; 921 #size-cells = <1>; 922 923 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 924 iommus = <&smmu TEGRA186_SID_HOST1X>; 925 926 dpaux1: dpaux@15040000 { 927 compatible = "nvidia,tegra186-dpaux"; 928 reg = <0x15040000 0x10000>; 929 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 931 <&bpmp TEGRA186_CLK_PLLDP>; 932 clock-names = "dpaux", "parent"; 933 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 934 reset-names = "dpaux"; 935 status = "disabled"; 936 937 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 938 939 state_dpaux1_aux: pinmux-aux { 940 groups = "dpaux-io"; 941 function = "aux"; 942 }; 943 944 state_dpaux1_i2c: pinmux-i2c { 945 groups = "dpaux-io"; 946 function = "i2c"; 947 }; 948 949 state_dpaux1_off: pinmux-off { 950 groups = "dpaux-io"; 951 function = "off"; 952 }; 953 954 i2c-bus { 955 #address-cells = <1>; 956 #size-cells = <0>; 957 }; 958 }; 959 960 display-hub@15200000 { 961 compatible = "nvidia,tegra186-display", "simple-bus"; 962 reg = <0x15200000 0x00040000>; 963 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 964 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 965 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 966 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 967 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 968 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 969 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 970 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 971 "wgrp3", "wgrp4", "wgrp5"; 972 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 973 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 974 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 975 clock-names = "disp", "dsc", "hub"; 976 status = "disabled"; 977 978 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 979 980 #address-cells = <1>; 981 #size-cells = <1>; 982 983 ranges = <0x15200000 0x15200000 0x40000>; 984 985 display@15200000 { 986 compatible = "nvidia,tegra186-dc"; 987 reg = <0x15200000 0x10000>; 988 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 990 clock-names = "dc"; 991 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 992 reset-names = "dc"; 993 994 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 995 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 996 997 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 998 nvidia,head = <0>; 999 }; 1000 1001 display@15210000 { 1002 compatible = "nvidia,tegra186-dc"; 1003 reg = <0x15210000 0x10000>; 1004 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1006 clock-names = "dc"; 1007 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1008 reset-names = "dc"; 1009 1010 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1011 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1012 1013 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1014 nvidia,head = <1>; 1015 }; 1016 1017 display@15220000 { 1018 compatible = "nvidia,tegra186-dc"; 1019 reg = <0x15220000 0x10000>; 1020 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1022 clock-names = "dc"; 1023 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1024 reset-names = "dc"; 1025 1026 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1027 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1028 1029 nvidia,outputs = <&sor0 &sor1>; 1030 nvidia,head = <2>; 1031 }; 1032 }; 1033 1034 dsia: dsi@15300000 { 1035 compatible = "nvidia,tegra186-dsi"; 1036 reg = <0x15300000 0x10000>; 1037 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&bpmp TEGRA186_CLK_DSI>, 1039 <&bpmp TEGRA186_CLK_DSIA_LP>, 1040 <&bpmp TEGRA186_CLK_PLLD>; 1041 clock-names = "dsi", "lp", "parent"; 1042 resets = <&bpmp TEGRA186_RESET_DSI>; 1043 reset-names = "dsi"; 1044 status = "disabled"; 1045 1046 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1047 }; 1048 1049 vic@15340000 { 1050 compatible = "nvidia,tegra186-vic"; 1051 reg = <0x15340000 0x40000>; 1052 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&bpmp TEGRA186_CLK_VIC>; 1054 clock-names = "vic"; 1055 resets = <&bpmp TEGRA186_RESET_VIC>; 1056 reset-names = "vic"; 1057 1058 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1059 iommus = <&smmu TEGRA186_SID_VIC>; 1060 }; 1061 1062 dsib: dsi@15400000 { 1063 compatible = "nvidia,tegra186-dsi"; 1064 reg = <0x15400000 0x10000>; 1065 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1067 <&bpmp TEGRA186_CLK_DSIB_LP>, 1068 <&bpmp TEGRA186_CLK_PLLD>; 1069 clock-names = "dsi", "lp", "parent"; 1070 resets = <&bpmp TEGRA186_RESET_DSIB>; 1071 reset-names = "dsi"; 1072 status = "disabled"; 1073 1074 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1075 }; 1076 1077 sor0: sor@15540000 { 1078 compatible = "nvidia,tegra186-sor"; 1079 reg = <0x15540000 0x10000>; 1080 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1082 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1083 <&bpmp TEGRA186_CLK_PLLD2>, 1084 <&bpmp TEGRA186_CLK_PLLDP>, 1085 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1086 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1087 clock-names = "sor", "out", "parent", "dp", "safe", 1088 "pad"; 1089 resets = <&bpmp TEGRA186_RESET_SOR0>; 1090 reset-names = "sor"; 1091 pinctrl-0 = <&state_dpaux_aux>; 1092 pinctrl-1 = <&state_dpaux_i2c>; 1093 pinctrl-2 = <&state_dpaux_off>; 1094 pinctrl-names = "aux", "i2c", "off"; 1095 status = "disabled"; 1096 1097 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1098 nvidia,interface = <0>; 1099 }; 1100 1101 sor1: sor@15580000 { 1102 compatible = "nvidia,tegra186-sor"; 1103 reg = <0x15580000 0x10000>; 1104 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1106 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1107 <&bpmp TEGRA186_CLK_PLLD3>, 1108 <&bpmp TEGRA186_CLK_PLLDP>, 1109 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1110 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1111 clock-names = "sor", "out", "parent", "dp", "safe", 1112 "pad"; 1113 resets = <&bpmp TEGRA186_RESET_SOR1>; 1114 reset-names = "sor"; 1115 pinctrl-0 = <&state_dpaux1_aux>; 1116 pinctrl-1 = <&state_dpaux1_i2c>; 1117 pinctrl-2 = <&state_dpaux1_off>; 1118 pinctrl-names = "aux", "i2c", "off"; 1119 status = "disabled"; 1120 1121 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1122 nvidia,interface = <1>; 1123 }; 1124 1125 dpaux: dpaux@155c0000 { 1126 compatible = "nvidia,tegra186-dpaux"; 1127 reg = <0x155c0000 0x10000>; 1128 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1130 <&bpmp TEGRA186_CLK_PLLDP>; 1131 clock-names = "dpaux", "parent"; 1132 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1133 reset-names = "dpaux"; 1134 status = "disabled"; 1135 1136 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1137 1138 state_dpaux_aux: pinmux-aux { 1139 groups = "dpaux-io"; 1140 function = "aux"; 1141 }; 1142 1143 state_dpaux_i2c: pinmux-i2c { 1144 groups = "dpaux-io"; 1145 function = "i2c"; 1146 }; 1147 1148 state_dpaux_off: pinmux-off { 1149 groups = "dpaux-io"; 1150 function = "off"; 1151 }; 1152 1153 i2c-bus { 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 }; 1157 }; 1158 1159 padctl@15880000 { 1160 compatible = "nvidia,tegra186-dsi-padctl"; 1161 reg = <0x15880000 0x10000>; 1162 resets = <&bpmp TEGRA186_RESET_DSI>; 1163 reset-names = "dsi"; 1164 status = "disabled"; 1165 }; 1166 1167 dsic: dsi@15900000 { 1168 compatible = "nvidia,tegra186-dsi"; 1169 reg = <0x15900000 0x10000>; 1170 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1172 <&bpmp TEGRA186_CLK_DSIC_LP>, 1173 <&bpmp TEGRA186_CLK_PLLD>; 1174 clock-names = "dsi", "lp", "parent"; 1175 resets = <&bpmp TEGRA186_RESET_DSIC>; 1176 reset-names = "dsi"; 1177 status = "disabled"; 1178 1179 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1180 }; 1181 1182 dsid: dsi@15940000 { 1183 compatible = "nvidia,tegra186-dsi"; 1184 reg = <0x15940000 0x10000>; 1185 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&bpmp TEGRA186_CLK_DSID>, 1187 <&bpmp TEGRA186_CLK_DSID_LP>, 1188 <&bpmp TEGRA186_CLK_PLLD>; 1189 clock-names = "dsi", "lp", "parent"; 1190 resets = <&bpmp TEGRA186_RESET_DSID>; 1191 reset-names = "dsi"; 1192 status = "disabled"; 1193 1194 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1195 }; 1196 }; 1197 1198 gpu@17000000 { 1199 compatible = "nvidia,gp10b"; 1200 reg = <0x0 0x17000000 0x0 0x1000000>, 1201 <0x0 0x18000000 0x0 0x1000000>; 1202 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1203 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1204 interrupt-names = "stall", "nonstall"; 1205 1206 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1207 <&bpmp TEGRA186_CLK_GPU>; 1208 clock-names = "gpu", "pwr"; 1209 resets = <&bpmp TEGRA186_RESET_GPU>; 1210 reset-names = "gpu"; 1211 status = "disabled"; 1212 1213 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1214 }; 1215 1216 sysram@30000000 { 1217 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1218 reg = <0x0 0x30000000 0x0 0x50000>; 1219 #address-cells = <2>; 1220 #size-cells = <2>; 1221 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 1222 1223 cpu_bpmp_tx: shmem@4e000 { 1224 compatible = "nvidia,tegra186-bpmp-shmem"; 1225 reg = <0x0 0x4e000 0x0 0x1000>; 1226 label = "cpu-bpmp-tx"; 1227 pool; 1228 }; 1229 1230 cpu_bpmp_rx: shmem@4f000 { 1231 compatible = "nvidia,tegra186-bpmp-shmem"; 1232 reg = <0x0 0x4f000 0x0 0x1000>; 1233 label = "cpu-bpmp-rx"; 1234 pool; 1235 }; 1236 }; 1237 1238 bpmp: bpmp { 1239 compatible = "nvidia,tegra186-bpmp"; 1240 iommus = <&smmu TEGRA186_SID_BPMP>; 1241 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1242 TEGRA_HSP_DB_MASTER_BPMP>; 1243 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1244 #clock-cells = <1>; 1245 #reset-cells = <1>; 1246 #power-domain-cells = <1>; 1247 1248 bpmp_i2c: i2c { 1249 compatible = "nvidia,tegra186-bpmp-i2c"; 1250 nvidia,bpmp-bus-id = <5>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 status = "disabled"; 1254 }; 1255 1256 bpmp_thermal: thermal { 1257 compatible = "nvidia,tegra186-bpmp-thermal"; 1258 #thermal-sensor-cells = <1>; 1259 }; 1260 }; 1261 1262 cpus { 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 1266 cpu@0 { 1267 compatible = "nvidia,tegra186-denver"; 1268 device_type = "cpu"; 1269 i-cache-size = <0x20000>; 1270 i-cache-line-size = <64>; 1271 i-cache-sets = <512>; 1272 d-cache-size = <0x10000>; 1273 d-cache-line-size = <64>; 1274 d-cache-sets = <256>; 1275 next-level-cache = <&L2_DENVER>; 1276 reg = <0x000>; 1277 }; 1278 1279 cpu@1 { 1280 compatible = "nvidia,tegra186-denver"; 1281 device_type = "cpu"; 1282 i-cache-size = <0x20000>; 1283 i-cache-line-size = <64>; 1284 i-cache-sets = <512>; 1285 d-cache-size = <0x10000>; 1286 d-cache-line-size = <64>; 1287 d-cache-sets = <256>; 1288 next-level-cache = <&L2_DENVER>; 1289 reg = <0x001>; 1290 }; 1291 1292 cpu@2 { 1293 compatible = "arm,cortex-a57"; 1294 device_type = "cpu"; 1295 i-cache-size = <0xC000>; 1296 i-cache-line-size = <64>; 1297 i-cache-sets = <256>; 1298 d-cache-size = <0x8000>; 1299 d-cache-line-size = <64>; 1300 d-cache-sets = <256>; 1301 next-level-cache = <&L2_A57>; 1302 reg = <0x100>; 1303 }; 1304 1305 cpu@3 { 1306 compatible = "arm,cortex-a57"; 1307 device_type = "cpu"; 1308 i-cache-size = <0xC000>; 1309 i-cache-line-size = <64>; 1310 i-cache-sets = <256>; 1311 d-cache-size = <0x8000>; 1312 d-cache-line-size = <64>; 1313 d-cache-sets = <256>; 1314 next-level-cache = <&L2_A57>; 1315 reg = <0x101>; 1316 }; 1317 1318 cpu@4 { 1319 compatible = "arm,cortex-a57"; 1320 device_type = "cpu"; 1321 i-cache-size = <0xC000>; 1322 i-cache-line-size = <64>; 1323 i-cache-sets = <256>; 1324 d-cache-size = <0x8000>; 1325 d-cache-line-size = <64>; 1326 d-cache-sets = <256>; 1327 next-level-cache = <&L2_A57>; 1328 reg = <0x102>; 1329 }; 1330 1331 cpu@5 { 1332 compatible = "arm,cortex-a57"; 1333 device_type = "cpu"; 1334 i-cache-size = <0xC000>; 1335 i-cache-line-size = <64>; 1336 i-cache-sets = <256>; 1337 d-cache-size = <0x8000>; 1338 d-cache-line-size = <64>; 1339 d-cache-sets = <256>; 1340 next-level-cache = <&L2_A57>; 1341 reg = <0x103>; 1342 }; 1343 1344 L2_DENVER: l2-cache0 { 1345 compatible = "cache"; 1346 cache-unified; 1347 cache-level = <2>; 1348 cache-size = <0x200000>; 1349 cache-line-size = <64>; 1350 cache-sets = <2048>; 1351 }; 1352 1353 L2_A57: l2-cache1 { 1354 compatible = "cache"; 1355 cache-unified; 1356 cache-level = <2>; 1357 cache-size = <0x200000>; 1358 cache-line-size = <64>; 1359 cache-sets = <2048>; 1360 }; 1361 }; 1362 1363 thermal-zones { 1364 a57 { 1365 polling-delay = <0>; 1366 polling-delay-passive = <1000>; 1367 1368 thermal-sensors = 1369 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1370 1371 trips { 1372 critical { 1373 temperature = <101000>; 1374 hysteresis = <0>; 1375 type = "critical"; 1376 }; 1377 }; 1378 1379 cooling-maps { 1380 }; 1381 }; 1382 1383 denver { 1384 polling-delay = <0>; 1385 polling-delay-passive = <1000>; 1386 1387 thermal-sensors = 1388 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1389 1390 trips { 1391 critical { 1392 temperature = <101000>; 1393 hysteresis = <0>; 1394 type = "critical"; 1395 }; 1396 }; 1397 1398 cooling-maps { 1399 }; 1400 }; 1401 1402 gpu { 1403 polling-delay = <0>; 1404 polling-delay-passive = <1000>; 1405 1406 thermal-sensors = 1407 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1408 1409 trips { 1410 critical { 1411 temperature = <101000>; 1412 hysteresis = <0>; 1413 type = "critical"; 1414 }; 1415 }; 1416 1417 cooling-maps { 1418 }; 1419 }; 1420 1421 pll { 1422 polling-delay = <0>; 1423 polling-delay-passive = <1000>; 1424 1425 thermal-sensors = 1426 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1427 1428 trips { 1429 critical { 1430 temperature = <101000>; 1431 hysteresis = <0>; 1432 type = "critical"; 1433 }; 1434 }; 1435 1436 cooling-maps { 1437 }; 1438 }; 1439 1440 always_on { 1441 polling-delay = <0>; 1442 polling-delay-passive = <1000>; 1443 1444 thermal-sensors = 1445 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1446 1447 trips { 1448 critical { 1449 temperature = <101000>; 1450 hysteresis = <0>; 1451 type = "critical"; 1452 }; 1453 }; 1454 1455 cooling-maps { 1456 }; 1457 }; 1458 }; 1459 1460 timer { 1461 compatible = "arm,armv8-timer"; 1462 interrupts = <GIC_PPI 13 1463 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1464 <GIC_PPI 14 1465 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1466 <GIC_PPI 11 1467 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1468 <GIC_PPI 10 1469 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1470 interrupt-parent = <&gic>; 1471 always-on; 1472 }; 1473}; 1474