1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/linux-event-codes.h> 5#include <dt-bindings/input/gpio-keys.h> 6 7#include "tegra186-p3310.dtsi" 8 9/ { 10 model = "NVIDIA Jetson TX2 Developer Kit"; 11 compatible = "nvidia,p2771-0000", "nvidia,tegra186"; 12 13 aconnect@2900000 { 14 status = "okay"; 15 16 dma-controller@2930000 { 17 status = "okay"; 18 }; 19 20 interrupt-controller@2a40000 { 21 status = "okay"; 22 }; 23 24 ahub@2900800 { 25 status = "okay"; 26 27 ports { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 port@0 { 32 reg = <0x0>; 33 34 xbar_admaif0_ep: endpoint { 35 remote-endpoint = <&admaif0_ep>; 36 }; 37 }; 38 39 port@1 { 40 reg = <0x1>; 41 42 xbar_admaif1_ep: endpoint { 43 remote-endpoint = <&admaif1_ep>; 44 }; 45 }; 46 47 port@2 { 48 reg = <0x2>; 49 50 xbar_admaif2_ep: endpoint { 51 remote-endpoint = <&admaif2_ep>; 52 }; 53 }; 54 55 port@3 { 56 reg = <0x3>; 57 58 xbar_admaif3_ep: endpoint { 59 remote-endpoint = <&admaif3_ep>; 60 }; 61 }; 62 63 port@4 { 64 reg = <0x4>; 65 66 xbar_admaif4_ep: endpoint { 67 remote-endpoint = <&admaif4_ep>; 68 }; 69 }; 70 71 port@5 { 72 reg = <0x5>; 73 74 xbar_admaif5_ep: endpoint { 75 remote-endpoint = <&admaif5_ep>; 76 }; 77 }; 78 79 port@6 { 80 reg = <0x6>; 81 82 xbar_admaif6_ep: endpoint { 83 remote-endpoint = <&admaif6_ep>; 84 }; 85 }; 86 87 port@7 { 88 reg = <0x7>; 89 90 xbar_admaif7_ep: endpoint { 91 remote-endpoint = <&admaif7_ep>; 92 }; 93 }; 94 95 port@8 { 96 reg = <0x8>; 97 98 xbar_admaif8_ep: endpoint { 99 remote-endpoint = <&admaif8_ep>; 100 }; 101 }; 102 103 port@9 { 104 reg = <0x9>; 105 106 xbar_admaif9_ep: endpoint { 107 remote-endpoint = <&admaif9_ep>; 108 }; 109 }; 110 111 port@a { 112 reg = <0xa>; 113 114 xbar_admaif10_ep: endpoint { 115 remote-endpoint = <&admaif10_ep>; 116 }; 117 }; 118 119 port@b { 120 reg = <0xb>; 121 122 xbar_admaif11_ep: endpoint { 123 remote-endpoint = <&admaif11_ep>; 124 }; 125 }; 126 127 port@c { 128 reg = <0xc>; 129 130 xbar_admaif12_ep: endpoint { 131 remote-endpoint = <&admaif12_ep>; 132 }; 133 }; 134 135 port@d { 136 reg = <0xd>; 137 138 xbar_admaif13_ep: endpoint { 139 remote-endpoint = <&admaif13_ep>; 140 }; 141 }; 142 143 port@e { 144 reg = <0xe>; 145 146 xbar_admaif14_ep: endpoint { 147 remote-endpoint = <&admaif14_ep>; 148 }; 149 }; 150 151 port@f { 152 reg = <0xf>; 153 154 xbar_admaif15_ep: endpoint { 155 remote-endpoint = <&admaif15_ep>; 156 }; 157 }; 158 159 port@10 { 160 reg = <0x10>; 161 162 xbar_admaif16_ep: endpoint { 163 remote-endpoint = <&admaif16_ep>; 164 }; 165 }; 166 167 port@11 { 168 reg = <0x11>; 169 170 xbar_admaif17_ep: endpoint { 171 remote-endpoint = <&admaif17_ep>; 172 }; 173 }; 174 175 port@12 { 176 reg = <0x12>; 177 178 xbar_admaif18_ep: endpoint { 179 remote-endpoint = <&admaif18_ep>; 180 }; 181 }; 182 183 port@13 { 184 reg = <0x13>; 185 186 xbar_admaif19_ep: endpoint { 187 remote-endpoint = <&admaif19_ep>; 188 }; 189 }; 190 191 xbar_i2s1_port: port@14 { 192 reg = <0x14>; 193 194 xbar_i2s1_ep: endpoint { 195 remote-endpoint = <&i2s1_cif_ep>; 196 }; 197 }; 198 199 xbar_i2s2_port: port@15 { 200 reg = <0x15>; 201 202 xbar_i2s2_ep: endpoint { 203 remote-endpoint = <&i2s2_cif_ep>; 204 }; 205 }; 206 207 xbar_i2s3_port: port@16 { 208 reg = <0x16>; 209 210 xbar_i2s3_ep: endpoint { 211 remote-endpoint = <&i2s3_cif_ep>; 212 }; 213 }; 214 215 xbar_i2s4_port: port@17 { 216 reg = <0x17>; 217 218 xbar_i2s4_ep: endpoint { 219 remote-endpoint = <&i2s4_cif_ep>; 220 }; 221 }; 222 223 xbar_i2s5_port: port@18 { 224 reg = <0x18>; 225 226 xbar_i2s5_ep: endpoint { 227 remote-endpoint = <&i2s5_cif_ep>; 228 }; 229 }; 230 231 xbar_i2s6_port: port@19 { 232 reg = <0x19>; 233 234 xbar_i2s6_ep: endpoint { 235 remote-endpoint = <&i2s6_cif_ep>; 236 }; 237 }; 238 239 xbar_dmic1_port: port@1a { 240 reg = <0x1a>; 241 242 xbar_dmic1_ep: endpoint { 243 remote-endpoint = <&dmic1_cif_ep>; 244 }; 245 }; 246 247 xbar_dmic2_port: port@1b { 248 reg = <0x1b>; 249 250 xbar_dmic2_ep: endpoint { 251 remote-endpoint = <&dmic2_cif_ep>; 252 }; 253 }; 254 255 xbar_dmic3_port: port@1c { 256 reg = <0x1c>; 257 258 xbar_dmic3_ep: endpoint { 259 remote-endpoint = <&dmic3_cif_ep>; 260 }; 261 }; 262 263 xbar_dspk1_port: port@1e { 264 reg = <0x1e>; 265 266 xbar_dspk1_ep: endpoint { 267 remote-endpoint = <&dspk1_cif_ep>; 268 }; 269 }; 270 271 xbar_dspk2_port: port@1f { 272 reg = <0x1f>; 273 274 xbar_dspk2_ep: endpoint { 275 remote-endpoint = <&dspk2_cif_ep>; 276 }; 277 }; 278 279 xbar_sfc1_in_port: port@20 { 280 reg = <0x20>; 281 282 xbar_sfc1_in_ep: endpoint { 283 remote-endpoint = <&sfc1_cif_in_ep>; 284 }; 285 }; 286 287 port@21 { 288 reg = <0x21>; 289 290 xbar_sfc1_out_ep: endpoint { 291 remote-endpoint = <&sfc1_cif_out_ep>; 292 }; 293 }; 294 295 xbar_sfc2_in_port: port@22 { 296 reg = <0x22>; 297 298 xbar_sfc2_in_ep: endpoint { 299 remote-endpoint = <&sfc2_cif_in_ep>; 300 }; 301 }; 302 303 port@23 { 304 reg = <0x23>; 305 306 xbar_sfc2_out_ep: endpoint { 307 remote-endpoint = <&sfc2_cif_out_ep>; 308 }; 309 }; 310 311 xbar_sfc3_in_port: port@24 { 312 reg = <0x24>; 313 314 xbar_sfc3_in_ep: endpoint { 315 remote-endpoint = <&sfc3_cif_in_ep>; 316 }; 317 }; 318 319 port@25 { 320 reg = <0x25>; 321 322 xbar_sfc3_out_ep: endpoint { 323 remote-endpoint = <&sfc3_cif_out_ep>; 324 }; 325 }; 326 327 xbar_sfc4_in_port: port@26 { 328 reg = <0x26>; 329 330 xbar_sfc4_in_ep: endpoint { 331 remote-endpoint = <&sfc4_cif_in_ep>; 332 }; 333 }; 334 335 port@27 { 336 reg = <0x27>; 337 338 xbar_sfc4_out_ep: endpoint { 339 remote-endpoint = <&sfc4_cif_out_ep>; 340 }; 341 }; 342 343 xbar_mvc1_in_port: port@28 { 344 reg = <0x28>; 345 346 xbar_mvc1_in_ep: endpoint { 347 remote-endpoint = <&mvc1_cif_in_ep>; 348 }; 349 }; 350 351 port@29 { 352 reg = <0x29>; 353 354 xbar_mvc1_out_ep: endpoint { 355 remote-endpoint = <&mvc1_cif_out_ep>; 356 }; 357 }; 358 359 xbar_mvc2_in_port: port@2a { 360 reg = <0x2a>; 361 362 xbar_mvc2_in_ep: endpoint { 363 remote-endpoint = <&mvc2_cif_in_ep>; 364 }; 365 }; 366 367 port@2b { 368 reg = <0x2b>; 369 370 xbar_mvc2_out_ep: endpoint { 371 remote-endpoint = <&mvc2_cif_out_ep>; 372 }; 373 }; 374 375 xbar_amx1_in1_port: port@2c { 376 reg = <0x2c>; 377 378 xbar_amx1_in1_ep: endpoint { 379 remote-endpoint = <&amx1_in1_ep>; 380 }; 381 }; 382 383 xbar_amx1_in2_port: port@2d { 384 reg = <0x2d>; 385 386 xbar_amx1_in2_ep: endpoint { 387 remote-endpoint = <&amx1_in2_ep>; 388 }; 389 }; 390 391 xbar_amx1_in3_port: port@2e { 392 reg = <0x2e>; 393 394 xbar_amx1_in3_ep: endpoint { 395 remote-endpoint = <&amx1_in3_ep>; 396 }; 397 }; 398 399 xbar_amx1_in4_port: port@2f { 400 reg = <0x2f>; 401 402 xbar_amx1_in4_ep: endpoint { 403 remote-endpoint = <&amx1_in4_ep>; 404 }; 405 }; 406 407 port@30 { 408 reg = <0x30>; 409 410 xbar_amx1_out_ep: endpoint { 411 remote-endpoint = <&amx1_out_ep>; 412 }; 413 }; 414 415 xbar_amx2_in1_port: port@31 { 416 reg = <0x31>; 417 418 xbar_amx2_in1_ep: endpoint { 419 remote-endpoint = <&amx2_in1_ep>; 420 }; 421 }; 422 423 xbar_amx2_in2_port: port@32 { 424 reg = <0x32>; 425 426 xbar_amx2_in2_ep: endpoint { 427 remote-endpoint = <&amx2_in2_ep>; 428 }; 429 }; 430 431 xbar_amx2_in3_port: port@33 { 432 reg = <0x33>; 433 434 xbar_amx2_in3_ep: endpoint { 435 remote-endpoint = <&amx2_in3_ep>; 436 }; 437 }; 438 439 xbar_amx2_in4_port: port@34 { 440 reg = <0x34>; 441 442 xbar_amx2_in4_ep: endpoint { 443 remote-endpoint = <&amx2_in4_ep>; 444 }; 445 }; 446 447 port@35 { 448 reg = <0x35>; 449 450 xbar_amx2_out_ep: endpoint { 451 remote-endpoint = <&amx2_out_ep>; 452 }; 453 }; 454 455 xbar_amx3_in1_port: port@36 { 456 reg = <0x36>; 457 458 xbar_amx3_in1_ep: endpoint { 459 remote-endpoint = <&amx3_in1_ep>; 460 }; 461 }; 462 463 xbar_amx3_in2_port: port@37 { 464 reg = <0x37>; 465 466 xbar_amx3_in2_ep: endpoint { 467 remote-endpoint = <&amx3_in2_ep>; 468 }; 469 }; 470 471 xbar_amx3_in3_port: port@38 { 472 reg = <0x38>; 473 474 xbar_amx3_in3_ep: endpoint { 475 remote-endpoint = <&amx3_in3_ep>; 476 }; 477 }; 478 479 xbar_amx3_in4_port: port@39 { 480 reg = <0x39>; 481 482 xbar_amx3_in4_ep: endpoint { 483 remote-endpoint = <&amx3_in4_ep>; 484 }; 485 }; 486 487 port@3a { 488 reg = <0x3a>; 489 490 xbar_amx3_out_ep: endpoint { 491 remote-endpoint = <&amx3_out_ep>; 492 }; 493 }; 494 495 xbar_amx4_in1_port: port@3b { 496 reg = <0x3b>; 497 498 xbar_amx4_in1_ep: endpoint { 499 remote-endpoint = <&amx4_in1_ep>; 500 }; 501 }; 502 503 xbar_amx4_in2_port: port@3c { 504 reg = <0x3c>; 505 506 xbar_amx4_in2_ep: endpoint { 507 remote-endpoint = <&amx4_in2_ep>; 508 }; 509 }; 510 511 xbar_amx4_in3_port: port@3d { 512 reg = <0x3d>; 513 514 xbar_amx4_in3_ep: endpoint { 515 remote-endpoint = <&amx4_in3_ep>; 516 }; 517 }; 518 519 xbar_amx4_in4_port: port@3e { 520 reg = <0x3e>; 521 522 xbar_amx4_in4_ep: endpoint { 523 remote-endpoint = <&amx4_in4_ep>; 524 }; 525 }; 526 527 port@3f { 528 reg = <0x3f>; 529 530 xbar_amx4_out_ep: endpoint { 531 remote-endpoint = <&amx4_out_ep>; 532 }; 533 }; 534 535 xbar_adx1_in_port: port@40 { 536 reg = <0x40>; 537 538 xbar_adx1_in_ep: endpoint { 539 remote-endpoint = <&adx1_in_ep>; 540 }; 541 }; 542 543 port@41 { 544 reg = <0x41>; 545 546 xbar_adx1_out1_ep: endpoint { 547 remote-endpoint = <&adx1_out1_ep>; 548 }; 549 }; 550 551 port@42 { 552 reg = <0x42>; 553 554 xbar_adx1_out2_ep: endpoint { 555 remote-endpoint = <&adx1_out2_ep>; 556 }; 557 }; 558 559 port@43 { 560 reg = <0x43>; 561 562 xbar_adx1_out3_ep: endpoint { 563 remote-endpoint = <&adx1_out3_ep>; 564 }; 565 }; 566 567 port@44 { 568 reg = <0x44>; 569 570 xbar_adx1_out4_ep: endpoint { 571 remote-endpoint = <&adx1_out4_ep>; 572 }; 573 }; 574 575 xbar_adx2_in_port: port@45 { 576 reg = <0x45>; 577 578 xbar_adx2_in_ep: endpoint { 579 remote-endpoint = <&adx2_in_ep>; 580 }; 581 }; 582 583 port@46 { 584 reg = <0x46>; 585 586 xbar_adx2_out1_ep: endpoint { 587 remote-endpoint = <&adx2_out1_ep>; 588 }; 589 }; 590 591 port@47 { 592 reg = <0x47>; 593 594 xbar_adx2_out2_ep: endpoint { 595 remote-endpoint = <&adx2_out2_ep>; 596 }; 597 }; 598 599 port@48 { 600 reg = <0x48>; 601 602 xbar_adx2_out3_ep: endpoint { 603 remote-endpoint = <&adx2_out3_ep>; 604 }; 605 }; 606 607 port@49 { 608 reg = <0x49>; 609 610 xbar_adx2_out4_ep: endpoint { 611 remote-endpoint = <&adx2_out4_ep>; 612 }; 613 }; 614 615 xbar_adx3_in_port: port@4a { 616 reg = <0x4a>; 617 618 xbar_adx3_in_ep: endpoint { 619 remote-endpoint = <&adx3_in_ep>; 620 }; 621 }; 622 623 port@4b { 624 reg = <0x4b>; 625 626 xbar_adx3_out1_ep: endpoint { 627 remote-endpoint = <&adx3_out1_ep>; 628 }; 629 }; 630 631 port@4c { 632 reg = <0x4c>; 633 634 xbar_adx3_out2_ep: endpoint { 635 remote-endpoint = <&adx3_out2_ep>; 636 }; 637 }; 638 639 port@4d { 640 reg = <0x4d>; 641 642 xbar_adx3_out3_ep: endpoint { 643 remote-endpoint = <&adx3_out3_ep>; 644 }; 645 }; 646 647 port@4e { 648 reg = <0x4e>; 649 650 xbar_adx3_out4_ep: endpoint { 651 remote-endpoint = <&adx3_out4_ep>; 652 }; 653 }; 654 655 xbar_adx4_in_port: port@4f { 656 reg = <0x4f>; 657 658 xbar_adx4_in_ep: endpoint { 659 remote-endpoint = <&adx4_in_ep>; 660 }; 661 }; 662 663 port@50 { 664 reg = <0x50>; 665 666 xbar_adx4_out1_ep: endpoint { 667 remote-endpoint = <&adx4_out1_ep>; 668 }; 669 }; 670 671 port@51 { 672 reg = <0x51>; 673 674 xbar_adx4_out2_ep: endpoint { 675 remote-endpoint = <&adx4_out2_ep>; 676 }; 677 }; 678 679 port@52 { 680 reg = <0x52>; 681 682 xbar_adx4_out3_ep: endpoint { 683 remote-endpoint = <&adx4_out3_ep>; 684 }; 685 }; 686 687 port@53 { 688 reg = <0x53>; 689 690 xbar_adx4_out4_ep: endpoint { 691 remote-endpoint = <&adx4_out4_ep>; 692 }; 693 }; 694 695 xbar_mixer_in1_port: port@54 { 696 reg = <0x54>; 697 698 xbar_mixer_in1_ep: endpoint { 699 remote-endpoint = <&mixer_in1_ep>; 700 }; 701 }; 702 703 xbar_mixer_in2_port: port@55 { 704 reg = <0x55>; 705 706 xbar_mixer_in2_ep: endpoint { 707 remote-endpoint = <&mixer_in2_ep>; 708 }; 709 }; 710 711 xbar_mixer_in3_port: port@56 { 712 reg = <0x56>; 713 714 xbar_mixer_in3_ep: endpoint { 715 remote-endpoint = <&mixer_in3_ep>; 716 }; 717 }; 718 719 xbar_mixer_in4_port: port@57 { 720 reg = <0x57>; 721 722 xbar_mixer_in4_ep: endpoint { 723 remote-endpoint = <&mixer_in4_ep>; 724 }; 725 }; 726 727 xbar_mixer_in5_port: port@58 { 728 reg = <0x58>; 729 730 xbar_mixer_in5_ep: endpoint { 731 remote-endpoint = <&mixer_in5_ep>; 732 }; 733 }; 734 735 xbar_mixer_in6_port: port@59 { 736 reg = <0x59>; 737 738 xbar_mixer_in6_ep: endpoint { 739 remote-endpoint = <&mixer_in6_ep>; 740 }; 741 }; 742 743 xbar_mixer_in7_port: port@5a { 744 reg = <0x5a>; 745 746 xbar_mixer_in7_ep: endpoint { 747 remote-endpoint = <&mixer_in7_ep>; 748 }; 749 }; 750 751 xbar_mixer_in8_port: port@5b { 752 reg = <0x5b>; 753 754 xbar_mixer_in8_ep: endpoint { 755 remote-endpoint = <&mixer_in8_ep>; 756 }; 757 }; 758 759 xbar_mixer_in9_port: port@5c { 760 reg = <0x5c>; 761 762 xbar_mixer_in9_ep: endpoint { 763 remote-endpoint = <&mixer_in9_ep>; 764 }; 765 }; 766 767 xbar_mixer_in10_port: port@5d { 768 reg = <0x5d>; 769 770 xbar_mixer_in10_ep: endpoint { 771 remote-endpoint = <&mixer_in10_ep>; 772 }; 773 }; 774 775 port@5e { 776 reg = <0x5e>; 777 778 xbar_mixer_out1_ep: endpoint { 779 remote-endpoint = <&mixer_out1_ep>; 780 }; 781 }; 782 783 port@5f { 784 reg = <0x5f>; 785 786 xbar_mixer_out2_ep: endpoint { 787 remote-endpoint = <&mixer_out2_ep>; 788 }; 789 }; 790 791 port@60 { 792 reg = <0x60>; 793 794 xbar_mixer_out3_ep: endpoint { 795 remote-endpoint = <&mixer_out3_ep>; 796 }; 797 }; 798 799 port@61 { 800 reg = <0x61>; 801 802 xbar_mixer_out4_ep: endpoint { 803 remote-endpoint = <&mixer_out4_ep>; 804 }; 805 }; 806 807 port@62 { 808 reg = <0x62>; 809 810 xbar_mixer_out5_ep: endpoint { 811 remote-endpoint = <&mixer_out5_ep>; 812 }; 813 }; 814 815 xbar_asrc_in1_port: port@63 { 816 reg = <0x63>; 817 818 xbar_asrc_in1_ep: endpoint { 819 remote-endpoint = <&asrc_in1_ep>; 820 }; 821 }; 822 823 port@64 { 824 reg = <0x64>; 825 826 xbar_asrc_out1_ep: endpoint { 827 remote-endpoint = <&asrc_out1_ep>; 828 }; 829 }; 830 831 xbar_asrc_in2_port: port@65 { 832 reg = <0x65>; 833 834 xbar_asrc_in2_ep: endpoint { 835 remote-endpoint = <&asrc_in2_ep>; 836 }; 837 }; 838 839 port@66 { 840 reg = <0x66>; 841 842 xbar_asrc_out2_ep: endpoint { 843 remote-endpoint = <&asrc_out2_ep>; 844 }; 845 }; 846 847 xbar_asrc_in3_port: port@67 { 848 reg = <0x67>; 849 850 xbar_asrc_in3_ep: endpoint { 851 remote-endpoint = <&asrc_in3_ep>; 852 }; 853 }; 854 855 port@68 { 856 reg = <0x68>; 857 858 xbar_asrc_out3_ep: endpoint { 859 remote-endpoint = <&asrc_out3_ep>; 860 }; 861 }; 862 863 xbar_asrc_in4_port: port@69 { 864 reg = <0x69>; 865 866 xbar_asrc_in4_ep: endpoint { 867 remote-endpoint = <&asrc_in4_ep>; 868 }; 869 }; 870 871 port@6a { 872 reg = <0x6a>; 873 874 xbar_asrc_out4_ep: endpoint { 875 remote-endpoint = <&asrc_out4_ep>; 876 }; 877 }; 878 879 xbar_asrc_in5_port: port@6b { 880 reg = <0x6b>; 881 882 xbar_asrc_in5_ep: endpoint { 883 remote-endpoint = <&asrc_in5_ep>; 884 }; 885 }; 886 887 port@6c { 888 reg = <0x6c>; 889 890 xbar_asrc_out5_ep: endpoint { 891 remote-endpoint = <&asrc_out5_ep>; 892 }; 893 }; 894 895 xbar_asrc_in6_port: port@6d { 896 reg = <0x6d>; 897 898 xbar_asrc_in6_ep: endpoint { 899 remote-endpoint = <&asrc_in6_ep>; 900 }; 901 }; 902 903 port@6e { 904 reg = <0x6e>; 905 906 xbar_asrc_out6_ep: endpoint { 907 remote-endpoint = <&asrc_out6_ep>; 908 }; 909 }; 910 911 xbar_asrc_in7_port: port@6f { 912 reg = <0x6f>; 913 914 xbar_asrc_in7_ep: endpoint { 915 remote-endpoint = <&asrc_in7_ep>; 916 }; 917 }; 918 }; 919 920 admaif@290f000 { 921 status = "okay"; 922 923 ports { 924 #address-cells = <1>; 925 #size-cells = <0>; 926 927 admaif0_port: port@0 { 928 reg = <0x0>; 929 930 admaif0_ep: endpoint { 931 remote-endpoint = <&xbar_admaif0_ep>; 932 }; 933 }; 934 935 admaif1_port: port@1 { 936 reg = <0x1>; 937 938 admaif1_ep: endpoint { 939 remote-endpoint = <&xbar_admaif1_ep>; 940 }; 941 }; 942 943 admaif2_port: port@2 { 944 reg = <0x2>; 945 946 admaif2_ep: endpoint { 947 remote-endpoint = <&xbar_admaif2_ep>; 948 }; 949 }; 950 951 admaif3_port: port@3 { 952 reg = <0x3>; 953 954 admaif3_ep: endpoint { 955 remote-endpoint = <&xbar_admaif3_ep>; 956 }; 957 }; 958 959 admaif4_port: port@4 { 960 reg = <0x4>; 961 962 admaif4_ep: endpoint { 963 remote-endpoint = <&xbar_admaif4_ep>; 964 }; 965 }; 966 967 admaif5_port: port@5 { 968 reg = <0x5>; 969 970 admaif5_ep: endpoint { 971 remote-endpoint = <&xbar_admaif5_ep>; 972 }; 973 }; 974 975 admaif6_port: port@6 { 976 reg = <0x6>; 977 978 admaif6_ep: endpoint { 979 remote-endpoint = <&xbar_admaif6_ep>; 980 }; 981 }; 982 983 admaif7_port: port@7 { 984 reg = <0x7>; 985 986 admaif7_ep: endpoint { 987 remote-endpoint = <&xbar_admaif7_ep>; 988 }; 989 }; 990 991 admaif8_port: port@8 { 992 reg = <0x8>; 993 994 admaif8_ep: endpoint { 995 remote-endpoint = <&xbar_admaif8_ep>; 996 }; 997 }; 998 999 admaif9_port: port@9 { 1000 reg = <0x9>; 1001 1002 admaif9_ep: endpoint { 1003 remote-endpoint = <&xbar_admaif9_ep>; 1004 }; 1005 }; 1006 1007 admaif10_port: port@a { 1008 reg = <0xa>; 1009 1010 admaif10_ep: endpoint { 1011 remote-endpoint = <&xbar_admaif10_ep>; 1012 }; 1013 }; 1014 1015 admaif11_port: port@b { 1016 reg = <0xb>; 1017 1018 admaif11_ep: endpoint { 1019 remote-endpoint = <&xbar_admaif11_ep>; 1020 }; 1021 }; 1022 1023 admaif12_port: port@c { 1024 reg = <0xc>; 1025 1026 admaif12_ep: endpoint { 1027 remote-endpoint = <&xbar_admaif12_ep>; 1028 }; 1029 }; 1030 1031 admaif13_port: port@d { 1032 reg = <0xd>; 1033 1034 admaif13_ep: endpoint { 1035 remote-endpoint = <&xbar_admaif13_ep>; 1036 }; 1037 }; 1038 1039 admaif14_port: port@e { 1040 reg = <0xe>; 1041 1042 admaif14_ep: endpoint { 1043 remote-endpoint = <&xbar_admaif14_ep>; 1044 }; 1045 }; 1046 1047 admaif15_port: port@f { 1048 reg = <0xf>; 1049 1050 admaif15_ep: endpoint { 1051 remote-endpoint = <&xbar_admaif15_ep>; 1052 }; 1053 }; 1054 1055 admaif16_port: port@10 { 1056 reg = <0x10>; 1057 1058 admaif16_ep: endpoint { 1059 remote-endpoint = <&xbar_admaif16_ep>; 1060 }; 1061 }; 1062 1063 admaif17_port: port@11 { 1064 reg = <0x11>; 1065 1066 admaif17_ep: endpoint { 1067 remote-endpoint = <&xbar_admaif17_ep>; 1068 }; 1069 }; 1070 1071 admaif18_port: port@12 { 1072 reg = <0x12>; 1073 1074 admaif18_ep: endpoint { 1075 remote-endpoint = <&xbar_admaif18_ep>; 1076 }; 1077 }; 1078 1079 admaif19_port: port@13 { 1080 reg = <0x13>; 1081 1082 admaif19_ep: endpoint { 1083 remote-endpoint = <&xbar_admaif19_ep>; 1084 }; 1085 }; 1086 }; 1087 }; 1088 1089 i2s@2901000 { 1090 status = "okay"; 1091 1092 ports { 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 1096 port@0 { 1097 reg = <0>; 1098 1099 i2s1_cif_ep: endpoint { 1100 remote-endpoint = <&xbar_i2s1_ep>; 1101 }; 1102 }; 1103 1104 i2s1_port: port@1 { 1105 reg = <1>; 1106 1107 i2s1_dap_ep: endpoint { 1108 dai-format = "i2s"; 1109 /* Placeholder for external Codec */ 1110 }; 1111 }; 1112 }; 1113 }; 1114 1115 i2s@2901100 { 1116 status = "okay"; 1117 1118 ports { 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 1122 port@0 { 1123 reg = <0>; 1124 1125 i2s2_cif_ep: endpoint { 1126 remote-endpoint = <&xbar_i2s2_ep>; 1127 }; 1128 }; 1129 1130 i2s2_port: port@1 { 1131 reg = <1>; 1132 1133 i2s2_dap_ep: endpoint { 1134 dai-format = "i2s"; 1135 /* Placeholder for external Codec */ 1136 }; 1137 }; 1138 }; 1139 }; 1140 1141 i2s@2901200 { 1142 status = "okay"; 1143 1144 ports { 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 1148 port@0 { 1149 reg = <0>; 1150 1151 i2s3_cif_ep: endpoint { 1152 remote-endpoint = <&xbar_i2s3_ep>; 1153 }; 1154 }; 1155 1156 i2s3_port: port@1 { 1157 reg = <1>; 1158 1159 i2s3_dap_ep: endpoint { 1160 dai-format = "i2s"; 1161 /* Placeholder for external Codec */ 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 i2s@2901300 { 1168 status = "okay"; 1169 1170 ports { 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 1174 port@0 { 1175 reg = <0>; 1176 1177 i2s4_cif_ep: endpoint { 1178 remote-endpoint = <&xbar_i2s4_ep>; 1179 }; 1180 }; 1181 1182 i2s4_port: port@1 { 1183 reg = <1>; 1184 1185 i2s4_dap_ep: endpoint { 1186 dai-format = "i2s"; 1187 /* Placeholder for external Codec */ 1188 }; 1189 }; 1190 }; 1191 }; 1192 1193 i2s@2901400 { 1194 status = "okay"; 1195 1196 ports { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 1200 port@0 { 1201 reg = <0>; 1202 1203 i2s5_cif_ep: endpoint { 1204 remote-endpoint = <&xbar_i2s5_ep>; 1205 }; 1206 }; 1207 1208 i2s5_port: port@1 { 1209 reg = <1>; 1210 1211 i2s5_dap_ep: endpoint { 1212 dai-format = "i2s"; 1213 /* Placeholder for external Codec */ 1214 }; 1215 }; 1216 }; 1217 }; 1218 1219 i2s@2901500 { 1220 status = "okay"; 1221 1222 ports { 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 1226 port@0 { 1227 reg = <0>; 1228 1229 i2s6_cif_ep: endpoint { 1230 remote-endpoint = <&xbar_i2s6_ep>; 1231 }; 1232 }; 1233 1234 i2s6_port: port@1 { 1235 reg = <1>; 1236 1237 i2s6_dap_ep: endpoint { 1238 dai-format = "i2s"; 1239 /* Placeholder for external Codec */ 1240 }; 1241 }; 1242 }; 1243 }; 1244 1245 dmic@2904000 { 1246 status = "okay"; 1247 1248 ports { 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 1252 port@0 { 1253 reg = <0>; 1254 1255 dmic1_cif_ep: endpoint { 1256 remote-endpoint = <&xbar_dmic1_ep>; 1257 }; 1258 }; 1259 1260 dmic1_port: port@1 { 1261 reg = <1>; 1262 1263 dmic1_dap_ep: endpoint { 1264 /* Place holder for external Codec */ 1265 }; 1266 }; 1267 }; 1268 }; 1269 1270 dmic@2904100 { 1271 status = "okay"; 1272 1273 ports { 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 1277 port@0 { 1278 reg = <0>; 1279 1280 dmic2_cif_ep: endpoint { 1281 remote-endpoint = <&xbar_dmic2_ep>; 1282 }; 1283 }; 1284 1285 dmic2_port: port@1 { 1286 reg = <1>; 1287 1288 dmic2_dap_ep: endpoint { 1289 /* Place holder for external Codec */ 1290 }; 1291 }; 1292 }; 1293 }; 1294 1295 dmic@2904200 { 1296 status = "okay"; 1297 1298 ports { 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 1302 port@0 { 1303 reg = <0>; 1304 1305 dmic3_cif_ep: endpoint { 1306 remote-endpoint = <&xbar_dmic3_ep>; 1307 }; 1308 }; 1309 1310 dmic3_port: port@1 { 1311 reg = <1>; 1312 1313 dmic3_dap_ep: endpoint { 1314 /* Place holder for external Codec */ 1315 }; 1316 }; 1317 }; 1318 }; 1319 1320 dspk@2905000 { 1321 status = "okay"; 1322 1323 ports { 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 1327 port@0 { 1328 reg = <0>; 1329 1330 dspk1_cif_ep: endpoint { 1331 remote-endpoint = <&xbar_dspk1_ep>; 1332 }; 1333 }; 1334 1335 dspk1_port: port@1 { 1336 reg = <1>; 1337 1338 dspk1_dap_ep: endpoint { 1339 /* Place holder for external Codec */ 1340 }; 1341 }; 1342 }; 1343 }; 1344 1345 dspk@2905100 { 1346 status = "okay"; 1347 1348 ports { 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 1352 port@0 { 1353 reg = <0>; 1354 1355 dspk2_cif_ep: endpoint { 1356 remote-endpoint = <&xbar_dspk2_ep>; 1357 }; 1358 }; 1359 1360 dspk2_port: port@1 { 1361 reg = <1>; 1362 1363 dspk2_dap_ep: endpoint { 1364 /* Place holder for external Codec */ 1365 }; 1366 }; 1367 }; 1368 }; 1369 1370 sfc@2902000 { 1371 status = "okay"; 1372 1373 ports { 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 1377 port@0 { 1378 reg = <0>; 1379 1380 sfc1_cif_in_ep: endpoint { 1381 remote-endpoint = <&xbar_sfc1_in_ep>; 1382 convert-rate = <44100>; 1383 }; 1384 }; 1385 1386 sfc1_out_port: port@1 { 1387 reg = <1>; 1388 1389 sfc1_cif_out_ep: endpoint { 1390 remote-endpoint = <&xbar_sfc1_out_ep>; 1391 convert-rate = <48000>; 1392 }; 1393 }; 1394 }; 1395 }; 1396 1397 sfc@2902200 { 1398 status = "okay"; 1399 1400 ports { 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 1404 port@0 { 1405 reg = <0>; 1406 1407 sfc2_cif_in_ep: endpoint { 1408 remote-endpoint = <&xbar_sfc2_in_ep>; 1409 }; 1410 }; 1411 1412 sfc2_out_port: port@1 { 1413 reg = <1>; 1414 1415 sfc2_cif_out_ep: endpoint { 1416 remote-endpoint = <&xbar_sfc2_out_ep>; 1417 }; 1418 }; 1419 }; 1420 }; 1421 1422 sfc@2902400 { 1423 status = "okay"; 1424 1425 ports { 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 1429 port@0 { 1430 reg = <0>; 1431 1432 sfc3_cif_in_ep: endpoint { 1433 remote-endpoint = <&xbar_sfc3_in_ep>; 1434 }; 1435 }; 1436 1437 sfc3_out_port: port@1 { 1438 reg = <1>; 1439 1440 sfc3_cif_out_ep: endpoint { 1441 remote-endpoint = <&xbar_sfc3_out_ep>; 1442 }; 1443 }; 1444 }; 1445 }; 1446 1447 sfc@2902600 { 1448 status = "okay"; 1449 1450 ports { 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 1454 port@0 { 1455 reg = <0>; 1456 1457 sfc4_cif_in_ep: endpoint { 1458 remote-endpoint = <&xbar_sfc4_in_ep>; 1459 }; 1460 }; 1461 1462 sfc4_out_port: port@1 { 1463 reg = <1>; 1464 1465 sfc4_cif_out_ep: endpoint { 1466 remote-endpoint = <&xbar_sfc4_out_ep>; 1467 }; 1468 }; 1469 }; 1470 }; 1471 1472 mvc@290a000 { 1473 status = "okay"; 1474 1475 ports { 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 1479 port@0 { 1480 reg = <0>; 1481 1482 mvc1_cif_in_ep: endpoint { 1483 remote-endpoint = <&xbar_mvc1_in_ep>; 1484 }; 1485 }; 1486 1487 mvc1_out_port: port@1 { 1488 reg = <1>; 1489 1490 mvc1_cif_out_ep: endpoint { 1491 remote-endpoint = <&xbar_mvc1_out_ep>; 1492 }; 1493 }; 1494 }; 1495 }; 1496 1497 mvc@290a200 { 1498 status = "okay"; 1499 1500 ports { 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 1504 port@0 { 1505 reg = <0>; 1506 1507 mvc2_cif_in_ep: endpoint { 1508 remote-endpoint = <&xbar_mvc2_in_ep>; 1509 }; 1510 }; 1511 1512 mvc2_out_port: port@1 { 1513 reg = <1>; 1514 1515 mvc2_cif_out_ep: endpoint { 1516 remote-endpoint = <&xbar_mvc2_out_ep>; 1517 }; 1518 }; 1519 }; 1520 }; 1521 1522 amx@2903000 { 1523 status = "okay"; 1524 1525 ports { 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 1529 port@0 { 1530 reg = <0>; 1531 1532 amx1_in1_ep: endpoint { 1533 remote-endpoint = <&xbar_amx1_in1_ep>; 1534 }; 1535 }; 1536 1537 port@1 { 1538 reg = <1>; 1539 1540 amx1_in2_ep: endpoint { 1541 remote-endpoint = <&xbar_amx1_in2_ep>; 1542 }; 1543 }; 1544 1545 port@2 { 1546 reg = <2>; 1547 1548 amx1_in3_ep: endpoint { 1549 remote-endpoint = <&xbar_amx1_in3_ep>; 1550 }; 1551 }; 1552 1553 port@3 { 1554 reg = <3>; 1555 1556 amx1_in4_ep: endpoint { 1557 remote-endpoint = <&xbar_amx1_in4_ep>; 1558 }; 1559 }; 1560 1561 amx1_out_port: port@4 { 1562 reg = <4>; 1563 1564 amx1_out_ep: endpoint { 1565 remote-endpoint = <&xbar_amx1_out_ep>; 1566 }; 1567 }; 1568 }; 1569 }; 1570 1571 amx@2903100 { 1572 status = "okay"; 1573 1574 ports { 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 1578 port@0 { 1579 reg = <0>; 1580 1581 amx2_in1_ep: endpoint { 1582 remote-endpoint = <&xbar_amx2_in1_ep>; 1583 }; 1584 }; 1585 1586 port@1 { 1587 reg = <1>; 1588 1589 amx2_in2_ep: endpoint { 1590 remote-endpoint = <&xbar_amx2_in2_ep>; 1591 }; 1592 }; 1593 1594 amx2_in3_port: port@2 { 1595 reg = <2>; 1596 1597 amx2_in3_ep: endpoint { 1598 remote-endpoint = <&xbar_amx2_in3_ep>; 1599 }; 1600 }; 1601 1602 amx2_in4_port: port@3 { 1603 reg = <3>; 1604 1605 amx2_in4_ep: endpoint { 1606 remote-endpoint = <&xbar_amx2_in4_ep>; 1607 }; 1608 }; 1609 1610 amx2_out_port: port@4 { 1611 reg = <4>; 1612 1613 amx2_out_ep: endpoint { 1614 remote-endpoint = <&xbar_amx2_out_ep>; 1615 }; 1616 }; 1617 }; 1618 }; 1619 1620 amx@2903200 { 1621 status = "okay"; 1622 1623 ports { 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 1627 port@0 { 1628 reg = <0>; 1629 1630 amx3_in1_ep: endpoint { 1631 remote-endpoint = <&xbar_amx3_in1_ep>; 1632 }; 1633 }; 1634 1635 port@1 { 1636 reg = <1>; 1637 1638 amx3_in2_ep: endpoint { 1639 remote-endpoint = <&xbar_amx3_in2_ep>; 1640 }; 1641 }; 1642 1643 port@2 { 1644 reg = <2>; 1645 1646 amx3_in3_ep: endpoint { 1647 remote-endpoint = <&xbar_amx3_in3_ep>; 1648 }; 1649 }; 1650 1651 port@3 { 1652 reg = <3>; 1653 1654 amx3_in4_ep: endpoint { 1655 remote-endpoint = <&xbar_amx3_in4_ep>; 1656 }; 1657 }; 1658 1659 amx3_out_port: port@4 { 1660 reg = <4>; 1661 1662 amx3_out_ep: endpoint { 1663 remote-endpoint = <&xbar_amx3_out_ep>; 1664 }; 1665 }; 1666 }; 1667 }; 1668 1669 amx@2903300 { 1670 status = "okay"; 1671 1672 ports { 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 1676 port@0 { 1677 reg = <0>; 1678 1679 amx4_in1_ep: endpoint { 1680 remote-endpoint = <&xbar_amx4_in1_ep>; 1681 }; 1682 }; 1683 1684 port@1 { 1685 reg = <1>; 1686 1687 amx4_in2_ep: endpoint { 1688 remote-endpoint = <&xbar_amx4_in2_ep>; 1689 }; 1690 }; 1691 1692 port@2 { 1693 reg = <2>; 1694 1695 amx4_in3_ep: endpoint { 1696 remote-endpoint = <&xbar_amx4_in3_ep>; 1697 }; 1698 }; 1699 1700 port@3 { 1701 reg = <3>; 1702 1703 amx4_in4_ep: endpoint { 1704 remote-endpoint = <&xbar_amx4_in4_ep>; 1705 }; 1706 }; 1707 1708 amx4_out_port: port@4 { 1709 reg = <4>; 1710 1711 amx4_out_ep: endpoint { 1712 remote-endpoint = <&xbar_amx4_out_ep>; 1713 }; 1714 }; 1715 }; 1716 }; 1717 1718 adx@2903800 { 1719 status = "okay"; 1720 1721 ports { 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 1725 port@0 { 1726 reg = <0>; 1727 1728 adx1_in_ep: endpoint { 1729 remote-endpoint = <&xbar_adx1_in_ep>; 1730 }; 1731 }; 1732 1733 adx1_out1_port: port@1 { 1734 reg = <1>; 1735 1736 adx1_out1_ep: endpoint { 1737 remote-endpoint = <&xbar_adx1_out1_ep>; 1738 }; 1739 }; 1740 1741 adx1_out2_port: port@2 { 1742 reg = <2>; 1743 1744 adx1_out2_ep: endpoint { 1745 remote-endpoint = <&xbar_adx1_out2_ep>; 1746 }; 1747 }; 1748 1749 adx1_out3_port: port@3 { 1750 reg = <3>; 1751 1752 adx1_out3_ep: endpoint { 1753 remote-endpoint = <&xbar_adx1_out3_ep>; 1754 }; 1755 }; 1756 1757 adx1_out4_port: port@4 { 1758 reg = <4>; 1759 1760 adx1_out4_ep: endpoint { 1761 remote-endpoint = <&xbar_adx1_out4_ep>; 1762 }; 1763 }; 1764 }; 1765 }; 1766 1767 adx@2903900 { 1768 status = "okay"; 1769 1770 ports { 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 1774 port@0 { 1775 reg = <0>; 1776 1777 adx2_in_ep: endpoint { 1778 remote-endpoint = <&xbar_adx2_in_ep>; 1779 }; 1780 }; 1781 1782 adx2_out1_port: port@1 { 1783 reg = <1>; 1784 1785 adx2_out1_ep: endpoint { 1786 remote-endpoint = <&xbar_adx2_out1_ep>; 1787 }; 1788 }; 1789 1790 adx2_out2_port: port@2 { 1791 reg = <2>; 1792 1793 adx2_out2_ep: endpoint { 1794 remote-endpoint = <&xbar_adx2_out2_ep>; 1795 }; 1796 }; 1797 1798 adx2_out3_port: port@3 { 1799 reg = <3>; 1800 1801 adx2_out3_ep: endpoint { 1802 remote-endpoint = <&xbar_adx2_out3_ep>; 1803 }; 1804 }; 1805 1806 adx2_out4_port: port@4 { 1807 reg = <4>; 1808 1809 adx2_out4_ep: endpoint { 1810 remote-endpoint = <&xbar_adx2_out4_ep>; 1811 }; 1812 }; 1813 }; 1814 }; 1815 1816 adx@2903a00 { 1817 status = "okay"; 1818 1819 ports { 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 1823 port@0 { 1824 reg = <0>; 1825 1826 adx3_in_ep: endpoint { 1827 remote-endpoint = <&xbar_adx3_in_ep>; 1828 }; 1829 }; 1830 1831 adx3_out1_port: port@1 { 1832 reg = <1>; 1833 1834 adx3_out1_ep: endpoint { 1835 remote-endpoint = <&xbar_adx3_out1_ep>; 1836 }; 1837 }; 1838 1839 adx3_out2_port: port@2 { 1840 reg = <2>; 1841 1842 adx3_out2_ep: endpoint { 1843 remote-endpoint = <&xbar_adx3_out2_ep>; 1844 }; 1845 }; 1846 1847 adx3_out3_port: port@3 { 1848 reg = <3>; 1849 1850 adx3_out3_ep: endpoint { 1851 remote-endpoint = <&xbar_adx3_out3_ep>; 1852 }; 1853 }; 1854 1855 adx3_out4_port: port@4 { 1856 reg = <4>; 1857 1858 adx3_out4_ep: endpoint { 1859 remote-endpoint = <&xbar_adx3_out4_ep>; 1860 }; 1861 }; 1862 }; 1863 }; 1864 1865 adx@2903b00 { 1866 status = "okay"; 1867 1868 ports { 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 1872 port@0 { 1873 reg = <0>; 1874 1875 adx4_in_ep: endpoint { 1876 remote-endpoint = <&xbar_adx4_in_ep>; 1877 }; 1878 }; 1879 1880 adx4_out1_port: port@1 { 1881 reg = <1>; 1882 1883 adx4_out1_ep: endpoint { 1884 remote-endpoint = <&xbar_adx4_out1_ep>; 1885 }; 1886 }; 1887 1888 adx4_out2_port: port@2 { 1889 reg = <2>; 1890 1891 adx4_out2_ep: endpoint { 1892 remote-endpoint = <&xbar_adx4_out2_ep>; 1893 }; 1894 }; 1895 1896 adx4_out3_port: port@3 { 1897 reg = <3>; 1898 1899 adx4_out3_ep: endpoint { 1900 remote-endpoint = <&xbar_adx4_out3_ep>; 1901 }; 1902 }; 1903 1904 adx4_out4_port: port@4 { 1905 reg = <4>; 1906 1907 adx4_out4_ep: endpoint { 1908 remote-endpoint = <&xbar_adx4_out4_ep>; 1909 }; 1910 }; 1911 }; 1912 }; 1913 1914 amixer@290bb00 { 1915 status = "okay"; 1916 1917 ports { 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 1921 port@0 { 1922 reg = <0x0>; 1923 1924 mixer_in1_ep: endpoint { 1925 remote-endpoint = <&xbar_mixer_in1_ep>; 1926 }; 1927 }; 1928 1929 port@1 { 1930 reg = <0x1>; 1931 1932 mixer_in2_ep: endpoint { 1933 remote-endpoint = <&xbar_mixer_in2_ep>; 1934 }; 1935 }; 1936 1937 port@2 { 1938 reg = <0x2>; 1939 1940 mixer_in3_ep: endpoint { 1941 remote-endpoint = <&xbar_mixer_in3_ep>; 1942 }; 1943 }; 1944 1945 port@3 { 1946 reg = <0x3>; 1947 1948 mixer_in4_ep: endpoint { 1949 remote-endpoint = <&xbar_mixer_in4_ep>; 1950 }; 1951 }; 1952 1953 port@4 { 1954 reg = <0x4>; 1955 1956 mixer_in5_ep: endpoint { 1957 remote-endpoint = <&xbar_mixer_in5_ep>; 1958 }; 1959 }; 1960 1961 port@5 { 1962 reg = <0x5>; 1963 1964 mixer_in6_ep: endpoint { 1965 remote-endpoint = <&xbar_mixer_in6_ep>; 1966 }; 1967 }; 1968 1969 port@6 { 1970 reg = <0x6>; 1971 1972 mixer_in7_ep: endpoint { 1973 remote-endpoint = <&xbar_mixer_in7_ep>; 1974 }; 1975 }; 1976 1977 port@7 { 1978 reg = <0x7>; 1979 1980 mixer_in8_ep: endpoint { 1981 remote-endpoint = <&xbar_mixer_in8_ep>; 1982 }; 1983 }; 1984 1985 port@8 { 1986 reg = <0x8>; 1987 1988 mixer_in9_ep: endpoint { 1989 remote-endpoint = <&xbar_mixer_in9_ep>; 1990 }; 1991 }; 1992 1993 port@9 { 1994 reg = <0x9>; 1995 1996 mixer_in10_ep: endpoint { 1997 remote-endpoint = <&xbar_mixer_in10_ep>; 1998 }; 1999 }; 2000 2001 mixer_out1_port: port@a { 2002 reg = <0xa>; 2003 2004 mixer_out1_ep: endpoint { 2005 remote-endpoint = <&xbar_mixer_out1_ep>; 2006 }; 2007 }; 2008 2009 mixer_out2_port: port@b { 2010 reg = <0xb>; 2011 2012 mixer_out2_ep: endpoint { 2013 remote-endpoint = <&xbar_mixer_out2_ep>; 2014 }; 2015 }; 2016 2017 mixer_out3_port: port@c { 2018 reg = <0xc>; 2019 2020 mixer_out3_ep: endpoint { 2021 remote-endpoint = <&xbar_mixer_out3_ep>; 2022 }; 2023 }; 2024 2025 mixer_out4_port: port@d { 2026 reg = <0xd>; 2027 2028 mixer_out4_ep: endpoint { 2029 remote-endpoint = <&xbar_mixer_out4_ep>; 2030 }; 2031 }; 2032 2033 mixer_out5_port: port@e { 2034 reg = <0xe>; 2035 2036 mixer_out5_ep: endpoint { 2037 remote-endpoint = <&xbar_mixer_out5_ep>; 2038 }; 2039 }; 2040 }; 2041 }; 2042 2043 asrc@2910000 { 2044 status = "okay"; 2045 2046 ports { 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 2050 port@0 { 2051 reg = <0x0>; 2052 2053 asrc_in1_ep: endpoint { 2054 remote-endpoint = <&xbar_asrc_in1_ep>; 2055 }; 2056 }; 2057 2058 port@1 { 2059 reg = <0x1>; 2060 2061 asrc_in2_ep: endpoint { 2062 remote-endpoint = <&xbar_asrc_in2_ep>; 2063 }; 2064 }; 2065 2066 port@2 { 2067 reg = <0x2>; 2068 2069 asrc_in3_ep: endpoint { 2070 remote-endpoint = <&xbar_asrc_in3_ep>; 2071 }; 2072 }; 2073 2074 port@3 { 2075 reg = <0x3>; 2076 2077 asrc_in4_ep: endpoint { 2078 remote-endpoint = <&xbar_asrc_in4_ep>; 2079 }; 2080 }; 2081 2082 port@4 { 2083 reg = <0x4>; 2084 2085 asrc_in5_ep: endpoint { 2086 remote-endpoint = <&xbar_asrc_in5_ep>; 2087 }; 2088 }; 2089 2090 port@5 { 2091 reg = <0x5>; 2092 2093 asrc_in6_ep: endpoint { 2094 remote-endpoint = <&xbar_asrc_in6_ep>; 2095 }; 2096 }; 2097 2098 port@6 { 2099 reg = <0x6>; 2100 2101 asrc_in7_ep: endpoint { 2102 remote-endpoint = <&xbar_asrc_in7_ep>; 2103 }; 2104 }; 2105 2106 asrc_out1_port: port@7 { 2107 reg = <0x7>; 2108 2109 asrc_out1_ep: endpoint { 2110 remote-endpoint = <&xbar_asrc_out1_ep>; 2111 }; 2112 }; 2113 2114 asrc_out2_port: port@8 { 2115 reg = <0x8>; 2116 2117 asrc_out2_ep: endpoint { 2118 remote-endpoint = <&xbar_asrc_out2_ep>; 2119 }; 2120 }; 2121 2122 asrc_out3_port: port@9 { 2123 reg = <0x9>; 2124 2125 asrc_out3_ep: endpoint { 2126 remote-endpoint = <&xbar_asrc_out3_ep>; 2127 }; 2128 }; 2129 2130 asrc_out4_port: port@a { 2131 reg = <0xa>; 2132 2133 asrc_out4_ep: endpoint { 2134 remote-endpoint = <&xbar_asrc_out4_ep>; 2135 }; 2136 }; 2137 2138 asrc_out5_port: port@b { 2139 reg = <0xb>; 2140 2141 asrc_out5_ep: endpoint { 2142 remote-endpoint = <&xbar_asrc_out5_ep>; 2143 }; 2144 }; 2145 2146 asrc_out6_port: port@c { 2147 reg = <0xc>; 2148 2149 asrc_out6_ep: endpoint { 2150 remote-endpoint = <&xbar_asrc_out6_ep>; 2151 }; 2152 }; 2153 }; 2154 }; 2155 }; 2156 }; 2157 2158 i2c@3160000 { 2159 power-monitor@42 { 2160 compatible = "ti,ina3221"; 2161 reg = <0x42>; 2162 #address-cells = <1>; 2163 #size-cells = <0>; 2164 2165 input@0 { 2166 reg = <0x0>; 2167 label = "VDD_MUX"; 2168 shunt-resistor-micro-ohms = <20000>; 2169 }; 2170 2171 input@1 { 2172 reg = <0x1>; 2173 label = "VDD_5V0_IO_SYS"; 2174 shunt-resistor-micro-ohms = <5000>; 2175 }; 2176 2177 input@2 { 2178 reg = <0x2>; 2179 label = "VDD_3V3_SYS"; 2180 shunt-resistor-micro-ohms = <10000>; 2181 }; 2182 }; 2183 2184 power-monitor@43 { 2185 compatible = "ti,ina3221"; 2186 reg = <0x43>; 2187 #address-cells = <1>; 2188 #size-cells = <0>; 2189 2190 input@0 { 2191 reg = <0x0>; 2192 label = "VDD_3V3_IO_SLP"; 2193 shunt-resistor-micro-ohms = <10000>; 2194 }; 2195 2196 input@1 { 2197 reg = <0x1>; 2198 label = "VDD_1V8_IO"; 2199 shunt-resistor-micro-ohms = <10000>; 2200 }; 2201 2202 input@2 { 2203 reg = <0x2>; 2204 label = "VDD_M2_IN"; 2205 shunt-resistor-micro-ohms = <10000>; 2206 }; 2207 }; 2208 2209 exp1: gpio@74 { 2210 compatible = "ti,tca9539"; 2211 reg = <0x74>; 2212 2213 interrupt-parent = <&gpio>; 2214 interrupts = <TEGRA186_MAIN_GPIO(Y, 0) 2215 GPIO_ACTIVE_LOW>; 2216 2217 #gpio-cells = <2>; 2218 gpio-controller; 2219 2220 vcc-supply = <&vdd_3v3_sys>; 2221 }; 2222 2223 exp2: gpio@77 { 2224 compatible = "ti,tca9539"; 2225 reg = <0x77>; 2226 2227 interrupt-parent = <&gpio>; 2228 interrupts = <TEGRA186_MAIN_GPIO(Y, 6) 2229 GPIO_ACTIVE_LOW>; 2230 2231 #gpio-cells = <2>; 2232 gpio-controller; 2233 2234 vcc-supply = <&vdd_1v8>; 2235 }; 2236 }; 2237 2238 /* SDMMC1 (SD/MMC) */ 2239 mmc@3400000 { 2240 status = "okay"; 2241 2242 vmmc-supply = <&vdd_sd>; 2243 }; 2244 2245 hda@3510000 { 2246 nvidia,model = "NVIDIA Jetson TX2 HDA"; 2247 status = "okay"; 2248 }; 2249 2250 padctl@3520000 { 2251 status = "okay"; 2252 2253 avdd-pll-erefeut-supply = <&vdd_1v8_pll>; 2254 avdd-usb-supply = <&vdd_3v3_sys>; 2255 vclamp-usb-supply = <&vdd_1v8>; 2256 vddio-hsic-supply = <&gnd>; 2257 2258 pads { 2259 usb2 { 2260 status = "okay"; 2261 2262 lanes { 2263 micro_b: usb2-0 { 2264 nvidia,function = "xusb"; 2265 status = "okay"; 2266 }; 2267 2268 usb2-1 { 2269 nvidia,function = "xusb"; 2270 status = "okay"; 2271 }; 2272 2273 usb2-2 { 2274 nvidia,function = "xusb"; 2275 status = "okay"; 2276 }; 2277 }; 2278 }; 2279 2280 usb3 { 2281 status = "okay"; 2282 2283 lanes { 2284 usb3-0 { 2285 nvidia,function = "xusb"; 2286 status = "okay"; 2287 }; 2288 2289 usb3-1 { 2290 nvidia,function = "xusb"; 2291 status = "okay"; 2292 }; 2293 2294 usb3-2 { 2295 nvidia,function = "xusb"; 2296 status = "okay"; 2297 }; 2298 }; 2299 }; 2300 }; 2301 2302 ports { 2303 usb2-0 { 2304 status = "okay"; 2305 mode = "otg"; 2306 vbus-supply = <&vdd_usb0>; 2307 usb-role-switch; 2308 2309 connector { 2310 compatible = "gpio-usb-b-connector", 2311 "usb-b-connector"; 2312 label = "micro-USB"; 2313 type = "micro"; 2314 vbus-gpios = <&gpio 2315 TEGRA186_MAIN_GPIO(X, 7) 2316 GPIO_ACTIVE_LOW>; 2317 id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; 2318 }; 2319 }; 2320 2321 usb2-1 { 2322 status = "okay"; 2323 mode = "host"; 2324 2325 vbus-supply = <&vdd_usb1>; 2326 }; 2327 2328 usb3-0 { 2329 nvidia,usb2-companion = <1>; 2330 vbus-supply = <&vdd_usb1>; 2331 status = "okay"; 2332 }; 2333 }; 2334 }; 2335 2336 usb@3530000 { 2337 status = "okay"; 2338 2339 phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, 2340 <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, 2341 <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>; 2342 phy-names = "usb2-0", "usb2-1", "usb3-0"; 2343 }; 2344 2345 usb@3550000 { 2346 status = "okay"; 2347 2348 phys = <µ_b>; 2349 phy-names = "usb2-0"; 2350 }; 2351 2352 i2c@c250000 { 2353 /* carrier board ID EEPROM */ 2354 eeprom@57 { 2355 compatible = "atmel,24c02"; 2356 reg = <0x57>; 2357 2358 label = "system"; 2359 vcc-supply = <&vdd_1v8>; 2360 address-width = <8>; 2361 pagesize = <8>; 2362 size = <256>; 2363 read-only; 2364 }; 2365 }; 2366 2367 pcie@10003000 { 2368 status = "okay"; 2369 2370 dvdd-pex-supply = <&vdd_pex>; 2371 hvdd-pex-pll-supply = <&vdd_1v8>; 2372 hvdd-pex-supply = <&vdd_1v8>; 2373 vddio-pexctl-aud-supply = <&vdd_1v8>; 2374 2375 pci@1,0 { 2376 nvidia,num-lanes = <4>; 2377 status = "okay"; 2378 }; 2379 2380 pci@2,0 { 2381 nvidia,num-lanes = <0>; 2382 status = "disabled"; 2383 }; 2384 2385 pci@3,0 { 2386 nvidia,num-lanes = <1>; 2387 status = "disabled"; 2388 }; 2389 }; 2390 2391 host1x@13e00000 { 2392 status = "okay"; 2393 2394 dpaux@15040000 { 2395 status = "okay"; 2396 }; 2397 2398 display-hub@15200000 { 2399 status = "okay"; 2400 }; 2401 2402 dsi@15300000 { 2403 status = "disabled"; 2404 }; 2405 2406 /* DP on E3320 */ 2407 sor@15540000 { 2408 status = "okay"; 2409 2410 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; 2411 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; 2412 2413 nvidia,dpaux = <&dpaux>; 2414 }; 2415 2416 sor@15580000 { 2417 status = "okay"; 2418 2419 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; 2420 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; 2421 hdmi-supply = <&vdd_hdmi>; 2422 2423 nvidia,ddc-i2c-bus = <&ddc>; 2424 nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) 2425 GPIO_ACTIVE_LOW>; 2426 }; 2427 2428 dpaux@155c0000 { 2429 status = "okay"; 2430 }; 2431 }; 2432 2433 sata@3507000 { 2434 status = "okay"; 2435 }; 2436 2437 gpio-keys { 2438 compatible = "gpio-keys"; 2439 2440 power { 2441 label = "Power"; 2442 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) 2443 GPIO_ACTIVE_LOW>; 2444 linux,input-type = <EV_KEY>; 2445 linux,code = <KEY_POWER>; 2446 debounce-interval = <10>; 2447 wakeup-event-action = <EV_ACT_ASSERTED>; 2448 wakeup-source; 2449 }; 2450 2451 volume-up { 2452 label = "Volume Up"; 2453 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) 2454 GPIO_ACTIVE_LOW>; 2455 linux,input-type = <EV_KEY>; 2456 linux,code = <KEY_VOLUMEUP>; 2457 debounce-interval = <10>; 2458 }; 2459 2460 volume-down { 2461 label = "Volume Down"; 2462 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) 2463 GPIO_ACTIVE_LOW>; 2464 linux,input-type = <EV_KEY>; 2465 linux,code = <KEY_VOLUMEDOWN>; 2466 debounce-interval = <10>; 2467 }; 2468 }; 2469 2470 vdd_sd: regulator-vdd-sd { 2471 compatible = "regulator-fixed"; 2472 regulator-name = "SD_CARD_SW_PWR"; 2473 regulator-min-microvolt = <3300000>; 2474 regulator-max-microvolt = <3300000>; 2475 2476 gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; 2477 enable-active-high; 2478 2479 vin-supply = <&vdd_3v3_sys>; 2480 }; 2481 2482 vdd_hdmi: regulator-vdd-hdmi { 2483 compatible = "regulator-fixed"; 2484 regulator-name = "VDD_HDMI_5V0"; 2485 regulator-min-microvolt = <5000000>; 2486 regulator-max-microvolt = <5000000>; 2487 2488 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; 2489 enable-active-high; 2490 2491 vin-supply = <&vdd_5v0_sys>; 2492 }; 2493 2494 vdd_usb0: regulator-vdd-usb0 { 2495 compatible = "regulator-fixed"; 2496 regulator-name = "VDD_USB0"; 2497 regulator-min-microvolt = <5000000>; 2498 regulator-max-microvolt = <5000000>; 2499 2500 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; 2501 enable-active-high; 2502 2503 vin-supply = <&vdd_5v0_sys>; 2504 }; 2505 2506 vdd_usb1: regulator-vdd-usb1 { 2507 compatible = "regulator-fixed"; 2508 regulator-name = "VDD_USB1"; 2509 regulator-min-microvolt = <5000000>; 2510 regulator-max-microvolt = <5000000>; 2511 2512 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; 2513 enable-active-high; 2514 2515 vin-supply = <&vdd_5v0_sys>; 2516 }; 2517 2518 sound { 2519 compatible = "nvidia,tegra186-audio-graph-card"; 2520 status = "okay"; 2521 2522 dais = /* FE */ 2523 <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 2524 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, 2525 <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, 2526 <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, 2527 <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, 2528 /* Router */ 2529 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, 2530 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>, 2531 <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>, 2532 <&xbar_dspk1_port>, <&xbar_dspk2_port>, 2533 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 2534 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 2535 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 2536 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 2537 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 2538 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 2539 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 2540 <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, 2541 <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, 2542 <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, 2543 <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, 2544 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 2545 <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, 2546 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 2547 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 2548 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 2549 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 2550 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 2551 <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, 2552 <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, 2553 <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, 2554 <&xbar_asrc_in7_port>, 2555 /* HW accelerators */ 2556 <&sfc1_out_port>, <&sfc2_out_port>, 2557 <&sfc3_out_port>, <&sfc4_out_port>, 2558 <&mvc1_out_port>, <&mvc2_out_port>, 2559 <&amx1_out_port>, <&amx2_out_port>, 2560 <&amx3_out_port>, <&amx4_out_port>, 2561 <&adx1_out1_port>, <&adx1_out2_port>, 2562 <&adx1_out3_port>, <&adx1_out4_port>, 2563 <&adx2_out1_port>, <&adx2_out2_port>, 2564 <&adx2_out3_port>, <&adx2_out4_port>, 2565 <&adx3_out1_port>, <&adx3_out2_port>, 2566 <&adx3_out3_port>, <&adx3_out4_port>, 2567 <&adx4_out1_port>, <&adx4_out2_port>, 2568 <&adx4_out3_port>, <&adx4_out4_port>, 2569 <&mixer_out1_port>, <&mixer_out2_port>, 2570 <&mixer_out3_port>, <&mixer_out4_port>, 2571 <&mixer_out5_port>, 2572 <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, 2573 <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, 2574 /* I/O */ 2575 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, 2576 <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, 2577 <&dmic3_port>, <&dspk1_port>, <&dspk2_port>; 2578 2579 label = "NVIDIA Jetson TX2 APE"; 2580 }; 2581}; 2582