1#include <dt-bindings/clock/tegra124-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra124-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/thermal/tegra124-soctherm.h> 8 9/ { 10 compatible = "nvidia,tegra132", "nvidia,tegra124"; 11 interrupt-parent = <&lic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 pcie@1003000 { 16 compatible = "nvidia,tegra124-pcie"; 17 device_type = "pci"; 18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 21 reg-names = "pads", "afi", "cs"; 22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24 interrupt-names = "intr", "msi"; 25 26 #interrupt-cells = <1>; 27 interrupt-map-mask = <0 0 0 0>; 28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 29 30 bus-range = <0x00 0xff>; 31 #address-cells = <3>; 32 #size-cells = <2>; 33 34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 39 40 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 41 <&tegra_car TEGRA124_CLK_AFI>, 42 <&tegra_car TEGRA124_CLK_PLL_E>, 43 <&tegra_car TEGRA124_CLK_CML0>; 44 clock-names = "pex", "afi", "pll_e", "cml"; 45 resets = <&tegra_car 70>, 46 <&tegra_car 72>, 47 <&tegra_car 74>; 48 reset-names = "pex", "afi", "pcie_x"; 49 status = "disabled"; 50 51 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 52 phy-names = "pcie"; 53 54 pci@1,0 { 55 device_type = "pci"; 56 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 57 reg = <0x000800 0 0 0 0>; 58 bus-range = <0x00 0xff>; 59 status = "disabled"; 60 61 #address-cells = <3>; 62 #size-cells = <2>; 63 ranges; 64 65 nvidia,num-lanes = <2>; 66 }; 67 68 pci@2,0 { 69 device_type = "pci"; 70 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 71 reg = <0x001000 0 0 0 0>; 72 bus-range = <0x00 0xff>; 73 status = "disabled"; 74 75 #address-cells = <3>; 76 #size-cells = <2>; 77 ranges; 78 79 nvidia,num-lanes = <1>; 80 }; 81 }; 82 83 host1x@50000000 { 84 compatible = "nvidia,tegra124-host1x", "simple-bus"; 85 reg = <0x0 0x50000000 0x0 0x00034000>; 86 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 87 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 88 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 89 clock-names = "host1x"; 90 resets = <&tegra_car 28>; 91 reset-names = "host1x"; 92 93 #address-cells = <2>; 94 #size-cells = <2>; 95 96 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 97 98 dc@54200000 { 99 compatible = "nvidia,tegra124-dc"; 100 reg = <0x0 0x54200000 0x0 0x00040000>; 101 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 103 <&tegra_car TEGRA124_CLK_PLL_P>; 104 clock-names = "dc", "parent"; 105 resets = <&tegra_car 27>; 106 reset-names = "dc"; 107 108 iommus = <&mc TEGRA_SWGROUP_DC>; 109 110 nvidia,head = <0>; 111 }; 112 113 dc@54240000 { 114 compatible = "nvidia,tegra124-dc"; 115 reg = <0x0 0x54240000 0x0 0x00040000>; 116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 118 <&tegra_car TEGRA124_CLK_PLL_P>; 119 clock-names = "dc", "parent"; 120 resets = <&tegra_car 26>; 121 reset-names = "dc"; 122 123 iommus = <&mc TEGRA_SWGROUP_DCB>; 124 125 nvidia,head = <1>; 126 }; 127 128 hdmi@54280000 { 129 compatible = "nvidia,tegra124-hdmi"; 130 reg = <0x0 0x54280000 0x0 0x00040000>; 131 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 133 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 134 clock-names = "hdmi", "parent"; 135 resets = <&tegra_car 51>; 136 reset-names = "hdmi"; 137 status = "disabled"; 138 }; 139 140 sor@54540000 { 141 compatible = "nvidia,tegra124-sor"; 142 reg = <0x0 0x54540000 0x0 0x00040000>; 143 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 146 <&tegra_car TEGRA124_CLK_PLL_DP>, 147 <&tegra_car TEGRA124_CLK_CLK_M>; 148 clock-names = "sor", "parent", "dp", "safe"; 149 resets = <&tegra_car 182>; 150 reset-names = "sor"; 151 status = "disabled"; 152 }; 153 154 dpaux: dpaux@545c0000 { 155 compatible = "nvidia,tegra124-dpaux"; 156 reg = <0x0 0x545c0000 0x0 0x00040000>; 157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 159 <&tegra_car TEGRA124_CLK_PLL_DP>; 160 clock-names = "dpaux", "parent"; 161 resets = <&tegra_car 181>; 162 reset-names = "dpaux"; 163 status = "disabled"; 164 }; 165 }; 166 167 gic: interrupt-controller@50041000 { 168 compatible = "arm,cortex-a15-gic"; 169 #interrupt-cells = <3>; 170 interrupt-controller; 171 reg = <0x0 0x50041000 0x0 0x1000>, 172 <0x0 0x50042000 0x0 0x2000>, 173 <0x0 0x50044000 0x0 0x2000>, 174 <0x0 0x50046000 0x0 0x2000>; 175 interrupts = <GIC_PPI 9 176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 177 interrupt-parent = <&gic>; 178 }; 179 180 gpu@57000000 { 181 compatible = "nvidia,gk20a"; 182 reg = <0x0 0x57000000 0x0 0x01000000>, 183 <0x0 0x58000000 0x0 0x01000000>; 184 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "stall", "nonstall"; 187 clocks = <&tegra_car TEGRA124_CLK_GPU>, 188 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 189 clock-names = "gpu", "pwr"; 190 resets = <&tegra_car 184>; 191 reset-names = "gpu"; 192 status = "disabled"; 193 }; 194 195 lic: interrupt-controller@60004000 { 196 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 197 reg = <0x0 0x60004000 0x0 0x100>, 198 <0x0 0x60004100 0x0 0x100>, 199 <0x0 0x60004200 0x0 0x100>, 200 <0x0 0x60004300 0x0 0x100>, 201 <0x0 0x60004400 0x0 0x100>; 202 interrupt-controller; 203 #interrupt-cells = <3>; 204 interrupt-parent = <&gic>; 205 }; 206 207 timer@60005000 { 208 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 209 reg = <0x0 0x60005000 0x0 0x400>; 210 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 217 clock-names = "timer"; 218 }; 219 220 tegra_car: clock@60006000 { 221 compatible = "nvidia,tegra132-car"; 222 reg = <0x0 0x60006000 0x0 0x1000>; 223 #clock-cells = <1>; 224 #reset-cells = <1>; 225 nvidia,external-memory-controller = <&emc>; 226 }; 227 228 flow-controller@60007000 { 229 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 230 reg = <0x0 0x60007000 0x0 0x1000>; 231 }; 232 233 actmon@6000c800 { 234 compatible = "nvidia,tegra124-actmon"; 235 reg = <0x0 0x6000c800 0x0 0x400>; 236 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 238 <&tegra_car TEGRA124_CLK_EMC>; 239 clock-names = "actmon", "emc"; 240 resets = <&tegra_car 119>; 241 reset-names = "actmon"; 242 }; 243 244 gpio: gpio@6000d000 { 245 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 246 reg = <0x0 0x6000d000 0x0 0x1000>; 247 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 255 #gpio-cells = <2>; 256 gpio-controller; 257 #interrupt-cells = <2>; 258 interrupt-controller; 259 }; 260 261 apbdma: dma@60020000 { 262 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 263 reg = <0x0 0x60020000 0x0 0x1400>; 264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 297 clock-names = "dma"; 298 resets = <&tegra_car 34>; 299 reset-names = "dma"; 300 #dma-cells = <1>; 301 }; 302 303 apbmisc@70000800 { 304 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 305 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 306 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 307 }; 308 309 pinmux: pinmux@70000868 { 310 compatible = "nvidia,tegra124-pinmux"; 311 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 312 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 313 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 314 }; 315 316 /* 317 * There are two serial driver i.e. 8250 based simple serial 318 * driver and APB DMA based serial driver for higher baudrate 319 * and performance. To enable the 8250 based driver, the compatible 320 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 321 * the APB DMA based serial driver, the compatible is 322 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 323 */ 324 uarta: serial@70006000 { 325 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 326 reg = <0x0 0x70006000 0x0 0x40>; 327 reg-shift = <2>; 328 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 330 clock-names = "serial"; 331 resets = <&tegra_car 6>; 332 reset-names = "serial"; 333 dmas = <&apbdma 8>, <&apbdma 8>; 334 dma-names = "rx", "tx"; 335 status = "disabled"; 336 }; 337 338 uartb: serial@70006040 { 339 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 340 reg = <0x0 0x70006040 0x0 0x40>; 341 reg-shift = <2>; 342 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 344 clock-names = "serial"; 345 resets = <&tegra_car 7>; 346 reset-names = "serial"; 347 dmas = <&apbdma 9>, <&apbdma 9>; 348 dma-names = "rx", "tx"; 349 status = "disabled"; 350 }; 351 352 uartc: serial@70006200 { 353 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 354 reg = <0x0 0x70006200 0x0 0x40>; 355 reg-shift = <2>; 356 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 358 clock-names = "serial"; 359 resets = <&tegra_car 55>; 360 reset-names = "serial"; 361 dmas = <&apbdma 10>, <&apbdma 10>; 362 dma-names = "rx", "tx"; 363 status = "disabled"; 364 }; 365 366 uartd: serial@70006300 { 367 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 368 reg = <0x0 0x70006300 0x0 0x40>; 369 reg-shift = <2>; 370 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 372 clock-names = "serial"; 373 resets = <&tegra_car 65>; 374 reset-names = "serial"; 375 dmas = <&apbdma 19>, <&apbdma 19>; 376 dma-names = "rx", "tx"; 377 status = "disabled"; 378 }; 379 380 pwm: pwm@7000a000 { 381 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 382 reg = <0x0 0x7000a000 0x0 0x100>; 383 #pwm-cells = <2>; 384 clocks = <&tegra_car TEGRA124_CLK_PWM>; 385 clock-names = "pwm"; 386 resets = <&tegra_car 17>; 387 reset-names = "pwm"; 388 status = "disabled"; 389 }; 390 391 i2c@7000c000 { 392 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 393 reg = <0x0 0x7000c000 0x0 0x100>; 394 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 398 clock-names = "div-clk"; 399 resets = <&tegra_car 12>; 400 reset-names = "i2c"; 401 dmas = <&apbdma 21>, <&apbdma 21>; 402 dma-names = "rx", "tx"; 403 status = "disabled"; 404 }; 405 406 i2c@7000c400 { 407 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 408 reg = <0x0 0x7000c400 0x0 0x100>; 409 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 413 clock-names = "div-clk"; 414 resets = <&tegra_car 54>; 415 reset-names = "i2c"; 416 dmas = <&apbdma 22>, <&apbdma 22>; 417 dma-names = "rx", "tx"; 418 status = "disabled"; 419 }; 420 421 i2c@7000c500 { 422 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 423 reg = <0x0 0x7000c500 0x0 0x100>; 424 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 428 clock-names = "div-clk"; 429 resets = <&tegra_car 67>; 430 reset-names = "i2c"; 431 dmas = <&apbdma 23>, <&apbdma 23>; 432 dma-names = "rx", "tx"; 433 status = "disabled"; 434 }; 435 436 i2c@7000c700 { 437 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 438 reg = <0x0 0x7000c700 0x0 0x100>; 439 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 443 clock-names = "div-clk"; 444 resets = <&tegra_car 103>; 445 reset-names = "i2c"; 446 dmas = <&apbdma 26>, <&apbdma 26>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 i2c@7000d000 { 452 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 453 reg = <0x0 0x7000d000 0x0 0x100>; 454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 458 clock-names = "div-clk"; 459 resets = <&tegra_car 47>; 460 reset-names = "i2c"; 461 dmas = <&apbdma 24>, <&apbdma 24>; 462 dma-names = "rx", "tx"; 463 status = "disabled"; 464 }; 465 466 i2c@7000d100 { 467 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 468 reg = <0x0 0x7000d100 0x0 0x100>; 469 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 473 clock-names = "div-clk"; 474 resets = <&tegra_car 166>; 475 reset-names = "i2c"; 476 dmas = <&apbdma 30>, <&apbdma 30>; 477 dma-names = "rx", "tx"; 478 status = "disabled"; 479 }; 480 481 spi@7000d400 { 482 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 483 reg = <0x0 0x7000d400 0x0 0x200>; 484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 488 clock-names = "spi"; 489 resets = <&tegra_car 41>; 490 reset-names = "spi"; 491 dmas = <&apbdma 15>, <&apbdma 15>; 492 dma-names = "rx", "tx"; 493 status = "disabled"; 494 }; 495 496 spi@7000d600 { 497 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 498 reg = <0x0 0x7000d600 0x0 0x200>; 499 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 503 clock-names = "spi"; 504 resets = <&tegra_car 44>; 505 reset-names = "spi"; 506 dmas = <&apbdma 16>, <&apbdma 16>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 spi@7000d800 { 512 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 513 reg = <0x0 0x7000d800 0x0 0x200>; 514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 518 clock-names = "spi"; 519 resets = <&tegra_car 46>; 520 reset-names = "spi"; 521 dmas = <&apbdma 17>, <&apbdma 17>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 spi@7000da00 { 527 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 528 reg = <0x0 0x7000da00 0x0 0x200>; 529 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 533 clock-names = "spi"; 534 resets = <&tegra_car 68>; 535 reset-names = "spi"; 536 dmas = <&apbdma 18>, <&apbdma 18>; 537 dma-names = "rx", "tx"; 538 status = "disabled"; 539 }; 540 541 spi@7000dc00 { 542 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 543 reg = <0x0 0x7000dc00 0x0 0x200>; 544 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 548 clock-names = "spi"; 549 resets = <&tegra_car 104>; 550 reset-names = "spi"; 551 dmas = <&apbdma 27>, <&apbdma 27>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 spi@7000de00 { 557 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 558 reg = <0x0 0x7000de00 0x0 0x200>; 559 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 563 clock-names = "spi"; 564 resets = <&tegra_car 105>; 565 reset-names = "spi"; 566 dmas = <&apbdma 28>, <&apbdma 28>; 567 dma-names = "rx", "tx"; 568 status = "disabled"; 569 }; 570 571 rtc@7000e000 { 572 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 573 reg = <0x0 0x7000e000 0x0 0x100>; 574 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&tegra_car TEGRA124_CLK_RTC>; 576 clock-names = "rtc"; 577 }; 578 579 pmc@7000e400 { 580 compatible = "nvidia,tegra124-pmc"; 581 reg = <0x0 0x7000e400 0x0 0x400>; 582 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 583 clock-names = "pclk", "clk32k_in"; 584 }; 585 586 fuse@7000f800 { 587 compatible = "nvidia,tegra124-efuse"; 588 reg = <0x0 0x7000f800 0x0 0x400>; 589 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 590 clock-names = "fuse"; 591 resets = <&tegra_car 39>; 592 reset-names = "fuse"; 593 }; 594 595 mc: memory-controller@70019000 { 596 compatible = "nvidia,tegra132-mc"; 597 reg = <0x0 0x70019000 0x0 0x1000>; 598 clocks = <&tegra_car TEGRA124_CLK_MC>; 599 clock-names = "mc"; 600 601 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 602 603 #iommu-cells = <1>; 604 }; 605 606 emc: emc@7001b000 { 607 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 608 reg = <0x0 0x7001b000 0x0 0x1000>; 609 610 nvidia,memory-controller = <&mc>; 611 }; 612 613 sata@70020000 { 614 compatible = "nvidia,tegra124-ahci"; 615 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 616 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 617 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&tegra_car TEGRA124_CLK_SATA>, 619 <&tegra_car TEGRA124_CLK_SATA_OOB>, 620 <&tegra_car TEGRA124_CLK_CML1>, 621 <&tegra_car TEGRA124_CLK_PLL_E>; 622 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 623 resets = <&tegra_car 124>, 624 <&tegra_car 123>, 625 <&tegra_car 129>; 626 reset-names = "sata", "sata-oob", "sata-cold"; 627 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 628 phy-names = "sata-phy"; 629 status = "disabled"; 630 }; 631 632 hda@70030000 { 633 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 634 "nvidia,tegra30-hda"; 635 reg = <0x0 0x70030000 0x0 0x10000>; 636 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&tegra_car TEGRA124_CLK_HDA>, 638 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 639 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 640 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 641 resets = <&tegra_car 125>, /* hda */ 642 <&tegra_car 128>, /* hda2hdmi */ 643 <&tegra_car 111>; /* hda2codec_2x */ 644 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 645 status = "disabled"; 646 }; 647 648 padctl: padctl@7009f000 { 649 compatible = "nvidia,tegra132-xusb-padctl", 650 "nvidia,tegra124-xusb-padctl"; 651 reg = <0x0 0x7009f000 0x0 0x1000>; 652 resets = <&tegra_car 142>; 653 reset-names = "padctl"; 654 655 #phy-cells = <1>; 656 657 phys { 658 pcie-0 { 659 status = "disabled"; 660 }; 661 662 sata-0 { 663 status = "disabled"; 664 }; 665 666 usb3-0 { 667 status = "disabled"; 668 }; 669 670 usb3-1 { 671 status = "disabled"; 672 }; 673 674 utmi-0 { 675 status = "disabled"; 676 }; 677 678 utmi-1 { 679 status = "disabled"; 680 }; 681 682 utmi-2 { 683 status = "disabled"; 684 }; 685 }; 686 }; 687 688 sdhci@700b0000 { 689 compatible = "nvidia,tegra124-sdhci"; 690 reg = <0x0 0x700b0000 0x0 0x200>; 691 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 693 clock-names = "sdhci"; 694 resets = <&tegra_car 14>; 695 reset-names = "sdhci"; 696 status = "disabled"; 697 }; 698 699 sdhci@700b0200 { 700 compatible = "nvidia,tegra124-sdhci"; 701 reg = <0x0 0x700b0200 0x0 0x200>; 702 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 704 clock-names = "sdhci"; 705 resets = <&tegra_car 9>; 706 reset-names = "sdhci"; 707 status = "disabled"; 708 }; 709 710 sdhci@700b0400 { 711 compatible = "nvidia,tegra124-sdhci"; 712 reg = <0x0 0x700b0400 0x0 0x200>; 713 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 715 clock-names = "sdhci"; 716 resets = <&tegra_car 69>; 717 reset-names = "sdhci"; 718 status = "disabled"; 719 }; 720 721 sdhci@700b0600 { 722 compatible = "nvidia,tegra124-sdhci"; 723 reg = <0x0 0x700b0600 0x0 0x200>; 724 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 726 clock-names = "sdhci"; 727 resets = <&tegra_car 15>; 728 reset-names = "sdhci"; 729 status = "disabled"; 730 }; 731 732 soctherm: thermal-sensor@700e2000 { 733 compatible = "nvidia,tegra132-soctherm"; 734 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ 735 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 736 reg-names = "soctherm-reg", "ccroc-reg"; 737 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 739 <&tegra_car TEGRA124_CLK_SOC_THERM>; 740 clock-names = "tsensor", "soctherm"; 741 resets = <&tegra_car 78>; 742 reset-names = "soctherm"; 743 #thermal-sensor-cells = <1>; 744 745 throttle-cfgs { 746 throttle_heavy: heavy { 747 nvidia,priority = <100>; 748 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 749 750 #cooling-cells = <2>; 751 }; 752 }; 753 }; 754 755 thermal-zones { 756 cpu { 757 polling-delay-passive = <1000>; 758 polling-delay = <0>; 759 760 thermal-sensors = 761 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 762 763 trips { 764 cpu_shutdown_trip { 765 temperature = <105000>; 766 hysteresis = <1000>; 767 type = "critical"; 768 }; 769 770 cpu_throttle_trip: throttle-trip { 771 temperature = <102000>; 772 hysteresis = <1000>; 773 type = "hot"; 774 }; 775 }; 776 777 cooling-maps { 778 map0 { 779 trip = <&cpu_throttle_trip>; 780 cooling-device = <&throttle_heavy 1 1>; 781 }; 782 }; 783 }; 784 mem { 785 polling-delay-passive = <0>; 786 polling-delay = <0>; 787 788 thermal-sensors = 789 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 790 791 trips { 792 mem_shutdown_trip { 793 temperature = <101000>; 794 hysteresis = <1000>; 795 type = "critical"; 796 }; 797 }; 798 799 cooling-maps { 800 /* 801 * There are currently no cooling maps, 802 * because there are no cooling devices. 803 */ 804 }; 805 }; 806 gpu { 807 polling-delay-passive = <1000>; 808 polling-delay = <0>; 809 810 thermal-sensors = 811 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 812 813 trips { 814 gpu_shutdown_trip { 815 temperature = <101000>; 816 hysteresis = <1000>; 817 type = "critical"; 818 }; 819 820 gpu_throttle_trip: throttle-trip { 821 temperature = <99000>; 822 hysteresis = <1000>; 823 type = "hot"; 824 }; 825 }; 826 827 cooling-maps { 828 map0 { 829 trip = <&gpu_throttle_trip>; 830 cooling-device = <&throttle_heavy 1 1>; 831 }; 832 }; 833 }; 834 pllx { 835 polling-delay-passive = <0>; 836 polling-delay = <0>; 837 838 thermal-sensors = 839 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 840 841 trips { 842 pllx_shutdown_trip { 843 temperature = <105000>; 844 hysteresis = <1000>; 845 type = "critical"; 846 }; 847 }; 848 849 cooling-maps { 850 /* 851 * There are currently no cooling maps, 852 * because there are no cooling devices. 853 */ 854 }; 855 }; 856 }; 857 858 ahub@70300000 { 859 compatible = "nvidia,tegra124-ahub"; 860 reg = <0x0 0x70300000 0x0 0x200>, 861 <0x0 0x70300800 0x0 0x800>, 862 <0x0 0x70300200 0x0 0x600>; 863 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 865 <&tegra_car TEGRA124_CLK_APBIF>; 866 clock-names = "d_audio", "apbif"; 867 resets = <&tegra_car 106>, /* d_audio */ 868 <&tegra_car 107>, /* apbif */ 869 <&tegra_car 30>, /* i2s0 */ 870 <&tegra_car 11>, /* i2s1 */ 871 <&tegra_car 18>, /* i2s2 */ 872 <&tegra_car 101>, /* i2s3 */ 873 <&tegra_car 102>, /* i2s4 */ 874 <&tegra_car 108>, /* dam0 */ 875 <&tegra_car 109>, /* dam1 */ 876 <&tegra_car 110>, /* dam2 */ 877 <&tegra_car 10>, /* spdif */ 878 <&tegra_car 153>, /* amx */ 879 <&tegra_car 185>, /* amx1 */ 880 <&tegra_car 154>, /* adx */ 881 <&tegra_car 180>, /* adx1 */ 882 <&tegra_car 186>, /* afc0 */ 883 <&tegra_car 187>, /* afc1 */ 884 <&tegra_car 188>, /* afc2 */ 885 <&tegra_car 189>, /* afc3 */ 886 <&tegra_car 190>, /* afc4 */ 887 <&tegra_car 191>; /* afc5 */ 888 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 889 "i2s3", "i2s4", "dam0", "dam1", "dam2", 890 "spdif", "amx", "amx1", "adx", "adx1", 891 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 892 dmas = <&apbdma 1>, <&apbdma 1>, 893 <&apbdma 2>, <&apbdma 2>, 894 <&apbdma 3>, <&apbdma 3>, 895 <&apbdma 4>, <&apbdma 4>, 896 <&apbdma 6>, <&apbdma 6>, 897 <&apbdma 7>, <&apbdma 7>, 898 <&apbdma 12>, <&apbdma 12>, 899 <&apbdma 13>, <&apbdma 13>, 900 <&apbdma 14>, <&apbdma 14>, 901 <&apbdma 29>, <&apbdma 29>; 902 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 903 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 904 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 905 "rx9", "tx9"; 906 ranges; 907 #address-cells = <2>; 908 #size-cells = <2>; 909 910 tegra_i2s0: i2s@70301000 { 911 compatible = "nvidia,tegra124-i2s"; 912 reg = <0x0 0x70301000 0x0 0x100>; 913 nvidia,ahub-cif-ids = <4 4>; 914 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 915 clock-names = "i2s"; 916 resets = <&tegra_car 30>; 917 reset-names = "i2s"; 918 status = "disabled"; 919 }; 920 921 tegra_i2s1: i2s@70301100 { 922 compatible = "nvidia,tegra124-i2s"; 923 reg = <0x0 0x70301100 0x0 0x100>; 924 nvidia,ahub-cif-ids = <5 5>; 925 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 926 clock-names = "i2s"; 927 resets = <&tegra_car 11>; 928 reset-names = "i2s"; 929 status = "disabled"; 930 }; 931 932 tegra_i2s2: i2s@70301200 { 933 compatible = "nvidia,tegra124-i2s"; 934 reg = <0x0 0x70301200 0x0 0x100>; 935 nvidia,ahub-cif-ids = <6 6>; 936 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 937 clock-names = "i2s"; 938 resets = <&tegra_car 18>; 939 reset-names = "i2s"; 940 status = "disabled"; 941 }; 942 943 tegra_i2s3: i2s@70301300 { 944 compatible = "nvidia,tegra124-i2s"; 945 reg = <0x0 0x70301300 0x0 0x100>; 946 nvidia,ahub-cif-ids = <7 7>; 947 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 948 clock-names = "i2s"; 949 resets = <&tegra_car 101>; 950 reset-names = "i2s"; 951 status = "disabled"; 952 }; 953 954 tegra_i2s4: i2s@70301400 { 955 compatible = "nvidia,tegra124-i2s"; 956 reg = <0x0 0x70301400 0x0 0x100>; 957 nvidia,ahub-cif-ids = <8 8>; 958 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 959 clock-names = "i2s"; 960 resets = <&tegra_car 102>; 961 reset-names = "i2s"; 962 status = "disabled"; 963 }; 964 }; 965 966 usb@7d000000 { 967 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 968 reg = <0x0 0x7d000000 0x0 0x4000>; 969 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 970 phy_type = "utmi"; 971 clocks = <&tegra_car TEGRA124_CLK_USBD>; 972 clock-names = "usb"; 973 resets = <&tegra_car 22>; 974 reset-names = "usb"; 975 nvidia,phy = <&phy1>; 976 status = "disabled"; 977 }; 978 979 phy1: usb-phy@7d000000 { 980 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 981 reg = <0x0 0x7d000000 0x0 0x4000>, 982 <0x0 0x7d000000 0x0 0x4000>; 983 phy_type = "utmi"; 984 clocks = <&tegra_car TEGRA124_CLK_USBD>, 985 <&tegra_car TEGRA124_CLK_PLL_U>, 986 <&tegra_car TEGRA124_CLK_USBD>; 987 clock-names = "reg", "pll_u", "utmi-pads"; 988 resets = <&tegra_car 22>, <&tegra_car 22>; 989 reset-names = "usb", "utmi-pads"; 990 nvidia,hssync-start-delay = <0>; 991 nvidia,idle-wait-delay = <17>; 992 nvidia,elastic-limit = <16>; 993 nvidia,term-range-adj = <6>; 994 nvidia,xcvr-setup = <9>; 995 nvidia,xcvr-lsfslew = <0>; 996 nvidia,xcvr-lsrslew = <3>; 997 nvidia,hssquelch-level = <2>; 998 nvidia,hsdiscon-level = <5>; 999 nvidia,xcvr-hsslew = <12>; 1000 nvidia,has-utmi-pad-registers; 1001 status = "disabled"; 1002 }; 1003 1004 usb@7d004000 { 1005 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1006 reg = <0x0 0x7d004000 0x0 0x4000>; 1007 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1008 phy_type = "utmi"; 1009 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1010 clock-names = "usb"; 1011 resets = <&tegra_car 58>; 1012 reset-names = "usb"; 1013 nvidia,phy = <&phy2>; 1014 status = "disabled"; 1015 }; 1016 1017 phy2: usb-phy@7d004000 { 1018 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1019 reg = <0x0 0x7d004000 0x0 0x4000>, 1020 <0x0 0x7d000000 0x0 0x4000>; 1021 phy_type = "utmi"; 1022 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1023 <&tegra_car TEGRA124_CLK_PLL_U>, 1024 <&tegra_car TEGRA124_CLK_USBD>; 1025 clock-names = "reg", "pll_u", "utmi-pads"; 1026 resets = <&tegra_car 58>, <&tegra_car 22>; 1027 reset-names = "usb", "utmi-pads"; 1028 nvidia,hssync-start-delay = <0>; 1029 nvidia,idle-wait-delay = <17>; 1030 nvidia,elastic-limit = <16>; 1031 nvidia,term-range-adj = <6>; 1032 nvidia,xcvr-setup = <9>; 1033 nvidia,xcvr-lsfslew = <0>; 1034 nvidia,xcvr-lsrslew = <3>; 1035 nvidia,hssquelch-level = <2>; 1036 nvidia,hsdiscon-level = <5>; 1037 nvidia,xcvr-hsslew = <12>; 1038 status = "disabled"; 1039 }; 1040 1041 usb@7d008000 { 1042 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1043 reg = <0x0 0x7d008000 0x0 0x4000>; 1044 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1045 phy_type = "utmi"; 1046 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1047 clock-names = "usb"; 1048 resets = <&tegra_car 59>; 1049 reset-names = "usb"; 1050 nvidia,phy = <&phy3>; 1051 status = "disabled"; 1052 }; 1053 1054 phy3: usb-phy@7d008000 { 1055 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1056 reg = <0x0 0x7d008000 0x0 0x4000>, 1057 <0x0 0x7d000000 0x0 0x4000>; 1058 phy_type = "utmi"; 1059 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1060 <&tegra_car TEGRA124_CLK_PLL_U>, 1061 <&tegra_car TEGRA124_CLK_USBD>; 1062 clock-names = "reg", "pll_u", "utmi-pads"; 1063 resets = <&tegra_car 59>, <&tegra_car 22>; 1064 reset-names = "usb", "utmi-pads"; 1065 nvidia,hssync-start-delay = <0>; 1066 nvidia,idle-wait-delay = <17>; 1067 nvidia,elastic-limit = <16>; 1068 nvidia,term-range-adj = <6>; 1069 nvidia,xcvr-setup = <9>; 1070 nvidia,xcvr-lsfslew = <0>; 1071 nvidia,xcvr-lsrslew = <3>; 1072 nvidia,hssquelch-level = <2>; 1073 nvidia,hsdiscon-level = <5>; 1074 nvidia,xcvr-hsslew = <12>; 1075 status = "disabled"; 1076 }; 1077 1078 cpus { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 cpu@0 { 1083 device_type = "cpu"; 1084 compatible = "nvidia,denver", "arm,armv8"; 1085 reg = <0>; 1086 }; 1087 1088 cpu@1 { 1089 device_type = "cpu"; 1090 compatible = "nvidia,denver", "arm,armv8"; 1091 reg = <1>; 1092 }; 1093 }; 1094 1095 timer { 1096 compatible = "arm,armv7-timer"; 1097 interrupts = <GIC_PPI 13 1098 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1099 <GIC_PPI 14 1100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1101 <GIC_PPI 11 1102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1103 <GIC_PPI 10 1104 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1105 interrupt-parent = <&gic>; 1106 }; 1107}; 1108