1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra132", "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 21 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 22 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 37 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 38 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 39 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 40 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 bus-range = <0x00 0xff>; 58 status = "disabled"; 59 60 #address-cells = <3>; 61 #size-cells = <2>; 62 ranges; 63 64 nvidia,num-lanes = <2>; 65 }; 66 67 pci@2,0 { 68 device_type = "pci"; 69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 70 reg = <0x001000 0 0 0 0>; 71 bus-range = <0x00 0xff>; 72 status = "disabled"; 73 74 #address-cells = <3>; 75 #size-cells = <2>; 76 ranges; 77 78 nvidia,num-lanes = <1>; 79 }; 80 }; 81 82 host1x@50000000 { 83 compatible = "nvidia,tegra132-host1x", 84 "nvidia,tegra124-host1x"; 85 reg = <0x0 0x50000000 0x0 0x00034000>; 86 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 87 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 88 interrupt-names = "syncpt", "host1x"; 89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 90 clock-names = "host1x"; 91 resets = <&tegra_car 28>; 92 reset-names = "host1x"; 93 94 #address-cells = <2>; 95 #size-cells = <2>; 96 97 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 98 99 dc@54200000 { 100 compatible = "nvidia,tegra124-dc"; 101 reg = <0x0 0x54200000 0x0 0x00040000>; 102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 104 clock-names = "dc"; 105 resets = <&tegra_car 27>; 106 reset-names = "dc"; 107 108 iommus = <&mc TEGRA_SWGROUP_DC>; 109 110 nvidia,head = <0>; 111 }; 112 113 dc@54240000 { 114 compatible = "nvidia,tegra124-dc"; 115 reg = <0x0 0x54240000 0x0 0x00040000>; 116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 118 clock-names = "dc"; 119 resets = <&tegra_car 26>; 120 reset-names = "dc"; 121 122 iommus = <&mc TEGRA_SWGROUP_DCB>; 123 124 nvidia,head = <1>; 125 }; 126 127 hdmi@54280000 { 128 compatible = "nvidia,tegra124-hdmi"; 129 reg = <0x0 0x54280000 0x0 0x00040000>; 130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 132 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 133 clock-names = "hdmi", "parent"; 134 resets = <&tegra_car 51>; 135 reset-names = "hdmi"; 136 status = "disabled"; 137 }; 138 139 sor@54540000 { 140 compatible = "nvidia,tegra124-sor"; 141 reg = <0x0 0x54540000 0x0 0x00040000>; 142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 144 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 146 <&tegra_car TEGRA124_CLK_PLL_DP>, 147 <&tegra_car TEGRA124_CLK_CLK_M>; 148 clock-names = "sor", "out", "parent", "dp", "safe"; 149 resets = <&tegra_car 182>; 150 reset-names = "sor"; 151 status = "disabled"; 152 }; 153 154 dpaux: dpaux@545c0000 { 155 compatible = "nvidia,tegra124-dpaux"; 156 reg = <0x0 0x545c0000 0x0 0x00040000>; 157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 159 <&tegra_car TEGRA124_CLK_PLL_DP>; 160 clock-names = "dpaux", "parent"; 161 resets = <&tegra_car 181>; 162 reset-names = "dpaux"; 163 status = "disabled"; 164 165 i2c-bus { 166 #address-cells = <1>; 167 #size-cells = <0>; 168 }; 169 }; 170 }; 171 172 gic: interrupt-controller@50041000 { 173 compatible = "arm,cortex-a15-gic"; 174 #interrupt-cells = <3>; 175 interrupt-controller; 176 reg = <0x0 0x50041000 0x0 0x1000>, 177 <0x0 0x50042000 0x0 0x2000>, 178 <0x0 0x50044000 0x0 0x2000>, 179 <0x0 0x50046000 0x0 0x2000>; 180 interrupts = <GIC_PPI 9 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 182 interrupt-parent = <&gic>; 183 }; 184 185 gpu@57000000 { 186 compatible = "nvidia,gk20a"; 187 reg = <0x0 0x57000000 0x0 0x01000000>, 188 <0x0 0x58000000 0x0 0x01000000>; 189 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 191 interrupt-names = "stall", "nonstall"; 192 clocks = <&tegra_car TEGRA124_CLK_GPU>, 193 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 194 clock-names = "gpu", "pwr"; 195 resets = <&tegra_car 184>; 196 reset-names = "gpu"; 197 status = "disabled"; 198 }; 199 200 lic: interrupt-controller@60004000 { 201 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 202 reg = <0x0 0x60004000 0x0 0x100>, 203 <0x0 0x60004100 0x0 0x100>, 204 <0x0 0x60004200 0x0 0x100>, 205 <0x0 0x60004300 0x0 0x100>, 206 <0x0 0x60004400 0x0 0x100>; 207 interrupt-controller; 208 #interrupt-cells = <3>; 209 interrupt-parent = <&gic>; 210 }; 211 212 timer@60005000 { 213 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 214 reg = <0x0 0x60005000 0x0 0x400>; 215 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 222 clock-names = "timer"; 223 }; 224 225 tegra_car: clock@60006000 { 226 compatible = "nvidia,tegra132-car"; 227 reg = <0x0 0x60006000 0x0 0x1000>; 228 #clock-cells = <1>; 229 #reset-cells = <1>; 230 nvidia,external-memory-controller = <&emc>; 231 }; 232 233 flow-controller@60007000 { 234 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 235 reg = <0x0 0x60007000 0x0 0x1000>; 236 }; 237 238 actmon@6000c800 { 239 compatible = "nvidia,tegra124-actmon"; 240 reg = <0x0 0x6000c800 0x0 0x400>; 241 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 243 <&tegra_car TEGRA124_CLK_EMC>; 244 clock-names = "actmon", "emc"; 245 resets = <&tegra_car 119>; 246 reset-names = "actmon"; 247 }; 248 249 gpio: gpio@6000d000 { 250 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 251 reg = <0x0 0x6000d000 0x0 0x1000>; 252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 260 #gpio-cells = <2>; 261 gpio-controller; 262 #interrupt-cells = <2>; 263 interrupt-controller; 264 }; 265 266 apbdma: dma@60020000 { 267 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 268 reg = <0x0 0x60020000 0x0 0x1400>; 269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 302 clock-names = "dma"; 303 resets = <&tegra_car 34>; 304 reset-names = "dma"; 305 #dma-cells = <1>; 306 }; 307 308 apbmisc@70000800 { 309 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 312 }; 313 314 pinmux: pinmux@70000868 { 315 compatible = "nvidia,tegra124-pinmux"; 316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 318 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 319 }; 320 321 /* 322 * There are two serial driver i.e. 8250 based simple serial 323 * driver and APB DMA based serial driver for higher baudrate 324 * and performance. To enable the 8250 based driver, the compatible 325 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 326 * the APB DMA based serial driver, the compatible is 327 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 328 */ 329 uarta: serial@70006000 { 330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 331 reg = <0x0 0x70006000 0x0 0x40>; 332 reg-shift = <2>; 333 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 335 clock-names = "serial"; 336 resets = <&tegra_car 6>; 337 reset-names = "serial"; 338 dmas = <&apbdma 8>, <&apbdma 8>; 339 dma-names = "rx", "tx"; 340 status = "disabled"; 341 }; 342 343 uartb: serial@70006040 { 344 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 345 reg = <0x0 0x70006040 0x0 0x40>; 346 reg-shift = <2>; 347 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 349 clock-names = "serial"; 350 resets = <&tegra_car 7>; 351 reset-names = "serial"; 352 dmas = <&apbdma 9>, <&apbdma 9>; 353 dma-names = "rx", "tx"; 354 status = "disabled"; 355 }; 356 357 uartc: serial@70006200 { 358 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 359 reg = <0x0 0x70006200 0x0 0x40>; 360 reg-shift = <2>; 361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 363 clock-names = "serial"; 364 resets = <&tegra_car 55>; 365 reset-names = "serial"; 366 dmas = <&apbdma 10>, <&apbdma 10>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 uartd: serial@70006300 { 372 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 373 reg = <0x0 0x70006300 0x0 0x40>; 374 reg-shift = <2>; 375 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 377 clock-names = "serial"; 378 resets = <&tegra_car 65>; 379 reset-names = "serial"; 380 dmas = <&apbdma 19>, <&apbdma 19>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 pwm: pwm@7000a000 { 386 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 387 reg = <0x0 0x7000a000 0x0 0x100>; 388 #pwm-cells = <2>; 389 clocks = <&tegra_car TEGRA124_CLK_PWM>; 390 clock-names = "pwm"; 391 resets = <&tegra_car 17>; 392 reset-names = "pwm"; 393 status = "disabled"; 394 }; 395 396 i2c@7000c000 { 397 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 398 reg = <0x0 0x7000c000 0x0 0x100>; 399 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 403 clock-names = "div-clk"; 404 resets = <&tegra_car 12>; 405 reset-names = "i2c"; 406 dmas = <&apbdma 21>, <&apbdma 21>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 i2c@7000c400 { 412 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 413 reg = <0x0 0x7000c400 0x0 0x100>; 414 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 418 clock-names = "div-clk"; 419 resets = <&tegra_car 54>; 420 reset-names = "i2c"; 421 dmas = <&apbdma 22>, <&apbdma 22>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 426 i2c@7000c500 { 427 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 428 reg = <0x0 0x7000c500 0x0 0x100>; 429 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 433 clock-names = "div-clk"; 434 resets = <&tegra_car 67>; 435 reset-names = "i2c"; 436 dmas = <&apbdma 23>, <&apbdma 23>; 437 dma-names = "rx", "tx"; 438 status = "disabled"; 439 }; 440 441 i2c@7000c700 { 442 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 443 reg = <0x0 0x7000c700 0x0 0x100>; 444 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 448 clock-names = "div-clk"; 449 resets = <&tegra_car 103>; 450 reset-names = "i2c"; 451 dmas = <&apbdma 26>, <&apbdma 26>; 452 dma-names = "rx", "tx"; 453 status = "disabled"; 454 }; 455 456 i2c@7000d000 { 457 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 458 reg = <0x0 0x7000d000 0x0 0x100>; 459 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 463 clock-names = "div-clk"; 464 resets = <&tegra_car 47>; 465 reset-names = "i2c"; 466 dmas = <&apbdma 24>, <&apbdma 24>; 467 dma-names = "rx", "tx"; 468 status = "disabled"; 469 }; 470 471 i2c@7000d100 { 472 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 473 reg = <0x0 0x7000d100 0x0 0x100>; 474 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 478 clock-names = "div-clk"; 479 resets = <&tegra_car 166>; 480 reset-names = "i2c"; 481 dmas = <&apbdma 30>, <&apbdma 30>; 482 dma-names = "rx", "tx"; 483 status = "disabled"; 484 }; 485 486 spi@7000d400 { 487 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 488 reg = <0x0 0x7000d400 0x0 0x200>; 489 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 493 clock-names = "spi"; 494 resets = <&tegra_car 41>; 495 reset-names = "spi"; 496 dmas = <&apbdma 15>, <&apbdma 15>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 spi@7000d600 { 502 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 503 reg = <0x0 0x7000d600 0x0 0x200>; 504 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 508 clock-names = "spi"; 509 resets = <&tegra_car 44>; 510 reset-names = "spi"; 511 dmas = <&apbdma 16>, <&apbdma 16>; 512 dma-names = "rx", "tx"; 513 status = "disabled"; 514 }; 515 516 spi@7000d800 { 517 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 518 reg = <0x0 0x7000d800 0x0 0x200>; 519 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 523 clock-names = "spi"; 524 resets = <&tegra_car 46>; 525 reset-names = "spi"; 526 dmas = <&apbdma 17>, <&apbdma 17>; 527 dma-names = "rx", "tx"; 528 status = "disabled"; 529 }; 530 531 spi@7000da00 { 532 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 533 reg = <0x0 0x7000da00 0x0 0x200>; 534 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 538 clock-names = "spi"; 539 resets = <&tegra_car 68>; 540 reset-names = "spi"; 541 dmas = <&apbdma 18>, <&apbdma 18>; 542 dma-names = "rx", "tx"; 543 status = "disabled"; 544 }; 545 546 spi@7000dc00 { 547 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 548 reg = <0x0 0x7000dc00 0x0 0x200>; 549 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 553 clock-names = "spi"; 554 resets = <&tegra_car 104>; 555 reset-names = "spi"; 556 dmas = <&apbdma 27>, <&apbdma 27>; 557 dma-names = "rx", "tx"; 558 status = "disabled"; 559 }; 560 561 spi@7000de00 { 562 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 563 reg = <0x0 0x7000de00 0x0 0x200>; 564 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 568 clock-names = "spi"; 569 resets = <&tegra_car 105>; 570 reset-names = "spi"; 571 dmas = <&apbdma 28>, <&apbdma 28>; 572 dma-names = "rx", "tx"; 573 status = "disabled"; 574 }; 575 576 rtc@7000e000 { 577 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 578 reg = <0x0 0x7000e000 0x0 0x100>; 579 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&tegra_car TEGRA124_CLK_RTC>; 581 clock-names = "rtc"; 582 }; 583 584 tegra_pmc: pmc@7000e400 { 585 compatible = "nvidia,tegra124-pmc"; 586 reg = <0x0 0x7000e400 0x0 0x400>; 587 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 588 clock-names = "pclk", "clk32k_in"; 589 #clock-cells = <1>; 590 }; 591 592 fuse@7000f800 { 593 compatible = "nvidia,tegra124-efuse"; 594 reg = <0x0 0x7000f800 0x0 0x400>; 595 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 596 clock-names = "fuse"; 597 resets = <&tegra_car 39>; 598 reset-names = "fuse"; 599 }; 600 601 mc: memory-controller@70019000 { 602 compatible = "nvidia,tegra132-mc"; 603 reg = <0x0 0x70019000 0x0 0x1000>; 604 clocks = <&tegra_car TEGRA124_CLK_MC>; 605 clock-names = "mc"; 606 607 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 608 609 #iommu-cells = <1>; 610 }; 611 612 emc: external-memory-controller@7001b000 { 613 compatible = "nvidia,tegra132-emc"; 614 reg = <0x0 0x7001b000 0x0 0x1000>; 615 clocks = <&tegra_car TEGRA124_CLK_EMC>; 616 clock-names = "emc"; 617 618 nvidia,memory-controller = <&mc>; 619 }; 620 621 sata@70020000 { 622 compatible = "nvidia,tegra124-ahci"; 623 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 624 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 625 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&tegra_car TEGRA124_CLK_SATA>, 627 <&tegra_car TEGRA124_CLK_SATA_OOB>, 628 <&tegra_car TEGRA124_CLK_CML1>, 629 <&tegra_car TEGRA124_CLK_PLL_E>; 630 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 631 resets = <&tegra_car 124>, 632 <&tegra_car 129>, 633 <&tegra_car 123>; 634 reset-names = "sata", "sata-cold", "sata-oob"; 635 status = "disabled"; 636 }; 637 638 hda@70030000 { 639 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 640 "nvidia,tegra30-hda"; 641 reg = <0x0 0x70030000 0x0 0x10000>; 642 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&tegra_car TEGRA124_CLK_HDA>, 644 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 645 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 646 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 647 resets = <&tegra_car 125>, /* hda */ 648 <&tegra_car 128>, /* hda2hdmi */ 649 <&tegra_car 111>; /* hda2codec_2x */ 650 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 651 status = "disabled"; 652 }; 653 654 usb@70090000 { 655 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 656 reg = <0x0 0x70090000 0x0 0x8000>, 657 <0x0 0x70098000 0x0 0x1000>, 658 <0x0 0x70099000 0x0 0x1000>; 659 reg-names = "hcd", "fpci", "ipfs"; 660 661 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 663 664 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 665 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 666 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 667 <&tegra_car TEGRA124_CLK_XUSB_SS>, 668 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 669 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 670 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 671 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 672 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 673 <&tegra_car TEGRA124_CLK_CLK_M>, 674 <&tegra_car TEGRA124_CLK_PLL_E>; 675 clock-names = "xusb_host", "xusb_host_src", 676 "xusb_falcon_src", "xusb_ss", 677 "xusb_ss_src", "xusb_ss_div2", 678 "xusb_hs_src", "xusb_fs_src", 679 "pll_u_480m", "clk_m", "pll_e"; 680 resets = <&tegra_car 89>, <&tegra_car 156>, 681 <&tegra_car 143>; 682 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 683 684 nvidia,xusb-padctl = <&padctl>; 685 686 status = "disabled"; 687 }; 688 689 padctl: padctl@7009f000 { 690 compatible = "nvidia,tegra132-xusb-padctl", 691 "nvidia,tegra124-xusb-padctl"; 692 reg = <0x0 0x7009f000 0x0 0x1000>; 693 resets = <&tegra_car 142>; 694 reset-names = "padctl"; 695 696 pads { 697 usb2 { 698 status = "disabled"; 699 700 lanes { 701 usb2-0 { 702 status = "disabled"; 703 #phy-cells = <0>; 704 }; 705 706 usb2-1 { 707 status = "disabled"; 708 #phy-cells = <0>; 709 }; 710 711 usb2-2 { 712 status = "disabled"; 713 #phy-cells = <0>; 714 }; 715 }; 716 }; 717 718 ulpi { 719 status = "disabled"; 720 721 lanes { 722 ulpi-0 { 723 status = "disabled"; 724 #phy-cells = <0>; 725 }; 726 }; 727 }; 728 729 hsic { 730 status = "disabled"; 731 732 lanes { 733 hsic-0 { 734 status = "disabled"; 735 #phy-cells = <0>; 736 }; 737 738 hsic-1 { 739 status = "disabled"; 740 #phy-cells = <0>; 741 }; 742 }; 743 }; 744 745 pcie { 746 status = "disabled"; 747 748 lanes { 749 pcie-0 { 750 status = "disabled"; 751 #phy-cells = <0>; 752 }; 753 754 pcie-1 { 755 status = "disabled"; 756 #phy-cells = <0>; 757 }; 758 759 pcie-2 { 760 status = "disabled"; 761 #phy-cells = <0>; 762 }; 763 764 pcie-3 { 765 status = "disabled"; 766 #phy-cells = <0>; 767 }; 768 769 pcie-4 { 770 status = "disabled"; 771 #phy-cells = <0>; 772 }; 773 }; 774 }; 775 776 sata { 777 status = "disabled"; 778 779 lanes { 780 sata-0 { 781 status = "disabled"; 782 #phy-cells = <0>; 783 }; 784 }; 785 }; 786 }; 787 788 ports { 789 usb2-0 { 790 status = "disabled"; 791 }; 792 793 usb2-1 { 794 status = "disabled"; 795 }; 796 797 usb2-2 { 798 status = "disabled"; 799 }; 800 801 hsic-0 { 802 status = "disabled"; 803 }; 804 805 hsic-1 { 806 status = "disabled"; 807 }; 808 809 usb3-0 { 810 status = "disabled"; 811 }; 812 813 usb3-1 { 814 status = "disabled"; 815 }; 816 }; 817 }; 818 819 mmc@700b0000 { 820 compatible = "nvidia,tegra124-sdhci"; 821 reg = <0x0 0x700b0000 0x0 0x200>; 822 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 824 clock-names = "sdhci"; 825 resets = <&tegra_car 14>; 826 reset-names = "sdhci"; 827 status = "disabled"; 828 }; 829 830 mmc@700b0200 { 831 compatible = "nvidia,tegra124-sdhci"; 832 reg = <0x0 0x700b0200 0x0 0x200>; 833 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 835 clock-names = "sdhci"; 836 resets = <&tegra_car 9>; 837 reset-names = "sdhci"; 838 status = "disabled"; 839 }; 840 841 mmc@700b0400 { 842 compatible = "nvidia,tegra124-sdhci"; 843 reg = <0x0 0x700b0400 0x0 0x200>; 844 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 846 clock-names = "sdhci"; 847 resets = <&tegra_car 69>; 848 reset-names = "sdhci"; 849 status = "disabled"; 850 }; 851 852 mmc@700b0600 { 853 compatible = "nvidia,tegra124-sdhci"; 854 reg = <0x0 0x700b0600 0x0 0x200>; 855 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 857 clock-names = "sdhci"; 858 resets = <&tegra_car 15>; 859 reset-names = "sdhci"; 860 status = "disabled"; 861 }; 862 863 soctherm: thermal-sensor@700e2000 { 864 compatible = "nvidia,tegra132-soctherm"; 865 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 866 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 867 reg-names = "soctherm-reg", "ccroc-reg"; 868 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "thermal", "edp"; 871 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 872 <&tegra_car TEGRA124_CLK_SOC_THERM>; 873 clock-names = "tsensor", "soctherm"; 874 resets = <&tegra_car 78>; 875 reset-names = "soctherm"; 876 #thermal-sensor-cells = <1>; 877 878 throttle-cfgs { 879 throttle_heavy: heavy { 880 nvidia,priority = <100>; 881 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 882 883 #cooling-cells = <2>; 884 }; 885 }; 886 }; 887 888 thermal-zones { 889 cpu { 890 polling-delay-passive = <1000>; 891 polling-delay = <0>; 892 893 thermal-sensors = 894 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 895 896 trips { 897 cpu_shutdown_trip { 898 temperature = <105000>; 899 hysteresis = <1000>; 900 type = "critical"; 901 }; 902 903 cpu_throttle_trip: throttle-trip { 904 temperature = <102000>; 905 hysteresis = <1000>; 906 type = "hot"; 907 }; 908 }; 909 910 cooling-maps { 911 map0 { 912 trip = <&cpu_throttle_trip>; 913 cooling-device = <&throttle_heavy 1 1>; 914 }; 915 }; 916 }; 917 mem { 918 polling-delay-passive = <0>; 919 polling-delay = <0>; 920 921 thermal-sensors = 922 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 923 924 trips { 925 mem_shutdown_trip { 926 temperature = <101000>; 927 hysteresis = <1000>; 928 type = "critical"; 929 }; 930 mem_throttle_trip { 931 temperature = <99000>; 932 hysteresis = <1000>; 933 type = "hot"; 934 }; 935 }; 936 937 cooling-maps { 938 /* 939 * There are currently no cooling maps, 940 * because there are no cooling devices. 941 */ 942 }; 943 }; 944 gpu { 945 polling-delay-passive = <1000>; 946 polling-delay = <0>; 947 948 thermal-sensors = 949 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 950 951 trips { 952 gpu_shutdown_trip { 953 temperature = <101000>; 954 hysteresis = <1000>; 955 type = "critical"; 956 }; 957 958 gpu_throttle_trip: throttle-trip { 959 temperature = <99000>; 960 hysteresis = <1000>; 961 type = "hot"; 962 }; 963 }; 964 965 cooling-maps { 966 map0 { 967 trip = <&gpu_throttle_trip>; 968 cooling-device = <&throttle_heavy 1 1>; 969 }; 970 }; 971 }; 972 pllx { 973 polling-delay-passive = <0>; 974 polling-delay = <0>; 975 976 thermal-sensors = 977 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 978 979 trips { 980 pllx_shutdown_trip { 981 temperature = <105000>; 982 hysteresis = <1000>; 983 type = "critical"; 984 }; 985 pllx_throttle_trip { 986 temperature = <99000>; 987 hysteresis = <1000>; 988 type = "hot"; 989 }; 990 }; 991 992 cooling-maps { 993 /* 994 * There are currently no cooling maps, 995 * because there are no cooling devices. 996 */ 997 }; 998 }; 999 }; 1000 1001 ahub@70300000 { 1002 compatible = "nvidia,tegra124-ahub"; 1003 reg = <0x0 0x70300000 0x0 0x200>, 1004 <0x0 0x70300800 0x0 0x800>, 1005 <0x0 0x70300200 0x0 0x600>; 1006 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 1008 <&tegra_car TEGRA124_CLK_APBIF>; 1009 clock-names = "d_audio", "apbif"; 1010 resets = <&tegra_car 106>, /* d_audio */ 1011 <&tegra_car 107>, /* apbif */ 1012 <&tegra_car 30>, /* i2s0 */ 1013 <&tegra_car 11>, /* i2s1 */ 1014 <&tegra_car 18>, /* i2s2 */ 1015 <&tegra_car 101>, /* i2s3 */ 1016 <&tegra_car 102>, /* i2s4 */ 1017 <&tegra_car 108>, /* dam0 */ 1018 <&tegra_car 109>, /* dam1 */ 1019 <&tegra_car 110>, /* dam2 */ 1020 <&tegra_car 10>, /* spdif */ 1021 <&tegra_car 153>, /* amx */ 1022 <&tegra_car 185>, /* amx1 */ 1023 <&tegra_car 154>, /* adx */ 1024 <&tegra_car 180>, /* adx1 */ 1025 <&tegra_car 186>, /* afc0 */ 1026 <&tegra_car 187>, /* afc1 */ 1027 <&tegra_car 188>, /* afc2 */ 1028 <&tegra_car 189>, /* afc3 */ 1029 <&tegra_car 190>, /* afc4 */ 1030 <&tegra_car 191>; /* afc5 */ 1031 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1032 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1033 "spdif", "amx", "amx1", "adx", "adx1", 1034 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 1035 dmas = <&apbdma 1>, <&apbdma 1>, 1036 <&apbdma 2>, <&apbdma 2>, 1037 <&apbdma 3>, <&apbdma 3>, 1038 <&apbdma 4>, <&apbdma 4>, 1039 <&apbdma 6>, <&apbdma 6>, 1040 <&apbdma 7>, <&apbdma 7>, 1041 <&apbdma 12>, <&apbdma 12>, 1042 <&apbdma 13>, <&apbdma 13>, 1043 <&apbdma 14>, <&apbdma 14>, 1044 <&apbdma 29>, <&apbdma 29>; 1045 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1046 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 1047 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 1048 "rx9", "tx9"; 1049 ranges; 1050 #address-cells = <2>; 1051 #size-cells = <2>; 1052 1053 tegra_i2s0: i2s@70301000 { 1054 compatible = "nvidia,tegra124-i2s"; 1055 reg = <0x0 0x70301000 0x0 0x100>; 1056 nvidia,ahub-cif-ids = <4 4>; 1057 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1058 clock-names = "i2s"; 1059 resets = <&tegra_car 30>; 1060 reset-names = "i2s"; 1061 status = "disabled"; 1062 }; 1063 1064 tegra_i2s1: i2s@70301100 { 1065 compatible = "nvidia,tegra124-i2s"; 1066 reg = <0x0 0x70301100 0x0 0x100>; 1067 nvidia,ahub-cif-ids = <5 5>; 1068 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1069 clock-names = "i2s"; 1070 resets = <&tegra_car 11>; 1071 reset-names = "i2s"; 1072 status = "disabled"; 1073 }; 1074 1075 tegra_i2s2: i2s@70301200 { 1076 compatible = "nvidia,tegra124-i2s"; 1077 reg = <0x0 0x70301200 0x0 0x100>; 1078 nvidia,ahub-cif-ids = <6 6>; 1079 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1080 clock-names = "i2s"; 1081 resets = <&tegra_car 18>; 1082 reset-names = "i2s"; 1083 status = "disabled"; 1084 }; 1085 1086 tegra_i2s3: i2s@70301300 { 1087 compatible = "nvidia,tegra124-i2s"; 1088 reg = <0x0 0x70301300 0x0 0x100>; 1089 nvidia,ahub-cif-ids = <7 7>; 1090 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1091 clock-names = "i2s"; 1092 resets = <&tegra_car 101>; 1093 reset-names = "i2s"; 1094 status = "disabled"; 1095 }; 1096 1097 tegra_i2s4: i2s@70301400 { 1098 compatible = "nvidia,tegra124-i2s"; 1099 reg = <0x0 0x70301400 0x0 0x100>; 1100 nvidia,ahub-cif-ids = <8 8>; 1101 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1102 clock-names = "i2s"; 1103 resets = <&tegra_car 102>; 1104 reset-names = "i2s"; 1105 status = "disabled"; 1106 }; 1107 }; 1108 1109 usb@7d000000 { 1110 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1111 reg = <0x0 0x7d000000 0x0 0x4000>; 1112 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1113 phy_type = "utmi"; 1114 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1115 clock-names = "usb"; 1116 resets = <&tegra_car 22>; 1117 reset-names = "usb"; 1118 nvidia,phy = <&phy1>; 1119 status = "disabled"; 1120 }; 1121 1122 phy1: usb-phy@7d000000 { 1123 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1124 reg = <0x0 0x7d000000 0x0 0x4000>, 1125 <0x0 0x7d000000 0x0 0x4000>; 1126 phy_type = "utmi"; 1127 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1128 <&tegra_car TEGRA124_CLK_PLL_U>, 1129 <&tegra_car TEGRA124_CLK_USBD>; 1130 clock-names = "reg", "pll_u", "utmi-pads"; 1131 resets = <&tegra_car 22>, <&tegra_car 22>; 1132 reset-names = "usb", "utmi-pads"; 1133 #phy-cells = <0>; 1134 nvidia,hssync-start-delay = <0>; 1135 nvidia,idle-wait-delay = <17>; 1136 nvidia,elastic-limit = <16>; 1137 nvidia,term-range-adj = <6>; 1138 nvidia,xcvr-setup = <9>; 1139 nvidia,xcvr-lsfslew = <0>; 1140 nvidia,xcvr-lsrslew = <3>; 1141 nvidia,hssquelch-level = <2>; 1142 nvidia,hsdiscon-level = <5>; 1143 nvidia,xcvr-hsslew = <12>; 1144 nvidia,has-utmi-pad-registers; 1145 status = "disabled"; 1146 }; 1147 1148 usb@7d004000 { 1149 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1150 reg = <0x0 0x7d004000 0x0 0x4000>; 1151 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1152 phy_type = "utmi"; 1153 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1154 clock-names = "usb"; 1155 resets = <&tegra_car 58>; 1156 reset-names = "usb"; 1157 nvidia,phy = <&phy2>; 1158 status = "disabled"; 1159 }; 1160 1161 phy2: usb-phy@7d004000 { 1162 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1163 reg = <0x0 0x7d004000 0x0 0x4000>, 1164 <0x0 0x7d000000 0x0 0x4000>; 1165 phy_type = "utmi"; 1166 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1167 <&tegra_car TEGRA124_CLK_PLL_U>, 1168 <&tegra_car TEGRA124_CLK_USBD>; 1169 clock-names = "reg", "pll_u", "utmi-pads"; 1170 resets = <&tegra_car 58>, <&tegra_car 22>; 1171 reset-names = "usb", "utmi-pads"; 1172 #phy-cells = <0>; 1173 nvidia,hssync-start-delay = <0>; 1174 nvidia,idle-wait-delay = <17>; 1175 nvidia,elastic-limit = <16>; 1176 nvidia,term-range-adj = <6>; 1177 nvidia,xcvr-setup = <9>; 1178 nvidia,xcvr-lsfslew = <0>; 1179 nvidia,xcvr-lsrslew = <3>; 1180 nvidia,hssquelch-level = <2>; 1181 nvidia,hsdiscon-level = <5>; 1182 nvidia,xcvr-hsslew = <12>; 1183 status = "disabled"; 1184 }; 1185 1186 usb@7d008000 { 1187 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1188 reg = <0x0 0x7d008000 0x0 0x4000>; 1189 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1190 phy_type = "utmi"; 1191 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1192 clock-names = "usb"; 1193 resets = <&tegra_car 59>; 1194 reset-names = "usb"; 1195 nvidia,phy = <&phy3>; 1196 status = "disabled"; 1197 }; 1198 1199 phy3: usb-phy@7d008000 { 1200 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1201 reg = <0x0 0x7d008000 0x0 0x4000>, 1202 <0x0 0x7d000000 0x0 0x4000>; 1203 phy_type = "utmi"; 1204 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1205 <&tegra_car TEGRA124_CLK_PLL_U>, 1206 <&tegra_car TEGRA124_CLK_USBD>; 1207 clock-names = "reg", "pll_u", "utmi-pads"; 1208 resets = <&tegra_car 59>, <&tegra_car 22>; 1209 reset-names = "usb", "utmi-pads"; 1210 #phy-cells = <0>; 1211 nvidia,hssync-start-delay = <0>; 1212 nvidia,idle-wait-delay = <17>; 1213 nvidia,elastic-limit = <16>; 1214 nvidia,term-range-adj = <6>; 1215 nvidia,xcvr-setup = <9>; 1216 nvidia,xcvr-lsfslew = <0>; 1217 nvidia,xcvr-lsrslew = <3>; 1218 nvidia,hssquelch-level = <2>; 1219 nvidia,hsdiscon-level = <5>; 1220 nvidia,xcvr-hsslew = <12>; 1221 status = "disabled"; 1222 }; 1223 1224 cpus { 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 1228 cpu@0 { 1229 device_type = "cpu"; 1230 compatible = "nvidia,denver"; 1231 reg = <0>; 1232 }; 1233 1234 cpu@1 { 1235 device_type = "cpu"; 1236 compatible = "nvidia,denver"; 1237 reg = <1>; 1238 }; 1239 }; 1240 1241 timer { 1242 compatible = "arm,armv7-timer"; 1243 interrupts = <GIC_PPI 13 1244 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1245 <GIC_PPI 14 1246 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1247 <GIC_PPI 11 1248 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1249 <GIC_PPI 10 1250 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1251 interrupt-parent = <&gic>; 1252 }; 1253}; 1254