1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Copyright (c) 2019 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8516-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/phy/phy.h>
12
13#include "mt8516-pinfunc.h"
14
15/ {
16	compatible = "mediatek,mt8516";
17	interrupt-parent = <&sysirq>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	cluster0_opp: opp-table-0 {
22		compatible = "operating-points-v2";
23		opp-shared;
24		opp-598000000 {
25			opp-hz = /bits/ 64 <598000000>;
26			opp-microvolt = <1150000>;
27		};
28		opp-747500000 {
29			opp-hz = /bits/ 64 <747500000>;
30			opp-microvolt = <1150000>;
31		};
32		opp-1040000000 {
33			opp-hz = /bits/ 64 <1040000000>;
34			opp-microvolt = <1200000>;
35		};
36		opp-1196000000 {
37			opp-hz = /bits/ 64 <1196000000>;
38			opp-microvolt = <1250000>;
39		};
40		opp-1300000000 {
41			opp-hz = /bits/ 64 <1300000000>;
42			opp-microvolt = <1300000>;
43		};
44	};
45
46	cpus {
47		#address-cells = <1>;
48		#size-cells = <0>;
49
50		cpu0: cpu@0 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a35";
53			reg = <0x0>;
54			enable-method = "psci";
55			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
56				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
57			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
58				 <&topckgen CLK_TOP_MAINPLL_D2>;
59			clock-names = "cpu", "intermediate";
60			operating-points-v2 = <&cluster0_opp>;
61		};
62
63		cpu1: cpu@1 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a35";
66			reg = <0x1>;
67			enable-method = "psci";
68			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
69				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
70			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
71				 <&topckgen CLK_TOP_MAINPLL_D2>;
72			clock-names = "cpu", "intermediate";
73			operating-points-v2 = <&cluster0_opp>;
74		};
75
76		cpu2: cpu@2 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a35";
79			reg = <0x2>;
80			enable-method = "psci";
81			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
82				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
83			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
84				 <&topckgen CLK_TOP_MAINPLL_D2>;
85			clock-names = "cpu", "intermediate";
86			operating-points-v2 = <&cluster0_opp>;
87		};
88
89		cpu3: cpu@3 {
90			device_type = "cpu";
91			compatible = "arm,cortex-a35";
92			reg = <0x3>;
93			enable-method = "psci";
94			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
95				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
96			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
97				 <&topckgen CLK_TOP_MAINPLL_D2>;
98			clock-names = "cpu", "intermediate", "armpll";
99			operating-points-v2 = <&cluster0_opp>;
100		};
101
102		idle-states {
103			entry-method = "psci";
104
105			CPU_SLEEP_0_0: cpu-sleep-0-0 {
106				compatible = "arm,idle-state";
107				entry-latency-us = <600>;
108				exit-latency-us = <600>;
109				min-residency-us = <1200>;
110				arm,psci-suspend-param = <0x0010000>;
111			};
112
113			CLUSTER_SLEEP_0: cluster-sleep-0 {
114				compatible = "arm,idle-state";
115				entry-latency-us = <800>;
116				exit-latency-us = <1000>;
117				min-residency-us = <2000>;
118				arm,psci-suspend-param = <0x2010000>;
119			};
120		};
121	};
122
123	psci {
124		compatible = "arm,psci-1.0";
125		method = "smc";
126	};
127
128	clk26m: clk26m {
129		compatible = "fixed-clock";
130		#clock-cells = <0>;
131		clock-frequency = <26000000>;
132		clock-output-names = "clk26m";
133	};
134
135	clk32k: clk32k {
136		compatible = "fixed-clock";
137		#clock-cells = <0>;
138		clock-frequency = <32000>;
139		clock-output-names = "clk32k";
140	};
141
142	reserved-memory {
143		#address-cells = <2>;
144		#size-cells = <2>;
145		ranges;
146
147		/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
148		bl31_secmon_reserved: secmon@43000000 {
149			no-map;
150			reg = <0 0x43000000 0 0x20000>;
151		};
152	};
153
154	timer {
155		compatible = "arm,armv8-timer";
156		interrupt-parent = <&gic>;
157		interrupts = <GIC_PPI 13
158			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
159			     <GIC_PPI 14
160			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
161			     <GIC_PPI 11
162			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
163			     <GIC_PPI 10
164			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
165	};
166
167	pmu {
168		compatible = "arm,armv8-pmuv3";
169		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
170			     <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
171			     <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
172			     <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
173		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
174	};
175
176	soc {
177		#address-cells = <2>;
178		#size-cells = <2>;
179		compatible = "simple-bus";
180		ranges;
181
182		topckgen: topckgen@10000000 {
183			compatible = "mediatek,mt8516-topckgen", "syscon";
184			reg = <0 0x10000000 0 0x1000>;
185			#clock-cells = <1>;
186		};
187
188		infracfg: infracfg@10001000 {
189			compatible = "mediatek,mt8516-infracfg", "syscon";
190			reg = <0 0x10001000 0 0x1000>;
191			#clock-cells = <1>;
192		};
193
194		pericfg: pericfg@10003050 {
195			compatible = "mediatek,mt8516-pericfg", "syscon";
196			reg = <0 0x10003050 0 0x1000>;
197		};
198
199		apmixedsys: apmixedsys@10018000 {
200			compatible = "mediatek,mt8516-apmixedsys", "syscon";
201			reg = <0 0x10018000 0 0x710>;
202			#clock-cells = <1>;
203		};
204
205		toprgu: toprgu@10007000 {
206			compatible = "mediatek,mt8516-wdt",
207				     "mediatek,mt6589-wdt";
208			reg = <0 0x10007000 0 0x1000>;
209			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
210			#reset-cells = <1>;
211		};
212
213		timer: timer@10008000 {
214			compatible = "mediatek,mt8516-timer",
215				     "mediatek,mt6577-timer";
216			reg = <0 0x10008000 0 0x1000>;
217			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
218			clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219				 <&topckgen CLK_TOP_APXGPT>;
220			clock-names = "clk13m", "bus";
221		};
222
223		syscfg_pctl: syscfg-pctl@10005000 {
224			compatible = "syscon";
225			reg = <0 0x10005000 0 0x1000>;
226		};
227
228		pio: pinctrl@1000b000 {
229			compatible = "mediatek,mt8516-pinctrl";
230			reg = <0 0x1000b000 0 0x1000>;
231			mediatek,pctl-regmap = <&syscfg_pctl>;
232			pins-are-numbered;
233			gpio-controller;
234			#gpio-cells = <2>;
235			interrupt-controller;
236			#interrupt-cells = <2>;
237			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
238		};
239
240		efuse: efuse@10009000 {
241			compatible = "mediatek,mt8516-efuse", "mediatek,efuse";
242			reg = <0 0x10009000 0 0x1000>;
243			#address-cells = <1>;
244			#size-cells = <1>;
245		};
246
247		pwrap: pwrap@1000f000 {
248			compatible = "mediatek,mt8516-pwrap";
249			reg = <0 0x1000f000 0 0x1000>;
250			reg-names = "pwrap";
251			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
252			clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
253				 <&topckgen CLK_TOP_PMICWRAP_AP>;
254			clock-names = "spi", "wrap";
255		};
256
257		sysirq: interrupt-controller@10200620 {
258			compatible = "mediatek,mt8516-sysirq",
259				     "mediatek,mt6577-sysirq";
260			interrupt-controller;
261			#interrupt-cells = <3>;
262			interrupt-parent = <&gic>;
263			reg = <0 0x10200620 0 0x20>;
264		};
265
266		gic: interrupt-controller@10310000 {
267			compatible = "arm,gic-400";
268			#interrupt-cells = <3>;
269			interrupt-parent = <&gic>;
270			interrupt-controller;
271			reg = <0 0x10310000 0 0x1000>,
272			      <0 0x10320000 0 0x1000>,
273			      <0 0x10340000 0 0x2000>,
274			      <0 0x10360000 0 0x2000>;
275			interrupts = <GIC_PPI 9
276				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
277		};
278
279		apdma: dma-controller@11000480 {
280			compatible = "mediatek,mt8516-uart-dma",
281				     "mediatek,mt6577-uart-dma";
282			reg = <0 0x11000480 0 0x80>,
283			      <0 0x11000500 0 0x80>,
284			      <0 0x11000580 0 0x80>,
285			      <0 0x11000600 0 0x80>,
286			      <0 0x11000980 0 0x80>,
287			      <0 0x11000a00 0 0x80>;
288			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
289				     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>,
290				     <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>,
291				     <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>,
292				     <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>,
293				     <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
294			dma-requests = <6>;
295			clocks = <&topckgen CLK_TOP_APDMA>;
296			clock-names = "apdma";
297			#dma-cells = <1>;
298		};
299
300		uart0: serial@11005000 {
301			compatible = "mediatek,mt8516-uart",
302				     "mediatek,mt6577-uart";
303			reg = <0 0x11005000 0 0x1000>;
304			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
305			clocks = <&topckgen CLK_TOP_UART0_SEL>,
306				 <&topckgen CLK_TOP_UART0>;
307			clock-names = "baud", "bus";
308			dmas = <&apdma 0
309				&apdma 1>;
310			dma-names = "tx", "rx";
311			status = "disabled";
312		};
313
314		uart1: serial@11006000 {
315			compatible = "mediatek,mt8516-uart",
316				     "mediatek,mt6577-uart";
317			reg = <0 0x11006000 0 0x1000>;
318			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
319			clocks = <&topckgen CLK_TOP_UART1_SEL>,
320				 <&topckgen CLK_TOP_UART1>;
321			clock-names = "baud", "bus";
322			dmas = <&apdma 2
323				&apdma 3>;
324			dma-names = "tx", "rx";
325			status = "disabled";
326		};
327
328		uart2: serial@11007000 {
329			compatible = "mediatek,mt8516-uart",
330				     "mediatek,mt6577-uart";
331			reg = <0 0x11007000 0 0x1000>;
332			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
333			clocks = <&topckgen CLK_TOP_UART2_SEL>,
334				 <&topckgen CLK_TOP_UART2>;
335			clock-names = "baud", "bus";
336			dmas = <&apdma 4
337				&apdma 5>;
338			dma-names = "tx", "rx";
339			status = "disabled";
340		};
341
342		i2c0: i2c@11009000 {
343			compatible = "mediatek,mt8516-i2c",
344				     "mediatek,mt2712-i2c";
345			reg = <0 0x11009000 0 0x90>,
346			      <0 0x11000180 0 0x80>;
347			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
348			clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
349				 <&infracfg CLK_IFR_I2C0_SEL>,
350				 <&topckgen CLK_TOP_I2C0>,
351				 <&topckgen CLK_TOP_APDMA>;
352			clock-names = "main-source",
353				      "main-sel",
354				      "main",
355				      "dma";
356			#address-cells = <1>;
357			#size-cells = <0>;
358			status = "disabled";
359		};
360
361		i2c1: i2c@1100a000 {
362			compatible = "mediatek,mt8516-i2c",
363				     "mediatek,mt2712-i2c";
364			reg = <0 0x1100a000 0 0x90>,
365			      <0 0x11000200 0 0x80>;
366			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
367			clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
368				 <&infracfg CLK_IFR_I2C1_SEL>,
369				 <&topckgen CLK_TOP_I2C1>,
370				 <&topckgen CLK_TOP_APDMA>;
371			clock-names = "main-source",
372				      "main-sel",
373				      "main",
374				      "dma";
375			#address-cells = <1>;
376			#size-cells = <0>;
377			status = "disabled";
378		};
379
380		i2c2: i2c@1100b000 {
381			compatible = "mediatek,mt8516-i2c",
382				     "mediatek,mt2712-i2c";
383			reg = <0 0x1100b000 0 0x90>,
384			      <0 0x11000280 0 0x80>;
385			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
386			clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
387				 <&infracfg CLK_IFR_I2C2_SEL>,
388				 <&topckgen CLK_TOP_I2C2>,
389				 <&topckgen CLK_TOP_APDMA>;
390			clock-names = "main-source",
391				      "main-sel",
392				      "main",
393				      "dma";
394			#address-cells = <1>;
395			#size-cells = <0>;
396			status = "disabled";
397		};
398
399		spi: spi@1100c000 {
400			compatible = "mediatek,mt8516-spi",
401				     "mediatek,mt2712-spi";
402			#address-cells = <1>;
403			#size-cells = <0>;
404			reg = <0 0x1100c000 0 0x1000>;
405			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
406			clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
407				 <&topckgen CLK_TOP_SPI_SEL>,
408				 <&topckgen CLK_TOP_SPI>;
409			clock-names = "parent-clk", "sel-clk", "spi-clk";
410			status = "disabled";
411		};
412
413		mmc0: mmc@11120000 {
414			compatible = "mediatek,mt8516-mmc";
415			reg = <0 0x11120000 0 0x1000>;
416			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
417			clocks = <&topckgen CLK_TOP_MSDC0>,
418				 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
419				 <&topckgen CLK_TOP_MSDC0_INFRA>;
420			clock-names = "source", "hclk", "source_cg";
421			status = "disabled";
422		};
423
424		mmc1: mmc@11130000 {
425			compatible = "mediatek,mt8516-mmc";
426			reg = <0 0x11130000 0 0x1000>;
427			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
428			clocks = <&topckgen CLK_TOP_MSDC1>,
429				 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
430				 <&topckgen CLK_TOP_MSDC1_INFRA>;
431			clock-names = "source", "hclk", "source_cg";
432			status = "disabled";
433		};
434
435		mmc2: mmc@11170000 {
436			compatible = "mediatek,mt8516-mmc";
437			reg = <0 0x11170000 0 0x1000>;
438			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
439			clocks = <&topckgen CLK_TOP_MSDC2>,
440				 <&topckgen CLK_TOP_RG_MSDC2>,
441				 <&topckgen CLK_TOP_MSDC2_INFRA>;
442			clock-names = "source", "hclk", "source_cg";
443			status = "disabled";
444		};
445
446		ethernet: ethernet@11180000 {
447			compatible = "mediatek,mt8516-eth";
448			reg = <0 0x11180000 0 0x1000>;
449			mediatek,pericfg = <&pericfg>;
450			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
451			clocks = <&topckgen CLK_TOP_RG_ETH>,
452				 <&topckgen CLK_TOP_66M_ETH>,
453				 <&topckgen CLK_TOP_133M_ETH>;
454			clock-names = "core", "reg", "trans";
455			status = "disabled";
456		};
457
458		rng: rng@1020c000 {
459			compatible = "mediatek,mt8516-rng",
460				     "mediatek,mt7623-rng";
461			reg = <0 0x1020c000 0 0x100>;
462			clocks = <&topckgen CLK_TOP_TRNG>;
463			clock-names = "rng";
464		};
465
466		pwm: pwm@11008000 {
467			compatible = "mediatek,mt8516-pwm";
468			reg = <0 0x11008000 0 0x1000>;
469			#pwm-cells = <2>;
470			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
471			clocks = <&topckgen CLK_TOP_PWM>,
472				 <&topckgen CLK_TOP_PWM_B>,
473				 <&topckgen CLK_TOP_PWM1_FB>,
474				 <&topckgen CLK_TOP_PWM2_FB>,
475				 <&topckgen CLK_TOP_PWM3_FB>,
476				 <&topckgen CLK_TOP_PWM4_FB>,
477				 <&topckgen CLK_TOP_PWM5_FB>;
478			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
479				      "pwm4", "pwm5";
480		};
481
482		usb0: usb@11100000 {
483			compatible = "mediatek,mtk-musb";
484			reg = <0 0x11100000 0 0x1000>;
485			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
486			interrupt-names = "mc";
487			phys = <&usb0_port PHY_TYPE_USB2>;
488			clocks = <&topckgen CLK_TOP_USB>,
489				 <&topckgen CLK_TOP_USBIF>,
490				 <&topckgen CLK_TOP_USB_1P>;
491			clock-names = "main","mcu","univpll";
492			status = "disabled";
493		};
494
495		usb1: usb@11190000 {
496			compatible = "mediatek,mtk-musb";
497			reg = <0 0x11190000 0 0x1000>;
498			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
499			interrupt-names = "mc";
500			phys = <&usb1_port PHY_TYPE_USB2>;
501			clocks = <&topckgen CLK_TOP_USB>,
502				 <&topckgen CLK_TOP_USBIF>,
503				 <&topckgen CLK_TOP_USB_1P>;
504			clock-names = "main","mcu","univpll";
505			dr_mode = "host";
506			status = "disabled";
507		};
508
509		usb_phy: usb@11110000 {
510			compatible = "mediatek,generic-tphy-v1";
511			reg = <0 0x11110000 0 0x800>;
512			#address-cells = <2>;
513			#size-cells = <2>;
514			ranges;
515			status = "disabled";
516
517			usb0_port: usb-phy@11110800 {
518				reg = <0 0x11110800 0 0x100>;
519				clocks = <&topckgen CLK_TOP_USB_PHY48M>;
520				clock-names = "ref";
521				#phy-cells = <1>;
522			};
523
524			usb1_port: usb-phy@11110900 {
525				reg = <0 0x11110900 0 0x100>;
526				clocks = <&topckgen CLK_TOP_USB_PHY48M>;
527				clock-names = "ref";
528				#phy-cells = <1>;
529			};
530		};
531
532		auxadc: adc@11003000 {
533			compatible = "mediatek,mt8516-auxadc",
534				     "mediatek,mt8173-auxadc";
535			reg = <0 0x11003000 0 0x1000>;
536			clocks = <&topckgen CLK_TOP_AUX_ADC>;
537			clock-names = "main";
538			#io-channel-cells = <1>;
539			status = "disabled";
540		};
541	};
542};
543