1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * (C) 2018 MediaTek Inc.
4 * Copyright (C) 2022 BayLibre SAS
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 */
8#include <dt-bindings/clock/mediatek,mt8365-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/phy/phy.h>
12
13/ {
14	compatible = "mediatek,mt8365";
15	interrupt-parent = <&sysirq>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu-map {
24			cluster0 {
25				core0 {
26					cpu = <&cpu0>;
27				};
28				core1 {
29					cpu = <&cpu1>;
30				};
31				core2 {
32					cpu = <&cpu2>;
33				};
34				core3 {
35					cpu = <&cpu3>;
36				};
37			};
38		};
39
40		cpu0: cpu@0 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a53";
43			reg = <0x0>;
44			#cooling-cells = <2>;
45			enable-method = "psci";
46			i-cache-size = <0x8000>;
47			i-cache-line-size = <64>;
48			i-cache-sets = <256>;
49			d-cache-size = <0x8000>;
50			d-cache-line-size = <64>;
51			d-cache-sets = <256>;
52			next-level-cache = <&l2>;
53		};
54
55		cpu1: cpu@1 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53";
58			reg = <0x1>;
59			#cooling-cells = <2>;
60			enable-method = "psci";
61			i-cache-size = <0x8000>;
62			i-cache-line-size = <64>;
63			i-cache-sets = <256>;
64			d-cache-size = <0x8000>;
65			d-cache-line-size = <64>;
66			d-cache-sets = <256>;
67			next-level-cache = <&l2>;
68		};
69
70		cpu2: cpu@2 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a53";
73			reg = <0x2>;
74			#cooling-cells = <2>;
75			enable-method = "psci";
76			i-cache-size = <0x8000>;
77			i-cache-line-size = <64>;
78			i-cache-sets = <256>;
79			d-cache-size = <0x8000>;
80			d-cache-line-size = <64>;
81			d-cache-sets = <256>;
82			next-level-cache = <&l2>;
83		};
84
85		cpu3: cpu@3 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a53";
88			reg = <0x3>;
89			#cooling-cells = <2>;
90			enable-method = "psci";
91			i-cache-size = <0x8000>;
92			i-cache-line-size = <64>;
93			i-cache-sets = <256>;
94			d-cache-size = <0x8000>;
95			d-cache-line-size = <64>;
96			d-cache-sets = <256>;
97			next-level-cache = <&l2>;
98		};
99
100		l2: l2-cache {
101			compatible = "cache";
102			cache-level = <2>;
103			cache-size = <0x80000>;
104			cache-line-size = <64>;
105			cache-sets = <512>;
106			cache-unified;
107		};
108	};
109
110	clk26m: oscillator {
111		compatible = "fixed-clock";
112		#clock-cells = <0>;
113		clock-frequency = <26000000>;
114		clock-output-names = "clk26m";
115	};
116
117	psci {
118		compatible = "arm,psci-1.0";
119		method = "smc";
120	};
121
122	soc {
123		#address-cells = <2>;
124		#size-cells = <2>;
125		compatible = "simple-bus";
126		ranges;
127
128		gic: interrupt-controller@c000000 {
129			compatible = "arm,gic-v3";
130			#interrupt-cells = <3>;
131			interrupt-parent = <&gic>;
132			interrupt-controller;
133			reg = <0 0x0c000000 0 0x10000>, /* GICD */
134			      <0 0x0c080000 0 0x80000>, /* GICR */
135			      <0 0x0c400000 0 0x2000>,  /* GICC */
136			      <0 0x0c410000 0 0x1000>,  /* GICH */
137			      <0 0x0c420000 0 0x2000>;  /* GICV */
138
139			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
140		};
141
142		topckgen: syscon@10000000 {
143			compatible = "mediatek,mt8365-topckgen", "syscon";
144			reg = <0 0x10000000 0 0x1000>;
145			#clock-cells = <1>;
146		};
147
148		infracfg: syscon@10001000 {
149			compatible = "mediatek,mt8365-infracfg", "syscon";
150			reg = <0 0x10001000 0 0x1000>;
151			#clock-cells = <1>;
152		};
153
154		pericfg: syscon@10003000 {
155			compatible = "mediatek,mt8365-pericfg", "syscon";
156			reg = <0 0x10003000 0 0x1000>;
157			#clock-cells = <1>;
158		};
159
160		syscfg_pctl: syscfg-pctl@10005000 {
161			compatible = "mediatek,mt8365-syscfg", "syscon";
162			reg = <0 0x10005000 0 0x1000>;
163		};
164
165		pio: pinctrl@1000b000 {
166			compatible = "mediatek,mt8365-pinctrl";
167			reg = <0 0x1000b000 0 0x1000>;
168			mediatek,pctl-regmap = <&syscfg_pctl>;
169			gpio-controller;
170			#gpio-cells = <2>;
171			interrupt-controller;
172			#interrupt-cells = <2>;
173			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
174		};
175
176		apmixedsys: syscon@1000c000 {
177			compatible = "mediatek,mt8365-apmixedsys", "syscon";
178			reg = <0 0x1000c000 0 0x1000>;
179			#clock-cells = <1>;
180		};
181
182		pwrap: pwrap@1000d000 {
183			compatible = "mediatek,mt8365-pwrap";
184			reg = <0 0x1000d000 0 0x1000>;
185			reg-names = "pwrap";
186			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
187			clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
188				 <&infracfg CLK_IFR_PMIC_AP>,
189				 <&infracfg CLK_IFR_PWRAP_SYS>,
190				 <&infracfg CLK_IFR_PWRAP_TMR>;
191			clock-names = "spi", "wrap", "sys", "tmr";
192		};
193
194		keypad: keypad@10010000 {
195			compatible = "mediatek,mt6779-keypad";
196			reg = <0 0x10010000 0 0x1000>;
197			wakeup-source;
198			interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
199			clocks = <&clk26m>;
200			clock-names = "kpd";
201			status = "disabled";
202		};
203
204		mcucfg: syscon@10200000 {
205			compatible = "mediatek,mt8365-mcucfg", "syscon";
206			reg = <0 0x10200000 0 0x2000>;
207			#clock-cells = <1>;
208		};
209
210		sysirq: interrupt-controller@10200a80 {
211			compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
212			interrupt-controller;
213			#interrupt-cells = <3>;
214			interrupt-parent = <&gic>;
215			reg = <0 0x10200a80 0 0x20>;
216		};
217
218		infracfg_nao: infracfg@1020e000 {
219			compatible = "mediatek,mt8365-infracfg", "syscon";
220			reg = <0 0x1020e000 0 0x1000>;
221			#clock-cells = <1>;
222		};
223
224		rng: rng@1020f000 {
225			compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
226			reg = <0 0x1020f000 0 0x100>;
227			clocks = <&infracfg CLK_IFR_TRNG>;
228			clock-names = "rng";
229		};
230
231		apdma: dma-controller@11000280 {
232			compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
233			reg = <0 0x11000280 0 0x80>,
234			      <0 0x11000300 0 0x80>,
235			      <0 0x11000380 0 0x80>,
236			      <0 0x11000400 0 0x80>,
237			      <0 0x11000580 0 0x80>,
238			      <0 0x11000600 0 0x80>;
239			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
240				     <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
241				     <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
242				     <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
243				     <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
244				     <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
245			dma-requests = <6>;
246			clocks = <&infracfg CLK_IFR_AP_DMA>;
247			clock-names = "apdma";
248			#dma-cells = <1>;
249		};
250
251		uart0: serial@11002000 {
252			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
253			reg = <0 0x11002000 0 0x1000>;
254			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
255			clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
256			clock-names = "baud", "bus";
257			dmas = <&apdma 0>, <&apdma 1>;
258			dma-names = "tx", "rx";
259			status = "disabled";
260		};
261
262		uart1: serial@11003000 {
263			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
264			reg = <0 0x11003000 0 0x1000>;
265			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
266			clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
267			clock-names = "baud", "bus";
268			dmas = <&apdma 2>, <&apdma 3>;
269			dma-names = "tx", "rx";
270			status = "disabled";
271		};
272
273		uart2: serial@11004000 {
274			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
275			reg = <0 0x11004000 0 0x1000>;
276			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
277			clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
278			clock-names = "baud", "bus";
279			dmas = <&apdma 4>, <&apdma 5>;
280			dma-names = "tx", "rx";
281			status = "disabled";
282		};
283
284		pwm: pwm@11006000 {
285			compatible = "mediatek,mt8365-pwm";
286			reg = <0 0x11006000 0 0x1000>;
287			#pwm-cells = <2>;
288			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
289			clocks = <&infracfg CLK_IFR_PWM_HCLK>,
290				 <&infracfg CLK_IFR_PWM>,
291				 <&infracfg CLK_IFR_PWM1>,
292				 <&infracfg CLK_IFR_PWM2>,
293				 <&infracfg CLK_IFR_PWM3>;
294			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
295		};
296
297		i2c0: i2c@11007000 {
298			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
299			reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
300			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
301			clock-div = <1>;
302			clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
303			clock-names = "main", "dma";
304			#address-cells = <1>;
305			#size-cells = <0>;
306			status = "disabled";
307		};
308
309		i2c1: i2c@11008000 {
310			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
311			reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
312			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
313			clock-div = <1>;
314			clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
315			clock-names = "main", "dma";
316			#address-cells = <1>;
317			#size-cells = <0>;
318			status = "disabled";
319		};
320
321		i2c2: i2c@11009000 {
322			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
323			reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
324			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
325			clock-div = <1>;
326			clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
327			clock-names = "main", "dma";
328			#address-cells = <1>;
329			#size-cells = <0>;
330			status = "disabled";
331		};
332
333		spi: spi@1100a000 {
334			compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
335			reg = <0 0x1100a000 0 0x100>;
336			#address-cells = <1>;
337			#size-cells = <0>;
338			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
339			clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
340				 <&topckgen CLK_TOP_SPI_SEL>,
341				 <&infracfg CLK_IFR_SPI0>;
342			clock-names = "parent-clk", "sel-clk", "spi-clk";
343			status = "disabled";
344		};
345
346		i2c3: i2c@1100f000 {
347			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
348			reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
349			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
350			clock-div = <1>;
351			clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
352			clock-names = "main", "dma";
353			#address-cells = <1>;
354			#size-cells = <0>;
355			status = "disabled";
356		};
357
358		ssusb: usb@11201000 {
359			compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
360			reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
361			reg-names = "mac", "ippc";
362			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
363			phys = <&u2port0 PHY_TYPE_USB2>,
364			       <&u2port1 PHY_TYPE_USB2>;
365			clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
366				 <&infracfg CLK_IFR_SSUSB_REF>,
367				 <&infracfg CLK_IFR_SSUSB_SYS>,
368				 <&infracfg CLK_IFR_ICUSB>;
369			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
370			#address-cells = <2>;
371			#size-cells = <2>;
372			ranges;
373			status = "disabled";
374
375			usb_host: usb@11200000 {
376				compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
377				reg = <0 0x11200000 0 0x1000>;
378				reg-names = "mac";
379				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
380				clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
381					 <&infracfg CLK_IFR_SSUSB_REF>,
382					 <&infracfg CLK_IFR_SSUSB_SYS>,
383					 <&infracfg CLK_IFR_ICUSB>,
384					 <&infracfg CLK_IFR_SSUSB_XHCI>;
385				clock-names = "sys_ck", "ref_ck", "mcu_ck",
386					      "dma_ck", "xhci_ck";
387				status = "disabled";
388			};
389		};
390
391		mmc0: mmc@11230000 {
392			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
393			reg = <0 0x11230000 0 0x1000>,
394			      <0 0x11cd0000 0 0x1000>;
395			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
396			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
397				 <&infracfg CLK_IFR_MSDC0_HCLK>,
398				 <&infracfg CLK_IFR_MSDC0_SRC>;
399			clock-names = "source", "hclk", "source_cg";
400			status = "disabled";
401		};
402
403		mmc1: mmc@11240000 {
404			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
405			reg = <0 0x11240000 0 0x1000>,
406			      <0 0x11c90000 0 0x1000>;
407			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
408			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
409				 <&infracfg CLK_IFR_MSDC1_HCLK>,
410				 <&infracfg CLK_IFR_MSDC1_SRC>;
411			clock-names = "source", "hclk", "source_cg";
412			status = "disabled";
413		};
414
415		mmc2: mmc@11250000 {
416			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
417			reg = <0 0x11250000 0 0x1000>,
418			      <0 0x11c60000 0 0x1000>;
419			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
420			clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
421				 <&infracfg CLK_IFR_MSDC2_HCLK>,
422				 <&infracfg CLK_IFR_MSDC2_SRC>,
423				 <&infracfg CLK_IFR_MSDC2_BK>,
424				 <&infracfg CLK_IFR_AP_MSDC0>;
425			clock-names = "source", "hclk", "source_cg",
426				      "bus_clk", "sys_cg";
427			status = "disabled";
428		};
429
430		ethernet: ethernet@112a0000 {
431			compatible = "mediatek,mt8365-eth";
432			reg = <0 0x112a0000 0 0x1000>;
433			mediatek,pericfg = <&infracfg>;
434			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
435			clocks = <&topckgen CLK_TOP_ETH_SEL>,
436				 <&infracfg CLK_IFR_NIC_AXI>,
437				 <&infracfg CLK_IFR_NIC_SLV_AXI>;
438			clock-names = "core", "reg", "trans";
439			status = "disabled";
440		};
441
442		u3phy: t-phy@11cc0000 {
443			compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
444			#address-cells = <1>;
445			#size-cells = <1>;
446			ranges = <0 0 0x11cc0000 0x9000>;
447
448			u2port0: usb-phy@0 {
449				reg = <0x0 0x400>;
450				clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
451					 <&topckgen CLK_TOP_USB20_48M_EN>;
452				clock-names = "ref", "da_ref";
453				#phy-cells = <1>;
454			};
455
456			u2port1: usb-phy@1000 {
457				reg = <0x1000 0x400>;
458				clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
459					 <&topckgen CLK_TOP_USB20_48M_EN>;
460				clock-names = "ref", "da_ref";
461				#phy-cells = <1>;
462			};
463		};
464	};
465
466	timer {
467		compatible = "arm,armv8-timer";
468		interrupt-parent = <&gic>;
469		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
470			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
471			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
472			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
473	};
474
475	system_clk: dummy13m {
476		compatible = "fixed-clock";
477		clock-frequency = <13000000>;
478		#clock-cells = <0>;
479	};
480
481	systimer: timer@10017000 {
482		compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
483		reg = <0 0x10017000 0 0x100>;
484		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
485		clocks = <&system_clk>;
486		clock-names = "clk13m";
487	};
488};
489