1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 */ 8#include <dt-bindings/clock/mediatek,mt8365-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12 13/ { 14 compatible = "mediatek,mt8365"; 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 core2 { 32 cpu = <&cpu2>; 33 }; 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0>; 44 #cooling-cells = <2>; 45 enable-method = "psci"; 46 i-cache-size = <0x8000>; 47 i-cache-line-size = <64>; 48 i-cache-sets = <256>; 49 d-cache-size = <0x8000>; 50 d-cache-line-size = <64>; 51 d-cache-sets = <256>; 52 next-level-cache = <&l2>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x1>; 59 #cooling-cells = <2>; 60 enable-method = "psci"; 61 i-cache-size = <0x8000>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <256>; 64 d-cache-size = <0x8000>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <256>; 67 next-level-cache = <&l2>; 68 }; 69 70 cpu2: cpu@2 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x2>; 74 #cooling-cells = <2>; 75 enable-method = "psci"; 76 i-cache-size = <0x8000>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <256>; 79 d-cache-size = <0x8000>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <256>; 82 next-level-cache = <&l2>; 83 }; 84 85 cpu3: cpu@3 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x3>; 89 #cooling-cells = <2>; 90 enable-method = "psci"; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <256>; 97 next-level-cache = <&l2>; 98 }; 99 100 l2: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 cache-size = <0x80000>; 104 cache-line-size = <64>; 105 cache-sets = <512>; 106 cache-unified; 107 }; 108 }; 109 110 clk26m: oscillator { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <26000000>; 114 clock-output-names = "clk26m"; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0"; 119 method = "smc"; 120 }; 121 122 soc { 123 #address-cells = <2>; 124 #size-cells = <2>; 125 compatible = "simple-bus"; 126 ranges; 127 128 gic: interrupt-controller@c000000 { 129 compatible = "arm,gic-v3"; 130 #interrupt-cells = <3>; 131 interrupt-parent = <&gic>; 132 interrupt-controller; 133 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 134 <0 0x0c080000 0 0x80000>, /* GICR */ 135 <0 0x0c400000 0 0x2000>, /* GICC */ 136 <0 0x0c410000 0 0x1000>, /* GICH */ 137 <0 0x0c420000 0 0x2000>; /* GICV */ 138 139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 140 }; 141 142 topckgen: syscon@10000000 { 143 compatible = "mediatek,mt8365-topckgen", "syscon"; 144 reg = <0 0x10000000 0 0x1000>; 145 #clock-cells = <1>; 146 }; 147 148 infracfg: syscon@10001000 { 149 compatible = "mediatek,mt8365-infracfg", "syscon"; 150 reg = <0 0x10001000 0 0x1000>; 151 #clock-cells = <1>; 152 }; 153 154 pericfg: syscon@10003000 { 155 compatible = "mediatek,mt8365-pericfg", "syscon"; 156 reg = <0 0x10003000 0 0x1000>; 157 #clock-cells = <1>; 158 }; 159 160 syscfg_pctl: syscfg-pctl@10005000 { 161 compatible = "mediatek,mt8365-syscfg", "syscon"; 162 reg = <0 0x10005000 0 0x1000>; 163 }; 164 165 watchdog: watchdog@10007000 { 166 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 167 reg = <0 0x10007000 0 0x100>; 168 #reset-cells = <1>; 169 }; 170 171 pio: pinctrl@1000b000 { 172 compatible = "mediatek,mt8365-pinctrl"; 173 reg = <0 0x1000b000 0 0x1000>; 174 mediatek,pctl-regmap = <&syscfg_pctl>; 175 gpio-controller; 176 #gpio-cells = <2>; 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 180 }; 181 182 apmixedsys: syscon@1000c000 { 183 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 184 reg = <0 0x1000c000 0 0x1000>; 185 #clock-cells = <1>; 186 }; 187 188 pwrap: pwrap@1000d000 { 189 compatible = "mediatek,mt8365-pwrap"; 190 reg = <0 0x1000d000 0 0x1000>; 191 reg-names = "pwrap"; 192 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 194 <&infracfg CLK_IFR_PMIC_AP>, 195 <&infracfg CLK_IFR_PWRAP_SYS>, 196 <&infracfg CLK_IFR_PWRAP_TMR>; 197 clock-names = "spi", "wrap", "sys", "tmr"; 198 }; 199 200 keypad: keypad@10010000 { 201 compatible = "mediatek,mt6779-keypad"; 202 reg = <0 0x10010000 0 0x1000>; 203 wakeup-source; 204 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 205 clocks = <&clk26m>; 206 clock-names = "kpd"; 207 status = "disabled"; 208 }; 209 210 mcucfg: syscon@10200000 { 211 compatible = "mediatek,mt8365-mcucfg", "syscon"; 212 reg = <0 0x10200000 0 0x2000>; 213 #clock-cells = <1>; 214 }; 215 216 sysirq: interrupt-controller@10200a80 { 217 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 218 interrupt-controller; 219 #interrupt-cells = <3>; 220 interrupt-parent = <&gic>; 221 reg = <0 0x10200a80 0 0x20>; 222 }; 223 224 infracfg_nao: infracfg@1020e000 { 225 compatible = "mediatek,mt8365-infracfg", "syscon"; 226 reg = <0 0x1020e000 0 0x1000>; 227 #clock-cells = <1>; 228 }; 229 230 rng: rng@1020f000 { 231 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 232 reg = <0 0x1020f000 0 0x100>; 233 clocks = <&infracfg CLK_IFR_TRNG>; 234 clock-names = "rng"; 235 }; 236 237 apdma: dma-controller@11000280 { 238 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 239 reg = <0 0x11000280 0 0x80>, 240 <0 0x11000300 0 0x80>, 241 <0 0x11000380 0 0x80>, 242 <0 0x11000400 0 0x80>, 243 <0 0x11000580 0 0x80>, 244 <0 0x11000600 0 0x80>; 245 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 246 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 247 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 248 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 249 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 250 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 251 dma-requests = <6>; 252 clocks = <&infracfg CLK_IFR_AP_DMA>; 253 clock-names = "apdma"; 254 #dma-cells = <1>; 255 }; 256 257 uart0: serial@11002000 { 258 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 259 reg = <0 0x11002000 0 0x1000>; 260 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 261 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 262 clock-names = "baud", "bus"; 263 dmas = <&apdma 0>, <&apdma 1>; 264 dma-names = "tx", "rx"; 265 status = "disabled"; 266 }; 267 268 uart1: serial@11003000 { 269 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 270 reg = <0 0x11003000 0 0x1000>; 271 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 272 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 273 clock-names = "baud", "bus"; 274 dmas = <&apdma 2>, <&apdma 3>; 275 dma-names = "tx", "rx"; 276 status = "disabled"; 277 }; 278 279 uart2: serial@11004000 { 280 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 281 reg = <0 0x11004000 0 0x1000>; 282 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 283 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 284 clock-names = "baud", "bus"; 285 dmas = <&apdma 4>, <&apdma 5>; 286 dma-names = "tx", "rx"; 287 status = "disabled"; 288 }; 289 290 pwm: pwm@11006000 { 291 compatible = "mediatek,mt8365-pwm"; 292 reg = <0 0x11006000 0 0x1000>; 293 #pwm-cells = <2>; 294 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 295 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 296 <&infracfg CLK_IFR_PWM>, 297 <&infracfg CLK_IFR_PWM1>, 298 <&infracfg CLK_IFR_PWM2>, 299 <&infracfg CLK_IFR_PWM3>; 300 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 301 }; 302 303 i2c0: i2c@11007000 { 304 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 305 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 306 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 307 clock-div = <1>; 308 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 309 clock-names = "main", "dma"; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 i2c1: i2c@11008000 { 316 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 317 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 318 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 319 clock-div = <1>; 320 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 321 clock-names = "main", "dma"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 }; 326 327 i2c2: i2c@11009000 { 328 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 329 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 330 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 331 clock-div = <1>; 332 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 333 clock-names = "main", "dma"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 spi: spi@1100a000 { 340 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 341 reg = <0 0x1100a000 0 0x100>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 345 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 346 <&topckgen CLK_TOP_SPI_SEL>, 347 <&infracfg CLK_IFR_SPI0>; 348 clock-names = "parent-clk", "sel-clk", "spi-clk"; 349 status = "disabled"; 350 }; 351 352 i2c3: i2c@1100f000 { 353 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 354 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 355 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 356 clock-div = <1>; 357 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 358 clock-names = "main", "dma"; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 status = "disabled"; 362 }; 363 364 ssusb: usb@11201000 { 365 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 366 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 367 reg-names = "mac", "ippc"; 368 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 369 phys = <&u2port0 PHY_TYPE_USB2>, 370 <&u2port1 PHY_TYPE_USB2>; 371 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 372 <&infracfg CLK_IFR_SSUSB_REF>, 373 <&infracfg CLK_IFR_SSUSB_SYS>, 374 <&infracfg CLK_IFR_ICUSB>; 375 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 376 #address-cells = <2>; 377 #size-cells = <2>; 378 ranges; 379 status = "disabled"; 380 381 usb_host: usb@11200000 { 382 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 383 reg = <0 0x11200000 0 0x1000>; 384 reg-names = "mac"; 385 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 386 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 387 <&infracfg CLK_IFR_SSUSB_REF>, 388 <&infracfg CLK_IFR_SSUSB_SYS>, 389 <&infracfg CLK_IFR_ICUSB>, 390 <&infracfg CLK_IFR_SSUSB_XHCI>; 391 clock-names = "sys_ck", "ref_ck", "mcu_ck", 392 "dma_ck", "xhci_ck"; 393 status = "disabled"; 394 }; 395 }; 396 397 mmc0: mmc@11230000 { 398 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 399 reg = <0 0x11230000 0 0x1000>, 400 <0 0x11cd0000 0 0x1000>; 401 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 402 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 403 <&infracfg CLK_IFR_MSDC0_HCLK>, 404 <&infracfg CLK_IFR_MSDC0_SRC>; 405 clock-names = "source", "hclk", "source_cg"; 406 status = "disabled"; 407 }; 408 409 mmc1: mmc@11240000 { 410 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 411 reg = <0 0x11240000 0 0x1000>, 412 <0 0x11c90000 0 0x1000>; 413 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 414 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 415 <&infracfg CLK_IFR_MSDC1_HCLK>, 416 <&infracfg CLK_IFR_MSDC1_SRC>; 417 clock-names = "source", "hclk", "source_cg"; 418 status = "disabled"; 419 }; 420 421 mmc2: mmc@11250000 { 422 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 423 reg = <0 0x11250000 0 0x1000>, 424 <0 0x11c60000 0 0x1000>; 425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 426 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 427 <&infracfg CLK_IFR_MSDC2_HCLK>, 428 <&infracfg CLK_IFR_MSDC2_SRC>, 429 <&infracfg CLK_IFR_MSDC2_BK>, 430 <&infracfg CLK_IFR_AP_MSDC0>; 431 clock-names = "source", "hclk", "source_cg", 432 "bus_clk", "sys_cg"; 433 status = "disabled"; 434 }; 435 436 ethernet: ethernet@112a0000 { 437 compatible = "mediatek,mt8365-eth"; 438 reg = <0 0x112a0000 0 0x1000>; 439 mediatek,pericfg = <&infracfg>; 440 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&topckgen CLK_TOP_ETH_SEL>, 442 <&infracfg CLK_IFR_NIC_AXI>, 443 <&infracfg CLK_IFR_NIC_SLV_AXI>; 444 clock-names = "core", "reg", "trans"; 445 status = "disabled"; 446 }; 447 448 u3phy: t-phy@11cc0000 { 449 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 ranges = <0 0 0x11cc0000 0x9000>; 453 454 u2port0: usb-phy@0 { 455 reg = <0x0 0x400>; 456 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 457 <&topckgen CLK_TOP_USB20_48M_EN>; 458 clock-names = "ref", "da_ref"; 459 #phy-cells = <1>; 460 }; 461 462 u2port1: usb-phy@1000 { 463 reg = <0x1000 0x400>; 464 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 465 <&topckgen CLK_TOP_USB20_48M_EN>; 466 clock-names = "ref", "da_ref"; 467 #phy-cells = <1>; 468 }; 469 }; 470 }; 471 472 timer { 473 compatible = "arm,armv8-timer"; 474 interrupt-parent = <&gic>; 475 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 476 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 477 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 478 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 479 }; 480 481 system_clk: dummy13m { 482 compatible = "fixed-clock"; 483 clock-frequency = <13000000>; 484 #clock-cells = <0>; 485 }; 486 487 systimer: timer@10017000 { 488 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 489 reg = <0 0x10017000 0 0x100>; 490 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&system_clk>; 492 clock-names = "clk13m"; 493 }; 494}; 495