1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 */ 8#include <dt-bindings/clock/mediatek,mt8365-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12 13/ { 14 compatible = "mediatek,mt8365"; 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 core2 { 32 cpu = <&cpu2>; 33 }; 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0>; 44 #cooling-cells = <2>; 45 enable-method = "psci"; 46 i-cache-size = <0x8000>; 47 i-cache-line-size = <64>; 48 i-cache-sets = <256>; 49 d-cache-size = <0x8000>; 50 d-cache-line-size = <64>; 51 d-cache-sets = <256>; 52 next-level-cache = <&l2>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x1>; 59 #cooling-cells = <2>; 60 enable-method = "psci"; 61 i-cache-size = <0x8000>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <256>; 64 d-cache-size = <0x8000>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <256>; 67 next-level-cache = <&l2>; 68 }; 69 70 cpu2: cpu@2 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x2>; 74 #cooling-cells = <2>; 75 enable-method = "psci"; 76 i-cache-size = <0x8000>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <256>; 79 d-cache-size = <0x8000>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <256>; 82 next-level-cache = <&l2>; 83 }; 84 85 cpu3: cpu@3 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x3>; 89 #cooling-cells = <2>; 90 enable-method = "psci"; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <256>; 97 next-level-cache = <&l2>; 98 }; 99 100 l2: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 cache-size = <0x80000>; 104 cache-line-size = <64>; 105 cache-sets = <512>; 106 cache-unified; 107 }; 108 }; 109 110 clk26m: oscillator { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <26000000>; 114 clock-output-names = "clk26m"; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0"; 119 method = "smc"; 120 }; 121 122 soc { 123 #address-cells = <2>; 124 #size-cells = <2>; 125 compatible = "simple-bus"; 126 ranges; 127 128 gic: interrupt-controller@c000000 { 129 compatible = "arm,gic-v3"; 130 #interrupt-cells = <3>; 131 interrupt-parent = <&gic>; 132 interrupt-controller; 133 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 134 <0 0x0c080000 0 0x80000>, /* GICR */ 135 <0 0x0c400000 0 0x2000>, /* GICC */ 136 <0 0x0c410000 0 0x1000>, /* GICH */ 137 <0 0x0c420000 0 0x2000>; /* GICV */ 138 139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 140 }; 141 142 topckgen: syscon@10000000 { 143 compatible = "mediatek,mt8365-topckgen", "syscon"; 144 reg = <0 0x10000000 0 0x1000>; 145 #clock-cells = <1>; 146 }; 147 148 infracfg: syscon@10001000 { 149 compatible = "mediatek,mt8365-infracfg", "syscon"; 150 reg = <0 0x10001000 0 0x1000>; 151 #clock-cells = <1>; 152 }; 153 154 pericfg: syscon@10003000 { 155 compatible = "mediatek,mt8365-pericfg", "syscon"; 156 reg = <0 0x10003000 0 0x1000>; 157 #clock-cells = <1>; 158 }; 159 160 syscfg_pctl: syscfg-pctl@10005000 { 161 compatible = "mediatek,mt8365-syscfg", "syscon"; 162 reg = <0 0x10005000 0 0x1000>; 163 }; 164 165 pio: pinctrl@1000b000 { 166 compatible = "mediatek,mt8365-pinctrl"; 167 reg = <0 0x1000b000 0 0x1000>; 168 mediatek,pctl-regmap = <&syscfg_pctl>; 169 gpio-controller; 170 #gpio-cells = <2>; 171 interrupt-controller; 172 #interrupt-cells = <2>; 173 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 174 }; 175 176 apmixedsys: syscon@1000c000 { 177 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 178 reg = <0 0x1000c000 0 0x1000>; 179 #clock-cells = <1>; 180 }; 181 182 keypad: keypad@10010000 { 183 compatible = "mediatek,mt6779-keypad"; 184 reg = <0 0x10010000 0 0x1000>; 185 wakeup-source; 186 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 187 clocks = <&clk26m>; 188 clock-names = "kpd"; 189 status = "disabled"; 190 }; 191 192 mcucfg: syscon@10200000 { 193 compatible = "mediatek,mt8365-mcucfg", "syscon"; 194 reg = <0 0x10200000 0 0x2000>; 195 #clock-cells = <1>; 196 }; 197 198 sysirq: interrupt-controller@10200a80 { 199 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 200 interrupt-controller; 201 #interrupt-cells = <3>; 202 interrupt-parent = <&gic>; 203 reg = <0 0x10200a80 0 0x20>; 204 }; 205 206 infracfg_nao: infracfg@1020e000 { 207 compatible = "mediatek,mt8365-infracfg", "syscon"; 208 reg = <0 0x1020e000 0 0x1000>; 209 #clock-cells = <1>; 210 }; 211 212 rng: rng@1020f000 { 213 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 214 reg = <0 0x1020f000 0 0x100>; 215 clocks = <&infracfg CLK_IFR_TRNG>; 216 clock-names = "rng"; 217 }; 218 219 apdma: dma-controller@11000280 { 220 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 221 reg = <0 0x11000280 0 0x80>, 222 <0 0x11000300 0 0x80>, 223 <0 0x11000380 0 0x80>, 224 <0 0x11000400 0 0x80>, 225 <0 0x11000580 0 0x80>, 226 <0 0x11000600 0 0x80>; 227 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 228 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 229 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 230 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 231 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 232 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 233 dma-requests = <6>; 234 clocks = <&infracfg CLK_IFR_AP_DMA>; 235 clock-names = "apdma"; 236 #dma-cells = <1>; 237 }; 238 239 uart0: serial@11002000 { 240 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 241 reg = <0 0x11002000 0 0x1000>; 242 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 243 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 244 clock-names = "baud", "bus"; 245 dmas = <&apdma 0>, <&apdma 1>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 uart1: serial@11003000 { 251 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 252 reg = <0 0x11003000 0 0x1000>; 253 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 254 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 255 clock-names = "baud", "bus"; 256 dmas = <&apdma 2>, <&apdma 3>; 257 dma-names = "tx", "rx"; 258 status = "disabled"; 259 }; 260 261 uart2: serial@11004000 { 262 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 263 reg = <0 0x11004000 0 0x1000>; 264 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 265 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 266 clock-names = "baud", "bus"; 267 dmas = <&apdma 4>, <&apdma 5>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 pwm: pwm@11006000 { 273 compatible = "mediatek,mt8365-pwm"; 274 reg = <0 0x11006000 0 0x1000>; 275 #pwm-cells = <2>; 276 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 277 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 278 <&infracfg CLK_IFR_PWM>, 279 <&infracfg CLK_IFR_PWM1>, 280 <&infracfg CLK_IFR_PWM2>, 281 <&infracfg CLK_IFR_PWM3>; 282 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 283 }; 284 285 spi: spi@1100a000 { 286 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 287 reg = <0 0x1100a000 0 0x100>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 291 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 292 <&topckgen CLK_TOP_SPI_SEL>, 293 <&infracfg CLK_IFR_SPI0>; 294 clock-names = "parent-clk", "sel-clk", "spi-clk"; 295 status = "disabled"; 296 }; 297 298 ssusb: usb@11201000 { 299 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 300 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 301 reg-names = "mac", "ippc"; 302 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 303 phys = <&u2port0 PHY_TYPE_USB2>, 304 <&u2port1 PHY_TYPE_USB2>; 305 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 306 <&infracfg CLK_IFR_SSUSB_REF>, 307 <&infracfg CLK_IFR_SSUSB_SYS>, 308 <&infracfg CLK_IFR_ICUSB>; 309 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 310 #address-cells = <2>; 311 #size-cells = <2>; 312 ranges; 313 status = "disabled"; 314 315 usb_host: usb@11200000 { 316 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 317 reg = <0 0x11200000 0 0x1000>; 318 reg-names = "mac"; 319 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 320 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 321 <&infracfg CLK_IFR_SSUSB_REF>, 322 <&infracfg CLK_IFR_SSUSB_SYS>, 323 <&infracfg CLK_IFR_ICUSB>, 324 <&infracfg CLK_IFR_SSUSB_XHCI>; 325 clock-names = "sys_ck", "ref_ck", "mcu_ck", 326 "dma_ck", "xhci_ck"; 327 status = "disabled"; 328 }; 329 }; 330 331 u3phy: t-phy@11cc0000 { 332 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 333 #address-cells = <1>; 334 #size-cells = <1>; 335 ranges = <0 0 0x11cc0000 0x9000>; 336 337 u2port0: usb-phy@0 { 338 reg = <0x0 0x400>; 339 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 340 <&topckgen CLK_TOP_USB20_48M_EN>; 341 clock-names = "ref", "da_ref"; 342 #phy-cells = <1>; 343 }; 344 345 u2port1: usb-phy@1000 { 346 reg = <0x1000 0x400>; 347 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 348 <&topckgen CLK_TOP_USB20_48M_EN>; 349 clock-names = "ref", "da_ref"; 350 #phy-cells = <1>; 351 }; 352 }; 353 }; 354 355 timer { 356 compatible = "arm,armv8-timer"; 357 interrupt-parent = <&gic>; 358 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 359 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 360 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 361 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 362 }; 363 364 system_clk: dummy13m { 365 compatible = "fixed-clock"; 366 clock-frequency = <13000000>; 367 #clock-cells = <0>; 368 }; 369 370 systimer: timer@10017000 { 371 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 372 reg = <0 0x10017000 0 0x100>; 373 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&system_clk>; 375 clock-names = "clk13m"; 376 }; 377}; 378