1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 }; 317 318 dmic_codec: dmic-codec { 319 compatible = "dmic-codec"; 320 num-channels = <2>; 321 wakeup-delay-ms = <50>; 322 }; 323 324 sound: mt8195-sound { 325 mediatek,platform = <&afe>; 326 status = "disabled"; 327 }; 328 329 clk13m: fixed-factor-clock-13m { 330 compatible = "fixed-factor-clock"; 331 #clock-cells = <0>; 332 clocks = <&clk26m>; 333 clock-div = <2>; 334 clock-mult = <1>; 335 clock-output-names = "clk13m"; 336 }; 337 338 clk26m: oscillator-26m { 339 compatible = "fixed-clock"; 340 #clock-cells = <0>; 341 clock-frequency = <26000000>; 342 clock-output-names = "clk26m"; 343 }; 344 345 clk32k: oscillator-32k { 346 compatible = "fixed-clock"; 347 #clock-cells = <0>; 348 clock-frequency = <32768>; 349 clock-output-names = "clk32k"; 350 }; 351 352 performance: performance-controller@11bc10 { 353 compatible = "mediatek,cpufreq-hw"; 354 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 355 #performance-domain-cells = <1>; 356 }; 357 358 gpu_opp_table: opp-table-gpu { 359 compatible = "operating-points-v2"; 360 opp-shared; 361 362 opp-390000000 { 363 opp-hz = /bits/ 64 <390000000>; 364 opp-microvolt = <625000>; 365 }; 366 opp-410000000 { 367 opp-hz = /bits/ 64 <410000000>; 368 opp-microvolt = <631250>; 369 }; 370 opp-431000000 { 371 opp-hz = /bits/ 64 <431000000>; 372 opp-microvolt = <631250>; 373 }; 374 opp-473000000 { 375 opp-hz = /bits/ 64 <473000000>; 376 opp-microvolt = <637500>; 377 }; 378 opp-515000000 { 379 opp-hz = /bits/ 64 <515000000>; 380 opp-microvolt = <637500>; 381 }; 382 opp-556000000 { 383 opp-hz = /bits/ 64 <556000000>; 384 opp-microvolt = <643750>; 385 }; 386 opp-598000000 { 387 opp-hz = /bits/ 64 <598000000>; 388 opp-microvolt = <650000>; 389 }; 390 opp-640000000 { 391 opp-hz = /bits/ 64 <640000000>; 392 opp-microvolt = <650000>; 393 }; 394 opp-670000000 { 395 opp-hz = /bits/ 64 <670000000>; 396 opp-microvolt = <662500>; 397 }; 398 opp-700000000 { 399 opp-hz = /bits/ 64 <700000000>; 400 opp-microvolt = <675000>; 401 }; 402 opp-730000000 { 403 opp-hz = /bits/ 64 <730000000>; 404 opp-microvolt = <687500>; 405 }; 406 opp-760000000 { 407 opp-hz = /bits/ 64 <760000000>; 408 opp-microvolt = <700000>; 409 }; 410 opp-790000000 { 411 opp-hz = /bits/ 64 <790000000>; 412 opp-microvolt = <712500>; 413 }; 414 opp-820000000 { 415 opp-hz = /bits/ 64 <820000000>; 416 opp-microvolt = <725000>; 417 }; 418 opp-850000000 { 419 opp-hz = /bits/ 64 <850000000>; 420 opp-microvolt = <737500>; 421 }; 422 opp-880000000 { 423 opp-hz = /bits/ 64 <880000000>; 424 opp-microvolt = <750000>; 425 }; 426 }; 427 428 pmu-a55 { 429 compatible = "arm,cortex-a55-pmu"; 430 interrupt-parent = <&gic>; 431 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 432 }; 433 434 pmu-a78 { 435 compatible = "arm,cortex-a78-pmu"; 436 interrupt-parent = <&gic>; 437 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 438 }; 439 440 psci { 441 compatible = "arm,psci-1.0"; 442 method = "smc"; 443 }; 444 445 timer: timer { 446 compatible = "arm,armv8-timer"; 447 interrupt-parent = <&gic>; 448 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 449 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 452 }; 453 454 soc { 455 #address-cells = <2>; 456 #size-cells = <2>; 457 compatible = "simple-bus"; 458 ranges; 459 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 460 461 gic: interrupt-controller@c000000 { 462 compatible = "arm,gic-v3"; 463 #interrupt-cells = <4>; 464 #redistributor-regions = <1>; 465 interrupt-parent = <&gic>; 466 interrupt-controller; 467 reg = <0 0x0c000000 0 0x40000>, 468 <0 0x0c040000 0 0x200000>; 469 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 470 471 ppi-partitions { 472 ppi_cluster0: interrupt-partition-0 { 473 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 474 }; 475 476 ppi_cluster1: interrupt-partition-1 { 477 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 478 }; 479 }; 480 }; 481 482 topckgen: syscon@10000000 { 483 compatible = "mediatek,mt8195-topckgen", "syscon"; 484 reg = <0 0x10000000 0 0x1000>; 485 #clock-cells = <1>; 486 }; 487 488 infracfg_ao: syscon@10001000 { 489 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 490 reg = <0 0x10001000 0 0x1000>; 491 #clock-cells = <1>; 492 #reset-cells = <1>; 493 }; 494 495 pericfg: syscon@10003000 { 496 compatible = "mediatek,mt8195-pericfg", "syscon"; 497 reg = <0 0x10003000 0 0x1000>; 498 #clock-cells = <1>; 499 }; 500 501 pio: pinctrl@10005000 { 502 compatible = "mediatek,mt8195-pinctrl"; 503 reg = <0 0x10005000 0 0x1000>, 504 <0 0x11d10000 0 0x1000>, 505 <0 0x11d30000 0 0x1000>, 506 <0 0x11d40000 0 0x1000>, 507 <0 0x11e20000 0 0x1000>, 508 <0 0x11eb0000 0 0x1000>, 509 <0 0x11f40000 0 0x1000>, 510 <0 0x1000b000 0 0x1000>; 511 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 512 "iocfg_br", "iocfg_lm", "iocfg_rb", 513 "iocfg_tl", "eint"; 514 gpio-controller; 515 #gpio-cells = <2>; 516 gpio-ranges = <&pio 0 0 144>; 517 interrupt-controller; 518 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 519 #interrupt-cells = <2>; 520 }; 521 522 scpsys: syscon@10006000 { 523 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 524 reg = <0 0x10006000 0 0x1000>; 525 526 /* System Power Manager */ 527 spm: power-controller { 528 compatible = "mediatek,mt8195-power-controller"; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 #power-domain-cells = <1>; 532 533 /* power domain of the SoC */ 534 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 535 reg = <MT8195_POWER_DOMAIN_MFG0>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 #power-domain-cells = <1>; 539 540 power-domain@MT8195_POWER_DOMAIN_MFG1 { 541 reg = <MT8195_POWER_DOMAIN_MFG1>; 542 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 543 <&topckgen CLK_TOP_MFG_CORE_TMP>; 544 clock-names = "mfg", "alt"; 545 mediatek,infracfg = <&infracfg_ao>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 #power-domain-cells = <1>; 549 550 power-domain@MT8195_POWER_DOMAIN_MFG2 { 551 reg = <MT8195_POWER_DOMAIN_MFG2>; 552 #power-domain-cells = <0>; 553 }; 554 555 power-domain@MT8195_POWER_DOMAIN_MFG3 { 556 reg = <MT8195_POWER_DOMAIN_MFG3>; 557 #power-domain-cells = <0>; 558 }; 559 560 power-domain@MT8195_POWER_DOMAIN_MFG4 { 561 reg = <MT8195_POWER_DOMAIN_MFG4>; 562 #power-domain-cells = <0>; 563 }; 564 565 power-domain@MT8195_POWER_DOMAIN_MFG5 { 566 reg = <MT8195_POWER_DOMAIN_MFG5>; 567 #power-domain-cells = <0>; 568 }; 569 570 power-domain@MT8195_POWER_DOMAIN_MFG6 { 571 reg = <MT8195_POWER_DOMAIN_MFG6>; 572 #power-domain-cells = <0>; 573 }; 574 }; 575 }; 576 577 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 578 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 579 clocks = <&topckgen CLK_TOP_VPP>, 580 <&topckgen CLK_TOP_CAM>, 581 <&topckgen CLK_TOP_CCU>, 582 <&topckgen CLK_TOP_IMG>, 583 <&topckgen CLK_TOP_VENC>, 584 <&topckgen CLK_TOP_VDEC>, 585 <&topckgen CLK_TOP_WPE_VPP>, 586 <&topckgen CLK_TOP_CFG_VPP0>, 587 <&vppsys0 CLK_VPP0_SMI_COMMON>, 588 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 590 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 592 <&vppsys0 CLK_VPP0_GALS_INFRA>, 593 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 594 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 596 <&vppsys0 CLK_VPP0_SMI_REORDER>, 597 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 598 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 599 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 600 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 601 <&vppsys0 CLK_VPP0_SMI_RSI>, 602 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 603 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 604 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 605 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 606 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 607 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 608 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 609 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 610 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 611 "vppsys0-12", "vppsys0-13", "vppsys0-14", 612 "vppsys0-15", "vppsys0-16", "vppsys0-17", 613 "vppsys0-18"; 614 mediatek,infracfg = <&infracfg_ao>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 #power-domain-cells = <1>; 618 619 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 620 reg = <MT8195_POWER_DOMAIN_VDEC1>; 621 clocks = <&vdecsys CLK_VDEC_LARB1>; 622 clock-names = "vdec1-0"; 623 mediatek,infracfg = <&infracfg_ao>; 624 #power-domain-cells = <0>; 625 }; 626 627 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 628 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 629 mediatek,infracfg = <&infracfg_ao>; 630 #power-domain-cells = <0>; 631 }; 632 633 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 634 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 635 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 636 <&vdosys0 CLK_VDO0_SMI_GALS>, 637 <&vdosys0 CLK_VDO0_SMI_COMMON>, 638 <&vdosys0 CLK_VDO0_SMI_EMI>, 639 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 640 <&vdosys0 CLK_VDO0_SMI_LARB>, 641 <&vdosys0 CLK_VDO0_SMI_RSI>; 642 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 643 "vdosys0-2", "vdosys0-3", 644 "vdosys0-4", "vdosys0-5"; 645 mediatek,infracfg = <&infracfg_ao>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 #power-domain-cells = <1>; 649 650 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 651 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 652 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 653 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 654 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 655 clock-names = "vppsys1", "vppsys1-0", 656 "vppsys1-1"; 657 mediatek,infracfg = <&infracfg_ao>; 658 #power-domain-cells = <0>; 659 }; 660 661 power-domain@MT8195_POWER_DOMAIN_WPESYS { 662 reg = <MT8195_POWER_DOMAIN_WPESYS>; 663 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 664 <&wpesys CLK_WPE_SMI_LARB8>, 665 <&wpesys CLK_WPE_SMI_LARB7_P>, 666 <&wpesys CLK_WPE_SMI_LARB8_P>; 667 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 668 "wepsys-3"; 669 mediatek,infracfg = <&infracfg_ao>; 670 #power-domain-cells = <0>; 671 }; 672 673 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 674 reg = <MT8195_POWER_DOMAIN_VDEC0>; 675 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 676 clock-names = "vdec0-0"; 677 mediatek,infracfg = <&infracfg_ao>; 678 #power-domain-cells = <0>; 679 }; 680 681 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 682 reg = <MT8195_POWER_DOMAIN_VDEC2>; 683 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 684 clock-names = "vdec2-0"; 685 mediatek,infracfg = <&infracfg_ao>; 686 #power-domain-cells = <0>; 687 }; 688 689 power-domain@MT8195_POWER_DOMAIN_VENC { 690 reg = <MT8195_POWER_DOMAIN_VENC>; 691 mediatek,infracfg = <&infracfg_ao>; 692 #power-domain-cells = <0>; 693 }; 694 695 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 696 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 697 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 698 <&vdosys1 CLK_VDO1_SMI_LARB2>, 699 <&vdosys1 CLK_VDO1_SMI_LARB3>, 700 <&vdosys1 CLK_VDO1_GALS>; 701 clock-names = "vdosys1", "vdosys1-0", 702 "vdosys1-1", "vdosys1-2"; 703 mediatek,infracfg = <&infracfg_ao>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 #power-domain-cells = <1>; 707 708 power-domain@MT8195_POWER_DOMAIN_DP_TX { 709 reg = <MT8195_POWER_DOMAIN_DP_TX>; 710 mediatek,infracfg = <&infracfg_ao>; 711 #power-domain-cells = <0>; 712 }; 713 714 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 715 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 716 mediatek,infracfg = <&infracfg_ao>; 717 #power-domain-cells = <0>; 718 }; 719 720 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 721 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 722 clocks = <&topckgen CLK_TOP_HDMI_APB>; 723 clock-names = "hdmi_tx"; 724 #power-domain-cells = <0>; 725 }; 726 }; 727 728 power-domain@MT8195_POWER_DOMAIN_IMG { 729 reg = <MT8195_POWER_DOMAIN_IMG>; 730 clocks = <&imgsys CLK_IMG_LARB9>, 731 <&imgsys CLK_IMG_GALS>; 732 clock-names = "img-0", "img-1"; 733 mediatek,infracfg = <&infracfg_ao>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 #power-domain-cells = <1>; 737 738 power-domain@MT8195_POWER_DOMAIN_DIP { 739 reg = <MT8195_POWER_DOMAIN_DIP>; 740 #power-domain-cells = <0>; 741 }; 742 743 power-domain@MT8195_POWER_DOMAIN_IPE { 744 reg = <MT8195_POWER_DOMAIN_IPE>; 745 clocks = <&topckgen CLK_TOP_IPE>, 746 <&imgsys CLK_IMG_IPE>, 747 <&ipesys CLK_IPE_SMI_LARB12>; 748 clock-names = "ipe", "ipe-0", "ipe-1"; 749 mediatek,infracfg = <&infracfg_ao>; 750 #power-domain-cells = <0>; 751 }; 752 }; 753 754 power-domain@MT8195_POWER_DOMAIN_CAM { 755 reg = <MT8195_POWER_DOMAIN_CAM>; 756 clocks = <&camsys CLK_CAM_LARB13>, 757 <&camsys CLK_CAM_LARB14>, 758 <&camsys CLK_CAM_CAM2MM0_GALS>, 759 <&camsys CLK_CAM_CAM2MM1_GALS>, 760 <&camsys CLK_CAM_CAM2SYS_GALS>; 761 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 762 "cam-4"; 763 mediatek,infracfg = <&infracfg_ao>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 #power-domain-cells = <1>; 767 768 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 769 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 770 #power-domain-cells = <0>; 771 }; 772 773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 774 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 775 #power-domain-cells = <0>; 776 }; 777 778 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 779 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 780 #power-domain-cells = <0>; 781 }; 782 }; 783 }; 784 }; 785 786 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 787 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 788 mediatek,infracfg = <&infracfg_ao>; 789 #power-domain-cells = <0>; 790 }; 791 792 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 793 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 794 mediatek,infracfg = <&infracfg_ao>; 795 #power-domain-cells = <0>; 796 }; 797 798 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 799 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 800 #power-domain-cells = <0>; 801 }; 802 803 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 804 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 805 #power-domain-cells = <0>; 806 }; 807 808 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 809 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 810 clocks = <&topckgen CLK_TOP_SENINF>, 811 <&topckgen CLK_TOP_SENINF2>; 812 clock-names = "csi_rx_top", "csi_rx_top1"; 813 #power-domain-cells = <0>; 814 }; 815 816 power-domain@MT8195_POWER_DOMAIN_ETHER { 817 reg = <MT8195_POWER_DOMAIN_ETHER>; 818 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 819 clock-names = "ether"; 820 #power-domain-cells = <0>; 821 }; 822 823 power-domain@MT8195_POWER_DOMAIN_ADSP { 824 reg = <MT8195_POWER_DOMAIN_ADSP>; 825 clocks = <&topckgen CLK_TOP_ADSP>, 826 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 827 clock-names = "adsp", "adsp1"; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 mediatek,infracfg = <&infracfg_ao>; 831 #power-domain-cells = <1>; 832 833 power-domain@MT8195_POWER_DOMAIN_AUDIO { 834 reg = <MT8195_POWER_DOMAIN_AUDIO>; 835 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 836 <&topckgen CLK_TOP_AUD_INTBUS>, 837 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 838 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 839 clock-names = "audio", "audio1", "audio2", 840 "audio3"; 841 mediatek,infracfg = <&infracfg_ao>; 842 #power-domain-cells = <0>; 843 }; 844 }; 845 }; 846 }; 847 848 watchdog: watchdog@10007000 { 849 compatible = "mediatek,mt8195-wdt"; 850 mediatek,disable-extrst; 851 reg = <0 0x10007000 0 0x100>; 852 #reset-cells = <1>; 853 }; 854 855 apmixedsys: syscon@1000c000 { 856 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 857 reg = <0 0x1000c000 0 0x1000>; 858 #clock-cells = <1>; 859 }; 860 861 systimer: timer@10017000 { 862 compatible = "mediatek,mt8195-timer", 863 "mediatek,mt6765-timer"; 864 reg = <0 0x10017000 0 0x1000>; 865 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 866 clocks = <&clk13m>; 867 }; 868 869 pwrap: pwrap@10024000 { 870 compatible = "mediatek,mt8195-pwrap", "syscon"; 871 reg = <0 0x10024000 0 0x1000>; 872 reg-names = "pwrap"; 873 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 874 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 875 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 876 clock-names = "spi", "wrap"; 877 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 878 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 879 }; 880 881 spmi: spmi@10027000 { 882 compatible = "mediatek,mt8195-spmi"; 883 reg = <0 0x10027000 0 0x000e00>, 884 <0 0x10029000 0 0x000100>; 885 reg-names = "pmif", "spmimst"; 886 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 887 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 888 <&topckgen CLK_TOP_SPMI_M_MST>; 889 clock-names = "pmif_sys_ck", 890 "pmif_tmr_ck", 891 "spmimst_clk_mux"; 892 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 893 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 894 }; 895 896 iommu_infra: infra-iommu@10315000 { 897 compatible = "mediatek,mt8195-iommu-infra"; 898 reg = <0 0x10315000 0 0x5000>; 899 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 900 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 901 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 902 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 903 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 904 #iommu-cells = <1>; 905 }; 906 907 gce0: mailbox@10320000 { 908 compatible = "mediatek,mt8195-gce"; 909 reg = <0 0x10320000 0 0x4000>; 910 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 911 #mbox-cells = <2>; 912 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 913 }; 914 915 gce1: mailbox@10330000 { 916 compatible = "mediatek,mt8195-gce"; 917 reg = <0 0x10330000 0 0x4000>; 918 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 919 #mbox-cells = <2>; 920 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 921 }; 922 923 scp: scp@10500000 { 924 compatible = "mediatek,mt8195-scp"; 925 reg = <0 0x10500000 0 0x100000>, 926 <0 0x10720000 0 0xe0000>, 927 <0 0x10700000 0 0x8000>; 928 reg-names = "sram", "cfg", "l1tcm"; 929 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 930 status = "disabled"; 931 }; 932 933 scp_adsp: clock-controller@10720000 { 934 compatible = "mediatek,mt8195-scp_adsp"; 935 reg = <0 0x10720000 0 0x1000>; 936 #clock-cells = <1>; 937 }; 938 939 adsp: dsp@10803000 { 940 compatible = "mediatek,mt8195-dsp"; 941 reg = <0 0x10803000 0 0x1000>, 942 <0 0x10840000 0 0x40000>; 943 reg-names = "cfg", "sram"; 944 clocks = <&topckgen CLK_TOP_ADSP>, 945 <&clk26m>, 946 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 947 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 948 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 949 <&topckgen CLK_TOP_AUDIO_H>; 950 clock-names = "adsp_sel", 951 "clk26m_ck", 952 "audio_local_bus", 953 "mainpll_d7_d2", 954 "scp_adsp_audiodsp", 955 "audio_h"; 956 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 957 mbox-names = "rx", "tx"; 958 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 959 status = "disabled"; 960 }; 961 962 adsp_mailbox0: mailbox@10816000 { 963 compatible = "mediatek,mt8195-adsp-mbox"; 964 #mbox-cells = <0>; 965 reg = <0 0x10816000 0 0x1000>; 966 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 967 }; 968 969 adsp_mailbox1: mailbox@10817000 { 970 compatible = "mediatek,mt8195-adsp-mbox"; 971 #mbox-cells = <0>; 972 reg = <0 0x10817000 0 0x1000>; 973 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 974 }; 975 976 afe: mt8195-afe-pcm@10890000 { 977 compatible = "mediatek,mt8195-audio"; 978 reg = <0 0x10890000 0 0x10000>; 979 mediatek,topckgen = <&topckgen>; 980 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 981 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 982 resets = <&watchdog 14>; 983 reset-names = "audiosys"; 984 clocks = <&clk26m>, 985 <&apmixedsys CLK_APMIXED_APLL1>, 986 <&apmixedsys CLK_APMIXED_APLL2>, 987 <&topckgen CLK_TOP_APLL12_DIV0>, 988 <&topckgen CLK_TOP_APLL12_DIV1>, 989 <&topckgen CLK_TOP_APLL12_DIV2>, 990 <&topckgen CLK_TOP_APLL12_DIV3>, 991 <&topckgen CLK_TOP_APLL12_DIV9>, 992 <&topckgen CLK_TOP_A1SYS_HP>, 993 <&topckgen CLK_TOP_AUD_INTBUS>, 994 <&topckgen CLK_TOP_AUDIO_H>, 995 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 996 <&topckgen CLK_TOP_DPTX_MCK>, 997 <&topckgen CLK_TOP_I2SO1_MCK>, 998 <&topckgen CLK_TOP_I2SO2_MCK>, 999 <&topckgen CLK_TOP_I2SI1_MCK>, 1000 <&topckgen CLK_TOP_I2SI2_MCK>, 1001 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1002 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1003 clock-names = "clk26m", 1004 "apll1_ck", 1005 "apll2_ck", 1006 "apll12_div0", 1007 "apll12_div1", 1008 "apll12_div2", 1009 "apll12_div3", 1010 "apll12_div9", 1011 "a1sys_hp_sel", 1012 "aud_intbus_sel", 1013 "audio_h_sel", 1014 "audio_local_bus_sel", 1015 "dptx_m_sel", 1016 "i2so1_m_sel", 1017 "i2so2_m_sel", 1018 "i2si1_m_sel", 1019 "i2si2_m_sel", 1020 "infra_ao_audio_26m_b", 1021 "scp_adsp_audiodsp"; 1022 status = "disabled"; 1023 }; 1024 1025 uart0: serial@11001100 { 1026 compatible = "mediatek,mt8195-uart", 1027 "mediatek,mt6577-uart"; 1028 reg = <0 0x11001100 0 0x100>; 1029 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1030 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1031 clock-names = "baud", "bus"; 1032 status = "disabled"; 1033 }; 1034 1035 uart1: serial@11001200 { 1036 compatible = "mediatek,mt8195-uart", 1037 "mediatek,mt6577-uart"; 1038 reg = <0 0x11001200 0 0x100>; 1039 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1040 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1041 clock-names = "baud", "bus"; 1042 status = "disabled"; 1043 }; 1044 1045 uart2: serial@11001300 { 1046 compatible = "mediatek,mt8195-uart", 1047 "mediatek,mt6577-uart"; 1048 reg = <0 0x11001300 0 0x100>; 1049 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1050 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1051 clock-names = "baud", "bus"; 1052 status = "disabled"; 1053 }; 1054 1055 uart3: serial@11001400 { 1056 compatible = "mediatek,mt8195-uart", 1057 "mediatek,mt6577-uart"; 1058 reg = <0 0x11001400 0 0x100>; 1059 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1060 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1061 clock-names = "baud", "bus"; 1062 status = "disabled"; 1063 }; 1064 1065 uart4: serial@11001500 { 1066 compatible = "mediatek,mt8195-uart", 1067 "mediatek,mt6577-uart"; 1068 reg = <0 0x11001500 0 0x100>; 1069 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1070 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1071 clock-names = "baud", "bus"; 1072 status = "disabled"; 1073 }; 1074 1075 uart5: serial@11001600 { 1076 compatible = "mediatek,mt8195-uart", 1077 "mediatek,mt6577-uart"; 1078 reg = <0 0x11001600 0 0x100>; 1079 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1080 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1081 clock-names = "baud", "bus"; 1082 status = "disabled"; 1083 }; 1084 1085 auxadc: auxadc@11002000 { 1086 compatible = "mediatek,mt8195-auxadc", 1087 "mediatek,mt8173-auxadc"; 1088 reg = <0 0x11002000 0 0x1000>; 1089 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1090 clock-names = "main"; 1091 #io-channel-cells = <1>; 1092 status = "disabled"; 1093 }; 1094 1095 pericfg_ao: syscon@11003000 { 1096 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1097 reg = <0 0x11003000 0 0x1000>; 1098 #clock-cells = <1>; 1099 }; 1100 1101 spi0: spi@1100a000 { 1102 compatible = "mediatek,mt8195-spi", 1103 "mediatek,mt6765-spi"; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 reg = <0 0x1100a000 0 0x1000>; 1107 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1108 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1109 <&topckgen CLK_TOP_SPI>, 1110 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1111 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1112 status = "disabled"; 1113 }; 1114 1115 lvts_ap: thermal-sensor@1100b000 { 1116 compatible = "mediatek,mt8195-lvts-ap"; 1117 reg = <0 0x1100b000 0 0x1000>; 1118 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1119 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1120 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1121 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1122 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1123 #thermal-sensor-cells = <1>; 1124 }; 1125 1126 disp_pwm0: pwm@1100e000 { 1127 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1128 reg = <0 0x1100e000 0 0x1000>; 1129 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1130 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1131 #pwm-cells = <2>; 1132 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1133 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1134 clock-names = "main", "mm"; 1135 status = "disabled"; 1136 }; 1137 1138 disp_pwm1: pwm@1100f000 { 1139 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1140 reg = <0 0x1100f000 0 0x1000>; 1141 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1142 #pwm-cells = <2>; 1143 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1144 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1145 clock-names = "main", "mm"; 1146 status = "disabled"; 1147 }; 1148 1149 spi1: spi@11010000 { 1150 compatible = "mediatek,mt8195-spi", 1151 "mediatek,mt6765-spi"; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 reg = <0 0x11010000 0 0x1000>; 1155 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1156 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1157 <&topckgen CLK_TOP_SPI>, 1158 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1159 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1160 status = "disabled"; 1161 }; 1162 1163 spi2: spi@11012000 { 1164 compatible = "mediatek,mt8195-spi", 1165 "mediatek,mt6765-spi"; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 reg = <0 0x11012000 0 0x1000>; 1169 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1170 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1171 <&topckgen CLK_TOP_SPI>, 1172 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1173 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1174 status = "disabled"; 1175 }; 1176 1177 spi3: spi@11013000 { 1178 compatible = "mediatek,mt8195-spi", 1179 "mediatek,mt6765-spi"; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 reg = <0 0x11013000 0 0x1000>; 1183 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1184 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1185 <&topckgen CLK_TOP_SPI>, 1186 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1187 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1188 status = "disabled"; 1189 }; 1190 1191 spi4: spi@11018000 { 1192 compatible = "mediatek,mt8195-spi", 1193 "mediatek,mt6765-spi"; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 reg = <0 0x11018000 0 0x1000>; 1197 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1198 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1199 <&topckgen CLK_TOP_SPI>, 1200 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1201 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1202 status = "disabled"; 1203 }; 1204 1205 spi5: spi@11019000 { 1206 compatible = "mediatek,mt8195-spi", 1207 "mediatek,mt6765-spi"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 reg = <0 0x11019000 0 0x1000>; 1211 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1212 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1213 <&topckgen CLK_TOP_SPI>, 1214 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1215 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1216 status = "disabled"; 1217 }; 1218 1219 spis0: spi@1101d000 { 1220 compatible = "mediatek,mt8195-spi-slave"; 1221 reg = <0 0x1101d000 0 0x1000>; 1222 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1223 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1224 clock-names = "spi"; 1225 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1226 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1227 status = "disabled"; 1228 }; 1229 1230 spis1: spi@1101e000 { 1231 compatible = "mediatek,mt8195-spi-slave"; 1232 reg = <0 0x1101e000 0 0x1000>; 1233 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1234 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1235 clock-names = "spi"; 1236 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1237 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1238 status = "disabled"; 1239 }; 1240 1241 eth: ethernet@11021000 { 1242 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1243 reg = <0 0x11021000 0 0x4000>; 1244 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1245 interrupt-names = "macirq"; 1246 clock-names = "axi", 1247 "apb", 1248 "mac_main", 1249 "ptp_ref", 1250 "rmii_internal", 1251 "mac_cg"; 1252 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1253 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1254 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1255 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1256 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1257 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1258 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1259 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1260 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1261 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1262 <&topckgen CLK_TOP_ETHPLL_D8>, 1263 <&topckgen CLK_TOP_ETHPLL_D10>; 1264 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1265 mediatek,pericfg = <&infracfg_ao>; 1266 snps,axi-config = <&stmmac_axi_setup>; 1267 snps,mtl-rx-config = <&mtl_rx_setup>; 1268 snps,mtl-tx-config = <&mtl_tx_setup>; 1269 snps,txpbl = <16>; 1270 snps,rxpbl = <16>; 1271 snps,clk-csr = <0>; 1272 status = "disabled"; 1273 1274 mdio { 1275 compatible = "snps,dwmac-mdio"; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 }; 1279 1280 stmmac_axi_setup: stmmac-axi-config { 1281 snps,wr_osr_lmt = <0x7>; 1282 snps,rd_osr_lmt = <0x7>; 1283 snps,blen = <0 0 0 0 16 8 4>; 1284 }; 1285 1286 mtl_rx_setup: rx-queues-config { 1287 snps,rx-queues-to-use = <4>; 1288 snps,rx-sched-sp; 1289 queue0 { 1290 snps,dcb-algorithm; 1291 snps,map-to-dma-channel = <0x0>; 1292 }; 1293 queue1 { 1294 snps,dcb-algorithm; 1295 snps,map-to-dma-channel = <0x0>; 1296 }; 1297 queue2 { 1298 snps,dcb-algorithm; 1299 snps,map-to-dma-channel = <0x0>; 1300 }; 1301 queue3 { 1302 snps,dcb-algorithm; 1303 snps,map-to-dma-channel = <0x0>; 1304 }; 1305 }; 1306 1307 mtl_tx_setup: tx-queues-config { 1308 snps,tx-queues-to-use = <4>; 1309 snps,tx-sched-wrr; 1310 queue0 { 1311 snps,weight = <0x10>; 1312 snps,dcb-algorithm; 1313 snps,priority = <0x0>; 1314 }; 1315 queue1 { 1316 snps,weight = <0x11>; 1317 snps,dcb-algorithm; 1318 snps,priority = <0x1>; 1319 }; 1320 queue2 { 1321 snps,weight = <0x12>; 1322 snps,dcb-algorithm; 1323 snps,priority = <0x2>; 1324 }; 1325 queue3 { 1326 snps,weight = <0x13>; 1327 snps,dcb-algorithm; 1328 snps,priority = <0x3>; 1329 }; 1330 }; 1331 }; 1332 1333 xhci0: usb@11200000 { 1334 compatible = "mediatek,mt8195-xhci", 1335 "mediatek,mtk-xhci"; 1336 reg = <0 0x11200000 0 0x1000>, 1337 <0 0x11203e00 0 0x0100>; 1338 reg-names = "mac", "ippc"; 1339 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1340 phys = <&u2port0 PHY_TYPE_USB2>, 1341 <&u3port0 PHY_TYPE_USB3>; 1342 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1343 <&topckgen CLK_TOP_SSUSB_XHCI>; 1344 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1345 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1346 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1347 <&topckgen CLK_TOP_SSUSB_REF>, 1348 <&apmixedsys CLK_APMIXED_USB1PLL>, 1349 <&clk26m>, 1350 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1351 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1352 "xhci_ck"; 1353 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1354 wakeup-source; 1355 status = "disabled"; 1356 }; 1357 1358 mmc0: mmc@11230000 { 1359 compatible = "mediatek,mt8195-mmc", 1360 "mediatek,mt8183-mmc"; 1361 reg = <0 0x11230000 0 0x10000>, 1362 <0 0x11f50000 0 0x1000>; 1363 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1364 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1365 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1366 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1367 clock-names = "source", "hclk", "source_cg"; 1368 status = "disabled"; 1369 }; 1370 1371 mmc1: mmc@11240000 { 1372 compatible = "mediatek,mt8195-mmc", 1373 "mediatek,mt8183-mmc"; 1374 reg = <0 0x11240000 0 0x1000>, 1375 <0 0x11c70000 0 0x1000>; 1376 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1377 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1378 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1379 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1380 clock-names = "source", "hclk", "source_cg"; 1381 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1382 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1383 status = "disabled"; 1384 }; 1385 1386 mmc2: mmc@11250000 { 1387 compatible = "mediatek,mt8195-mmc", 1388 "mediatek,mt8183-mmc"; 1389 reg = <0 0x11250000 0 0x1000>, 1390 <0 0x11e60000 0 0x1000>; 1391 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1392 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1393 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1394 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1395 clock-names = "source", "hclk", "source_cg"; 1396 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1397 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1398 status = "disabled"; 1399 }; 1400 1401 lvts_mcu: thermal-sensor@11278000 { 1402 compatible = "mediatek,mt8195-lvts-mcu"; 1403 reg = <0 0x11278000 0 0x1000>; 1404 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1405 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1406 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1407 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1408 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1409 #thermal-sensor-cells = <1>; 1410 }; 1411 1412 xhci1: usb@11290000 { 1413 compatible = "mediatek,mt8195-xhci", 1414 "mediatek,mtk-xhci"; 1415 reg = <0 0x11290000 0 0x1000>, 1416 <0 0x11293e00 0 0x0100>; 1417 reg-names = "mac", "ippc"; 1418 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1419 phys = <&u2port1 PHY_TYPE_USB2>; 1420 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1421 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1422 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1423 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1424 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1425 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1426 <&apmixedsys CLK_APMIXED_USB1PLL>, 1427 <&clk26m>, 1428 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1429 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1430 "xhci_ck"; 1431 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1432 wakeup-source; 1433 status = "disabled"; 1434 }; 1435 1436 xhci2: usb@112a0000 { 1437 compatible = "mediatek,mt8195-xhci", 1438 "mediatek,mtk-xhci"; 1439 reg = <0 0x112a0000 0 0x1000>, 1440 <0 0x112a3e00 0 0x0100>; 1441 reg-names = "mac", "ippc"; 1442 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1443 phys = <&u2port2 PHY_TYPE_USB2>; 1444 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1445 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1446 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1447 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1448 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1449 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1450 <&clk26m>, 1451 <&clk26m>, 1452 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1453 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1454 "xhci_ck"; 1455 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1456 wakeup-source; 1457 status = "disabled"; 1458 }; 1459 1460 xhci3: usb@112b0000 { 1461 compatible = "mediatek,mt8195-xhci", 1462 "mediatek,mtk-xhci"; 1463 reg = <0 0x112b0000 0 0x1000>, 1464 <0 0x112b3e00 0 0x0100>; 1465 reg-names = "mac", "ippc"; 1466 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1467 phys = <&u2port3 PHY_TYPE_USB2>; 1468 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1469 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1470 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1471 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1472 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1473 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1474 <&clk26m>, 1475 <&clk26m>, 1476 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1477 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1478 "xhci_ck"; 1479 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1480 wakeup-source; 1481 status = "disabled"; 1482 }; 1483 1484 pcie0: pcie@112f0000 { 1485 compatible = "mediatek,mt8195-pcie", 1486 "mediatek,mt8192-pcie"; 1487 device_type = "pci"; 1488 #address-cells = <3>; 1489 #size-cells = <2>; 1490 reg = <0 0x112f0000 0 0x4000>; 1491 reg-names = "pcie-mac"; 1492 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1493 bus-range = <0x00 0xff>; 1494 ranges = <0x81000000 0 0x20000000 1495 0x0 0x20000000 0 0x200000>, 1496 <0x82000000 0 0x20200000 1497 0x0 0x20200000 0 0x3e00000>; 1498 1499 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1500 iommu-map-mask = <0x0>; 1501 1502 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1503 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1504 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1505 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1506 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1507 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1508 clock-names = "pl_250m", "tl_26m", "tl_96m", 1509 "tl_32k", "peri_26m", "peri_mem"; 1510 assigned-clocks = <&topckgen CLK_TOP_TL>; 1511 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1512 1513 phys = <&pciephy>; 1514 phy-names = "pcie-phy"; 1515 1516 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1517 1518 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1519 reset-names = "mac"; 1520 1521 #interrupt-cells = <1>; 1522 interrupt-map-mask = <0 0 0 7>; 1523 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1524 <0 0 0 2 &pcie_intc0 1>, 1525 <0 0 0 3 &pcie_intc0 2>, 1526 <0 0 0 4 &pcie_intc0 3>; 1527 status = "disabled"; 1528 1529 pcie_intc0: interrupt-controller { 1530 interrupt-controller; 1531 #address-cells = <0>; 1532 #interrupt-cells = <1>; 1533 }; 1534 }; 1535 1536 pcie1: pcie@112f8000 { 1537 compatible = "mediatek,mt8195-pcie", 1538 "mediatek,mt8192-pcie"; 1539 device_type = "pci"; 1540 #address-cells = <3>; 1541 #size-cells = <2>; 1542 reg = <0 0x112f8000 0 0x4000>; 1543 reg-names = "pcie-mac"; 1544 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1545 bus-range = <0x00 0xff>; 1546 ranges = <0x81000000 0 0x24000000 1547 0x0 0x24000000 0 0x200000>, 1548 <0x82000000 0 0x24200000 1549 0x0 0x24200000 0 0x3e00000>; 1550 1551 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1552 iommu-map-mask = <0x0>; 1553 1554 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1555 <&clk26m>, 1556 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1557 <&clk26m>, 1558 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1559 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1560 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1561 clock-names = "pl_250m", "tl_26m", "tl_96m", 1562 "tl_32k", "peri_26m", "peri_mem"; 1563 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1564 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1565 1566 phys = <&u3port1 PHY_TYPE_PCIE>; 1567 phy-names = "pcie-phy"; 1568 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1569 1570 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1571 reset-names = "mac"; 1572 1573 #interrupt-cells = <1>; 1574 interrupt-map-mask = <0 0 0 7>; 1575 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1576 <0 0 0 2 &pcie_intc1 1>, 1577 <0 0 0 3 &pcie_intc1 2>, 1578 <0 0 0 4 &pcie_intc1 3>; 1579 status = "disabled"; 1580 1581 pcie_intc1: interrupt-controller { 1582 interrupt-controller; 1583 #address-cells = <0>; 1584 #interrupt-cells = <1>; 1585 }; 1586 }; 1587 1588 nor_flash: spi@1132c000 { 1589 compatible = "mediatek,mt8195-nor", 1590 "mediatek,mt8173-nor"; 1591 reg = <0 0x1132c000 0 0x1000>; 1592 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1593 clocks = <&topckgen CLK_TOP_SPINOR>, 1594 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1595 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1596 clock-names = "spi", "sf", "axi"; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 status = "disabled"; 1600 }; 1601 1602 efuse: efuse@11c10000 { 1603 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1604 reg = <0 0x11c10000 0 0x1000>; 1605 #address-cells = <1>; 1606 #size-cells = <1>; 1607 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1608 reg = <0x184 0x1>; 1609 bits = <0 5>; 1610 }; 1611 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1612 reg = <0x184 0x2>; 1613 bits = <5 5>; 1614 }; 1615 u3_intr_p0: usb3-intr@185 { 1616 reg = <0x185 0x1>; 1617 bits = <2 6>; 1618 }; 1619 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1620 reg = <0x186 0x1>; 1621 bits = <0 5>; 1622 }; 1623 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1624 reg = <0x186 0x2>; 1625 bits = <5 5>; 1626 }; 1627 comb_intr_p1: usb3-intr@187 { 1628 reg = <0x187 0x1>; 1629 bits = <2 6>; 1630 }; 1631 u2_intr_p0: usb2-intr-p0@188,1 { 1632 reg = <0x188 0x1>; 1633 bits = <0 5>; 1634 }; 1635 u2_intr_p1: usb2-intr-p1@188,2 { 1636 reg = <0x188 0x2>; 1637 bits = <5 5>; 1638 }; 1639 u2_intr_p2: usb2-intr-p2@189,1 { 1640 reg = <0x189 0x1>; 1641 bits = <2 5>; 1642 }; 1643 u2_intr_p3: usb2-intr-p3@189,2 { 1644 reg = <0x189 0x2>; 1645 bits = <7 5>; 1646 }; 1647 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1648 reg = <0x190 0x1>; 1649 bits = <0 4>; 1650 }; 1651 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1652 reg = <0x190 0x1>; 1653 bits = <4 4>; 1654 }; 1655 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1656 reg = <0x191 0x1>; 1657 bits = <0 4>; 1658 }; 1659 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1660 reg = <0x191 0x1>; 1661 bits = <4 4>; 1662 }; 1663 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1664 reg = <0x192 0x1>; 1665 bits = <0 4>; 1666 }; 1667 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1668 reg = <0x192 0x1>; 1669 bits = <4 4>; 1670 }; 1671 pciephy_glb_intr: pciephy-glb-intr@193 { 1672 reg = <0x193 0x1>; 1673 bits = <0 4>; 1674 }; 1675 dp_calibration: dp-data@1ac { 1676 reg = <0x1ac 0x10>; 1677 }; 1678 lvts_efuse_data1: lvts1-calib@1bc { 1679 reg = <0x1bc 0x14>; 1680 }; 1681 lvts_efuse_data2: lvts2-calib@1d0 { 1682 reg = <0x1d0 0x38>; 1683 }; 1684 }; 1685 1686 u3phy2: t-phy@11c40000 { 1687 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1688 #address-cells = <1>; 1689 #size-cells = <1>; 1690 ranges = <0 0 0x11c40000 0x700>; 1691 status = "disabled"; 1692 1693 u2port2: usb-phy@0 { 1694 reg = <0x0 0x700>; 1695 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1696 clock-names = "ref"; 1697 #phy-cells = <1>; 1698 }; 1699 }; 1700 1701 u3phy3: t-phy@11c50000 { 1702 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1703 #address-cells = <1>; 1704 #size-cells = <1>; 1705 ranges = <0 0 0x11c50000 0x700>; 1706 status = "disabled"; 1707 1708 u2port3: usb-phy@0 { 1709 reg = <0x0 0x700>; 1710 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1711 clock-names = "ref"; 1712 #phy-cells = <1>; 1713 }; 1714 }; 1715 1716 i2c5: i2c@11d00000 { 1717 compatible = "mediatek,mt8195-i2c", 1718 "mediatek,mt8192-i2c"; 1719 reg = <0 0x11d00000 0 0x1000>, 1720 <0 0x10220580 0 0x80>; 1721 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1722 clock-div = <1>; 1723 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1724 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1725 clock-names = "main", "dma"; 1726 #address-cells = <1>; 1727 #size-cells = <0>; 1728 status = "disabled"; 1729 }; 1730 1731 i2c6: i2c@11d01000 { 1732 compatible = "mediatek,mt8195-i2c", 1733 "mediatek,mt8192-i2c"; 1734 reg = <0 0x11d01000 0 0x1000>, 1735 <0 0x10220600 0 0x80>; 1736 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1737 clock-div = <1>; 1738 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1739 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1740 clock-names = "main", "dma"; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 status = "disabled"; 1744 }; 1745 1746 i2c7: i2c@11d02000 { 1747 compatible = "mediatek,mt8195-i2c", 1748 "mediatek,mt8192-i2c"; 1749 reg = <0 0x11d02000 0 0x1000>, 1750 <0 0x10220680 0 0x80>; 1751 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1752 clock-div = <1>; 1753 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1754 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1755 clock-names = "main", "dma"; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 status = "disabled"; 1759 }; 1760 1761 imp_iic_wrap_s: clock-controller@11d03000 { 1762 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1763 reg = <0 0x11d03000 0 0x1000>; 1764 #clock-cells = <1>; 1765 }; 1766 1767 i2c0: i2c@11e00000 { 1768 compatible = "mediatek,mt8195-i2c", 1769 "mediatek,mt8192-i2c"; 1770 reg = <0 0x11e00000 0 0x1000>, 1771 <0 0x10220080 0 0x80>; 1772 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1773 clock-div = <1>; 1774 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1775 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1776 clock-names = "main", "dma"; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 i2c1: i2c@11e01000 { 1783 compatible = "mediatek,mt8195-i2c", 1784 "mediatek,mt8192-i2c"; 1785 reg = <0 0x11e01000 0 0x1000>, 1786 <0 0x10220200 0 0x80>; 1787 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1788 clock-div = <1>; 1789 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1790 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1791 clock-names = "main", "dma"; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 status = "disabled"; 1795 }; 1796 1797 i2c2: i2c@11e02000 { 1798 compatible = "mediatek,mt8195-i2c", 1799 "mediatek,mt8192-i2c"; 1800 reg = <0 0x11e02000 0 0x1000>, 1801 <0 0x10220380 0 0x80>; 1802 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1803 clock-div = <1>; 1804 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1805 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1806 clock-names = "main", "dma"; 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 status = "disabled"; 1810 }; 1811 1812 i2c3: i2c@11e03000 { 1813 compatible = "mediatek,mt8195-i2c", 1814 "mediatek,mt8192-i2c"; 1815 reg = <0 0x11e03000 0 0x1000>, 1816 <0 0x10220480 0 0x80>; 1817 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1818 clock-div = <1>; 1819 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1820 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1821 clock-names = "main", "dma"; 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 status = "disabled"; 1825 }; 1826 1827 i2c4: i2c@11e04000 { 1828 compatible = "mediatek,mt8195-i2c", 1829 "mediatek,mt8192-i2c"; 1830 reg = <0 0x11e04000 0 0x1000>, 1831 <0 0x10220500 0 0x80>; 1832 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1833 clock-div = <1>; 1834 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1835 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1836 clock-names = "main", "dma"; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 status = "disabled"; 1840 }; 1841 1842 imp_iic_wrap_w: clock-controller@11e05000 { 1843 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1844 reg = <0 0x11e05000 0 0x1000>; 1845 #clock-cells = <1>; 1846 }; 1847 1848 u3phy1: t-phy@11e30000 { 1849 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1850 #address-cells = <1>; 1851 #size-cells = <1>; 1852 ranges = <0 0 0x11e30000 0xe00>; 1853 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1854 status = "disabled"; 1855 1856 u2port1: usb-phy@0 { 1857 reg = <0x0 0x700>; 1858 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1859 <&clk26m>; 1860 clock-names = "ref", "da_ref"; 1861 #phy-cells = <1>; 1862 }; 1863 1864 u3port1: usb-phy@700 { 1865 reg = <0x700 0x700>; 1866 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1867 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1868 clock-names = "ref", "da_ref"; 1869 nvmem-cells = <&comb_intr_p1>, 1870 <&comb_rx_imp_p1>, 1871 <&comb_tx_imp_p1>; 1872 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1873 #phy-cells = <1>; 1874 }; 1875 }; 1876 1877 u3phy0: t-phy@11e40000 { 1878 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1879 #address-cells = <1>; 1880 #size-cells = <1>; 1881 ranges = <0 0 0x11e40000 0xe00>; 1882 status = "disabled"; 1883 1884 u2port0: usb-phy@0 { 1885 reg = <0x0 0x700>; 1886 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1887 <&clk26m>; 1888 clock-names = "ref", "da_ref"; 1889 #phy-cells = <1>; 1890 }; 1891 1892 u3port0: usb-phy@700 { 1893 reg = <0x700 0x700>; 1894 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1895 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1896 clock-names = "ref", "da_ref"; 1897 nvmem-cells = <&u3_intr_p0>, 1898 <&u3_rx_imp_p0>, 1899 <&u3_tx_imp_p0>; 1900 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1901 #phy-cells = <1>; 1902 }; 1903 }; 1904 1905 pciephy: phy@11e80000 { 1906 compatible = "mediatek,mt8195-pcie-phy"; 1907 reg = <0 0x11e80000 0 0x10000>; 1908 reg-names = "sif"; 1909 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1910 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1911 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1912 <&pciephy_rx_ln1>; 1913 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1914 "tx_ln0_nmos", "rx_ln0", 1915 "tx_ln1_pmos", "tx_ln1_nmos", 1916 "rx_ln1"; 1917 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1918 #phy-cells = <0>; 1919 status = "disabled"; 1920 }; 1921 1922 ufsphy: ufs-phy@11fa0000 { 1923 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1924 reg = <0 0x11fa0000 0 0xc000>; 1925 clocks = <&clk26m>, <&clk26m>; 1926 clock-names = "unipro", "mp"; 1927 #phy-cells = <0>; 1928 status = "disabled"; 1929 }; 1930 1931 gpu: gpu@13000000 { 1932 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 1933 "arm,mali-valhall-jm"; 1934 reg = <0 0x13000000 0 0x4000>; 1935 1936 clocks = <&mfgcfg CLK_MFG_BG3D>; 1937 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 1938 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 1939 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 1940 interrupt-names = "job", "mmu", "gpu"; 1941 operating-points-v2 = <&gpu_opp_table>; 1942 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 1943 <&spm MT8195_POWER_DOMAIN_MFG3>, 1944 <&spm MT8195_POWER_DOMAIN_MFG4>, 1945 <&spm MT8195_POWER_DOMAIN_MFG5>, 1946 <&spm MT8195_POWER_DOMAIN_MFG6>; 1947 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1948 status = "disabled"; 1949 }; 1950 1951 mfgcfg: clock-controller@13fbf000 { 1952 compatible = "mediatek,mt8195-mfgcfg"; 1953 reg = <0 0x13fbf000 0 0x1000>; 1954 #clock-cells = <1>; 1955 }; 1956 1957 vppsys0: syscon@14000000 { 1958 compatible = "mediatek,mt8195-vppsys0", "syscon"; 1959 reg = <0 0x14000000 0 0x1000>; 1960 #clock-cells = <1>; 1961 }; 1962 1963 mutex@1400f000 { 1964 compatible = "mediatek,mt8195-vpp-mutex"; 1965 reg = <0 0x1400f000 0 0x1000>; 1966 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 1967 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 1968 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 1969 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1970 }; 1971 1972 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1973 compatible = "mediatek,mt8195-smi-sub-common"; 1974 reg = <0 0x14010000 0 0x1000>; 1975 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1976 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1977 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1978 clock-names = "apb", "smi", "gals0"; 1979 mediatek,smi = <&smi_common_vpp>; 1980 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1981 }; 1982 1983 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1984 compatible = "mediatek,mt8195-smi-sub-common"; 1985 reg = <0 0x14011000 0 0x1000>; 1986 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1987 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1988 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1989 clock-names = "apb", "smi", "gals0"; 1990 mediatek,smi = <&smi_common_vpp>; 1991 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1992 }; 1993 1994 smi_common_vpp: smi@14012000 { 1995 compatible = "mediatek,mt8195-smi-common-vpp"; 1996 reg = <0 0x14012000 0 0x1000>; 1997 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1998 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1999 <&vppsys0 CLK_VPP0_SMI_RSI>, 2000 <&vppsys0 CLK_VPP0_SMI_RSI>; 2001 clock-names = "apb", "smi", "gals0", "gals1"; 2002 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2003 }; 2004 2005 larb4: larb@14013000 { 2006 compatible = "mediatek,mt8195-smi-larb"; 2007 reg = <0 0x14013000 0 0x1000>; 2008 mediatek,larb-id = <4>; 2009 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2010 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2011 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2012 clock-names = "apb", "smi"; 2013 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2014 }; 2015 2016 iommu_vpp: iommu@14018000 { 2017 compatible = "mediatek,mt8195-iommu-vpp"; 2018 reg = <0 0x14018000 0 0x1000>; 2019 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2020 &larb12 &larb14 &larb16 &larb18 2021 &larb20 &larb22 &larb23 &larb26 2022 &larb27>; 2023 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2024 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2025 clock-names = "bclk"; 2026 #iommu-cells = <1>; 2027 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2028 }; 2029 2030 wpesys: clock-controller@14e00000 { 2031 compatible = "mediatek,mt8195-wpesys"; 2032 reg = <0 0x14e00000 0 0x1000>; 2033 #clock-cells = <1>; 2034 }; 2035 2036 wpesys_vpp0: clock-controller@14e02000 { 2037 compatible = "mediatek,mt8195-wpesys_vpp0"; 2038 reg = <0 0x14e02000 0 0x1000>; 2039 #clock-cells = <1>; 2040 }; 2041 2042 wpesys_vpp1: clock-controller@14e03000 { 2043 compatible = "mediatek,mt8195-wpesys_vpp1"; 2044 reg = <0 0x14e03000 0 0x1000>; 2045 #clock-cells = <1>; 2046 }; 2047 2048 larb7: larb@14e04000 { 2049 compatible = "mediatek,mt8195-smi-larb"; 2050 reg = <0 0x14e04000 0 0x1000>; 2051 mediatek,larb-id = <7>; 2052 mediatek,smi = <&smi_common_vdo>; 2053 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2054 <&wpesys CLK_WPE_SMI_LARB7>; 2055 clock-names = "apb", "smi"; 2056 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2057 }; 2058 2059 larb8: larb@14e05000 { 2060 compatible = "mediatek,mt8195-smi-larb"; 2061 reg = <0 0x14e05000 0 0x1000>; 2062 mediatek,larb-id = <8>; 2063 mediatek,smi = <&smi_common_vpp>; 2064 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2065 <&wpesys CLK_WPE_SMI_LARB8>, 2066 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2067 clock-names = "apb", "smi", "gals"; 2068 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2069 }; 2070 2071 vppsys1: syscon@14f00000 { 2072 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2073 reg = <0 0x14f00000 0 0x1000>; 2074 #clock-cells = <1>; 2075 }; 2076 2077 mutex@14f01000 { 2078 compatible = "mediatek,mt8195-vpp-mutex"; 2079 reg = <0 0x14f01000 0 0x1000>; 2080 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2081 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2082 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2083 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2084 }; 2085 2086 larb5: larb@14f02000 { 2087 compatible = "mediatek,mt8195-smi-larb"; 2088 reg = <0 0x14f02000 0 0x1000>; 2089 mediatek,larb-id = <5>; 2090 mediatek,smi = <&smi_common_vdo>; 2091 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2092 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2093 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2094 clock-names = "apb", "smi", "gals"; 2095 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2096 }; 2097 2098 larb6: larb@14f03000 { 2099 compatible = "mediatek,mt8195-smi-larb"; 2100 reg = <0 0x14f03000 0 0x1000>; 2101 mediatek,larb-id = <6>; 2102 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2103 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2104 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2105 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2106 clock-names = "apb", "smi", "gals"; 2107 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2108 }; 2109 2110 imgsys: clock-controller@15000000 { 2111 compatible = "mediatek,mt8195-imgsys"; 2112 reg = <0 0x15000000 0 0x1000>; 2113 #clock-cells = <1>; 2114 }; 2115 2116 larb9: larb@15001000 { 2117 compatible = "mediatek,mt8195-smi-larb"; 2118 reg = <0 0x15001000 0 0x1000>; 2119 mediatek,larb-id = <9>; 2120 mediatek,smi = <&smi_sub_common_img1_3x1>; 2121 clocks = <&imgsys CLK_IMG_LARB9>, 2122 <&imgsys CLK_IMG_LARB9>, 2123 <&imgsys CLK_IMG_GALS>; 2124 clock-names = "apb", "smi", "gals"; 2125 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2126 }; 2127 2128 smi_sub_common_img0_3x1: smi@15002000 { 2129 compatible = "mediatek,mt8195-smi-sub-common"; 2130 reg = <0 0x15002000 0 0x1000>; 2131 clocks = <&imgsys CLK_IMG_IPE>, 2132 <&imgsys CLK_IMG_IPE>, 2133 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2134 clock-names = "apb", "smi", "gals0"; 2135 mediatek,smi = <&smi_common_vpp>; 2136 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2137 }; 2138 2139 smi_sub_common_img1_3x1: smi@15003000 { 2140 compatible = "mediatek,mt8195-smi-sub-common"; 2141 reg = <0 0x15003000 0 0x1000>; 2142 clocks = <&imgsys CLK_IMG_LARB9>, 2143 <&imgsys CLK_IMG_LARB9>, 2144 <&imgsys CLK_IMG_GALS>; 2145 clock-names = "apb", "smi", "gals0"; 2146 mediatek,smi = <&smi_common_vdo>; 2147 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2148 }; 2149 2150 imgsys1_dip_top: clock-controller@15110000 { 2151 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2152 reg = <0 0x15110000 0 0x1000>; 2153 #clock-cells = <1>; 2154 }; 2155 2156 larb10: larb@15120000 { 2157 compatible = "mediatek,mt8195-smi-larb"; 2158 reg = <0 0x15120000 0 0x1000>; 2159 mediatek,larb-id = <10>; 2160 mediatek,smi = <&smi_sub_common_img1_3x1>; 2161 clocks = <&imgsys CLK_IMG_DIP0>, 2162 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2163 clock-names = "apb", "smi"; 2164 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2165 }; 2166 2167 imgsys1_dip_nr: clock-controller@15130000 { 2168 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2169 reg = <0 0x15130000 0 0x1000>; 2170 #clock-cells = <1>; 2171 }; 2172 2173 imgsys1_wpe: clock-controller@15220000 { 2174 compatible = "mediatek,mt8195-imgsys1_wpe"; 2175 reg = <0 0x15220000 0 0x1000>; 2176 #clock-cells = <1>; 2177 }; 2178 2179 larb11: larb@15230000 { 2180 compatible = "mediatek,mt8195-smi-larb"; 2181 reg = <0 0x15230000 0 0x1000>; 2182 mediatek,larb-id = <11>; 2183 mediatek,smi = <&smi_sub_common_img1_3x1>; 2184 clocks = <&imgsys CLK_IMG_WPE0>, 2185 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2186 clock-names = "apb", "smi"; 2187 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2188 }; 2189 2190 ipesys: clock-controller@15330000 { 2191 compatible = "mediatek,mt8195-ipesys"; 2192 reg = <0 0x15330000 0 0x1000>; 2193 #clock-cells = <1>; 2194 }; 2195 2196 larb12: larb@15340000 { 2197 compatible = "mediatek,mt8195-smi-larb"; 2198 reg = <0 0x15340000 0 0x1000>; 2199 mediatek,larb-id = <12>; 2200 mediatek,smi = <&smi_sub_common_img0_3x1>; 2201 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2202 <&ipesys CLK_IPE_SMI_LARB12>; 2203 clock-names = "apb", "smi"; 2204 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2205 }; 2206 2207 camsys: clock-controller@16000000 { 2208 compatible = "mediatek,mt8195-camsys"; 2209 reg = <0 0x16000000 0 0x1000>; 2210 #clock-cells = <1>; 2211 }; 2212 2213 larb13: larb@16001000 { 2214 compatible = "mediatek,mt8195-smi-larb"; 2215 reg = <0 0x16001000 0 0x1000>; 2216 mediatek,larb-id = <13>; 2217 mediatek,smi = <&smi_sub_common_cam_4x1>; 2218 clocks = <&camsys CLK_CAM_LARB13>, 2219 <&camsys CLK_CAM_LARB13>, 2220 <&camsys CLK_CAM_CAM2MM0_GALS>; 2221 clock-names = "apb", "smi", "gals"; 2222 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2223 }; 2224 2225 larb14: larb@16002000 { 2226 compatible = "mediatek,mt8195-smi-larb"; 2227 reg = <0 0x16002000 0 0x1000>; 2228 mediatek,larb-id = <14>; 2229 mediatek,smi = <&smi_sub_common_cam_7x1>; 2230 clocks = <&camsys CLK_CAM_LARB14>, 2231 <&camsys CLK_CAM_LARB14>; 2232 clock-names = "apb", "smi"; 2233 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2234 }; 2235 2236 smi_sub_common_cam_4x1: smi@16004000 { 2237 compatible = "mediatek,mt8195-smi-sub-common"; 2238 reg = <0 0x16004000 0 0x1000>; 2239 clocks = <&camsys CLK_CAM_LARB13>, 2240 <&camsys CLK_CAM_LARB13>, 2241 <&camsys CLK_CAM_CAM2MM0_GALS>; 2242 clock-names = "apb", "smi", "gals0"; 2243 mediatek,smi = <&smi_common_vdo>; 2244 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2245 }; 2246 2247 smi_sub_common_cam_7x1: smi@16005000 { 2248 compatible = "mediatek,mt8195-smi-sub-common"; 2249 reg = <0 0x16005000 0 0x1000>; 2250 clocks = <&camsys CLK_CAM_LARB14>, 2251 <&camsys CLK_CAM_CAM2MM1_GALS>, 2252 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2253 clock-names = "apb", "smi", "gals0"; 2254 mediatek,smi = <&smi_common_vpp>; 2255 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2256 }; 2257 2258 larb16: larb@16012000 { 2259 compatible = "mediatek,mt8195-smi-larb"; 2260 reg = <0 0x16012000 0 0x1000>; 2261 mediatek,larb-id = <16>; 2262 mediatek,smi = <&smi_sub_common_cam_7x1>; 2263 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2264 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2265 clock-names = "apb", "smi"; 2266 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2267 }; 2268 2269 larb17: larb@16013000 { 2270 compatible = "mediatek,mt8195-smi-larb"; 2271 reg = <0 0x16013000 0 0x1000>; 2272 mediatek,larb-id = <17>; 2273 mediatek,smi = <&smi_sub_common_cam_4x1>; 2274 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2275 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2276 clock-names = "apb", "smi"; 2277 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2278 }; 2279 2280 larb27: larb@16014000 { 2281 compatible = "mediatek,mt8195-smi-larb"; 2282 reg = <0 0x16014000 0 0x1000>; 2283 mediatek,larb-id = <27>; 2284 mediatek,smi = <&smi_sub_common_cam_7x1>; 2285 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2286 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2287 clock-names = "apb", "smi"; 2288 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2289 }; 2290 2291 larb28: larb@16015000 { 2292 compatible = "mediatek,mt8195-smi-larb"; 2293 reg = <0 0x16015000 0 0x1000>; 2294 mediatek,larb-id = <28>; 2295 mediatek,smi = <&smi_sub_common_cam_4x1>; 2296 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2297 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2298 clock-names = "apb", "smi"; 2299 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2300 }; 2301 2302 camsys_rawa: clock-controller@1604f000 { 2303 compatible = "mediatek,mt8195-camsys_rawa"; 2304 reg = <0 0x1604f000 0 0x1000>; 2305 #clock-cells = <1>; 2306 }; 2307 2308 camsys_yuva: clock-controller@1606f000 { 2309 compatible = "mediatek,mt8195-camsys_yuva"; 2310 reg = <0 0x1606f000 0 0x1000>; 2311 #clock-cells = <1>; 2312 }; 2313 2314 camsys_rawb: clock-controller@1608f000 { 2315 compatible = "mediatek,mt8195-camsys_rawb"; 2316 reg = <0 0x1608f000 0 0x1000>; 2317 #clock-cells = <1>; 2318 }; 2319 2320 camsys_yuvb: clock-controller@160af000 { 2321 compatible = "mediatek,mt8195-camsys_yuvb"; 2322 reg = <0 0x160af000 0 0x1000>; 2323 #clock-cells = <1>; 2324 }; 2325 2326 camsys_mraw: clock-controller@16140000 { 2327 compatible = "mediatek,mt8195-camsys_mraw"; 2328 reg = <0 0x16140000 0 0x1000>; 2329 #clock-cells = <1>; 2330 }; 2331 2332 larb25: larb@16141000 { 2333 compatible = "mediatek,mt8195-smi-larb"; 2334 reg = <0 0x16141000 0 0x1000>; 2335 mediatek,larb-id = <25>; 2336 mediatek,smi = <&smi_sub_common_cam_4x1>; 2337 clocks = <&camsys CLK_CAM_LARB13>, 2338 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2339 <&camsys CLK_CAM_CAM2MM0_GALS>; 2340 clock-names = "apb", "smi", "gals"; 2341 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2342 }; 2343 2344 larb26: larb@16142000 { 2345 compatible = "mediatek,mt8195-smi-larb"; 2346 reg = <0 0x16142000 0 0x1000>; 2347 mediatek,larb-id = <26>; 2348 mediatek,smi = <&smi_sub_common_cam_7x1>; 2349 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2350 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2351 clock-names = "apb", "smi"; 2352 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2353 2354 }; 2355 2356 ccusys: clock-controller@17200000 { 2357 compatible = "mediatek,mt8195-ccusys"; 2358 reg = <0 0x17200000 0 0x1000>; 2359 #clock-cells = <1>; 2360 }; 2361 2362 larb18: larb@17201000 { 2363 compatible = "mediatek,mt8195-smi-larb"; 2364 reg = <0 0x17201000 0 0x1000>; 2365 mediatek,larb-id = <18>; 2366 mediatek,smi = <&smi_sub_common_cam_7x1>; 2367 clocks = <&ccusys CLK_CCU_LARB18>, 2368 <&ccusys CLK_CCU_LARB18>; 2369 clock-names = "apb", "smi"; 2370 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2371 }; 2372 2373 video-codec@18000000 { 2374 compatible = "mediatek,mt8195-vcodec-dec"; 2375 mediatek,scp = <&scp>; 2376 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2377 #address-cells = <2>; 2378 #size-cells = <2>; 2379 reg = <0 0x18000000 0 0x1000>, 2380 <0 0x18004000 0 0x1000>; 2381 ranges = <0 0 0 0x18000000 0 0x26000>; 2382 2383 video-codec@2000 { 2384 compatible = "mediatek,mtk-vcodec-lat-soc"; 2385 reg = <0 0x2000 0 0x800>; 2386 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2387 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2388 clocks = <&topckgen CLK_TOP_VDEC>, 2389 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2390 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2391 <&topckgen CLK_TOP_UNIVPLL_D4>; 2392 clock-names = "sel", "vdec", "lat", "top"; 2393 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2394 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2395 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2396 }; 2397 2398 video-codec@10000 { 2399 compatible = "mediatek,mtk-vcodec-lat"; 2400 reg = <0 0x10000 0 0x800>; 2401 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2402 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2403 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2404 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2405 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2406 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2407 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2408 clocks = <&topckgen CLK_TOP_VDEC>, 2409 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2410 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2411 <&topckgen CLK_TOP_UNIVPLL_D4>; 2412 clock-names = "sel", "vdec", "lat", "top"; 2413 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2414 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2415 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2416 }; 2417 2418 video-codec@25000 { 2419 compatible = "mediatek,mtk-vcodec-core"; 2420 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2421 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2422 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2423 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2424 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2425 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2426 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2427 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2428 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2429 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2430 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2431 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2432 clocks = <&topckgen CLK_TOP_VDEC>, 2433 <&vdecsys CLK_VDEC_VDEC>, 2434 <&vdecsys CLK_VDEC_LAT>, 2435 <&topckgen CLK_TOP_UNIVPLL_D4>; 2436 clock-names = "sel", "vdec", "lat", "top"; 2437 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2438 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2439 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2440 }; 2441 }; 2442 2443 larb24: larb@1800d000 { 2444 compatible = "mediatek,mt8195-smi-larb"; 2445 reg = <0 0x1800d000 0 0x1000>; 2446 mediatek,larb-id = <24>; 2447 mediatek,smi = <&smi_common_vdo>; 2448 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2449 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2450 clock-names = "apb", "smi"; 2451 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2452 }; 2453 2454 larb23: larb@1800e000 { 2455 compatible = "mediatek,mt8195-smi-larb"; 2456 reg = <0 0x1800e000 0 0x1000>; 2457 mediatek,larb-id = <23>; 2458 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2459 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2460 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2461 clock-names = "apb", "smi"; 2462 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2463 }; 2464 2465 vdecsys_soc: clock-controller@1800f000 { 2466 compatible = "mediatek,mt8195-vdecsys_soc"; 2467 reg = <0 0x1800f000 0 0x1000>; 2468 #clock-cells = <1>; 2469 }; 2470 2471 larb21: larb@1802e000 { 2472 compatible = "mediatek,mt8195-smi-larb"; 2473 reg = <0 0x1802e000 0 0x1000>; 2474 mediatek,larb-id = <21>; 2475 mediatek,smi = <&smi_common_vdo>; 2476 clocks = <&vdecsys CLK_VDEC_LARB1>, 2477 <&vdecsys CLK_VDEC_LARB1>; 2478 clock-names = "apb", "smi"; 2479 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2480 }; 2481 2482 vdecsys: clock-controller@1802f000 { 2483 compatible = "mediatek,mt8195-vdecsys"; 2484 reg = <0 0x1802f000 0 0x1000>; 2485 #clock-cells = <1>; 2486 }; 2487 2488 larb22: larb@1803e000 { 2489 compatible = "mediatek,mt8195-smi-larb"; 2490 reg = <0 0x1803e000 0 0x1000>; 2491 mediatek,larb-id = <22>; 2492 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2493 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2494 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2495 clock-names = "apb", "smi"; 2496 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2497 }; 2498 2499 vdecsys_core1: clock-controller@1803f000 { 2500 compatible = "mediatek,mt8195-vdecsys_core1"; 2501 reg = <0 0x1803f000 0 0x1000>; 2502 #clock-cells = <1>; 2503 }; 2504 2505 apusys_pll: clock-controller@190f3000 { 2506 compatible = "mediatek,mt8195-apusys_pll"; 2507 reg = <0 0x190f3000 0 0x1000>; 2508 #clock-cells = <1>; 2509 }; 2510 2511 vencsys: clock-controller@1a000000 { 2512 compatible = "mediatek,mt8195-vencsys"; 2513 reg = <0 0x1a000000 0 0x1000>; 2514 #clock-cells = <1>; 2515 }; 2516 2517 larb19: larb@1a010000 { 2518 compatible = "mediatek,mt8195-smi-larb"; 2519 reg = <0 0x1a010000 0 0x1000>; 2520 mediatek,larb-id = <19>; 2521 mediatek,smi = <&smi_common_vdo>; 2522 clocks = <&vencsys CLK_VENC_VENC>, 2523 <&vencsys CLK_VENC_GALS>; 2524 clock-names = "apb", "smi"; 2525 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2526 }; 2527 2528 venc: video-codec@1a020000 { 2529 compatible = "mediatek,mt8195-vcodec-enc"; 2530 reg = <0 0x1a020000 0 0x10000>; 2531 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2532 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2533 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2534 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2535 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2536 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2537 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2538 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2539 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2540 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2541 mediatek,scp = <&scp>; 2542 clocks = <&vencsys CLK_VENC_VENC>; 2543 clock-names = "venc_sel"; 2544 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2545 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2546 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2547 #address-cells = <2>; 2548 #size-cells = <2>; 2549 }; 2550 2551 jpgdec-master { 2552 compatible = "mediatek,mt8195-jpgdec"; 2553 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2554 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2555 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2556 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2557 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2558 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2559 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2560 #address-cells = <2>; 2561 #size-cells = <2>; 2562 ranges; 2563 2564 jpgdec@1a040000 { 2565 compatible = "mediatek,mt8195-jpgdec-hw"; 2566 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2567 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2568 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2569 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2570 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2571 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2572 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2573 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2574 clocks = <&vencsys CLK_VENC_JPGDEC>; 2575 clock-names = "jpgdec"; 2576 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2577 }; 2578 2579 jpgdec@1a050000 { 2580 compatible = "mediatek,mt8195-jpgdec-hw"; 2581 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2582 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2583 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2584 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2585 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2586 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2587 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2588 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 2589 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 2590 clock-names = "jpgdec"; 2591 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2592 }; 2593 2594 jpgdec@1b040000 { 2595 compatible = "mediatek,mt8195-jpgdec-hw"; 2596 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 2597 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 2598 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 2599 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 2600 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 2601 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 2602 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 2603 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 2604 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 2605 clock-names = "jpgdec"; 2606 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2607 }; 2608 }; 2609 2610 vencsys_core1: clock-controller@1b000000 { 2611 compatible = "mediatek,mt8195-vencsys_core1"; 2612 reg = <0 0x1b000000 0 0x1000>; 2613 #clock-cells = <1>; 2614 }; 2615 2616 vdosys0: syscon@1c01a000 { 2617 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 2618 reg = <0 0x1c01a000 0 0x1000>; 2619 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2620 #clock-cells = <1>; 2621 }; 2622 2623 2624 jpgenc-master { 2625 compatible = "mediatek,mt8195-jpgenc"; 2626 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2627 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2628 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2629 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2630 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2631 #address-cells = <2>; 2632 #size-cells = <2>; 2633 ranges; 2634 2635 jpgenc@1a030000 { 2636 compatible = "mediatek,mt8195-jpgenc-hw"; 2637 reg = <0 0x1a030000 0 0x10000>; 2638 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 2639 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 2640 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 2641 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 2642 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 2643 clocks = <&vencsys CLK_VENC_JPGENC>; 2644 clock-names = "jpgenc"; 2645 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2646 }; 2647 2648 jpgenc@1b030000 { 2649 compatible = "mediatek,mt8195-jpgenc-hw"; 2650 reg = <0 0x1b030000 0 0x10000>; 2651 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2652 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2653 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2654 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2655 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 2656 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 2657 clock-names = "jpgenc"; 2658 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2659 }; 2660 }; 2661 2662 larb20: larb@1b010000 { 2663 compatible = "mediatek,mt8195-smi-larb"; 2664 reg = <0 0x1b010000 0 0x1000>; 2665 mediatek,larb-id = <20>; 2666 mediatek,smi = <&smi_common_vpp>; 2667 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2668 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2669 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2670 clock-names = "apb", "smi", "gals"; 2671 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2672 }; 2673 2674 ovl0: ovl@1c000000 { 2675 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2676 reg = <0 0x1c000000 0 0x1000>; 2677 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2678 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2679 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2680 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2681 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2682 }; 2683 2684 rdma0: rdma@1c002000 { 2685 compatible = "mediatek,mt8195-disp-rdma"; 2686 reg = <0 0x1c002000 0 0x1000>; 2687 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2688 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2689 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2690 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2691 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2692 }; 2693 2694 color0: color@1c003000 { 2695 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2696 reg = <0 0x1c003000 0 0x1000>; 2697 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2698 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2699 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2700 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2701 }; 2702 2703 ccorr0: ccorr@1c004000 { 2704 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2705 reg = <0 0x1c004000 0 0x1000>; 2706 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2707 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2708 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2709 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2710 }; 2711 2712 aal0: aal@1c005000 { 2713 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2714 reg = <0 0x1c005000 0 0x1000>; 2715 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2716 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2717 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2718 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2719 }; 2720 2721 gamma0: gamma@1c006000 { 2722 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2723 reg = <0 0x1c006000 0 0x1000>; 2724 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2725 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2726 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2727 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2728 }; 2729 2730 dither0: dither@1c007000 { 2731 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2732 reg = <0 0x1c007000 0 0x1000>; 2733 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2734 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2735 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2736 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2737 }; 2738 2739 dsc0: dsc@1c009000 { 2740 compatible = "mediatek,mt8195-disp-dsc"; 2741 reg = <0 0x1c009000 0 0x1000>; 2742 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2743 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2744 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2745 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2746 }; 2747 2748 merge0: merge@1c014000 { 2749 compatible = "mediatek,mt8195-disp-merge"; 2750 reg = <0 0x1c014000 0 0x1000>; 2751 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2752 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2753 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2754 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2755 }; 2756 2757 dp_intf0: dp-intf@1c015000 { 2758 compatible = "mediatek,mt8195-dp-intf"; 2759 reg = <0 0x1c015000 0 0x1000>; 2760 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2761 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2762 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2763 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2764 clock-names = "engine", "pixel", "pll"; 2765 status = "disabled"; 2766 }; 2767 2768 mutex: mutex@1c016000 { 2769 compatible = "mediatek,mt8195-disp-mutex"; 2770 reg = <0 0x1c016000 0 0x1000>; 2771 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2772 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2773 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2774 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2775 }; 2776 2777 larb0: larb@1c018000 { 2778 compatible = "mediatek,mt8195-smi-larb"; 2779 reg = <0 0x1c018000 0 0x1000>; 2780 mediatek,larb-id = <0>; 2781 mediatek,smi = <&smi_common_vdo>; 2782 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2783 <&vdosys0 CLK_VDO0_SMI_LARB>, 2784 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2785 clock-names = "apb", "smi", "gals"; 2786 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2787 }; 2788 2789 larb1: larb@1c019000 { 2790 compatible = "mediatek,mt8195-smi-larb"; 2791 reg = <0 0x1c019000 0 0x1000>; 2792 mediatek,larb-id = <1>; 2793 mediatek,smi = <&smi_common_vpp>; 2794 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2795 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2796 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2797 clock-names = "apb", "smi", "gals"; 2798 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2799 }; 2800 2801 vdosys1: syscon@1c100000 { 2802 compatible = "mediatek,mt8195-vdosys1", "syscon"; 2803 reg = <0 0x1c100000 0 0x1000>; 2804 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 2805 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 2806 #clock-cells = <1>; 2807 #reset-cells = <1>; 2808 }; 2809 2810 smi_common_vdo: smi@1c01b000 { 2811 compatible = "mediatek,mt8195-smi-common-vdo"; 2812 reg = <0 0x1c01b000 0 0x1000>; 2813 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2814 <&vdosys0 CLK_VDO0_SMI_EMI>, 2815 <&vdosys0 CLK_VDO0_SMI_RSI>, 2816 <&vdosys0 CLK_VDO0_SMI_GALS>; 2817 clock-names = "apb", "smi", "gals0", "gals1"; 2818 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2819 2820 }; 2821 2822 iommu_vdo: iommu@1c01f000 { 2823 compatible = "mediatek,mt8195-iommu-vdo"; 2824 reg = <0 0x1c01f000 0 0x1000>; 2825 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2826 &larb10 &larb11 &larb13 &larb17 2827 &larb19 &larb21 &larb24 &larb25 2828 &larb28>; 2829 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2830 #iommu-cells = <1>; 2831 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2832 clock-names = "bclk"; 2833 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2834 }; 2835 2836 mutex1: mutex@1c101000 { 2837 compatible = "mediatek,mt8195-disp-mutex"; 2838 reg = <0 0x1c101000 0 0x1000>; 2839 reg-names = "vdo1_mutex"; 2840 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 2841 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2842 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 2843 clock-names = "vdo1_mutex"; 2844 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 2845 }; 2846 2847 larb2: larb@1c102000 { 2848 compatible = "mediatek,mt8195-smi-larb"; 2849 reg = <0 0x1c102000 0 0x1000>; 2850 mediatek,larb-id = <2>; 2851 mediatek,smi = <&smi_common_vdo>; 2852 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2853 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2854 <&vdosys1 CLK_VDO1_GALS>; 2855 clock-names = "apb", "smi", "gals"; 2856 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2857 }; 2858 2859 larb3: larb@1c103000 { 2860 compatible = "mediatek,mt8195-smi-larb"; 2861 reg = <0 0x1c103000 0 0x1000>; 2862 mediatek,larb-id = <3>; 2863 mediatek,smi = <&smi_common_vpp>; 2864 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2865 <&vdosys1 CLK_VDO1_GALS>, 2866 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2867 clock-names = "apb", "smi", "gals"; 2868 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2869 }; 2870 2871 vdo1_rdma0: rdma@1c104000 { 2872 compatible = "mediatek,mt8195-vdo1-rdma"; 2873 reg = <0 0x1c104000 0 0x1000>; 2874 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 2875 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 2876 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2877 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 2878 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 2879 }; 2880 2881 vdo1_rdma1: rdma@1c105000 { 2882 compatible = "mediatek,mt8195-vdo1-rdma"; 2883 reg = <0 0x1c105000 0 0x1000>; 2884 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 2885 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 2886 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2887 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 2888 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 2889 }; 2890 2891 vdo1_rdma2: rdma@1c106000 { 2892 compatible = "mediatek,mt8195-vdo1-rdma"; 2893 reg = <0 0x1c106000 0 0x1000>; 2894 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 2895 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 2896 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2897 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 2898 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 2899 }; 2900 2901 vdo1_rdma3: rdma@1c107000 { 2902 compatible = "mediatek,mt8195-vdo1-rdma"; 2903 reg = <0 0x1c107000 0 0x1000>; 2904 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 2905 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 2906 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2907 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 2908 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 2909 }; 2910 2911 vdo1_rdma4: rdma@1c108000 { 2912 compatible = "mediatek,mt8195-vdo1-rdma"; 2913 reg = <0 0x1c108000 0 0x1000>; 2914 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 2915 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 2916 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2917 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 2918 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 2919 }; 2920 2921 vdo1_rdma5: rdma@1c109000 { 2922 compatible = "mediatek,mt8195-vdo1-rdma"; 2923 reg = <0 0x1c109000 0 0x1000>; 2924 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 2925 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 2926 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2927 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 2928 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 2929 }; 2930 2931 vdo1_rdma6: rdma@1c10a000 { 2932 compatible = "mediatek,mt8195-vdo1-rdma"; 2933 reg = <0 0x1c10a000 0 0x1000>; 2934 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 2935 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 2936 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2937 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 2938 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 2939 }; 2940 2941 vdo1_rdma7: rdma@1c10b000 { 2942 compatible = "mediatek,mt8195-vdo1-rdma"; 2943 reg = <0 0x1c10b000 0 0x1000>; 2944 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 2945 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 2946 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2947 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 2948 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 2949 }; 2950 2951 merge1: vpp-merge@1c10c000 { 2952 compatible = "mediatek,mt8195-disp-merge"; 2953 reg = <0 0x1c10c000 0 0x1000>; 2954 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 2955 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 2956 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 2957 clock-names = "merge","merge_async"; 2958 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2959 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 2960 mediatek,merge-mute = <1>; 2961 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 2962 }; 2963 2964 merge2: vpp-merge@1c10d000 { 2965 compatible = "mediatek,mt8195-disp-merge"; 2966 reg = <0 0x1c10d000 0 0x1000>; 2967 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 2968 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 2969 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 2970 clock-names = "merge","merge_async"; 2971 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2972 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 2973 mediatek,merge-mute = <1>; 2974 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 2975 }; 2976 2977 merge3: vpp-merge@1c10e000 { 2978 compatible = "mediatek,mt8195-disp-merge"; 2979 reg = <0 0x1c10e000 0 0x1000>; 2980 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 2981 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 2982 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 2983 clock-names = "merge","merge_async"; 2984 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2985 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 2986 mediatek,merge-mute = <1>; 2987 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 2988 }; 2989 2990 merge4: vpp-merge@1c10f000 { 2991 compatible = "mediatek,mt8195-disp-merge"; 2992 reg = <0 0x1c10f000 0 0x1000>; 2993 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 2994 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 2995 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 2996 clock-names = "merge","merge_async"; 2997 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2998 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 2999 mediatek,merge-mute = <1>; 3000 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3001 }; 3002 3003 merge5: vpp-merge@1c110000 { 3004 compatible = "mediatek,mt8195-disp-merge"; 3005 reg = <0 0x1c110000 0 0x1000>; 3006 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3007 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3008 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3009 clock-names = "merge","merge_async"; 3010 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3011 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3012 mediatek,merge-fifo-en = <1>; 3013 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3014 }; 3015 3016 dp_intf1: dp-intf@1c113000 { 3017 compatible = "mediatek,mt8195-dp-intf"; 3018 reg = <0 0x1c113000 0 0x1000>; 3019 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3020 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3021 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3022 <&vdosys1 CLK_VDO1_DPINTF>, 3023 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3024 clock-names = "engine", "pixel", "pll"; 3025 status = "disabled"; 3026 }; 3027 3028 ethdr0: hdr-engine@1c114000 { 3029 compatible = "mediatek,mt8195-disp-ethdr"; 3030 reg = <0 0x1c114000 0 0x1000>, 3031 <0 0x1c115000 0 0x1000>, 3032 <0 0x1c117000 0 0x1000>, 3033 <0 0x1c119000 0 0x1000>, 3034 <0 0x1c11a000 0 0x1000>, 3035 <0 0x1c11b000 0 0x1000>, 3036 <0 0x1c11c000 0 0x1000>; 3037 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3038 "vdo_be", "adl_ds"; 3039 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3040 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3041 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3042 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3043 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3044 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3045 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3046 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3047 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3048 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3049 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3050 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3051 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3052 <&vdosys1 CLK_VDO1_26M_SLOW>, 3053 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3054 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3055 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3056 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3057 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3058 <&topckgen CLK_TOP_ETHDR>; 3059 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3060 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3061 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3062 "ethdr_top"; 3063 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3064 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3065 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3066 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3067 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3068 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3069 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3070 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3071 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3072 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3073 "gfx_fe1_async", "vdo_be_async"; 3074 }; 3075 3076 edp_tx: edp-tx@1c500000 { 3077 compatible = "mediatek,mt8195-edp-tx"; 3078 reg = <0 0x1c500000 0 0x8000>; 3079 nvmem-cells = <&dp_calibration>; 3080 nvmem-cell-names = "dp_calibration_data"; 3081 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3082 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3083 max-linkrate-mhz = <8100>; 3084 status = "disabled"; 3085 }; 3086 3087 dp_tx: dp-tx@1c600000 { 3088 compatible = "mediatek,mt8195-dp-tx"; 3089 reg = <0 0x1c600000 0 0x8000>; 3090 nvmem-cells = <&dp_calibration>; 3091 nvmem-cell-names = "dp_calibration_data"; 3092 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3093 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3094 max-linkrate-mhz = <8100>; 3095 status = "disabled"; 3096 }; 3097 }; 3098 3099 thermal_zones: thermal-zones { 3100 cpu0-thermal { 3101 polling-delay = <1000>; 3102 polling-delay-passive = <250>; 3103 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3104 3105 trips { 3106 cpu0_alert: trip-alert { 3107 temperature = <85000>; 3108 hysteresis = <2000>; 3109 type = "passive"; 3110 }; 3111 3112 cpu0_crit: trip-crit { 3113 temperature = <100000>; 3114 hysteresis = <2000>; 3115 type = "critical"; 3116 }; 3117 }; 3118 3119 cooling-maps { 3120 map0 { 3121 trip = <&cpu0_alert>; 3122 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3123 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3124 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3125 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3126 }; 3127 }; 3128 }; 3129 3130 cpu1-thermal { 3131 polling-delay = <1000>; 3132 polling-delay-passive = <250>; 3133 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3134 3135 trips { 3136 cpu1_alert: trip-alert { 3137 temperature = <85000>; 3138 hysteresis = <2000>; 3139 type = "passive"; 3140 }; 3141 3142 cpu1_crit: trip-crit { 3143 temperature = <100000>; 3144 hysteresis = <2000>; 3145 type = "critical"; 3146 }; 3147 }; 3148 3149 cooling-maps { 3150 map0 { 3151 trip = <&cpu1_alert>; 3152 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3153 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3154 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3155 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3156 }; 3157 }; 3158 }; 3159 3160 cpu2-thermal { 3161 polling-delay = <1000>; 3162 polling-delay-passive = <250>; 3163 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3164 3165 trips { 3166 cpu2_alert: trip-alert { 3167 temperature = <85000>; 3168 hysteresis = <2000>; 3169 type = "passive"; 3170 }; 3171 3172 cpu2_crit: trip-crit { 3173 temperature = <100000>; 3174 hysteresis = <2000>; 3175 type = "critical"; 3176 }; 3177 }; 3178 3179 cooling-maps { 3180 map0 { 3181 trip = <&cpu2_alert>; 3182 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3183 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3184 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3185 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3186 }; 3187 }; 3188 }; 3189 3190 cpu3-thermal { 3191 polling-delay = <1000>; 3192 polling-delay-passive = <250>; 3193 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3194 3195 trips { 3196 cpu3_alert: trip-alert { 3197 temperature = <85000>; 3198 hysteresis = <2000>; 3199 type = "passive"; 3200 }; 3201 3202 cpu3_crit: trip-crit { 3203 temperature = <100000>; 3204 hysteresis = <2000>; 3205 type = "critical"; 3206 }; 3207 }; 3208 3209 cooling-maps { 3210 map0 { 3211 trip = <&cpu3_alert>; 3212 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3213 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3214 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3215 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3216 }; 3217 }; 3218 }; 3219 3220 cpu4-thermal { 3221 polling-delay = <1000>; 3222 polling-delay-passive = <250>; 3223 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3224 3225 trips { 3226 cpu4_alert: trip-alert { 3227 temperature = <85000>; 3228 hysteresis = <2000>; 3229 type = "passive"; 3230 }; 3231 3232 cpu4_crit: trip-crit { 3233 temperature = <100000>; 3234 hysteresis = <2000>; 3235 type = "critical"; 3236 }; 3237 }; 3238 3239 cooling-maps { 3240 map0 { 3241 trip = <&cpu4_alert>; 3242 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3243 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3244 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3245 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3246 }; 3247 }; 3248 }; 3249 3250 cpu5-thermal { 3251 polling-delay = <1000>; 3252 polling-delay-passive = <250>; 3253 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3254 3255 trips { 3256 cpu5_alert: trip-alert { 3257 temperature = <85000>; 3258 hysteresis = <2000>; 3259 type = "passive"; 3260 }; 3261 3262 cpu5_crit: trip-crit { 3263 temperature = <100000>; 3264 hysteresis = <2000>; 3265 type = "critical"; 3266 }; 3267 }; 3268 3269 cooling-maps { 3270 map0 { 3271 trip = <&cpu5_alert>; 3272 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3273 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3274 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3275 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3276 }; 3277 }; 3278 }; 3279 3280 cpu6-thermal { 3281 polling-delay = <1000>; 3282 polling-delay-passive = <250>; 3283 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3284 3285 trips { 3286 cpu6_alert: trip-alert { 3287 temperature = <85000>; 3288 hysteresis = <2000>; 3289 type = "passive"; 3290 }; 3291 3292 cpu6_crit: trip-crit { 3293 temperature = <100000>; 3294 hysteresis = <2000>; 3295 type = "critical"; 3296 }; 3297 }; 3298 3299 cooling-maps { 3300 map0 { 3301 trip = <&cpu6_alert>; 3302 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3303 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3304 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3305 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3306 }; 3307 }; 3308 }; 3309 3310 cpu7-thermal { 3311 polling-delay = <1000>; 3312 polling-delay-passive = <250>; 3313 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3314 3315 trips { 3316 cpu7_alert: trip-alert { 3317 temperature = <85000>; 3318 hysteresis = <2000>; 3319 type = "passive"; 3320 }; 3321 3322 cpu7_crit: trip-crit { 3323 temperature = <100000>; 3324 hysteresis = <2000>; 3325 type = "critical"; 3326 }; 3327 }; 3328 3329 cooling-maps { 3330 map0 { 3331 trip = <&cpu7_alert>; 3332 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3333 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3334 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3335 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3336 }; 3337 }; 3338 }; 3339 3340 vpu0-thermal { 3341 polling-delay = <1000>; 3342 polling-delay-passive = <250>; 3343 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 3344 3345 trips { 3346 vpu0_alert: trip-alert { 3347 temperature = <85000>; 3348 hysteresis = <2000>; 3349 type = "passive"; 3350 }; 3351 3352 vpu0_crit: trip-crit { 3353 temperature = <100000>; 3354 hysteresis = <2000>; 3355 type = "critical"; 3356 }; 3357 }; 3358 }; 3359 3360 vpu1-thermal { 3361 polling-delay = <1000>; 3362 polling-delay-passive = <250>; 3363 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 3364 3365 trips { 3366 vpu1_alert: trip-alert { 3367 temperature = <85000>; 3368 hysteresis = <2000>; 3369 type = "passive"; 3370 }; 3371 3372 vpu1_crit: trip-crit { 3373 temperature = <100000>; 3374 hysteresis = <2000>; 3375 type = "critical"; 3376 }; 3377 }; 3378 }; 3379 3380 gpu0-thermal { 3381 polling-delay = <1000>; 3382 polling-delay-passive = <250>; 3383 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 3384 3385 trips { 3386 gpu0_alert: trip-alert { 3387 temperature = <85000>; 3388 hysteresis = <2000>; 3389 type = "passive"; 3390 }; 3391 3392 gpu0_crit: trip-crit { 3393 temperature = <100000>; 3394 hysteresis = <2000>; 3395 type = "critical"; 3396 }; 3397 }; 3398 }; 3399 3400 gpu1-thermal { 3401 polling-delay = <1000>; 3402 polling-delay-passive = <250>; 3403 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 3404 3405 trips { 3406 gpu1_alert: trip-alert { 3407 temperature = <85000>; 3408 hysteresis = <2000>; 3409 type = "passive"; 3410 }; 3411 3412 gpu1_crit: trip-crit { 3413 temperature = <100000>; 3414 hysteresis = <2000>; 3415 type = "critical"; 3416 }; 3417 }; 3418 }; 3419 3420 vdec-thermal { 3421 polling-delay = <1000>; 3422 polling-delay-passive = <250>; 3423 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 3424 3425 trips { 3426 vdec_alert: trip-alert { 3427 temperature = <85000>; 3428 hysteresis = <2000>; 3429 type = "passive"; 3430 }; 3431 3432 vdec_crit: trip-crit { 3433 temperature = <100000>; 3434 hysteresis = <2000>; 3435 type = "critical"; 3436 }; 3437 }; 3438 }; 3439 3440 img-thermal { 3441 polling-delay = <1000>; 3442 polling-delay-passive = <250>; 3443 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 3444 3445 trips { 3446 img_alert: trip-alert { 3447 temperature = <85000>; 3448 hysteresis = <2000>; 3449 type = "passive"; 3450 }; 3451 3452 img_crit: trip-crit { 3453 temperature = <100000>; 3454 hysteresis = <2000>; 3455 type = "critical"; 3456 }; 3457 }; 3458 }; 3459 3460 infra-thermal { 3461 polling-delay = <1000>; 3462 polling-delay-passive = <250>; 3463 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 3464 3465 trips { 3466 infra_alert: trip-alert { 3467 temperature = <85000>; 3468 hysteresis = <2000>; 3469 type = "passive"; 3470 }; 3471 3472 infra_crit: trip-crit { 3473 temperature = <100000>; 3474 hysteresis = <2000>; 3475 type = "critical"; 3476 }; 3477 }; 3478 }; 3479 3480 cam0-thermal { 3481 polling-delay = <1000>; 3482 polling-delay-passive = <250>; 3483 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 3484 3485 trips { 3486 cam0_alert: trip-alert { 3487 temperature = <85000>; 3488 hysteresis = <2000>; 3489 type = "passive"; 3490 }; 3491 3492 cam0_crit: trip-crit { 3493 temperature = <100000>; 3494 hysteresis = <2000>; 3495 type = "critical"; 3496 }; 3497 }; 3498 }; 3499 3500 cam1-thermal { 3501 polling-delay = <1000>; 3502 polling-delay-passive = <250>; 3503 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 3504 3505 trips { 3506 cam1_alert: trip-alert { 3507 temperature = <85000>; 3508 hysteresis = <2000>; 3509 type = "passive"; 3510 }; 3511 3512 cam1_crit: trip-crit { 3513 temperature = <100000>; 3514 hysteresis = <2000>; 3515 type = "critical"; 3516 }; 3517 }; 3518 }; 3519 }; 3520}; 3521