1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/gce/mt8195-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8195-memory-port.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15#include <dt-bindings/power/mt8195-power.h>
16
17/ {
18	compatible = "mediatek,mt8195";
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	aliases {
24		gce0 = &gce0;
25		gce1 = &gce1;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a55";
35			reg = <0x000>;
36			enable-method = "psci";
37			performance-domains = <&performance 0>;
38			clock-frequency = <1701000000>;
39			capacity-dmips-mhz = <578>;
40			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
41			next-level-cache = <&l2_0>;
42			#cooling-cells = <2>;
43		};
44
45		cpu1: cpu@100 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a55";
48			reg = <0x100>;
49			enable-method = "psci";
50			performance-domains = <&performance 0>;
51			clock-frequency = <1701000000>;
52			capacity-dmips-mhz = <578>;
53			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
54			next-level-cache = <&l2_0>;
55			#cooling-cells = <2>;
56		};
57
58		cpu2: cpu@200 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a55";
61			reg = <0x200>;
62			enable-method = "psci";
63			performance-domains = <&performance 0>;
64			clock-frequency = <1701000000>;
65			capacity-dmips-mhz = <578>;
66			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
67			next-level-cache = <&l2_0>;
68			#cooling-cells = <2>;
69		};
70
71		cpu3: cpu@300 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a55";
74			reg = <0x300>;
75			enable-method = "psci";
76			performance-domains = <&performance 0>;
77			clock-frequency = <1701000000>;
78			capacity-dmips-mhz = <578>;
79			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
80			next-level-cache = <&l2_0>;
81			#cooling-cells = <2>;
82		};
83
84		cpu4: cpu@400 {
85			device_type = "cpu";
86			compatible = "arm,cortex-a78";
87			reg = <0x400>;
88			enable-method = "psci";
89			performance-domains = <&performance 1>;
90			clock-frequency = <2171000000>;
91			capacity-dmips-mhz = <1024>;
92			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
93			next-level-cache = <&l2_1>;
94			#cooling-cells = <2>;
95		};
96
97		cpu5: cpu@500 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a78";
100			reg = <0x500>;
101			enable-method = "psci";
102			performance-domains = <&performance 1>;
103			clock-frequency = <2171000000>;
104			capacity-dmips-mhz = <1024>;
105			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
106			next-level-cache = <&l2_1>;
107			#cooling-cells = <2>;
108		};
109
110		cpu6: cpu@600 {
111			device_type = "cpu";
112			compatible = "arm,cortex-a78";
113			reg = <0x600>;
114			enable-method = "psci";
115			performance-domains = <&performance 1>;
116			clock-frequency = <2171000000>;
117			capacity-dmips-mhz = <1024>;
118			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
119			next-level-cache = <&l2_1>;
120			#cooling-cells = <2>;
121		};
122
123		cpu7: cpu@700 {
124			device_type = "cpu";
125			compatible = "arm,cortex-a78";
126			reg = <0x700>;
127			enable-method = "psci";
128			performance-domains = <&performance 1>;
129			clock-frequency = <2171000000>;
130			capacity-dmips-mhz = <1024>;
131			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
132			next-level-cache = <&l2_1>;
133			#cooling-cells = <2>;
134		};
135
136		cpu-map {
137			cluster0 {
138				core0 {
139					cpu = <&cpu0>;
140				};
141
142				core1 {
143					cpu = <&cpu1>;
144				};
145
146				core2 {
147					cpu = <&cpu2>;
148				};
149
150				core3 {
151					cpu = <&cpu3>;
152				};
153			};
154
155			cluster1 {
156				core0 {
157					cpu = <&cpu4>;
158				};
159
160				core1 {
161					cpu = <&cpu5>;
162				};
163
164				core2 {
165					cpu = <&cpu6>;
166				};
167
168				core3 {
169					cpu = <&cpu7>;
170				};
171			};
172		};
173
174		idle-states {
175			entry-method = "psci";
176
177			cpu_off_l: cpu-off-l {
178				compatible = "arm,idle-state";
179				arm,psci-suspend-param = <0x00010001>;
180				local-timer-stop;
181				entry-latency-us = <50>;
182				exit-latency-us = <95>;
183				min-residency-us = <580>;
184			};
185
186			cpu_off_b: cpu-off-b {
187				compatible = "arm,idle-state";
188				arm,psci-suspend-param = <0x00010001>;
189				local-timer-stop;
190				entry-latency-us = <45>;
191				exit-latency-us = <140>;
192				min-residency-us = <740>;
193			};
194
195			cluster_off_l: cluster-off-l {
196				compatible = "arm,idle-state";
197				arm,psci-suspend-param = <0x01010002>;
198				local-timer-stop;
199				entry-latency-us = <55>;
200				exit-latency-us = <155>;
201				min-residency-us = <840>;
202			};
203
204			cluster_off_b: cluster-off-b {
205				compatible = "arm,idle-state";
206				arm,psci-suspend-param = <0x01010002>;
207				local-timer-stop;
208				entry-latency-us = <50>;
209				exit-latency-us = <200>;
210				min-residency-us = <1000>;
211			};
212		};
213
214		l2_0: l2-cache0 {
215			compatible = "cache";
216			next-level-cache = <&l3_0>;
217		};
218
219		l2_1: l2-cache1 {
220			compatible = "cache";
221			next-level-cache = <&l3_0>;
222		};
223
224		l3_0: l3-cache {
225			compatible = "cache";
226		};
227	};
228
229	dsu-pmu {
230		compatible = "arm,dsu-pmu";
231		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
232		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
233		       <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
234	};
235
236	dmic_codec: dmic-codec {
237		compatible = "dmic-codec";
238		num-channels = <2>;
239		wakeup-delay-ms = <50>;
240	};
241
242	sound: mt8195-sound {
243		mediatek,platform = <&afe>;
244		status = "disabled";
245	};
246
247	clk26m: oscillator-26m {
248		compatible = "fixed-clock";
249		#clock-cells = <0>;
250		clock-frequency = <26000000>;
251		clock-output-names = "clk26m";
252	};
253
254	clk32k: oscillator-32k {
255		compatible = "fixed-clock";
256		#clock-cells = <0>;
257		clock-frequency = <32768>;
258		clock-output-names = "clk32k";
259	};
260
261	performance: performance-controller@11bc10 {
262		compatible = "mediatek,cpufreq-hw";
263		reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
264		#performance-domain-cells = <1>;
265	};
266
267	pmu-a55 {
268		compatible = "arm,cortex-a55-pmu";
269		interrupt-parent = <&gic>;
270		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
271	};
272
273	pmu-a78 {
274		compatible = "arm,cortex-a78-pmu";
275		interrupt-parent = <&gic>;
276		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
277	};
278
279	psci {
280		compatible = "arm,psci-1.0";
281		method = "smc";
282	};
283
284	timer: timer {
285		compatible = "arm,armv8-timer";
286		interrupt-parent = <&gic>;
287		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
288			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
289			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
290			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
291	};
292
293	soc {
294		#address-cells = <2>;
295		#size-cells = <2>;
296		compatible = "simple-bus";
297		ranges;
298
299		gic: interrupt-controller@c000000 {
300			compatible = "arm,gic-v3";
301			#interrupt-cells = <4>;
302			#redistributor-regions = <1>;
303			interrupt-parent = <&gic>;
304			interrupt-controller;
305			reg = <0 0x0c000000 0 0x40000>,
306			      <0 0x0c040000 0 0x200000>;
307			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
308
309			ppi-partitions {
310				ppi_cluster0: interrupt-partition-0 {
311					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
312				};
313
314				ppi_cluster1: interrupt-partition-1 {
315					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
316				};
317			};
318		};
319
320		topckgen: syscon@10000000 {
321			compatible = "mediatek,mt8195-topckgen", "syscon";
322			reg = <0 0x10000000 0 0x1000>;
323			#clock-cells = <1>;
324		};
325
326		infracfg_ao: syscon@10001000 {
327			compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
328			reg = <0 0x10001000 0 0x1000>;
329			#clock-cells = <1>;
330			#reset-cells = <1>;
331		};
332
333		pericfg: syscon@10003000 {
334			compatible = "mediatek,mt8195-pericfg", "syscon";
335			reg = <0 0x10003000 0 0x1000>;
336			#clock-cells = <1>;
337		};
338
339		pio: pinctrl@10005000 {
340			compatible = "mediatek,mt8195-pinctrl";
341			reg = <0 0x10005000 0 0x1000>,
342			      <0 0x11d10000 0 0x1000>,
343			      <0 0x11d30000 0 0x1000>,
344			      <0 0x11d40000 0 0x1000>,
345			      <0 0x11e20000 0 0x1000>,
346			      <0 0x11eb0000 0 0x1000>,
347			      <0 0x11f40000 0 0x1000>,
348			      <0 0x1000b000 0 0x1000>;
349			reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
350				    "iocfg_br", "iocfg_lm", "iocfg_rb",
351				    "iocfg_tl", "eint";
352			gpio-controller;
353			#gpio-cells = <2>;
354			gpio-ranges = <&pio 0 0 144>;
355			interrupt-controller;
356			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
357			#interrupt-cells = <2>;
358		};
359
360		scpsys: syscon@10006000 {
361			compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
362			reg = <0 0x10006000 0 0x1000>;
363
364			/* System Power Manager */
365			spm: power-controller {
366				compatible = "mediatek,mt8195-power-controller";
367				#address-cells = <1>;
368				#size-cells = <0>;
369				#power-domain-cells = <1>;
370
371				/* power domain of the SoC */
372				mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
373					reg = <MT8195_POWER_DOMAIN_MFG0>;
374					#address-cells = <1>;
375					#size-cells = <0>;
376					#power-domain-cells = <1>;
377
378					power-domain@MT8195_POWER_DOMAIN_MFG1 {
379						reg = <MT8195_POWER_DOMAIN_MFG1>;
380						clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
381						clock-names = "mfg";
382						mediatek,infracfg = <&infracfg_ao>;
383						#address-cells = <1>;
384						#size-cells = <0>;
385						#power-domain-cells = <1>;
386
387						power-domain@MT8195_POWER_DOMAIN_MFG2 {
388							reg = <MT8195_POWER_DOMAIN_MFG2>;
389							#power-domain-cells = <0>;
390						};
391
392						power-domain@MT8195_POWER_DOMAIN_MFG3 {
393							reg = <MT8195_POWER_DOMAIN_MFG3>;
394							#power-domain-cells = <0>;
395						};
396
397						power-domain@MT8195_POWER_DOMAIN_MFG4 {
398							reg = <MT8195_POWER_DOMAIN_MFG4>;
399							#power-domain-cells = <0>;
400						};
401
402						power-domain@MT8195_POWER_DOMAIN_MFG5 {
403							reg = <MT8195_POWER_DOMAIN_MFG5>;
404							#power-domain-cells = <0>;
405						};
406
407						power-domain@MT8195_POWER_DOMAIN_MFG6 {
408							reg = <MT8195_POWER_DOMAIN_MFG6>;
409							#power-domain-cells = <0>;
410						};
411					};
412				};
413
414				power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
415					reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
416					clocks = <&topckgen CLK_TOP_VPP>,
417						 <&topckgen CLK_TOP_CAM>,
418						 <&topckgen CLK_TOP_CCU>,
419						 <&topckgen CLK_TOP_IMG>,
420						 <&topckgen CLK_TOP_VENC>,
421						 <&topckgen CLK_TOP_VDEC>,
422						 <&topckgen CLK_TOP_WPE_VPP>,
423						 <&topckgen CLK_TOP_CFG_VPP0>,
424						 <&vppsys0 CLK_VPP0_SMI_COMMON>,
425						 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
426						 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
427						 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
428						 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
429						 <&vppsys0 CLK_VPP0_GALS_INFRA>,
430						 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
431						 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
432						 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
433						 <&vppsys0 CLK_VPP0_SMI_REORDER>,
434						 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
435						 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
436						 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
437						 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
438						 <&vppsys0 CLK_VPP0_SMI_RSI>,
439						 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
440						 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
441						 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
442						 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
443					clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
444						      "vppsys4", "vppsys5", "vppsys6", "vppsys7",
445						      "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
446						      "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
447						      "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
448						      "vppsys0-12", "vppsys0-13", "vppsys0-14",
449						      "vppsys0-15", "vppsys0-16", "vppsys0-17",
450						      "vppsys0-18";
451					mediatek,infracfg = <&infracfg_ao>;
452					#address-cells = <1>;
453					#size-cells = <0>;
454					#power-domain-cells = <1>;
455
456					power-domain@MT8195_POWER_DOMAIN_VDEC1 {
457						reg = <MT8195_POWER_DOMAIN_VDEC1>;
458						clocks = <&vdecsys CLK_VDEC_LARB1>;
459						clock-names = "vdec1-0";
460						mediatek,infracfg = <&infracfg_ao>;
461						#power-domain-cells = <0>;
462					};
463
464					power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
465						reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
466						mediatek,infracfg = <&infracfg_ao>;
467						#power-domain-cells = <0>;
468					};
469
470					power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
471						reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
472						clocks = <&topckgen CLK_TOP_CFG_VDO0>,
473							 <&vdosys0 CLK_VDO0_SMI_GALS>,
474							 <&vdosys0 CLK_VDO0_SMI_COMMON>,
475							 <&vdosys0 CLK_VDO0_SMI_EMI>,
476							 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
477							 <&vdosys0 CLK_VDO0_SMI_LARB>,
478							 <&vdosys0 CLK_VDO0_SMI_RSI>;
479						clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
480							      "vdosys0-2", "vdosys0-3",
481							      "vdosys0-4", "vdosys0-5";
482						mediatek,infracfg = <&infracfg_ao>;
483						#address-cells = <1>;
484						#size-cells = <0>;
485						#power-domain-cells = <1>;
486
487						power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
488							reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
489							clocks = <&topckgen CLK_TOP_CFG_VPP1>,
490								 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
491								 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
492							clock-names = "vppsys1", "vppsys1-0",
493								      "vppsys1-1";
494							mediatek,infracfg = <&infracfg_ao>;
495							#power-domain-cells = <0>;
496						};
497
498						power-domain@MT8195_POWER_DOMAIN_WPESYS {
499							reg = <MT8195_POWER_DOMAIN_WPESYS>;
500							clocks = <&wpesys CLK_WPE_SMI_LARB7>,
501								 <&wpesys CLK_WPE_SMI_LARB8>,
502								 <&wpesys CLK_WPE_SMI_LARB7_P>,
503								 <&wpesys CLK_WPE_SMI_LARB8_P>;
504							clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
505								      "wepsys-3";
506							mediatek,infracfg = <&infracfg_ao>;
507							#power-domain-cells = <0>;
508						};
509
510						power-domain@MT8195_POWER_DOMAIN_VDEC0 {
511							reg = <MT8195_POWER_DOMAIN_VDEC0>;
512							clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
513							clock-names = "vdec0-0";
514							mediatek,infracfg = <&infracfg_ao>;
515							#power-domain-cells = <0>;
516						};
517
518						power-domain@MT8195_POWER_DOMAIN_VDEC2 {
519							reg = <MT8195_POWER_DOMAIN_VDEC2>;
520							clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
521							clock-names = "vdec2-0";
522							mediatek,infracfg = <&infracfg_ao>;
523							#power-domain-cells = <0>;
524						};
525
526						power-domain@MT8195_POWER_DOMAIN_VENC {
527							reg = <MT8195_POWER_DOMAIN_VENC>;
528							mediatek,infracfg = <&infracfg_ao>;
529							#power-domain-cells = <0>;
530						};
531
532						power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
533							reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
534							clocks = <&topckgen CLK_TOP_CFG_VDO1>,
535								 <&vdosys1 CLK_VDO1_SMI_LARB2>,
536								 <&vdosys1 CLK_VDO1_SMI_LARB3>,
537								 <&vdosys1 CLK_VDO1_GALS>;
538							clock-names = "vdosys1", "vdosys1-0",
539								      "vdosys1-1", "vdosys1-2";
540							mediatek,infracfg = <&infracfg_ao>;
541							#address-cells = <1>;
542							#size-cells = <0>;
543							#power-domain-cells = <1>;
544
545							power-domain@MT8195_POWER_DOMAIN_DP_TX {
546								reg = <MT8195_POWER_DOMAIN_DP_TX>;
547								mediatek,infracfg = <&infracfg_ao>;
548								#power-domain-cells = <0>;
549							};
550
551							power-domain@MT8195_POWER_DOMAIN_EPD_TX {
552								reg = <MT8195_POWER_DOMAIN_EPD_TX>;
553								mediatek,infracfg = <&infracfg_ao>;
554								#power-domain-cells = <0>;
555							};
556
557							power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
558								reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
559								clocks = <&topckgen CLK_TOP_HDMI_APB>;
560								clock-names = "hdmi_tx";
561								#power-domain-cells = <0>;
562							};
563						};
564
565						power-domain@MT8195_POWER_DOMAIN_IMG {
566							reg = <MT8195_POWER_DOMAIN_IMG>;
567							clocks = <&imgsys CLK_IMG_LARB9>,
568								 <&imgsys CLK_IMG_GALS>;
569							clock-names = "img-0", "img-1";
570							mediatek,infracfg = <&infracfg_ao>;
571							#address-cells = <1>;
572							#size-cells = <0>;
573							#power-domain-cells = <1>;
574
575							power-domain@MT8195_POWER_DOMAIN_DIP {
576								reg = <MT8195_POWER_DOMAIN_DIP>;
577								#power-domain-cells = <0>;
578							};
579
580							power-domain@MT8195_POWER_DOMAIN_IPE {
581								reg = <MT8195_POWER_DOMAIN_IPE>;
582								clocks = <&topckgen CLK_TOP_IPE>,
583									 <&imgsys CLK_IMG_IPE>,
584									 <&ipesys CLK_IPE_SMI_LARB12>;
585								clock-names = "ipe", "ipe-0", "ipe-1";
586								mediatek,infracfg = <&infracfg_ao>;
587								#power-domain-cells = <0>;
588							};
589						};
590
591						power-domain@MT8195_POWER_DOMAIN_CAM {
592							reg = <MT8195_POWER_DOMAIN_CAM>;
593							clocks = <&camsys CLK_CAM_LARB13>,
594								 <&camsys CLK_CAM_LARB14>,
595								 <&camsys CLK_CAM_CAM2MM0_GALS>,
596								 <&camsys CLK_CAM_CAM2MM1_GALS>,
597								 <&camsys CLK_CAM_CAM2SYS_GALS>;
598							clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
599								      "cam-4";
600							mediatek,infracfg = <&infracfg_ao>;
601							#address-cells = <1>;
602							#size-cells = <0>;
603							#power-domain-cells = <1>;
604
605							power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
606								reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
607								#power-domain-cells = <0>;
608							};
609
610							power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
611								reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
612								#power-domain-cells = <0>;
613							};
614
615							power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
616								reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
617								#power-domain-cells = <0>;
618							};
619						};
620					};
621				};
622
623				power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
624					reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
625					mediatek,infracfg = <&infracfg_ao>;
626					#power-domain-cells = <0>;
627				};
628
629				power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
630					reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
631					mediatek,infracfg = <&infracfg_ao>;
632					#power-domain-cells = <0>;
633				};
634
635				power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
636					reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
637					#power-domain-cells = <0>;
638				};
639
640				power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
641					reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
642					#power-domain-cells = <0>;
643				};
644
645				power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
646					reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
647					clocks = <&topckgen CLK_TOP_SENINF>,
648						 <&topckgen CLK_TOP_SENINF2>;
649					clock-names = "csi_rx_top", "csi_rx_top1";
650					#power-domain-cells = <0>;
651				};
652
653				power-domain@MT8195_POWER_DOMAIN_ETHER {
654					reg = <MT8195_POWER_DOMAIN_ETHER>;
655					clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
656					clock-names = "ether";
657					#power-domain-cells = <0>;
658				};
659
660				power-domain@MT8195_POWER_DOMAIN_ADSP {
661					reg = <MT8195_POWER_DOMAIN_ADSP>;
662					clocks = <&topckgen CLK_TOP_ADSP>,
663						 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
664					clock-names = "adsp", "adsp1";
665					#address-cells = <1>;
666					#size-cells = <0>;
667					mediatek,infracfg = <&infracfg_ao>;
668					#power-domain-cells = <1>;
669
670					power-domain@MT8195_POWER_DOMAIN_AUDIO {
671						reg = <MT8195_POWER_DOMAIN_AUDIO>;
672						clocks = <&topckgen CLK_TOP_A1SYS_HP>,
673							 <&topckgen CLK_TOP_AUD_INTBUS>,
674							 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
675							 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
676						clock-names = "audio", "audio1", "audio2",
677							      "audio3";
678						mediatek,infracfg = <&infracfg_ao>;
679						#power-domain-cells = <0>;
680					};
681				};
682			};
683		};
684
685		watchdog: watchdog@10007000 {
686			compatible = "mediatek,mt8195-wdt",
687				     "mediatek,mt6589-wdt";
688			mediatek,disable-extrst;
689			reg = <0 0x10007000 0 0x100>;
690			#reset-cells = <1>;
691		};
692
693		apmixedsys: syscon@1000c000 {
694			compatible = "mediatek,mt8195-apmixedsys", "syscon";
695			reg = <0 0x1000c000 0 0x1000>;
696			#clock-cells = <1>;
697		};
698
699		systimer: timer@10017000 {
700			compatible = "mediatek,mt8195-timer",
701				     "mediatek,mt6765-timer";
702			reg = <0 0x10017000 0 0x1000>;
703			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
704			clocks = <&topckgen CLK_TOP_CLK26M_D2>;
705		};
706
707		pwrap: pwrap@10024000 {
708			compatible = "mediatek,mt8195-pwrap", "syscon";
709			reg = <0 0x10024000 0 0x1000>;
710			reg-names = "pwrap";
711			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
712			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
713				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
714			clock-names = "spi", "wrap";
715			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
716			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
717		};
718
719		spmi: spmi@10027000 {
720			compatible = "mediatek,mt8195-spmi";
721			reg = <0 0x10027000 0 0x000e00>,
722			      <0 0x10029000 0 0x000100>;
723			reg-names = "pmif", "spmimst";
724			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
725				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
726				 <&topckgen CLK_TOP_SPMI_M_MST>;
727			clock-names = "pmif_sys_ck",
728				      "pmif_tmr_ck",
729				      "spmimst_clk_mux";
730			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
731			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
732		};
733
734		iommu_infra: infra-iommu@10315000 {
735			compatible = "mediatek,mt8195-iommu-infra";
736			reg = <0 0x10315000 0 0x5000>;
737			interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
738				     <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
739				     <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
740				     <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
741				     <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
742			#iommu-cells = <1>;
743		};
744
745		gce0: mailbox@10320000 {
746			compatible = "mediatek,mt8195-gce";
747			reg = <0 0x10320000 0 0x4000>;
748			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
749			#mbox-cells = <2>;
750			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
751		};
752
753		gce1: mailbox@10330000 {
754			compatible = "mediatek,mt8195-gce";
755			reg = <0 0x10330000 0 0x4000>;
756			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
757			#mbox-cells = <2>;
758			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
759		};
760
761		scp: scp@10500000 {
762			compatible = "mediatek,mt8195-scp";
763			reg = <0 0x10500000 0 0x100000>,
764			      <0 0x10720000 0 0xe0000>,
765			      <0 0x10700000 0 0x8000>;
766			reg-names = "sram", "cfg", "l1tcm";
767			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
768			status = "disabled";
769		};
770
771		scp_adsp: clock-controller@10720000 {
772			compatible = "mediatek,mt8195-scp_adsp";
773			reg = <0 0x10720000 0 0x1000>;
774			#clock-cells = <1>;
775		};
776
777		adsp: dsp@10803000 {
778			compatible = "mediatek,mt8195-dsp";
779			reg = <0 0x10803000 0 0x1000>,
780			      <0 0x10840000 0 0x40000>;
781			reg-names = "cfg", "sram";
782			clocks = <&topckgen CLK_TOP_ADSP>,
783				 <&clk26m>,
784				 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
785				 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
786				 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
787				 <&topckgen CLK_TOP_AUDIO_H>;
788			clock-names = "adsp_sel",
789				 "clk26m_ck",
790				 "audio_local_bus",
791				 "mainpll_d7_d2",
792				 "scp_adsp_audiodsp",
793				 "audio_h";
794			power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
795			mbox-names = "rx", "tx";
796			mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
797			status = "disabled";
798		};
799
800		adsp_mailbox0: mailbox@10816000 {
801			compatible = "mediatek,mt8195-adsp-mbox";
802			#mbox-cells = <0>;
803			reg = <0 0x10816000 0 0x1000>;
804			interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
805		};
806
807		adsp_mailbox1: mailbox@10817000 {
808			compatible = "mediatek,mt8195-adsp-mbox";
809			#mbox-cells = <0>;
810			reg = <0 0x10817000 0 0x1000>;
811			interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
812		};
813
814		afe: mt8195-afe-pcm@10890000 {
815			compatible = "mediatek,mt8195-audio";
816			reg = <0 0x10890000 0 0x10000>;
817			mediatek,topckgen = <&topckgen>;
818			power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
819			interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
820			resets = <&watchdog 14>;
821			reset-names = "audiosys";
822			clocks = <&clk26m>,
823				<&apmixedsys CLK_APMIXED_APLL1>,
824				<&apmixedsys CLK_APMIXED_APLL2>,
825				<&topckgen CLK_TOP_APLL12_DIV0>,
826				<&topckgen CLK_TOP_APLL12_DIV1>,
827				<&topckgen CLK_TOP_APLL12_DIV2>,
828				<&topckgen CLK_TOP_APLL12_DIV3>,
829				<&topckgen CLK_TOP_APLL12_DIV9>,
830				<&topckgen CLK_TOP_A1SYS_HP>,
831				<&topckgen CLK_TOP_AUD_INTBUS>,
832				<&topckgen CLK_TOP_AUDIO_H>,
833				<&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
834				<&topckgen CLK_TOP_DPTX_MCK>,
835				<&topckgen CLK_TOP_I2SO1_MCK>,
836				<&topckgen CLK_TOP_I2SO2_MCK>,
837				<&topckgen CLK_TOP_I2SI1_MCK>,
838				<&topckgen CLK_TOP_I2SI2_MCK>,
839				<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
840				<&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
841			clock-names = "clk26m",
842				"apll1_ck",
843				"apll2_ck",
844				"apll12_div0",
845				"apll12_div1",
846				"apll12_div2",
847				"apll12_div3",
848				"apll12_div9",
849				"a1sys_hp_sel",
850				"aud_intbus_sel",
851				"audio_h_sel",
852				"audio_local_bus_sel",
853				"dptx_m_sel",
854				"i2so1_m_sel",
855				"i2so2_m_sel",
856				"i2si1_m_sel",
857				"i2si2_m_sel",
858				"infra_ao_audio_26m_b",
859				"scp_adsp_audiodsp";
860			status = "disabled";
861		};
862
863		uart0: serial@11001100 {
864			compatible = "mediatek,mt8195-uart",
865				     "mediatek,mt6577-uart";
866			reg = <0 0x11001100 0 0x100>;
867			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
868			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
869			clock-names = "baud", "bus";
870			status = "disabled";
871		};
872
873		uart1: serial@11001200 {
874			compatible = "mediatek,mt8195-uart",
875				     "mediatek,mt6577-uart";
876			reg = <0 0x11001200 0 0x100>;
877			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
878			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
879			clock-names = "baud", "bus";
880			status = "disabled";
881		};
882
883		uart2: serial@11001300 {
884			compatible = "mediatek,mt8195-uart",
885				     "mediatek,mt6577-uart";
886			reg = <0 0x11001300 0 0x100>;
887			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
888			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
889			clock-names = "baud", "bus";
890			status = "disabled";
891		};
892
893		uart3: serial@11001400 {
894			compatible = "mediatek,mt8195-uart",
895				     "mediatek,mt6577-uart";
896			reg = <0 0x11001400 0 0x100>;
897			interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
898			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
899			clock-names = "baud", "bus";
900			status = "disabled";
901		};
902
903		uart4: serial@11001500 {
904			compatible = "mediatek,mt8195-uart",
905				     "mediatek,mt6577-uart";
906			reg = <0 0x11001500 0 0x100>;
907			interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
908			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
909			clock-names = "baud", "bus";
910			status = "disabled";
911		};
912
913		uart5: serial@11001600 {
914			compatible = "mediatek,mt8195-uart",
915				     "mediatek,mt6577-uart";
916			reg = <0 0x11001600 0 0x100>;
917			interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
918			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
919			clock-names = "baud", "bus";
920			status = "disabled";
921		};
922
923		auxadc: auxadc@11002000 {
924			compatible = "mediatek,mt8195-auxadc",
925				     "mediatek,mt8173-auxadc";
926			reg = <0 0x11002000 0 0x1000>;
927			clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
928			clock-names = "main";
929			#io-channel-cells = <1>;
930			status = "disabled";
931		};
932
933		pericfg_ao: syscon@11003000 {
934			compatible = "mediatek,mt8195-pericfg_ao", "syscon";
935			reg = <0 0x11003000 0 0x1000>;
936			#clock-cells = <1>;
937		};
938
939		spi0: spi@1100a000 {
940			compatible = "mediatek,mt8195-spi",
941				     "mediatek,mt6765-spi";
942			#address-cells = <1>;
943			#size-cells = <0>;
944			reg = <0 0x1100a000 0 0x1000>;
945			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
946			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
947				 <&topckgen CLK_TOP_SPI>,
948				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
949			clock-names = "parent-clk", "sel-clk", "spi-clk";
950			status = "disabled";
951		};
952
953		spi1: spi@11010000 {
954			compatible = "mediatek,mt8195-spi",
955				     "mediatek,mt6765-spi";
956			#address-cells = <1>;
957			#size-cells = <0>;
958			reg = <0 0x11010000 0 0x1000>;
959			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
960			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
961				 <&topckgen CLK_TOP_SPI>,
962				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
963			clock-names = "parent-clk", "sel-clk", "spi-clk";
964			status = "disabled";
965		};
966
967		spi2: spi@11012000 {
968			compatible = "mediatek,mt8195-spi",
969				     "mediatek,mt6765-spi";
970			#address-cells = <1>;
971			#size-cells = <0>;
972			reg = <0 0x11012000 0 0x1000>;
973			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
974			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
975				 <&topckgen CLK_TOP_SPI>,
976				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
977			clock-names = "parent-clk", "sel-clk", "spi-clk";
978			status = "disabled";
979		};
980
981		spi3: spi@11013000 {
982			compatible = "mediatek,mt8195-spi",
983				     "mediatek,mt6765-spi";
984			#address-cells = <1>;
985			#size-cells = <0>;
986			reg = <0 0x11013000 0 0x1000>;
987			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
988			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
989				 <&topckgen CLK_TOP_SPI>,
990				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
991			clock-names = "parent-clk", "sel-clk", "spi-clk";
992			status = "disabled";
993		};
994
995		spi4: spi@11018000 {
996			compatible = "mediatek,mt8195-spi",
997				     "mediatek,mt6765-spi";
998			#address-cells = <1>;
999			#size-cells = <0>;
1000			reg = <0 0x11018000 0 0x1000>;
1001			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1002			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1003				 <&topckgen CLK_TOP_SPI>,
1004				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1005			clock-names = "parent-clk", "sel-clk", "spi-clk";
1006			status = "disabled";
1007		};
1008
1009		spi5: spi@11019000 {
1010			compatible = "mediatek,mt8195-spi",
1011				     "mediatek,mt6765-spi";
1012			#address-cells = <1>;
1013			#size-cells = <0>;
1014			reg = <0 0x11019000 0 0x1000>;
1015			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1016			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1017				 <&topckgen CLK_TOP_SPI>,
1018				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1019			clock-names = "parent-clk", "sel-clk", "spi-clk";
1020			status = "disabled";
1021		};
1022
1023		spis0: spi@1101d000 {
1024			compatible = "mediatek,mt8195-spi-slave";
1025			reg = <0 0x1101d000 0 0x1000>;
1026			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1027			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1028			clock-names = "spi";
1029			assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1030			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1031			status = "disabled";
1032		};
1033
1034		spis1: spi@1101e000 {
1035			compatible = "mediatek,mt8195-spi-slave";
1036			reg = <0 0x1101e000 0 0x1000>;
1037			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1038			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1039			clock-names = "spi";
1040			assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1041			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1042			status = "disabled";
1043		};
1044
1045		xhci0: usb@11200000 {
1046			compatible = "mediatek,mt8195-xhci",
1047				     "mediatek,mtk-xhci";
1048			reg = <0 0x11200000 0 0x1000>,
1049			      <0 0x11203e00 0 0x0100>;
1050			reg-names = "mac", "ippc";
1051			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1052			phys = <&u2port0 PHY_TYPE_USB2>,
1053			       <&u3port0 PHY_TYPE_USB3>;
1054			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1055					  <&topckgen CLK_TOP_SSUSB_XHCI>;
1056			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1057						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1058			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1059				 <&topckgen CLK_TOP_SSUSB_REF>,
1060				 <&apmixedsys CLK_APMIXED_USB1PLL>,
1061				 <&clk26m>,
1062				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1063			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1064				      "xhci_ck";
1065			mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1066			wakeup-source;
1067			status = "disabled";
1068		};
1069
1070		mmc0: mmc@11230000 {
1071			compatible = "mediatek,mt8195-mmc",
1072				     "mediatek,mt8183-mmc";
1073			reg = <0 0x11230000 0 0x10000>,
1074			      <0 0x11f50000 0 0x1000>;
1075			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1076			clocks = <&topckgen CLK_TOP_MSDC50_0>,
1077				 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1078				 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1079			clock-names = "source", "hclk", "source_cg";
1080			status = "disabled";
1081		};
1082
1083		mmc1: mmc@11240000 {
1084			compatible = "mediatek,mt8195-mmc",
1085				     "mediatek,mt8183-mmc";
1086			reg = <0 0x11240000 0 0x1000>,
1087			      <0 0x11c70000 0 0x1000>;
1088			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1089			clocks = <&topckgen CLK_TOP_MSDC30_1>,
1090				 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1091				 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1092			clock-names = "source", "hclk", "source_cg";
1093			assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1094			assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1095			status = "disabled";
1096		};
1097
1098		mmc2: mmc@11250000 {
1099			compatible = "mediatek,mt8195-mmc",
1100				     "mediatek,mt8183-mmc";
1101			reg = <0 0x11250000 0 0x1000>,
1102			      <0 0x11e60000 0 0x1000>;
1103			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1104			clocks = <&topckgen CLK_TOP_MSDC30_2>,
1105				 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1106				 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1107			clock-names = "source", "hclk", "source_cg";
1108			assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1109			assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1110			status = "disabled";
1111		};
1112
1113		xhci1: usb@11290000 {
1114			compatible = "mediatek,mt8195-xhci",
1115				     "mediatek,mtk-xhci";
1116			reg = <0 0x11290000 0 0x1000>,
1117			      <0 0x11293e00 0 0x0100>;
1118			reg-names = "mac", "ippc";
1119			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1120			phys = <&u2port1 PHY_TYPE_USB2>;
1121			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1122					  <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1123			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1124						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1125			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1126				 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1127				 <&apmixedsys CLK_APMIXED_USB1PLL>,
1128				 <&clk26m>,
1129				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1130			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1131				      "xhci_ck";
1132			mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1133			wakeup-source;
1134			status = "disabled";
1135		};
1136
1137		xhci2: usb@112a0000 {
1138			compatible = "mediatek,mt8195-xhci",
1139				     "mediatek,mtk-xhci";
1140			reg = <0 0x112a0000 0 0x1000>,
1141			      <0 0x112a3e00 0 0x0100>;
1142			reg-names = "mac", "ippc";
1143			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1144			phys = <&u2port2 PHY_TYPE_USB2>;
1145			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1146					  <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1147			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1148						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1149			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1150				 <&topckgen CLK_TOP_SSUSB_P2_REF>,
1151				 <&clk26m>,
1152				 <&clk26m>,
1153				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1154			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1155				      "xhci_ck";
1156			mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1157			wakeup-source;
1158			status = "disabled";
1159		};
1160
1161		xhci3: usb@112b0000 {
1162			compatible = "mediatek,mt8195-xhci",
1163				     "mediatek,mtk-xhci";
1164			reg = <0 0x112b0000 0 0x1000>,
1165			      <0 0x112b3e00 0 0x0100>;
1166			reg-names = "mac", "ippc";
1167			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1168			phys = <&u2port3 PHY_TYPE_USB2>;
1169			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1170					  <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1171			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1172						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1173			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1174				 <&topckgen CLK_TOP_SSUSB_P3_REF>,
1175				 <&clk26m>,
1176				 <&clk26m>,
1177				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1178			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1179				      "xhci_ck";
1180			mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1181			wakeup-source;
1182			status = "disabled";
1183		};
1184
1185		nor_flash: spi@1132c000 {
1186			compatible = "mediatek,mt8195-nor",
1187				     "mediatek,mt8173-nor";
1188			reg = <0 0x1132c000 0 0x1000>;
1189			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1190			clocks = <&topckgen CLK_TOP_SPINOR>,
1191				 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1192				 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1193			clock-names = "spi", "sf", "axi";
1194			#address-cells = <1>;
1195			#size-cells = <0>;
1196			status = "disabled";
1197		};
1198
1199		efuse: efuse@11c10000 {
1200			compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1201			reg = <0 0x11c10000 0 0x1000>;
1202			#address-cells = <1>;
1203			#size-cells = <1>;
1204			u3_tx_imp_p0: usb3-tx-imp@184,1 {
1205				reg = <0x184 0x1>;
1206				bits = <0 5>;
1207			};
1208			u3_rx_imp_p0: usb3-rx-imp@184,2 {
1209				reg = <0x184 0x2>;
1210				bits = <5 5>;
1211			};
1212			u3_intr_p0: usb3-intr@185 {
1213				reg = <0x185 0x1>;
1214				bits = <2 6>;
1215			};
1216			comb_tx_imp_p1: usb3-tx-imp@186,1 {
1217				reg = <0x186 0x1>;
1218				bits = <0 5>;
1219			};
1220			comb_rx_imp_p1: usb3-rx-imp@186,2 {
1221				reg = <0x186 0x2>;
1222				bits = <5 5>;
1223			};
1224			comb_intr_p1: usb3-intr@187 {
1225				reg = <0x187 0x1>;
1226				bits = <2 6>;
1227			};
1228			u2_intr_p0: usb2-intr-p0@188,1 {
1229				reg = <0x188 0x1>;
1230				bits = <0 5>;
1231			};
1232			u2_intr_p1: usb2-intr-p1@188,2 {
1233				reg = <0x188 0x2>;
1234				bits = <5 5>;
1235			};
1236			u2_intr_p2: usb2-intr-p2@189,1 {
1237				reg = <0x189 0x1>;
1238				bits = <2 5>;
1239			};
1240			u2_intr_p3: usb2-intr-p3@189,2 {
1241				reg = <0x189 0x2>;
1242				bits = <7 5>;
1243			};
1244		};
1245
1246		u3phy2: t-phy@11c40000 {
1247			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1248			#address-cells = <1>;
1249			#size-cells = <1>;
1250			ranges = <0 0 0x11c40000 0x700>;
1251			status = "disabled";
1252
1253			u2port2: usb-phy@0 {
1254				reg = <0x0 0x700>;
1255				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1256				clock-names = "ref";
1257				#phy-cells = <1>;
1258			};
1259		};
1260
1261		u3phy3: t-phy@11c50000 {
1262			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1263			#address-cells = <1>;
1264			#size-cells = <1>;
1265			ranges = <0 0 0x11c50000 0x700>;
1266			status = "disabled";
1267
1268			u2port3: usb-phy@0 {
1269				reg = <0x0 0x700>;
1270				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1271				clock-names = "ref";
1272				#phy-cells = <1>;
1273			};
1274		};
1275
1276		i2c5: i2c@11d00000 {
1277			compatible = "mediatek,mt8195-i2c",
1278				     "mediatek,mt8192-i2c";
1279			reg = <0 0x11d00000 0 0x1000>,
1280			      <0 0x10220580 0 0x80>;
1281			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1282			clock-div = <1>;
1283			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1284				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1285			clock-names = "main", "dma";
1286			#address-cells = <1>;
1287			#size-cells = <0>;
1288			status = "disabled";
1289		};
1290
1291		i2c6: i2c@11d01000 {
1292			compatible = "mediatek,mt8195-i2c",
1293				     "mediatek,mt8192-i2c";
1294			reg = <0 0x11d01000 0 0x1000>,
1295			      <0 0x10220600 0 0x80>;
1296			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1297			clock-div = <1>;
1298			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1299				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1300			clock-names = "main", "dma";
1301			#address-cells = <1>;
1302			#size-cells = <0>;
1303			status = "disabled";
1304		};
1305
1306		i2c7: i2c@11d02000 {
1307			compatible = "mediatek,mt8195-i2c",
1308				     "mediatek,mt8192-i2c";
1309			reg = <0 0x11d02000 0 0x1000>,
1310			      <0 0x10220680 0 0x80>;
1311			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1312			clock-div = <1>;
1313			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1314				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1315			clock-names = "main", "dma";
1316			#address-cells = <1>;
1317			#size-cells = <0>;
1318			status = "disabled";
1319		};
1320
1321		imp_iic_wrap_s: clock-controller@11d03000 {
1322			compatible = "mediatek,mt8195-imp_iic_wrap_s";
1323			reg = <0 0x11d03000 0 0x1000>;
1324			#clock-cells = <1>;
1325		};
1326
1327		i2c0: i2c@11e00000 {
1328			compatible = "mediatek,mt8195-i2c",
1329				     "mediatek,mt8192-i2c";
1330			reg = <0 0x11e00000 0 0x1000>,
1331			      <0 0x10220080 0 0x80>;
1332			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1333			clock-div = <1>;
1334			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1335				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1336			clock-names = "main", "dma";
1337			#address-cells = <1>;
1338			#size-cells = <0>;
1339			status = "disabled";
1340		};
1341
1342		i2c1: i2c@11e01000 {
1343			compatible = "mediatek,mt8195-i2c",
1344				     "mediatek,mt8192-i2c";
1345			reg = <0 0x11e01000 0 0x1000>,
1346			      <0 0x10220200 0 0x80>;
1347			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1348			clock-div = <1>;
1349			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1350				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1351			clock-names = "main", "dma";
1352			#address-cells = <1>;
1353			#size-cells = <0>;
1354			status = "disabled";
1355		};
1356
1357		i2c2: i2c@11e02000 {
1358			compatible = "mediatek,mt8195-i2c",
1359				     "mediatek,mt8192-i2c";
1360			reg = <0 0x11e02000 0 0x1000>,
1361			      <0 0x10220380 0 0x80>;
1362			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1363			clock-div = <1>;
1364			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1365				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1366			clock-names = "main", "dma";
1367			#address-cells = <1>;
1368			#size-cells = <0>;
1369			status = "disabled";
1370		};
1371
1372		i2c3: i2c@11e03000 {
1373			compatible = "mediatek,mt8195-i2c",
1374				     "mediatek,mt8192-i2c";
1375			reg = <0 0x11e03000 0 0x1000>,
1376			      <0 0x10220480 0 0x80>;
1377			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1378			clock-div = <1>;
1379			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1380				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1381			clock-names = "main", "dma";
1382			#address-cells = <1>;
1383			#size-cells = <0>;
1384			status = "disabled";
1385		};
1386
1387		i2c4: i2c@11e04000 {
1388			compatible = "mediatek,mt8195-i2c",
1389				     "mediatek,mt8192-i2c";
1390			reg = <0 0x11e04000 0 0x1000>,
1391			      <0 0x10220500 0 0x80>;
1392			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1393			clock-div = <1>;
1394			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1395				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1396			clock-names = "main", "dma";
1397			#address-cells = <1>;
1398			#size-cells = <0>;
1399			status = "disabled";
1400		};
1401
1402		imp_iic_wrap_w: clock-controller@11e05000 {
1403			compatible = "mediatek,mt8195-imp_iic_wrap_w";
1404			reg = <0 0x11e05000 0 0x1000>;
1405			#clock-cells = <1>;
1406		};
1407
1408		u3phy1: t-phy@11e30000 {
1409			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1410			#address-cells = <1>;
1411			#size-cells = <1>;
1412			ranges = <0 0 0x11e30000 0xe00>;
1413			status = "disabled";
1414
1415			u2port1: usb-phy@0 {
1416				reg = <0x0 0x700>;
1417				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1418					 <&clk26m>;
1419				clock-names = "ref", "da_ref";
1420				#phy-cells = <1>;
1421			};
1422
1423			u3port1: usb-phy@700 {
1424				reg = <0x700 0x700>;
1425				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1426					 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1427				clock-names = "ref", "da_ref";
1428				nvmem-cells = <&comb_intr_p1>,
1429					      <&comb_rx_imp_p1>,
1430					      <&comb_tx_imp_p1>;
1431				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1432				#phy-cells = <1>;
1433			};
1434		};
1435
1436		u3phy0: t-phy@11e40000 {
1437			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1438			#address-cells = <1>;
1439			#size-cells = <1>;
1440			ranges = <0 0 0x11e40000 0xe00>;
1441			status = "disabled";
1442
1443			u2port0: usb-phy@0 {
1444				reg = <0x0 0x700>;
1445				clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1446					 <&clk26m>;
1447				clock-names = "ref", "da_ref";
1448				#phy-cells = <1>;
1449			};
1450
1451			u3port0: usb-phy@700 {
1452				reg = <0x700 0x700>;
1453				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1454					 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1455				clock-names = "ref", "da_ref";
1456				nvmem-cells = <&u3_intr_p0>,
1457					      <&u3_rx_imp_p0>,
1458					      <&u3_tx_imp_p0>;
1459				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1460				#phy-cells = <1>;
1461			};
1462		};
1463
1464		ufsphy: ufs-phy@11fa0000 {
1465			compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1466			reg = <0 0x11fa0000 0 0xc000>;
1467			clocks = <&clk26m>, <&clk26m>;
1468			clock-names = "unipro", "mp";
1469			#phy-cells = <0>;
1470			status = "disabled";
1471		};
1472
1473		mfgcfg: clock-controller@13fbf000 {
1474			compatible = "mediatek,mt8195-mfgcfg";
1475			reg = <0 0x13fbf000 0 0x1000>;
1476			#clock-cells = <1>;
1477		};
1478
1479		vppsys0: clock-controller@14000000 {
1480			compatible = "mediatek,mt8195-vppsys0";
1481			reg = <0 0x14000000 0 0x1000>;
1482			#clock-cells = <1>;
1483		};
1484
1485		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1486			compatible = "mediatek,mt8195-smi-sub-common";
1487			reg = <0 0x14010000 0 0x1000>;
1488			clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1489			       <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1490			       <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1491			clock-names = "apb", "smi", "gals0";
1492			mediatek,smi = <&smi_common_vpp>;
1493			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1494		};
1495
1496		smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
1497			compatible = "mediatek,mt8195-smi-sub-common";
1498			reg = <0 0x14011000 0 0x1000>;
1499			clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1500				 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1501				 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
1502			clock-names = "apb", "smi", "gals0";
1503			mediatek,smi = <&smi_common_vpp>;
1504			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1505		};
1506
1507		smi_common_vpp: smi@14012000 {
1508			compatible = "mediatek,mt8195-smi-common-vpp";
1509			reg = <0 0x14012000 0 0x1000>;
1510			clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1511			       <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1512			       <&vppsys0 CLK_VPP0_SMI_RSI>,
1513			       <&vppsys0 CLK_VPP0_SMI_RSI>;
1514			clock-names = "apb", "smi", "gals0", "gals1";
1515			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1516		};
1517
1518		larb4: larb@14013000 {
1519			compatible = "mediatek,mt8195-smi-larb";
1520			reg = <0 0x14013000 0 0x1000>;
1521			mediatek,larb-id = <4>;
1522			mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
1523			clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1524			       <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
1525			clock-names = "apb", "smi";
1526			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1527		};
1528
1529		iommu_vpp: iommu@14018000 {
1530			compatible = "mediatek,mt8195-iommu-vpp";
1531			reg = <0 0x14018000 0 0x1000>;
1532			mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
1533					  &larb12 &larb14 &larb16 &larb18
1534					  &larb20 &larb22 &larb23 &larb26
1535					  &larb27>;
1536			interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
1537			clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
1538			clock-names = "bclk";
1539			#iommu-cells = <1>;
1540			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1541		};
1542
1543		wpesys: clock-controller@14e00000 {
1544			compatible = "mediatek,mt8195-wpesys";
1545			reg = <0 0x14e00000 0 0x1000>;
1546			#clock-cells = <1>;
1547		};
1548
1549		wpesys_vpp0: clock-controller@14e02000 {
1550			compatible = "mediatek,mt8195-wpesys_vpp0";
1551			reg = <0 0x14e02000 0 0x1000>;
1552			#clock-cells = <1>;
1553		};
1554
1555		wpesys_vpp1: clock-controller@14e03000 {
1556			compatible = "mediatek,mt8195-wpesys_vpp1";
1557			reg = <0 0x14e03000 0 0x1000>;
1558			#clock-cells = <1>;
1559		};
1560
1561		larb7: larb@14e04000 {
1562			compatible = "mediatek,mt8195-smi-larb";
1563			reg = <0 0x14e04000 0 0x1000>;
1564			mediatek,larb-id = <7>;
1565			mediatek,smi = <&smi_common_vdo>;
1566			clocks = <&wpesys CLK_WPE_SMI_LARB7>,
1567				 <&wpesys CLK_WPE_SMI_LARB7>;
1568			clock-names = "apb", "smi";
1569			power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1570		};
1571
1572		larb8: larb@14e05000 {
1573			compatible = "mediatek,mt8195-smi-larb";
1574			reg = <0 0x14e05000 0 0x1000>;
1575			mediatek,larb-id = <8>;
1576			mediatek,smi = <&smi_common_vpp>;
1577			clocks = <&wpesys CLK_WPE_SMI_LARB8>,
1578			       <&wpesys CLK_WPE_SMI_LARB8>,
1579			       <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1580			clock-names = "apb", "smi", "gals";
1581			power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1582		};
1583
1584		vppsys1: clock-controller@14f00000 {
1585			compatible = "mediatek,mt8195-vppsys1";
1586			reg = <0 0x14f00000 0 0x1000>;
1587			#clock-cells = <1>;
1588		};
1589
1590		larb5: larb@14f02000 {
1591			compatible = "mediatek,mt8195-smi-larb";
1592			reg = <0 0x14f02000 0 0x1000>;
1593			mediatek,larb-id = <5>;
1594			mediatek,smi = <&smi_common_vdo>;
1595			clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1596			       <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1597			       <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
1598			clock-names = "apb", "smi", "gals";
1599			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1600		};
1601
1602		larb6: larb@14f03000 {
1603			compatible = "mediatek,mt8195-smi-larb";
1604			reg = <0 0x14f03000 0 0x1000>;
1605			mediatek,larb-id = <6>;
1606			mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
1607			clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1608			       <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1609			       <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
1610			clock-names = "apb", "smi", "gals";
1611			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1612		};
1613
1614		imgsys: clock-controller@15000000 {
1615			compatible = "mediatek,mt8195-imgsys";
1616			reg = <0 0x15000000 0 0x1000>;
1617			#clock-cells = <1>;
1618		};
1619
1620		larb9: larb@15001000 {
1621			compatible = "mediatek,mt8195-smi-larb";
1622			reg = <0 0x15001000 0 0x1000>;
1623			mediatek,larb-id = <9>;
1624			mediatek,smi = <&smi_sub_common_img1_3x1>;
1625			clocks = <&imgsys CLK_IMG_LARB9>,
1626				 <&imgsys CLK_IMG_LARB9>,
1627				 <&imgsys CLK_IMG_GALS>;
1628			clock-names = "apb", "smi", "gals";
1629			power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1630		};
1631
1632		smi_sub_common_img0_3x1: smi@15002000 {
1633			compatible = "mediatek,mt8195-smi-sub-common";
1634			reg = <0 0x15002000 0 0x1000>;
1635			clocks = <&imgsys CLK_IMG_IPE>,
1636				 <&imgsys CLK_IMG_IPE>,
1637				 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
1638			clock-names = "apb", "smi", "gals0";
1639			mediatek,smi = <&smi_common_vpp>;
1640			power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1641		};
1642
1643		smi_sub_common_img1_3x1: smi@15003000 {
1644			compatible = "mediatek,mt8195-smi-sub-common";
1645			reg = <0 0x15003000 0 0x1000>;
1646			clocks = <&imgsys CLK_IMG_LARB9>,
1647				 <&imgsys CLK_IMG_LARB9>,
1648				 <&imgsys CLK_IMG_GALS>;
1649			clock-names = "apb", "smi", "gals0";
1650			mediatek,smi = <&smi_common_vdo>;
1651			power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1652		};
1653
1654		imgsys1_dip_top: clock-controller@15110000 {
1655			compatible = "mediatek,mt8195-imgsys1_dip_top";
1656			reg = <0 0x15110000 0 0x1000>;
1657			#clock-cells = <1>;
1658		};
1659
1660		larb10: larb@15120000 {
1661			compatible = "mediatek,mt8195-smi-larb";
1662			reg = <0 0x15120000 0 0x1000>;
1663			mediatek,larb-id = <10>;
1664			mediatek,smi = <&smi_sub_common_img1_3x1>;
1665			clocks = <&imgsys CLK_IMG_DIP0>,
1666			       <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
1667			clock-names = "apb", "smi";
1668			power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1669		};
1670
1671		imgsys1_dip_nr: clock-controller@15130000 {
1672			compatible = "mediatek,mt8195-imgsys1_dip_nr";
1673			reg = <0 0x15130000 0 0x1000>;
1674			#clock-cells = <1>;
1675		};
1676
1677		imgsys1_wpe: clock-controller@15220000 {
1678			compatible = "mediatek,mt8195-imgsys1_wpe";
1679			reg = <0 0x15220000 0 0x1000>;
1680			#clock-cells = <1>;
1681		};
1682
1683		larb11: larb@15230000 {
1684			compatible = "mediatek,mt8195-smi-larb";
1685			reg = <0 0x15230000 0 0x1000>;
1686			mediatek,larb-id = <11>;
1687			mediatek,smi = <&smi_sub_common_img1_3x1>;
1688			clocks = <&imgsys CLK_IMG_WPE0>,
1689			       <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
1690			clock-names = "apb", "smi";
1691			power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1692		};
1693
1694		ipesys: clock-controller@15330000 {
1695			compatible = "mediatek,mt8195-ipesys";
1696			reg = <0 0x15330000 0 0x1000>;
1697			#clock-cells = <1>;
1698		};
1699
1700		larb12: larb@15340000 {
1701			compatible = "mediatek,mt8195-smi-larb";
1702			reg = <0 0x15340000 0 0x1000>;
1703			mediatek,larb-id = <12>;
1704			mediatek,smi = <&smi_sub_common_img0_3x1>;
1705			clocks = <&ipesys CLK_IPE_SMI_LARB12>,
1706				 <&ipesys CLK_IPE_SMI_LARB12>;
1707			clock-names = "apb", "smi";
1708			power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
1709		};
1710
1711		camsys: clock-controller@16000000 {
1712			compatible = "mediatek,mt8195-camsys";
1713			reg = <0 0x16000000 0 0x1000>;
1714			#clock-cells = <1>;
1715		};
1716
1717		larb13: larb@16001000 {
1718			compatible = "mediatek,mt8195-smi-larb";
1719			reg = <0 0x16001000 0 0x1000>;
1720			mediatek,larb-id = <13>;
1721			mediatek,smi = <&smi_sub_common_cam_4x1>;
1722			clocks = <&camsys CLK_CAM_LARB13>,
1723			       <&camsys CLK_CAM_LARB13>,
1724			       <&camsys CLK_CAM_CAM2MM0_GALS>;
1725			clock-names = "apb", "smi", "gals";
1726			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1727		};
1728
1729		larb14: larb@16002000 {
1730			compatible = "mediatek,mt8195-smi-larb";
1731			reg = <0 0x16002000 0 0x1000>;
1732			mediatek,larb-id = <14>;
1733			mediatek,smi = <&smi_sub_common_cam_7x1>;
1734			clocks = <&camsys CLK_CAM_LARB14>,
1735				 <&camsys CLK_CAM_LARB14>;
1736			clock-names = "apb", "smi";
1737			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1738		};
1739
1740		smi_sub_common_cam_4x1: smi@16004000 {
1741			compatible = "mediatek,mt8195-smi-sub-common";
1742			reg = <0 0x16004000 0 0x1000>;
1743			clocks = <&camsys CLK_CAM_LARB13>,
1744				 <&camsys CLK_CAM_LARB13>,
1745				 <&camsys CLK_CAM_CAM2MM0_GALS>;
1746			clock-names = "apb", "smi", "gals0";
1747			mediatek,smi = <&smi_common_vdo>;
1748			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1749		};
1750
1751		smi_sub_common_cam_7x1: smi@16005000 {
1752			compatible = "mediatek,mt8195-smi-sub-common";
1753			reg = <0 0x16005000 0 0x1000>;
1754			clocks = <&camsys CLK_CAM_LARB14>,
1755				 <&camsys CLK_CAM_CAM2MM1_GALS>,
1756				 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
1757			clock-names = "apb", "smi", "gals0";
1758			mediatek,smi = <&smi_common_vpp>;
1759			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1760		};
1761
1762		larb16: larb@16012000 {
1763			compatible = "mediatek,mt8195-smi-larb";
1764			reg = <0 0x16012000 0 0x1000>;
1765			mediatek,larb-id = <16>;
1766			mediatek,smi = <&smi_sub_common_cam_7x1>;
1767			clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
1768				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1769			clock-names = "apb", "smi";
1770			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1771		};
1772
1773		larb17: larb@16013000 {
1774			compatible = "mediatek,mt8195-smi-larb";
1775			reg = <0 0x16013000 0 0x1000>;
1776			mediatek,larb-id = <17>;
1777			mediatek,smi = <&smi_sub_common_cam_4x1>;
1778			clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
1779				 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
1780			clock-names = "apb", "smi";
1781			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1782		};
1783
1784		larb27: larb@16014000 {
1785			compatible = "mediatek,mt8195-smi-larb";
1786			reg = <0 0x16014000 0 0x1000>;
1787			mediatek,larb-id = <27>;
1788			mediatek,smi = <&smi_sub_common_cam_7x1>;
1789			clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
1790				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1791			clock-names = "apb", "smi";
1792			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1793		};
1794
1795		larb28: larb@16015000 {
1796			compatible = "mediatek,mt8195-smi-larb";
1797			reg = <0 0x16015000 0 0x1000>;
1798			mediatek,larb-id = <28>;
1799			mediatek,smi = <&smi_sub_common_cam_4x1>;
1800			clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
1801				 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
1802			clock-names = "apb", "smi";
1803			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1804		};
1805
1806		camsys_rawa: clock-controller@1604f000 {
1807			compatible = "mediatek,mt8195-camsys_rawa";
1808			reg = <0 0x1604f000 0 0x1000>;
1809			#clock-cells = <1>;
1810		};
1811
1812		camsys_yuva: clock-controller@1606f000 {
1813			compatible = "mediatek,mt8195-camsys_yuva";
1814			reg = <0 0x1606f000 0 0x1000>;
1815			#clock-cells = <1>;
1816		};
1817
1818		camsys_rawb: clock-controller@1608f000 {
1819			compatible = "mediatek,mt8195-camsys_rawb";
1820			reg = <0 0x1608f000 0 0x1000>;
1821			#clock-cells = <1>;
1822		};
1823
1824		camsys_yuvb: clock-controller@160af000 {
1825			compatible = "mediatek,mt8195-camsys_yuvb";
1826			reg = <0 0x160af000 0 0x1000>;
1827			#clock-cells = <1>;
1828		};
1829
1830		camsys_mraw: clock-controller@16140000 {
1831			compatible = "mediatek,mt8195-camsys_mraw";
1832			reg = <0 0x16140000 0 0x1000>;
1833			#clock-cells = <1>;
1834		};
1835
1836		larb25: larb@16141000 {
1837			compatible = "mediatek,mt8195-smi-larb";
1838			reg = <0 0x16141000 0 0x1000>;
1839			mediatek,larb-id = <25>;
1840			mediatek,smi = <&smi_sub_common_cam_4x1>;
1841			clocks = <&camsys CLK_CAM_LARB13>,
1842				 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
1843				 <&camsys CLK_CAM_CAM2MM0_GALS>;
1844			clock-names = "apb", "smi", "gals";
1845			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1846		};
1847
1848		larb26: larb@16142000 {
1849			compatible = "mediatek,mt8195-smi-larb";
1850			reg = <0 0x16142000 0 0x1000>;
1851			mediatek,larb-id = <26>;
1852			mediatek,smi = <&smi_sub_common_cam_7x1>;
1853			clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
1854				 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
1855			clock-names = "apb", "smi";
1856			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1857
1858		};
1859
1860		ccusys: clock-controller@17200000 {
1861			compatible = "mediatek,mt8195-ccusys";
1862			reg = <0 0x17200000 0 0x1000>;
1863			#clock-cells = <1>;
1864		};
1865
1866		larb18: larb@17201000 {
1867			compatible = "mediatek,mt8195-smi-larb";
1868			reg = <0 0x17201000 0 0x1000>;
1869			mediatek,larb-id = <18>;
1870			mediatek,smi = <&smi_sub_common_cam_7x1>;
1871			clocks = <&ccusys CLK_CCU_LARB18>,
1872				 <&ccusys CLK_CCU_LARB18>;
1873			clock-names = "apb", "smi";
1874			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1875		};
1876
1877		larb24: larb@1800d000 {
1878			compatible = "mediatek,mt8195-smi-larb";
1879			reg = <0 0x1800d000 0 0x1000>;
1880			mediatek,larb-id = <24>;
1881			mediatek,smi = <&smi_common_vdo>;
1882			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1883				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1884			clock-names = "apb", "smi";
1885			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1886		};
1887
1888		larb23: larb@1800e000 {
1889			compatible = "mediatek,mt8195-smi-larb";
1890			reg = <0 0x1800e000 0 0x1000>;
1891			mediatek,larb-id = <23>;
1892			mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
1893			clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1894				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1895			clock-names = "apb", "smi";
1896			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1897		};
1898
1899		vdecsys_soc: clock-controller@1800f000 {
1900			compatible = "mediatek,mt8195-vdecsys_soc";
1901			reg = <0 0x1800f000 0 0x1000>;
1902			#clock-cells = <1>;
1903		};
1904
1905		larb21: larb@1802e000 {
1906			compatible = "mediatek,mt8195-smi-larb";
1907			reg = <0 0x1802e000 0 0x1000>;
1908			mediatek,larb-id = <21>;
1909			mediatek,smi = <&smi_common_vdo>;
1910			clocks = <&vdecsys CLK_VDEC_LARB1>,
1911				 <&vdecsys CLK_VDEC_LARB1>;
1912			clock-names = "apb", "smi";
1913			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
1914		};
1915
1916		vdecsys: clock-controller@1802f000 {
1917			compatible = "mediatek,mt8195-vdecsys";
1918			reg = <0 0x1802f000 0 0x1000>;
1919			#clock-cells = <1>;
1920		};
1921
1922		larb22: larb@1803e000 {
1923			compatible = "mediatek,mt8195-smi-larb";
1924			reg = <0 0x1803e000 0 0x1000>;
1925			mediatek,larb-id = <22>;
1926			mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
1927			clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1928				 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
1929			clock-names = "apb", "smi";
1930			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
1931		};
1932
1933		vdecsys_core1: clock-controller@1803f000 {
1934			compatible = "mediatek,mt8195-vdecsys_core1";
1935			reg = <0 0x1803f000 0 0x1000>;
1936			#clock-cells = <1>;
1937		};
1938
1939		apusys_pll: clock-controller@190f3000 {
1940			compatible = "mediatek,mt8195-apusys_pll";
1941			reg = <0 0x190f3000 0 0x1000>;
1942			#clock-cells = <1>;
1943		};
1944
1945		vencsys: clock-controller@1a000000 {
1946			compatible = "mediatek,mt8195-vencsys";
1947			reg = <0 0x1a000000 0 0x1000>;
1948			#clock-cells = <1>;
1949		};
1950
1951		larb19: larb@1a010000 {
1952			compatible = "mediatek,mt8195-smi-larb";
1953			reg = <0 0x1a010000 0 0x1000>;
1954			mediatek,larb-id = <19>;
1955			mediatek,smi = <&smi_common_vdo>;
1956			clocks = <&vencsys CLK_VENC_VENC>,
1957				 <&vencsys CLK_VENC_GALS>;
1958			clock-names = "apb", "smi";
1959			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
1960		};
1961
1962		vencsys_core1: clock-controller@1b000000 {
1963			compatible = "mediatek,mt8195-vencsys_core1";
1964			reg = <0 0x1b000000 0 0x1000>;
1965			#clock-cells = <1>;
1966		};
1967
1968		vdosys0: syscon@1c01a000 {
1969			compatible = "mediatek,mt8195-mmsys", "syscon";
1970			reg = <0 0x1c01a000 0 0x1000>;
1971			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
1972			#clock-cells = <1>;
1973		};
1974
1975		larb20: larb@1b010000 {
1976			compatible = "mediatek,mt8195-smi-larb";
1977			reg = <0 0x1b010000 0 0x1000>;
1978			mediatek,larb-id = <20>;
1979			mediatek,smi = <&smi_common_vpp>;
1980			clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
1981				 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
1982				 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
1983			clock-names = "apb", "smi", "gals";
1984			power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
1985		};
1986
1987		ovl0: ovl@1c000000 {
1988			compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
1989			reg = <0 0x1c000000 0 0x1000>;
1990			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
1991			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1992			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
1993			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
1994			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
1995		};
1996
1997		rdma0: rdma@1c002000 {
1998			compatible = "mediatek,mt8195-disp-rdma";
1999			reg = <0 0x1c002000 0 0x1000>;
2000			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
2001			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2002			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
2003			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
2004			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2005		};
2006
2007		color0: color@1c003000 {
2008			compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2009			reg = <0 0x1c003000 0 0x1000>;
2010			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
2011			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2012			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
2013			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2014		};
2015
2016		ccorr0: ccorr@1c004000 {
2017			compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2018			reg = <0 0x1c004000 0 0x1000>;
2019			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
2020			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2021			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
2022			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2023		};
2024
2025		aal0: aal@1c005000 {
2026			compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2027			reg = <0 0x1c005000 0 0x1000>;
2028			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
2029			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2030			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
2031			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2032		};
2033
2034		gamma0: gamma@1c006000 {
2035			compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2036			reg = <0 0x1c006000 0 0x1000>;
2037			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
2038			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2039			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
2040			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2041		};
2042
2043		dither0: dither@1c007000 {
2044			compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2045			reg = <0 0x1c007000 0 0x1000>;
2046			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
2047			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2048			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
2049			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2050		};
2051
2052		dsc0: dsc@1c009000 {
2053			compatible = "mediatek,mt8195-disp-dsc";
2054			reg = <0 0x1c009000 0 0x1000>;
2055			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
2056			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2057			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
2058			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2059		};
2060
2061		merge0: merge@1c014000 {
2062			compatible = "mediatek,mt8195-disp-merge";
2063			reg = <0 0x1c014000 0 0x1000>;
2064			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
2065			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2066			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
2067			mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2068		};
2069
2070		mutex: mutex@1c016000 {
2071			compatible = "mediatek,mt8195-disp-mutex";
2072			reg = <0 0x1c016000 0 0x1000>;
2073			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2074			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2075			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2076			mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2077		};
2078
2079		larb0: larb@1c018000 {
2080			compatible = "mediatek,mt8195-smi-larb";
2081			reg = <0 0x1c018000 0 0x1000>;
2082			mediatek,larb-id = <0>;
2083			mediatek,smi = <&smi_common_vdo>;
2084			clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2085				 <&vdosys0 CLK_VDO0_SMI_LARB>,
2086				 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
2087			clock-names = "apb", "smi", "gals";
2088			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2089		};
2090
2091		larb1: larb@1c019000 {
2092			compatible = "mediatek,mt8195-smi-larb";
2093			reg = <0 0x1c019000 0 0x1000>;
2094			mediatek,larb-id = <1>;
2095			mediatek,smi = <&smi_common_vpp>;
2096			clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2097				 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
2098				 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
2099			clock-names = "apb", "smi", "gals";
2100			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2101		};
2102
2103		vdosys1: syscon@1c100000 {
2104			compatible = "mediatek,mt8195-mmsys", "syscon";
2105			reg = <0 0x1c100000 0 0x1000>;
2106			#clock-cells = <1>;
2107		};
2108
2109		smi_common_vdo: smi@1c01b000 {
2110			compatible = "mediatek,mt8195-smi-common-vdo";
2111			reg = <0 0x1c01b000 0 0x1000>;
2112			clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
2113				 <&vdosys0 CLK_VDO0_SMI_EMI>,
2114				 <&vdosys0 CLK_VDO0_SMI_RSI>,
2115				 <&vdosys0 CLK_VDO0_SMI_GALS>;
2116			clock-names = "apb", "smi", "gals0", "gals1";
2117			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2118
2119		};
2120
2121		iommu_vdo: iommu@1c01f000 {
2122			compatible = "mediatek,mt8195-iommu-vdo";
2123			reg = <0 0x1c01f000 0 0x1000>;
2124			mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
2125					  &larb10 &larb11 &larb13 &larb17
2126					  &larb19 &larb21 &larb24 &larb25
2127					  &larb28>;
2128			interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
2129			#iommu-cells = <1>;
2130			clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
2131			clock-names = "bclk";
2132			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2133		};
2134
2135		larb2: larb@1c102000 {
2136			compatible = "mediatek,mt8195-smi-larb";
2137			reg = <0 0x1c102000 0 0x1000>;
2138			mediatek,larb-id = <2>;
2139			mediatek,smi = <&smi_common_vdo>;
2140			clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
2141				 <&vdosys1 CLK_VDO1_SMI_LARB2>,
2142				 <&vdosys1 CLK_VDO1_GALS>;
2143			clock-names = "apb", "smi", "gals";
2144			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2145		};
2146
2147		larb3: larb@1c103000 {
2148			compatible = "mediatek,mt8195-smi-larb";
2149			reg = <0 0x1c103000 0 0x1000>;
2150			mediatek,larb-id = <3>;
2151			mediatek,smi = <&smi_common_vpp>;
2152			clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2153				 <&vdosys1 CLK_VDO1_GALS>,
2154				 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2155			clock-names = "apb", "smi", "gals";
2156			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2157		};
2158	};
2159};
2160