1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17 18/ { 19 compatible = "mediatek,mt8195"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 gce0 = &gce0; 26 gce1 = &gce1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a55"; 36 reg = <0x000>; 37 enable-method = "psci"; 38 performance-domains = <&performance 0>; 39 clock-frequency = <1701000000>; 40 capacity-dmips-mhz = <308>; 41 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 42 i-cache-size = <32768>; 43 i-cache-line-size = <64>; 44 i-cache-sets = <128>; 45 d-cache-size = <32768>; 46 d-cache-line-size = <64>; 47 d-cache-sets = <128>; 48 next-level-cache = <&l2_0>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu1: cpu@100 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x100>; 56 enable-method = "psci"; 57 performance-domains = <&performance 0>; 58 clock-frequency = <1701000000>; 59 capacity-dmips-mhz = <308>; 60 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 61 i-cache-size = <32768>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <128>; 64 d-cache-size = <32768>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <128>; 67 next-level-cache = <&l2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x200>; 75 enable-method = "psci"; 76 performance-domains = <&performance 0>; 77 clock-frequency = <1701000000>; 78 capacity-dmips-mhz = <308>; 79 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <128>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_0>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu3: cpu@300 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x300>; 94 enable-method = "psci"; 95 performance-domains = <&performance 0>; 96 clock-frequency = <1701000000>; 97 capacity-dmips-mhz = <308>; 98 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 99 i-cache-size = <32768>; 100 i-cache-line-size = <64>; 101 i-cache-sets = <128>; 102 d-cache-size = <32768>; 103 d-cache-line-size = <64>; 104 d-cache-sets = <128>; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu4: cpu@400 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a78"; 112 reg = <0x400>; 113 enable-method = "psci"; 114 performance-domains = <&performance 1>; 115 clock-frequency = <2171000000>; 116 capacity-dmips-mhz = <1024>; 117 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 118 i-cache-size = <65536>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <256>; 121 d-cache-size = <65536>; 122 d-cache-line-size = <64>; 123 d-cache-sets = <256>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu5: cpu@500 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a78"; 131 reg = <0x500>; 132 enable-method = "psci"; 133 performance-domains = <&performance 1>; 134 clock-frequency = <2171000000>; 135 capacity-dmips-mhz = <1024>; 136 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 137 i-cache-size = <65536>; 138 i-cache-line-size = <64>; 139 i-cache-sets = <256>; 140 d-cache-size = <65536>; 141 d-cache-line-size = <64>; 142 d-cache-sets = <256>; 143 next-level-cache = <&l2_1>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu6: cpu@600 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a78"; 150 reg = <0x600>; 151 enable-method = "psci"; 152 performance-domains = <&performance 1>; 153 clock-frequency = <2171000000>; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 156 i-cache-size = <65536>; 157 i-cache-line-size = <64>; 158 i-cache-sets = <256>; 159 d-cache-size = <65536>; 160 d-cache-line-size = <64>; 161 d-cache-sets = <256>; 162 next-level-cache = <&l2_1>; 163 #cooling-cells = <2>; 164 }; 165 166 cpu7: cpu@700 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a78"; 169 reg = <0x700>; 170 enable-method = "psci"; 171 performance-domains = <&performance 1>; 172 clock-frequency = <2171000000>; 173 capacity-dmips-mhz = <1024>; 174 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 175 i-cache-size = <65536>; 176 i-cache-line-size = <64>; 177 i-cache-sets = <256>; 178 d-cache-size = <65536>; 179 d-cache-line-size = <64>; 180 d-cache-sets = <256>; 181 next-level-cache = <&l2_1>; 182 #cooling-cells = <2>; 183 }; 184 185 cpu-map { 186 cluster0 { 187 core0 { 188 cpu = <&cpu0>; 189 }; 190 191 core1 { 192 cpu = <&cpu1>; 193 }; 194 195 core2 { 196 cpu = <&cpu2>; 197 }; 198 199 core3 { 200 cpu = <&cpu3>; 201 }; 202 203 core4 { 204 cpu = <&cpu4>; 205 }; 206 207 core5 { 208 cpu = <&cpu5>; 209 }; 210 211 core6 { 212 cpu = <&cpu6>; 213 }; 214 215 core7 { 216 cpu = <&cpu7>; 217 }; 218 }; 219 }; 220 221 idle-states { 222 entry-method = "psci"; 223 224 cpu_ret_l: cpu-retention-l { 225 compatible = "arm,idle-state"; 226 arm,psci-suspend-param = <0x00010001>; 227 local-timer-stop; 228 entry-latency-us = <50>; 229 exit-latency-us = <95>; 230 min-residency-us = <580>; 231 }; 232 233 cpu_ret_b: cpu-retention-b { 234 compatible = "arm,idle-state"; 235 arm,psci-suspend-param = <0x00010001>; 236 local-timer-stop; 237 entry-latency-us = <45>; 238 exit-latency-us = <140>; 239 min-residency-us = <740>; 240 }; 241 242 cpu_off_l: cpu-off-l { 243 compatible = "arm,idle-state"; 244 arm,psci-suspend-param = <0x01010002>; 245 local-timer-stop; 246 entry-latency-us = <55>; 247 exit-latency-us = <155>; 248 min-residency-us = <840>; 249 }; 250 251 cpu_off_b: cpu-off-b { 252 compatible = "arm,idle-state"; 253 arm,psci-suspend-param = <0x01010002>; 254 local-timer-stop; 255 entry-latency-us = <50>; 256 exit-latency-us = <200>; 257 min-residency-us = <1000>; 258 }; 259 }; 260 261 l2_0: l2-cache0 { 262 compatible = "cache"; 263 cache-level = <2>; 264 cache-size = <131072>; 265 cache-line-size = <64>; 266 cache-sets = <512>; 267 next-level-cache = <&l3_0>; 268 }; 269 270 l2_1: l2-cache1 { 271 compatible = "cache"; 272 cache-level = <2>; 273 cache-size = <262144>; 274 cache-line-size = <64>; 275 cache-sets = <512>; 276 next-level-cache = <&l3_0>; 277 }; 278 279 l3_0: l3-cache { 280 compatible = "cache"; 281 cache-level = <3>; 282 cache-size = <2097152>; 283 cache-line-size = <64>; 284 cache-sets = <2048>; 285 cache-unified; 286 }; 287 }; 288 289 dsu-pmu { 290 compatible = "arm,dsu-pmu"; 291 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 292 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 293 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 294 }; 295 296 dmic_codec: dmic-codec { 297 compatible = "dmic-codec"; 298 num-channels = <2>; 299 wakeup-delay-ms = <50>; 300 }; 301 302 sound: mt8195-sound { 303 mediatek,platform = <&afe>; 304 status = "disabled"; 305 }; 306 307 clk13m: fixed-factor-clock-13m { 308 compatible = "fixed-factor-clock"; 309 #clock-cells = <0>; 310 clocks = <&clk26m>; 311 clock-div = <2>; 312 clock-mult = <1>; 313 clock-output-names = "clk13m"; 314 }; 315 316 clk26m: oscillator-26m { 317 compatible = "fixed-clock"; 318 #clock-cells = <0>; 319 clock-frequency = <26000000>; 320 clock-output-names = "clk26m"; 321 }; 322 323 clk32k: oscillator-32k { 324 compatible = "fixed-clock"; 325 #clock-cells = <0>; 326 clock-frequency = <32768>; 327 clock-output-names = "clk32k"; 328 }; 329 330 performance: performance-controller@11bc10 { 331 compatible = "mediatek,cpufreq-hw"; 332 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 333 #performance-domain-cells = <1>; 334 }; 335 336 pmu-a55 { 337 compatible = "arm,cortex-a55-pmu"; 338 interrupt-parent = <&gic>; 339 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 340 }; 341 342 pmu-a78 { 343 compatible = "arm,cortex-a78-pmu"; 344 interrupt-parent = <&gic>; 345 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 346 }; 347 348 psci { 349 compatible = "arm,psci-1.0"; 350 method = "smc"; 351 }; 352 353 timer: timer { 354 compatible = "arm,armv8-timer"; 355 interrupt-parent = <&gic>; 356 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 357 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 358 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 360 }; 361 362 soc { 363 #address-cells = <2>; 364 #size-cells = <2>; 365 compatible = "simple-bus"; 366 ranges; 367 368 gic: interrupt-controller@c000000 { 369 compatible = "arm,gic-v3"; 370 #interrupt-cells = <4>; 371 #redistributor-regions = <1>; 372 interrupt-parent = <&gic>; 373 interrupt-controller; 374 reg = <0 0x0c000000 0 0x40000>, 375 <0 0x0c040000 0 0x200000>; 376 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 377 378 ppi-partitions { 379 ppi_cluster0: interrupt-partition-0 { 380 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 381 }; 382 383 ppi_cluster1: interrupt-partition-1 { 384 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 385 }; 386 }; 387 }; 388 389 topckgen: syscon@10000000 { 390 compatible = "mediatek,mt8195-topckgen", "syscon"; 391 reg = <0 0x10000000 0 0x1000>; 392 #clock-cells = <1>; 393 }; 394 395 infracfg_ao: syscon@10001000 { 396 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 397 reg = <0 0x10001000 0 0x1000>; 398 #clock-cells = <1>; 399 #reset-cells = <1>; 400 }; 401 402 pericfg: syscon@10003000 { 403 compatible = "mediatek,mt8195-pericfg", "syscon"; 404 reg = <0 0x10003000 0 0x1000>; 405 #clock-cells = <1>; 406 }; 407 408 pio: pinctrl@10005000 { 409 compatible = "mediatek,mt8195-pinctrl"; 410 reg = <0 0x10005000 0 0x1000>, 411 <0 0x11d10000 0 0x1000>, 412 <0 0x11d30000 0 0x1000>, 413 <0 0x11d40000 0 0x1000>, 414 <0 0x11e20000 0 0x1000>, 415 <0 0x11eb0000 0 0x1000>, 416 <0 0x11f40000 0 0x1000>, 417 <0 0x1000b000 0 0x1000>; 418 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 419 "iocfg_br", "iocfg_lm", "iocfg_rb", 420 "iocfg_tl", "eint"; 421 gpio-controller; 422 #gpio-cells = <2>; 423 gpio-ranges = <&pio 0 0 144>; 424 interrupt-controller; 425 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 426 #interrupt-cells = <2>; 427 }; 428 429 scpsys: syscon@10006000 { 430 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 431 reg = <0 0x10006000 0 0x1000>; 432 433 /* System Power Manager */ 434 spm: power-controller { 435 compatible = "mediatek,mt8195-power-controller"; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 #power-domain-cells = <1>; 439 440 /* power domain of the SoC */ 441 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 442 reg = <MT8195_POWER_DOMAIN_MFG0>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 #power-domain-cells = <1>; 446 447 power-domain@MT8195_POWER_DOMAIN_MFG1 { 448 reg = <MT8195_POWER_DOMAIN_MFG1>; 449 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 450 clock-names = "mfg"; 451 mediatek,infracfg = <&infracfg_ao>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 #power-domain-cells = <1>; 455 456 power-domain@MT8195_POWER_DOMAIN_MFG2 { 457 reg = <MT8195_POWER_DOMAIN_MFG2>; 458 #power-domain-cells = <0>; 459 }; 460 461 power-domain@MT8195_POWER_DOMAIN_MFG3 { 462 reg = <MT8195_POWER_DOMAIN_MFG3>; 463 #power-domain-cells = <0>; 464 }; 465 466 power-domain@MT8195_POWER_DOMAIN_MFG4 { 467 reg = <MT8195_POWER_DOMAIN_MFG4>; 468 #power-domain-cells = <0>; 469 }; 470 471 power-domain@MT8195_POWER_DOMAIN_MFG5 { 472 reg = <MT8195_POWER_DOMAIN_MFG5>; 473 #power-domain-cells = <0>; 474 }; 475 476 power-domain@MT8195_POWER_DOMAIN_MFG6 { 477 reg = <MT8195_POWER_DOMAIN_MFG6>; 478 #power-domain-cells = <0>; 479 }; 480 }; 481 }; 482 483 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 484 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 485 clocks = <&topckgen CLK_TOP_VPP>, 486 <&topckgen CLK_TOP_CAM>, 487 <&topckgen CLK_TOP_CCU>, 488 <&topckgen CLK_TOP_IMG>, 489 <&topckgen CLK_TOP_VENC>, 490 <&topckgen CLK_TOP_VDEC>, 491 <&topckgen CLK_TOP_WPE_VPP>, 492 <&topckgen CLK_TOP_CFG_VPP0>, 493 <&vppsys0 CLK_VPP0_SMI_COMMON>, 494 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 495 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 496 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 497 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 498 <&vppsys0 CLK_VPP0_GALS_INFRA>, 499 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 500 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 501 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 502 <&vppsys0 CLK_VPP0_SMI_REORDER>, 503 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 504 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 505 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 506 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 507 <&vppsys0 CLK_VPP0_SMI_RSI>, 508 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 509 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 510 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 511 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 512 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 513 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 514 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 515 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 516 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 517 "vppsys0-12", "vppsys0-13", "vppsys0-14", 518 "vppsys0-15", "vppsys0-16", "vppsys0-17", 519 "vppsys0-18"; 520 mediatek,infracfg = <&infracfg_ao>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 #power-domain-cells = <1>; 524 525 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 526 reg = <MT8195_POWER_DOMAIN_VDEC1>; 527 clocks = <&vdecsys CLK_VDEC_LARB1>; 528 clock-names = "vdec1-0"; 529 mediatek,infracfg = <&infracfg_ao>; 530 #power-domain-cells = <0>; 531 }; 532 533 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 534 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 535 mediatek,infracfg = <&infracfg_ao>; 536 #power-domain-cells = <0>; 537 }; 538 539 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 540 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 541 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 542 <&vdosys0 CLK_VDO0_SMI_GALS>, 543 <&vdosys0 CLK_VDO0_SMI_COMMON>, 544 <&vdosys0 CLK_VDO0_SMI_EMI>, 545 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 546 <&vdosys0 CLK_VDO0_SMI_LARB>, 547 <&vdosys0 CLK_VDO0_SMI_RSI>; 548 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 549 "vdosys0-2", "vdosys0-3", 550 "vdosys0-4", "vdosys0-5"; 551 mediatek,infracfg = <&infracfg_ao>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 #power-domain-cells = <1>; 555 556 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 557 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 558 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 559 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 560 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 561 clock-names = "vppsys1", "vppsys1-0", 562 "vppsys1-1"; 563 mediatek,infracfg = <&infracfg_ao>; 564 #power-domain-cells = <0>; 565 }; 566 567 power-domain@MT8195_POWER_DOMAIN_WPESYS { 568 reg = <MT8195_POWER_DOMAIN_WPESYS>; 569 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 570 <&wpesys CLK_WPE_SMI_LARB8>, 571 <&wpesys CLK_WPE_SMI_LARB7_P>, 572 <&wpesys CLK_WPE_SMI_LARB8_P>; 573 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 574 "wepsys-3"; 575 mediatek,infracfg = <&infracfg_ao>; 576 #power-domain-cells = <0>; 577 }; 578 579 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 580 reg = <MT8195_POWER_DOMAIN_VDEC0>; 581 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 582 clock-names = "vdec0-0"; 583 mediatek,infracfg = <&infracfg_ao>; 584 #power-domain-cells = <0>; 585 }; 586 587 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 588 reg = <MT8195_POWER_DOMAIN_VDEC2>; 589 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 590 clock-names = "vdec2-0"; 591 mediatek,infracfg = <&infracfg_ao>; 592 #power-domain-cells = <0>; 593 }; 594 595 power-domain@MT8195_POWER_DOMAIN_VENC { 596 reg = <MT8195_POWER_DOMAIN_VENC>; 597 mediatek,infracfg = <&infracfg_ao>; 598 #power-domain-cells = <0>; 599 }; 600 601 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 602 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 603 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 604 <&vdosys1 CLK_VDO1_SMI_LARB2>, 605 <&vdosys1 CLK_VDO1_SMI_LARB3>, 606 <&vdosys1 CLK_VDO1_GALS>; 607 clock-names = "vdosys1", "vdosys1-0", 608 "vdosys1-1", "vdosys1-2"; 609 mediatek,infracfg = <&infracfg_ao>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 #power-domain-cells = <1>; 613 614 power-domain@MT8195_POWER_DOMAIN_DP_TX { 615 reg = <MT8195_POWER_DOMAIN_DP_TX>; 616 mediatek,infracfg = <&infracfg_ao>; 617 #power-domain-cells = <0>; 618 }; 619 620 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 621 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 622 mediatek,infracfg = <&infracfg_ao>; 623 #power-domain-cells = <0>; 624 }; 625 626 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 627 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 628 clocks = <&topckgen CLK_TOP_HDMI_APB>; 629 clock-names = "hdmi_tx"; 630 #power-domain-cells = <0>; 631 }; 632 }; 633 634 power-domain@MT8195_POWER_DOMAIN_IMG { 635 reg = <MT8195_POWER_DOMAIN_IMG>; 636 clocks = <&imgsys CLK_IMG_LARB9>, 637 <&imgsys CLK_IMG_GALS>; 638 clock-names = "img-0", "img-1"; 639 mediatek,infracfg = <&infracfg_ao>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 #power-domain-cells = <1>; 643 644 power-domain@MT8195_POWER_DOMAIN_DIP { 645 reg = <MT8195_POWER_DOMAIN_DIP>; 646 #power-domain-cells = <0>; 647 }; 648 649 power-domain@MT8195_POWER_DOMAIN_IPE { 650 reg = <MT8195_POWER_DOMAIN_IPE>; 651 clocks = <&topckgen CLK_TOP_IPE>, 652 <&imgsys CLK_IMG_IPE>, 653 <&ipesys CLK_IPE_SMI_LARB12>; 654 clock-names = "ipe", "ipe-0", "ipe-1"; 655 mediatek,infracfg = <&infracfg_ao>; 656 #power-domain-cells = <0>; 657 }; 658 }; 659 660 power-domain@MT8195_POWER_DOMAIN_CAM { 661 reg = <MT8195_POWER_DOMAIN_CAM>; 662 clocks = <&camsys CLK_CAM_LARB13>, 663 <&camsys CLK_CAM_LARB14>, 664 <&camsys CLK_CAM_CAM2MM0_GALS>, 665 <&camsys CLK_CAM_CAM2MM1_GALS>, 666 <&camsys CLK_CAM_CAM2SYS_GALS>; 667 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 668 "cam-4"; 669 mediatek,infracfg = <&infracfg_ao>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 #power-domain-cells = <1>; 673 674 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 675 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 676 #power-domain-cells = <0>; 677 }; 678 679 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 680 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 681 #power-domain-cells = <0>; 682 }; 683 684 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 685 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 686 #power-domain-cells = <0>; 687 }; 688 }; 689 }; 690 }; 691 692 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 693 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 694 mediatek,infracfg = <&infracfg_ao>; 695 #power-domain-cells = <0>; 696 }; 697 698 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 699 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 700 mediatek,infracfg = <&infracfg_ao>; 701 #power-domain-cells = <0>; 702 }; 703 704 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 705 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 706 #power-domain-cells = <0>; 707 }; 708 709 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 710 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 711 #power-domain-cells = <0>; 712 }; 713 714 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 715 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 716 clocks = <&topckgen CLK_TOP_SENINF>, 717 <&topckgen CLK_TOP_SENINF2>; 718 clock-names = "csi_rx_top", "csi_rx_top1"; 719 #power-domain-cells = <0>; 720 }; 721 722 power-domain@MT8195_POWER_DOMAIN_ETHER { 723 reg = <MT8195_POWER_DOMAIN_ETHER>; 724 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 725 clock-names = "ether"; 726 #power-domain-cells = <0>; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_ADSP { 730 reg = <MT8195_POWER_DOMAIN_ADSP>; 731 clocks = <&topckgen CLK_TOP_ADSP>, 732 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 733 clock-names = "adsp", "adsp1"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 mediatek,infracfg = <&infracfg_ao>; 737 #power-domain-cells = <1>; 738 739 power-domain@MT8195_POWER_DOMAIN_AUDIO { 740 reg = <MT8195_POWER_DOMAIN_AUDIO>; 741 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 742 <&topckgen CLK_TOP_AUD_INTBUS>, 743 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 744 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 745 clock-names = "audio", "audio1", "audio2", 746 "audio3"; 747 mediatek,infracfg = <&infracfg_ao>; 748 #power-domain-cells = <0>; 749 }; 750 }; 751 }; 752 }; 753 754 watchdog: watchdog@10007000 { 755 compatible = "mediatek,mt8195-wdt"; 756 mediatek,disable-extrst; 757 reg = <0 0x10007000 0 0x100>; 758 #reset-cells = <1>; 759 }; 760 761 apmixedsys: syscon@1000c000 { 762 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 763 reg = <0 0x1000c000 0 0x1000>; 764 #clock-cells = <1>; 765 }; 766 767 systimer: timer@10017000 { 768 compatible = "mediatek,mt8195-timer", 769 "mediatek,mt6765-timer"; 770 reg = <0 0x10017000 0 0x1000>; 771 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 772 clocks = <&clk13m>; 773 }; 774 775 pwrap: pwrap@10024000 { 776 compatible = "mediatek,mt8195-pwrap", "syscon"; 777 reg = <0 0x10024000 0 0x1000>; 778 reg-names = "pwrap"; 779 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 780 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 781 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 782 clock-names = "spi", "wrap"; 783 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 784 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 785 }; 786 787 spmi: spmi@10027000 { 788 compatible = "mediatek,mt8195-spmi"; 789 reg = <0 0x10027000 0 0x000e00>, 790 <0 0x10029000 0 0x000100>; 791 reg-names = "pmif", "spmimst"; 792 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 793 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 794 <&topckgen CLK_TOP_SPMI_M_MST>; 795 clock-names = "pmif_sys_ck", 796 "pmif_tmr_ck", 797 "spmimst_clk_mux"; 798 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 799 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 800 }; 801 802 iommu_infra: infra-iommu@10315000 { 803 compatible = "mediatek,mt8195-iommu-infra"; 804 reg = <0 0x10315000 0 0x5000>; 805 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 806 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 807 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 808 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 809 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 810 #iommu-cells = <1>; 811 }; 812 813 gce0: mailbox@10320000 { 814 compatible = "mediatek,mt8195-gce"; 815 reg = <0 0x10320000 0 0x4000>; 816 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 817 #mbox-cells = <2>; 818 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 819 }; 820 821 gce1: mailbox@10330000 { 822 compatible = "mediatek,mt8195-gce"; 823 reg = <0 0x10330000 0 0x4000>; 824 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 825 #mbox-cells = <2>; 826 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 827 }; 828 829 scp: scp@10500000 { 830 compatible = "mediatek,mt8195-scp"; 831 reg = <0 0x10500000 0 0x100000>, 832 <0 0x10720000 0 0xe0000>, 833 <0 0x10700000 0 0x8000>; 834 reg-names = "sram", "cfg", "l1tcm"; 835 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 836 status = "disabled"; 837 }; 838 839 scp_adsp: clock-controller@10720000 { 840 compatible = "mediatek,mt8195-scp_adsp"; 841 reg = <0 0x10720000 0 0x1000>; 842 #clock-cells = <1>; 843 }; 844 845 adsp: dsp@10803000 { 846 compatible = "mediatek,mt8195-dsp"; 847 reg = <0 0x10803000 0 0x1000>, 848 <0 0x10840000 0 0x40000>; 849 reg-names = "cfg", "sram"; 850 clocks = <&topckgen CLK_TOP_ADSP>, 851 <&clk26m>, 852 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 853 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 854 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 855 <&topckgen CLK_TOP_AUDIO_H>; 856 clock-names = "adsp_sel", 857 "clk26m_ck", 858 "audio_local_bus", 859 "mainpll_d7_d2", 860 "scp_adsp_audiodsp", 861 "audio_h"; 862 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 863 mbox-names = "rx", "tx"; 864 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 865 status = "disabled"; 866 }; 867 868 adsp_mailbox0: mailbox@10816000 { 869 compatible = "mediatek,mt8195-adsp-mbox"; 870 #mbox-cells = <0>; 871 reg = <0 0x10816000 0 0x1000>; 872 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 873 }; 874 875 adsp_mailbox1: mailbox@10817000 { 876 compatible = "mediatek,mt8195-adsp-mbox"; 877 #mbox-cells = <0>; 878 reg = <0 0x10817000 0 0x1000>; 879 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 880 }; 881 882 afe: mt8195-afe-pcm@10890000 { 883 compatible = "mediatek,mt8195-audio"; 884 reg = <0 0x10890000 0 0x10000>; 885 mediatek,topckgen = <&topckgen>; 886 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 887 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 888 resets = <&watchdog 14>; 889 reset-names = "audiosys"; 890 clocks = <&clk26m>, 891 <&apmixedsys CLK_APMIXED_APLL1>, 892 <&apmixedsys CLK_APMIXED_APLL2>, 893 <&topckgen CLK_TOP_APLL12_DIV0>, 894 <&topckgen CLK_TOP_APLL12_DIV1>, 895 <&topckgen CLK_TOP_APLL12_DIV2>, 896 <&topckgen CLK_TOP_APLL12_DIV3>, 897 <&topckgen CLK_TOP_APLL12_DIV9>, 898 <&topckgen CLK_TOP_A1SYS_HP>, 899 <&topckgen CLK_TOP_AUD_INTBUS>, 900 <&topckgen CLK_TOP_AUDIO_H>, 901 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 902 <&topckgen CLK_TOP_DPTX_MCK>, 903 <&topckgen CLK_TOP_I2SO1_MCK>, 904 <&topckgen CLK_TOP_I2SO2_MCK>, 905 <&topckgen CLK_TOP_I2SI1_MCK>, 906 <&topckgen CLK_TOP_I2SI2_MCK>, 907 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 908 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 909 clock-names = "clk26m", 910 "apll1_ck", 911 "apll2_ck", 912 "apll12_div0", 913 "apll12_div1", 914 "apll12_div2", 915 "apll12_div3", 916 "apll12_div9", 917 "a1sys_hp_sel", 918 "aud_intbus_sel", 919 "audio_h_sel", 920 "audio_local_bus_sel", 921 "dptx_m_sel", 922 "i2so1_m_sel", 923 "i2so2_m_sel", 924 "i2si1_m_sel", 925 "i2si2_m_sel", 926 "infra_ao_audio_26m_b", 927 "scp_adsp_audiodsp"; 928 status = "disabled"; 929 }; 930 931 uart0: serial@11001100 { 932 compatible = "mediatek,mt8195-uart", 933 "mediatek,mt6577-uart"; 934 reg = <0 0x11001100 0 0x100>; 935 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 936 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 937 clock-names = "baud", "bus"; 938 status = "disabled"; 939 }; 940 941 uart1: serial@11001200 { 942 compatible = "mediatek,mt8195-uart", 943 "mediatek,mt6577-uart"; 944 reg = <0 0x11001200 0 0x100>; 945 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 946 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 947 clock-names = "baud", "bus"; 948 status = "disabled"; 949 }; 950 951 uart2: serial@11001300 { 952 compatible = "mediatek,mt8195-uart", 953 "mediatek,mt6577-uart"; 954 reg = <0 0x11001300 0 0x100>; 955 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 956 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 957 clock-names = "baud", "bus"; 958 status = "disabled"; 959 }; 960 961 uart3: serial@11001400 { 962 compatible = "mediatek,mt8195-uart", 963 "mediatek,mt6577-uart"; 964 reg = <0 0x11001400 0 0x100>; 965 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 966 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 967 clock-names = "baud", "bus"; 968 status = "disabled"; 969 }; 970 971 uart4: serial@11001500 { 972 compatible = "mediatek,mt8195-uart", 973 "mediatek,mt6577-uart"; 974 reg = <0 0x11001500 0 0x100>; 975 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 976 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 977 clock-names = "baud", "bus"; 978 status = "disabled"; 979 }; 980 981 uart5: serial@11001600 { 982 compatible = "mediatek,mt8195-uart", 983 "mediatek,mt6577-uart"; 984 reg = <0 0x11001600 0 0x100>; 985 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 986 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 987 clock-names = "baud", "bus"; 988 status = "disabled"; 989 }; 990 991 auxadc: auxadc@11002000 { 992 compatible = "mediatek,mt8195-auxadc", 993 "mediatek,mt8173-auxadc"; 994 reg = <0 0x11002000 0 0x1000>; 995 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 996 clock-names = "main"; 997 #io-channel-cells = <1>; 998 status = "disabled"; 999 }; 1000 1001 pericfg_ao: syscon@11003000 { 1002 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1003 reg = <0 0x11003000 0 0x1000>; 1004 #clock-cells = <1>; 1005 }; 1006 1007 spi0: spi@1100a000 { 1008 compatible = "mediatek,mt8195-spi", 1009 "mediatek,mt6765-spi"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 reg = <0 0x1100a000 0 0x1000>; 1013 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1014 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1015 <&topckgen CLK_TOP_SPI>, 1016 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1017 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1018 status = "disabled"; 1019 }; 1020 1021 spi1: spi@11010000 { 1022 compatible = "mediatek,mt8195-spi", 1023 "mediatek,mt6765-spi"; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 reg = <0 0x11010000 0 0x1000>; 1027 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1028 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1029 <&topckgen CLK_TOP_SPI>, 1030 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1031 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1032 status = "disabled"; 1033 }; 1034 1035 spi2: spi@11012000 { 1036 compatible = "mediatek,mt8195-spi", 1037 "mediatek,mt6765-spi"; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 reg = <0 0x11012000 0 0x1000>; 1041 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1042 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1043 <&topckgen CLK_TOP_SPI>, 1044 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1045 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1046 status = "disabled"; 1047 }; 1048 1049 spi3: spi@11013000 { 1050 compatible = "mediatek,mt8195-spi", 1051 "mediatek,mt6765-spi"; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 reg = <0 0x11013000 0 0x1000>; 1055 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1056 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1057 <&topckgen CLK_TOP_SPI>, 1058 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1059 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1060 status = "disabled"; 1061 }; 1062 1063 spi4: spi@11018000 { 1064 compatible = "mediatek,mt8195-spi", 1065 "mediatek,mt6765-spi"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 reg = <0 0x11018000 0 0x1000>; 1069 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1070 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1071 <&topckgen CLK_TOP_SPI>, 1072 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1073 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1074 status = "disabled"; 1075 }; 1076 1077 spi5: spi@11019000 { 1078 compatible = "mediatek,mt8195-spi", 1079 "mediatek,mt6765-spi"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 reg = <0 0x11019000 0 0x1000>; 1083 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1084 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1085 <&topckgen CLK_TOP_SPI>, 1086 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1087 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1088 status = "disabled"; 1089 }; 1090 1091 spis0: spi@1101d000 { 1092 compatible = "mediatek,mt8195-spi-slave"; 1093 reg = <0 0x1101d000 0 0x1000>; 1094 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1095 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1096 clock-names = "spi"; 1097 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1098 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1099 status = "disabled"; 1100 }; 1101 1102 spis1: spi@1101e000 { 1103 compatible = "mediatek,mt8195-spi-slave"; 1104 reg = <0 0x1101e000 0 0x1000>; 1105 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1106 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1107 clock-names = "spi"; 1108 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1109 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1110 status = "disabled"; 1111 }; 1112 1113 eth: ethernet@11021000 { 1114 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1115 reg = <0 0x11021000 0 0x4000>; 1116 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1117 interrupt-names = "macirq"; 1118 clock-names = "axi", 1119 "apb", 1120 "mac_main", 1121 "ptp_ref", 1122 "rmii_internal", 1123 "mac_cg"; 1124 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1125 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1126 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1127 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1128 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1129 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1130 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1131 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1132 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1133 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1134 <&topckgen CLK_TOP_ETHPLL_D8>, 1135 <&topckgen CLK_TOP_ETHPLL_D10>; 1136 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1137 mediatek,pericfg = <&infracfg_ao>; 1138 snps,axi-config = <&stmmac_axi_setup>; 1139 snps,mtl-rx-config = <&mtl_rx_setup>; 1140 snps,mtl-tx-config = <&mtl_tx_setup>; 1141 snps,txpbl = <16>; 1142 snps,rxpbl = <16>; 1143 snps,clk-csr = <0>; 1144 status = "disabled"; 1145 1146 mdio { 1147 compatible = "snps,dwmac-mdio"; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 }; 1151 1152 stmmac_axi_setup: stmmac-axi-config { 1153 snps,wr_osr_lmt = <0x7>; 1154 snps,rd_osr_lmt = <0x7>; 1155 snps,blen = <0 0 0 0 16 8 4>; 1156 }; 1157 1158 mtl_rx_setup: rx-queues-config { 1159 snps,rx-queues-to-use = <4>; 1160 snps,rx-sched-sp; 1161 queue0 { 1162 snps,dcb-algorithm; 1163 snps,map-to-dma-channel = <0x0>; 1164 }; 1165 queue1 { 1166 snps,dcb-algorithm; 1167 snps,map-to-dma-channel = <0x0>; 1168 }; 1169 queue2 { 1170 snps,dcb-algorithm; 1171 snps,map-to-dma-channel = <0x0>; 1172 }; 1173 queue3 { 1174 snps,dcb-algorithm; 1175 snps,map-to-dma-channel = <0x0>; 1176 }; 1177 }; 1178 1179 mtl_tx_setup: tx-queues-config { 1180 snps,tx-queues-to-use = <4>; 1181 snps,tx-sched-wrr; 1182 queue0 { 1183 snps,weight = <0x10>; 1184 snps,dcb-algorithm; 1185 snps,priority = <0x0>; 1186 }; 1187 queue1 { 1188 snps,weight = <0x11>; 1189 snps,dcb-algorithm; 1190 snps,priority = <0x1>; 1191 }; 1192 queue2 { 1193 snps,weight = <0x12>; 1194 snps,dcb-algorithm; 1195 snps,priority = <0x2>; 1196 }; 1197 queue3 { 1198 snps,weight = <0x13>; 1199 snps,dcb-algorithm; 1200 snps,priority = <0x3>; 1201 }; 1202 }; 1203 }; 1204 1205 xhci0: usb@11200000 { 1206 compatible = "mediatek,mt8195-xhci", 1207 "mediatek,mtk-xhci"; 1208 reg = <0 0x11200000 0 0x1000>, 1209 <0 0x11203e00 0 0x0100>; 1210 reg-names = "mac", "ippc"; 1211 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1212 phys = <&u2port0 PHY_TYPE_USB2>, 1213 <&u3port0 PHY_TYPE_USB3>; 1214 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1215 <&topckgen CLK_TOP_SSUSB_XHCI>; 1216 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1217 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1218 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1219 <&topckgen CLK_TOP_SSUSB_REF>, 1220 <&apmixedsys CLK_APMIXED_USB1PLL>, 1221 <&clk26m>, 1222 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1223 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1224 "xhci_ck"; 1225 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1226 wakeup-source; 1227 status = "disabled"; 1228 }; 1229 1230 mmc0: mmc@11230000 { 1231 compatible = "mediatek,mt8195-mmc", 1232 "mediatek,mt8183-mmc"; 1233 reg = <0 0x11230000 0 0x10000>, 1234 <0 0x11f50000 0 0x1000>; 1235 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1236 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1237 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1238 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1239 clock-names = "source", "hclk", "source_cg"; 1240 status = "disabled"; 1241 }; 1242 1243 mmc1: mmc@11240000 { 1244 compatible = "mediatek,mt8195-mmc", 1245 "mediatek,mt8183-mmc"; 1246 reg = <0 0x11240000 0 0x1000>, 1247 <0 0x11c70000 0 0x1000>; 1248 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1249 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1250 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1251 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1252 clock-names = "source", "hclk", "source_cg"; 1253 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1254 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1255 status = "disabled"; 1256 }; 1257 1258 mmc2: mmc@11250000 { 1259 compatible = "mediatek,mt8195-mmc", 1260 "mediatek,mt8183-mmc"; 1261 reg = <0 0x11250000 0 0x1000>, 1262 <0 0x11e60000 0 0x1000>; 1263 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1264 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1265 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1266 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1267 clock-names = "source", "hclk", "source_cg"; 1268 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1269 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1270 status = "disabled"; 1271 }; 1272 1273 xhci1: usb@11290000 { 1274 compatible = "mediatek,mt8195-xhci", 1275 "mediatek,mtk-xhci"; 1276 reg = <0 0x11290000 0 0x1000>, 1277 <0 0x11293e00 0 0x0100>; 1278 reg-names = "mac", "ippc"; 1279 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1280 phys = <&u2port1 PHY_TYPE_USB2>; 1281 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1282 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1283 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1284 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1285 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1286 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1287 <&apmixedsys CLK_APMIXED_USB1PLL>, 1288 <&clk26m>, 1289 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1290 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1291 "xhci_ck"; 1292 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1293 wakeup-source; 1294 status = "disabled"; 1295 }; 1296 1297 xhci2: usb@112a0000 { 1298 compatible = "mediatek,mt8195-xhci", 1299 "mediatek,mtk-xhci"; 1300 reg = <0 0x112a0000 0 0x1000>, 1301 <0 0x112a3e00 0 0x0100>; 1302 reg-names = "mac", "ippc"; 1303 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1304 phys = <&u2port2 PHY_TYPE_USB2>; 1305 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1306 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1307 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1308 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1309 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1310 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1311 <&clk26m>, 1312 <&clk26m>, 1313 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1314 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1315 "xhci_ck"; 1316 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1317 wakeup-source; 1318 status = "disabled"; 1319 }; 1320 1321 xhci3: usb@112b0000 { 1322 compatible = "mediatek,mt8195-xhci", 1323 "mediatek,mtk-xhci"; 1324 reg = <0 0x112b0000 0 0x1000>, 1325 <0 0x112b3e00 0 0x0100>; 1326 reg-names = "mac", "ippc"; 1327 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1328 phys = <&u2port3 PHY_TYPE_USB2>; 1329 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1330 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1331 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1332 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1333 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1334 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1335 <&clk26m>, 1336 <&clk26m>, 1337 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1338 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1339 "xhci_ck"; 1340 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1341 wakeup-source; 1342 status = "disabled"; 1343 }; 1344 1345 pcie0: pcie@112f0000 { 1346 compatible = "mediatek,mt8195-pcie", 1347 "mediatek,mt8192-pcie"; 1348 device_type = "pci"; 1349 #address-cells = <3>; 1350 #size-cells = <2>; 1351 reg = <0 0x112f0000 0 0x4000>; 1352 reg-names = "pcie-mac"; 1353 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1354 bus-range = <0x00 0xff>; 1355 ranges = <0x81000000 0 0x20000000 1356 0x0 0x20000000 0 0x200000>, 1357 <0x82000000 0 0x20200000 1358 0x0 0x20200000 0 0x3e00000>; 1359 1360 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1361 iommu-map-mask = <0x0>; 1362 1363 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1364 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1365 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1366 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1367 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1368 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1369 clock-names = "pl_250m", "tl_26m", "tl_96m", 1370 "tl_32k", "peri_26m", "peri_mem"; 1371 assigned-clocks = <&topckgen CLK_TOP_TL>; 1372 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1373 1374 phys = <&pciephy>; 1375 phy-names = "pcie-phy"; 1376 1377 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1378 1379 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1380 reset-names = "mac"; 1381 1382 #interrupt-cells = <1>; 1383 interrupt-map-mask = <0 0 0 7>; 1384 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1385 <0 0 0 2 &pcie_intc0 1>, 1386 <0 0 0 3 &pcie_intc0 2>, 1387 <0 0 0 4 &pcie_intc0 3>; 1388 status = "disabled"; 1389 1390 pcie_intc0: interrupt-controller { 1391 interrupt-controller; 1392 #address-cells = <0>; 1393 #interrupt-cells = <1>; 1394 }; 1395 }; 1396 1397 pcie1: pcie@112f8000 { 1398 compatible = "mediatek,mt8195-pcie", 1399 "mediatek,mt8192-pcie"; 1400 device_type = "pci"; 1401 #address-cells = <3>; 1402 #size-cells = <2>; 1403 reg = <0 0x112f8000 0 0x4000>; 1404 reg-names = "pcie-mac"; 1405 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1406 bus-range = <0x00 0xff>; 1407 ranges = <0x81000000 0 0x24000000 1408 0x0 0x24000000 0 0x200000>, 1409 <0x82000000 0 0x24200000 1410 0x0 0x24200000 0 0x3e00000>; 1411 1412 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1413 iommu-map-mask = <0x0>; 1414 1415 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1416 <&clk26m>, 1417 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1418 <&clk26m>, 1419 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1420 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1421 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1422 clock-names = "pl_250m", "tl_26m", "tl_96m", 1423 "tl_32k", "peri_26m", "peri_mem"; 1424 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1425 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1426 1427 phys = <&u3port1 PHY_TYPE_PCIE>; 1428 phy-names = "pcie-phy"; 1429 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1430 1431 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1432 reset-names = "mac"; 1433 1434 #interrupt-cells = <1>; 1435 interrupt-map-mask = <0 0 0 7>; 1436 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1437 <0 0 0 2 &pcie_intc1 1>, 1438 <0 0 0 3 &pcie_intc1 2>, 1439 <0 0 0 4 &pcie_intc1 3>; 1440 status = "disabled"; 1441 1442 pcie_intc1: interrupt-controller { 1443 interrupt-controller; 1444 #address-cells = <0>; 1445 #interrupt-cells = <1>; 1446 }; 1447 }; 1448 1449 nor_flash: spi@1132c000 { 1450 compatible = "mediatek,mt8195-nor", 1451 "mediatek,mt8173-nor"; 1452 reg = <0 0x1132c000 0 0x1000>; 1453 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1454 clocks = <&topckgen CLK_TOP_SPINOR>, 1455 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1456 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1457 clock-names = "spi", "sf", "axi"; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 1463 efuse: efuse@11c10000 { 1464 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1465 reg = <0 0x11c10000 0 0x1000>; 1466 #address-cells = <1>; 1467 #size-cells = <1>; 1468 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1469 reg = <0x184 0x1>; 1470 bits = <0 5>; 1471 }; 1472 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1473 reg = <0x184 0x2>; 1474 bits = <5 5>; 1475 }; 1476 u3_intr_p0: usb3-intr@185 { 1477 reg = <0x185 0x1>; 1478 bits = <2 6>; 1479 }; 1480 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1481 reg = <0x186 0x1>; 1482 bits = <0 5>; 1483 }; 1484 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1485 reg = <0x186 0x2>; 1486 bits = <5 5>; 1487 }; 1488 comb_intr_p1: usb3-intr@187 { 1489 reg = <0x187 0x1>; 1490 bits = <2 6>; 1491 }; 1492 u2_intr_p0: usb2-intr-p0@188,1 { 1493 reg = <0x188 0x1>; 1494 bits = <0 5>; 1495 }; 1496 u2_intr_p1: usb2-intr-p1@188,2 { 1497 reg = <0x188 0x2>; 1498 bits = <5 5>; 1499 }; 1500 u2_intr_p2: usb2-intr-p2@189,1 { 1501 reg = <0x189 0x1>; 1502 bits = <2 5>; 1503 }; 1504 u2_intr_p3: usb2-intr-p3@189,2 { 1505 reg = <0x189 0x2>; 1506 bits = <7 5>; 1507 }; 1508 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1509 reg = <0x190 0x1>; 1510 bits = <0 4>; 1511 }; 1512 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1513 reg = <0x190 0x1>; 1514 bits = <4 4>; 1515 }; 1516 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1517 reg = <0x191 0x1>; 1518 bits = <0 4>; 1519 }; 1520 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1521 reg = <0x191 0x1>; 1522 bits = <4 4>; 1523 }; 1524 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1525 reg = <0x192 0x1>; 1526 bits = <0 4>; 1527 }; 1528 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1529 reg = <0x192 0x1>; 1530 bits = <4 4>; 1531 }; 1532 pciephy_glb_intr: pciephy-glb-intr@193 { 1533 reg = <0x193 0x1>; 1534 bits = <0 4>; 1535 }; 1536 dp_calibration: dp-data@1ac { 1537 reg = <0x1ac 0x10>; 1538 }; 1539 lvts_efuse_data1: lvts1-calib@1bc { 1540 reg = <0x1bc 0x14>; 1541 }; 1542 lvts_efuse_data2: lvts2-calib@1d0 { 1543 reg = <0x1d0 0x38>; 1544 }; 1545 }; 1546 1547 u3phy2: t-phy@11c40000 { 1548 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1549 #address-cells = <1>; 1550 #size-cells = <1>; 1551 ranges = <0 0 0x11c40000 0x700>; 1552 status = "disabled"; 1553 1554 u2port2: usb-phy@0 { 1555 reg = <0x0 0x700>; 1556 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1557 clock-names = "ref"; 1558 #phy-cells = <1>; 1559 }; 1560 }; 1561 1562 u3phy3: t-phy@11c50000 { 1563 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1564 #address-cells = <1>; 1565 #size-cells = <1>; 1566 ranges = <0 0 0x11c50000 0x700>; 1567 status = "disabled"; 1568 1569 u2port3: usb-phy@0 { 1570 reg = <0x0 0x700>; 1571 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1572 clock-names = "ref"; 1573 #phy-cells = <1>; 1574 }; 1575 }; 1576 1577 i2c5: i2c@11d00000 { 1578 compatible = "mediatek,mt8195-i2c", 1579 "mediatek,mt8192-i2c"; 1580 reg = <0 0x11d00000 0 0x1000>, 1581 <0 0x10220580 0 0x80>; 1582 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1583 clock-div = <1>; 1584 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1585 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1586 clock-names = "main", "dma"; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 i2c6: i2c@11d01000 { 1593 compatible = "mediatek,mt8195-i2c", 1594 "mediatek,mt8192-i2c"; 1595 reg = <0 0x11d01000 0 0x1000>, 1596 <0 0x10220600 0 0x80>; 1597 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1598 clock-div = <1>; 1599 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1600 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1601 clock-names = "main", "dma"; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 i2c7: i2c@11d02000 { 1608 compatible = "mediatek,mt8195-i2c", 1609 "mediatek,mt8192-i2c"; 1610 reg = <0 0x11d02000 0 0x1000>, 1611 <0 0x10220680 0 0x80>; 1612 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1613 clock-div = <1>; 1614 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1615 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1616 clock-names = "main", "dma"; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 status = "disabled"; 1620 }; 1621 1622 imp_iic_wrap_s: clock-controller@11d03000 { 1623 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1624 reg = <0 0x11d03000 0 0x1000>; 1625 #clock-cells = <1>; 1626 }; 1627 1628 i2c0: i2c@11e00000 { 1629 compatible = "mediatek,mt8195-i2c", 1630 "mediatek,mt8192-i2c"; 1631 reg = <0 0x11e00000 0 0x1000>, 1632 <0 0x10220080 0 0x80>; 1633 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1634 clock-div = <1>; 1635 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1636 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1637 clock-names = "main", "dma"; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 status = "disabled"; 1641 }; 1642 1643 i2c1: i2c@11e01000 { 1644 compatible = "mediatek,mt8195-i2c", 1645 "mediatek,mt8192-i2c"; 1646 reg = <0 0x11e01000 0 0x1000>, 1647 <0 0x10220200 0 0x80>; 1648 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1649 clock-div = <1>; 1650 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1651 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1652 clock-names = "main", "dma"; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 status = "disabled"; 1656 }; 1657 1658 i2c2: i2c@11e02000 { 1659 compatible = "mediatek,mt8195-i2c", 1660 "mediatek,mt8192-i2c"; 1661 reg = <0 0x11e02000 0 0x1000>, 1662 <0 0x10220380 0 0x80>; 1663 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1664 clock-div = <1>; 1665 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1666 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1667 clock-names = "main", "dma"; 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 status = "disabled"; 1671 }; 1672 1673 i2c3: i2c@11e03000 { 1674 compatible = "mediatek,mt8195-i2c", 1675 "mediatek,mt8192-i2c"; 1676 reg = <0 0x11e03000 0 0x1000>, 1677 <0 0x10220480 0 0x80>; 1678 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1679 clock-div = <1>; 1680 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1681 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1682 clock-names = "main", "dma"; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 status = "disabled"; 1686 }; 1687 1688 i2c4: i2c@11e04000 { 1689 compatible = "mediatek,mt8195-i2c", 1690 "mediatek,mt8192-i2c"; 1691 reg = <0 0x11e04000 0 0x1000>, 1692 <0 0x10220500 0 0x80>; 1693 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1694 clock-div = <1>; 1695 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1696 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1697 clock-names = "main", "dma"; 1698 #address-cells = <1>; 1699 #size-cells = <0>; 1700 status = "disabled"; 1701 }; 1702 1703 imp_iic_wrap_w: clock-controller@11e05000 { 1704 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1705 reg = <0 0x11e05000 0 0x1000>; 1706 #clock-cells = <1>; 1707 }; 1708 1709 u3phy1: t-phy@11e30000 { 1710 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1711 #address-cells = <1>; 1712 #size-cells = <1>; 1713 ranges = <0 0 0x11e30000 0xe00>; 1714 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1715 status = "disabled"; 1716 1717 u2port1: usb-phy@0 { 1718 reg = <0x0 0x700>; 1719 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1720 <&clk26m>; 1721 clock-names = "ref", "da_ref"; 1722 #phy-cells = <1>; 1723 }; 1724 1725 u3port1: usb-phy@700 { 1726 reg = <0x700 0x700>; 1727 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1728 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1729 clock-names = "ref", "da_ref"; 1730 nvmem-cells = <&comb_intr_p1>, 1731 <&comb_rx_imp_p1>, 1732 <&comb_tx_imp_p1>; 1733 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1734 #phy-cells = <1>; 1735 }; 1736 }; 1737 1738 u3phy0: t-phy@11e40000 { 1739 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1740 #address-cells = <1>; 1741 #size-cells = <1>; 1742 ranges = <0 0 0x11e40000 0xe00>; 1743 status = "disabled"; 1744 1745 u2port0: usb-phy@0 { 1746 reg = <0x0 0x700>; 1747 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1748 <&clk26m>; 1749 clock-names = "ref", "da_ref"; 1750 #phy-cells = <1>; 1751 }; 1752 1753 u3port0: usb-phy@700 { 1754 reg = <0x700 0x700>; 1755 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1756 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1757 clock-names = "ref", "da_ref"; 1758 nvmem-cells = <&u3_intr_p0>, 1759 <&u3_rx_imp_p0>, 1760 <&u3_tx_imp_p0>; 1761 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1762 #phy-cells = <1>; 1763 }; 1764 }; 1765 1766 pciephy: phy@11e80000 { 1767 compatible = "mediatek,mt8195-pcie-phy"; 1768 reg = <0 0x11e80000 0 0x10000>; 1769 reg-names = "sif"; 1770 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1771 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1772 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1773 <&pciephy_rx_ln1>; 1774 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1775 "tx_ln0_nmos", "rx_ln0", 1776 "tx_ln1_pmos", "tx_ln1_nmos", 1777 "rx_ln1"; 1778 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1779 #phy-cells = <0>; 1780 status = "disabled"; 1781 }; 1782 1783 ufsphy: ufs-phy@11fa0000 { 1784 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1785 reg = <0 0x11fa0000 0 0xc000>; 1786 clocks = <&clk26m>, <&clk26m>; 1787 clock-names = "unipro", "mp"; 1788 #phy-cells = <0>; 1789 status = "disabled"; 1790 }; 1791 1792 mfgcfg: clock-controller@13fbf000 { 1793 compatible = "mediatek,mt8195-mfgcfg"; 1794 reg = <0 0x13fbf000 0 0x1000>; 1795 #clock-cells = <1>; 1796 }; 1797 1798 vppsys0: clock-controller@14000000 { 1799 compatible = "mediatek,mt8195-vppsys0"; 1800 reg = <0 0x14000000 0 0x1000>; 1801 #clock-cells = <1>; 1802 }; 1803 1804 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1805 compatible = "mediatek,mt8195-smi-sub-common"; 1806 reg = <0 0x14010000 0 0x1000>; 1807 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1808 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1809 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1810 clock-names = "apb", "smi", "gals0"; 1811 mediatek,smi = <&smi_common_vpp>; 1812 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1813 }; 1814 1815 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1816 compatible = "mediatek,mt8195-smi-sub-common"; 1817 reg = <0 0x14011000 0 0x1000>; 1818 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1819 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1820 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1821 clock-names = "apb", "smi", "gals0"; 1822 mediatek,smi = <&smi_common_vpp>; 1823 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1824 }; 1825 1826 smi_common_vpp: smi@14012000 { 1827 compatible = "mediatek,mt8195-smi-common-vpp"; 1828 reg = <0 0x14012000 0 0x1000>; 1829 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1830 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1831 <&vppsys0 CLK_VPP0_SMI_RSI>, 1832 <&vppsys0 CLK_VPP0_SMI_RSI>; 1833 clock-names = "apb", "smi", "gals0", "gals1"; 1834 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1835 }; 1836 1837 larb4: larb@14013000 { 1838 compatible = "mediatek,mt8195-smi-larb"; 1839 reg = <0 0x14013000 0 0x1000>; 1840 mediatek,larb-id = <4>; 1841 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1842 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1843 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1844 clock-names = "apb", "smi"; 1845 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1846 }; 1847 1848 iommu_vpp: iommu@14018000 { 1849 compatible = "mediatek,mt8195-iommu-vpp"; 1850 reg = <0 0x14018000 0 0x1000>; 1851 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1852 &larb12 &larb14 &larb16 &larb18 1853 &larb20 &larb22 &larb23 &larb26 1854 &larb27>; 1855 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1856 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1857 clock-names = "bclk"; 1858 #iommu-cells = <1>; 1859 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1860 }; 1861 1862 wpesys: clock-controller@14e00000 { 1863 compatible = "mediatek,mt8195-wpesys"; 1864 reg = <0 0x14e00000 0 0x1000>; 1865 #clock-cells = <1>; 1866 }; 1867 1868 wpesys_vpp0: clock-controller@14e02000 { 1869 compatible = "mediatek,mt8195-wpesys_vpp0"; 1870 reg = <0 0x14e02000 0 0x1000>; 1871 #clock-cells = <1>; 1872 }; 1873 1874 wpesys_vpp1: clock-controller@14e03000 { 1875 compatible = "mediatek,mt8195-wpesys_vpp1"; 1876 reg = <0 0x14e03000 0 0x1000>; 1877 #clock-cells = <1>; 1878 }; 1879 1880 larb7: larb@14e04000 { 1881 compatible = "mediatek,mt8195-smi-larb"; 1882 reg = <0 0x14e04000 0 0x1000>; 1883 mediatek,larb-id = <7>; 1884 mediatek,smi = <&smi_common_vdo>; 1885 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 1886 <&wpesys CLK_WPE_SMI_LARB7>; 1887 clock-names = "apb", "smi"; 1888 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1889 }; 1890 1891 larb8: larb@14e05000 { 1892 compatible = "mediatek,mt8195-smi-larb"; 1893 reg = <0 0x14e05000 0 0x1000>; 1894 mediatek,larb-id = <8>; 1895 mediatek,smi = <&smi_common_vpp>; 1896 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 1897 <&wpesys CLK_WPE_SMI_LARB8>, 1898 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1899 clock-names = "apb", "smi", "gals"; 1900 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1901 }; 1902 1903 vppsys1: clock-controller@14f00000 { 1904 compatible = "mediatek,mt8195-vppsys1"; 1905 reg = <0 0x14f00000 0 0x1000>; 1906 #clock-cells = <1>; 1907 }; 1908 1909 larb5: larb@14f02000 { 1910 compatible = "mediatek,mt8195-smi-larb"; 1911 reg = <0 0x14f02000 0 0x1000>; 1912 mediatek,larb-id = <5>; 1913 mediatek,smi = <&smi_common_vdo>; 1914 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1915 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1916 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 1917 clock-names = "apb", "smi", "gals"; 1918 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1919 }; 1920 1921 larb6: larb@14f03000 { 1922 compatible = "mediatek,mt8195-smi-larb"; 1923 reg = <0 0x14f03000 0 0x1000>; 1924 mediatek,larb-id = <6>; 1925 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1926 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1927 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1928 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 1929 clock-names = "apb", "smi", "gals"; 1930 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1931 }; 1932 1933 imgsys: clock-controller@15000000 { 1934 compatible = "mediatek,mt8195-imgsys"; 1935 reg = <0 0x15000000 0 0x1000>; 1936 #clock-cells = <1>; 1937 }; 1938 1939 larb9: larb@15001000 { 1940 compatible = "mediatek,mt8195-smi-larb"; 1941 reg = <0 0x15001000 0 0x1000>; 1942 mediatek,larb-id = <9>; 1943 mediatek,smi = <&smi_sub_common_img1_3x1>; 1944 clocks = <&imgsys CLK_IMG_LARB9>, 1945 <&imgsys CLK_IMG_LARB9>, 1946 <&imgsys CLK_IMG_GALS>; 1947 clock-names = "apb", "smi", "gals"; 1948 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1949 }; 1950 1951 smi_sub_common_img0_3x1: smi@15002000 { 1952 compatible = "mediatek,mt8195-smi-sub-common"; 1953 reg = <0 0x15002000 0 0x1000>; 1954 clocks = <&imgsys CLK_IMG_IPE>, 1955 <&imgsys CLK_IMG_IPE>, 1956 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1957 clock-names = "apb", "smi", "gals0"; 1958 mediatek,smi = <&smi_common_vpp>; 1959 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1960 }; 1961 1962 smi_sub_common_img1_3x1: smi@15003000 { 1963 compatible = "mediatek,mt8195-smi-sub-common"; 1964 reg = <0 0x15003000 0 0x1000>; 1965 clocks = <&imgsys CLK_IMG_LARB9>, 1966 <&imgsys CLK_IMG_LARB9>, 1967 <&imgsys CLK_IMG_GALS>; 1968 clock-names = "apb", "smi", "gals0"; 1969 mediatek,smi = <&smi_common_vdo>; 1970 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1971 }; 1972 1973 imgsys1_dip_top: clock-controller@15110000 { 1974 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1975 reg = <0 0x15110000 0 0x1000>; 1976 #clock-cells = <1>; 1977 }; 1978 1979 larb10: larb@15120000 { 1980 compatible = "mediatek,mt8195-smi-larb"; 1981 reg = <0 0x15120000 0 0x1000>; 1982 mediatek,larb-id = <10>; 1983 mediatek,smi = <&smi_sub_common_img1_3x1>; 1984 clocks = <&imgsys CLK_IMG_DIP0>, 1985 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 1986 clock-names = "apb", "smi"; 1987 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1988 }; 1989 1990 imgsys1_dip_nr: clock-controller@15130000 { 1991 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1992 reg = <0 0x15130000 0 0x1000>; 1993 #clock-cells = <1>; 1994 }; 1995 1996 imgsys1_wpe: clock-controller@15220000 { 1997 compatible = "mediatek,mt8195-imgsys1_wpe"; 1998 reg = <0 0x15220000 0 0x1000>; 1999 #clock-cells = <1>; 2000 }; 2001 2002 larb11: larb@15230000 { 2003 compatible = "mediatek,mt8195-smi-larb"; 2004 reg = <0 0x15230000 0 0x1000>; 2005 mediatek,larb-id = <11>; 2006 mediatek,smi = <&smi_sub_common_img1_3x1>; 2007 clocks = <&imgsys CLK_IMG_WPE0>, 2008 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2009 clock-names = "apb", "smi"; 2010 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2011 }; 2012 2013 ipesys: clock-controller@15330000 { 2014 compatible = "mediatek,mt8195-ipesys"; 2015 reg = <0 0x15330000 0 0x1000>; 2016 #clock-cells = <1>; 2017 }; 2018 2019 larb12: larb@15340000 { 2020 compatible = "mediatek,mt8195-smi-larb"; 2021 reg = <0 0x15340000 0 0x1000>; 2022 mediatek,larb-id = <12>; 2023 mediatek,smi = <&smi_sub_common_img0_3x1>; 2024 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2025 <&ipesys CLK_IPE_SMI_LARB12>; 2026 clock-names = "apb", "smi"; 2027 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2028 }; 2029 2030 camsys: clock-controller@16000000 { 2031 compatible = "mediatek,mt8195-camsys"; 2032 reg = <0 0x16000000 0 0x1000>; 2033 #clock-cells = <1>; 2034 }; 2035 2036 larb13: larb@16001000 { 2037 compatible = "mediatek,mt8195-smi-larb"; 2038 reg = <0 0x16001000 0 0x1000>; 2039 mediatek,larb-id = <13>; 2040 mediatek,smi = <&smi_sub_common_cam_4x1>; 2041 clocks = <&camsys CLK_CAM_LARB13>, 2042 <&camsys CLK_CAM_LARB13>, 2043 <&camsys CLK_CAM_CAM2MM0_GALS>; 2044 clock-names = "apb", "smi", "gals"; 2045 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2046 }; 2047 2048 larb14: larb@16002000 { 2049 compatible = "mediatek,mt8195-smi-larb"; 2050 reg = <0 0x16002000 0 0x1000>; 2051 mediatek,larb-id = <14>; 2052 mediatek,smi = <&smi_sub_common_cam_7x1>; 2053 clocks = <&camsys CLK_CAM_LARB14>, 2054 <&camsys CLK_CAM_LARB14>; 2055 clock-names = "apb", "smi"; 2056 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2057 }; 2058 2059 smi_sub_common_cam_4x1: smi@16004000 { 2060 compatible = "mediatek,mt8195-smi-sub-common"; 2061 reg = <0 0x16004000 0 0x1000>; 2062 clocks = <&camsys CLK_CAM_LARB13>, 2063 <&camsys CLK_CAM_LARB13>, 2064 <&camsys CLK_CAM_CAM2MM0_GALS>; 2065 clock-names = "apb", "smi", "gals0"; 2066 mediatek,smi = <&smi_common_vdo>; 2067 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2068 }; 2069 2070 smi_sub_common_cam_7x1: smi@16005000 { 2071 compatible = "mediatek,mt8195-smi-sub-common"; 2072 reg = <0 0x16005000 0 0x1000>; 2073 clocks = <&camsys CLK_CAM_LARB14>, 2074 <&camsys CLK_CAM_CAM2MM1_GALS>, 2075 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2076 clock-names = "apb", "smi", "gals0"; 2077 mediatek,smi = <&smi_common_vpp>; 2078 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2079 }; 2080 2081 larb16: larb@16012000 { 2082 compatible = "mediatek,mt8195-smi-larb"; 2083 reg = <0 0x16012000 0 0x1000>; 2084 mediatek,larb-id = <16>; 2085 mediatek,smi = <&smi_sub_common_cam_7x1>; 2086 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2087 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2088 clock-names = "apb", "smi"; 2089 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2090 }; 2091 2092 larb17: larb@16013000 { 2093 compatible = "mediatek,mt8195-smi-larb"; 2094 reg = <0 0x16013000 0 0x1000>; 2095 mediatek,larb-id = <17>; 2096 mediatek,smi = <&smi_sub_common_cam_4x1>; 2097 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2098 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2099 clock-names = "apb", "smi"; 2100 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2101 }; 2102 2103 larb27: larb@16014000 { 2104 compatible = "mediatek,mt8195-smi-larb"; 2105 reg = <0 0x16014000 0 0x1000>; 2106 mediatek,larb-id = <27>; 2107 mediatek,smi = <&smi_sub_common_cam_7x1>; 2108 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2109 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2110 clock-names = "apb", "smi"; 2111 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2112 }; 2113 2114 larb28: larb@16015000 { 2115 compatible = "mediatek,mt8195-smi-larb"; 2116 reg = <0 0x16015000 0 0x1000>; 2117 mediatek,larb-id = <28>; 2118 mediatek,smi = <&smi_sub_common_cam_4x1>; 2119 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2120 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2121 clock-names = "apb", "smi"; 2122 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2123 }; 2124 2125 camsys_rawa: clock-controller@1604f000 { 2126 compatible = "mediatek,mt8195-camsys_rawa"; 2127 reg = <0 0x1604f000 0 0x1000>; 2128 #clock-cells = <1>; 2129 }; 2130 2131 camsys_yuva: clock-controller@1606f000 { 2132 compatible = "mediatek,mt8195-camsys_yuva"; 2133 reg = <0 0x1606f000 0 0x1000>; 2134 #clock-cells = <1>; 2135 }; 2136 2137 camsys_rawb: clock-controller@1608f000 { 2138 compatible = "mediatek,mt8195-camsys_rawb"; 2139 reg = <0 0x1608f000 0 0x1000>; 2140 #clock-cells = <1>; 2141 }; 2142 2143 camsys_yuvb: clock-controller@160af000 { 2144 compatible = "mediatek,mt8195-camsys_yuvb"; 2145 reg = <0 0x160af000 0 0x1000>; 2146 #clock-cells = <1>; 2147 }; 2148 2149 camsys_mraw: clock-controller@16140000 { 2150 compatible = "mediatek,mt8195-camsys_mraw"; 2151 reg = <0 0x16140000 0 0x1000>; 2152 #clock-cells = <1>; 2153 }; 2154 2155 larb25: larb@16141000 { 2156 compatible = "mediatek,mt8195-smi-larb"; 2157 reg = <0 0x16141000 0 0x1000>; 2158 mediatek,larb-id = <25>; 2159 mediatek,smi = <&smi_sub_common_cam_4x1>; 2160 clocks = <&camsys CLK_CAM_LARB13>, 2161 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2162 <&camsys CLK_CAM_CAM2MM0_GALS>; 2163 clock-names = "apb", "smi", "gals"; 2164 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2165 }; 2166 2167 larb26: larb@16142000 { 2168 compatible = "mediatek,mt8195-smi-larb"; 2169 reg = <0 0x16142000 0 0x1000>; 2170 mediatek,larb-id = <26>; 2171 mediatek,smi = <&smi_sub_common_cam_7x1>; 2172 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2173 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2174 clock-names = "apb", "smi"; 2175 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2176 2177 }; 2178 2179 ccusys: clock-controller@17200000 { 2180 compatible = "mediatek,mt8195-ccusys"; 2181 reg = <0 0x17200000 0 0x1000>; 2182 #clock-cells = <1>; 2183 }; 2184 2185 larb18: larb@17201000 { 2186 compatible = "mediatek,mt8195-smi-larb"; 2187 reg = <0 0x17201000 0 0x1000>; 2188 mediatek,larb-id = <18>; 2189 mediatek,smi = <&smi_sub_common_cam_7x1>; 2190 clocks = <&ccusys CLK_CCU_LARB18>, 2191 <&ccusys CLK_CCU_LARB18>; 2192 clock-names = "apb", "smi"; 2193 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2194 }; 2195 2196 larb24: larb@1800d000 { 2197 compatible = "mediatek,mt8195-smi-larb"; 2198 reg = <0 0x1800d000 0 0x1000>; 2199 mediatek,larb-id = <24>; 2200 mediatek,smi = <&smi_common_vdo>; 2201 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2202 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2203 clock-names = "apb", "smi"; 2204 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2205 }; 2206 2207 larb23: larb@1800e000 { 2208 compatible = "mediatek,mt8195-smi-larb"; 2209 reg = <0 0x1800e000 0 0x1000>; 2210 mediatek,larb-id = <23>; 2211 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2212 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2213 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2214 clock-names = "apb", "smi"; 2215 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2216 }; 2217 2218 vdecsys_soc: clock-controller@1800f000 { 2219 compatible = "mediatek,mt8195-vdecsys_soc"; 2220 reg = <0 0x1800f000 0 0x1000>; 2221 #clock-cells = <1>; 2222 }; 2223 2224 larb21: larb@1802e000 { 2225 compatible = "mediatek,mt8195-smi-larb"; 2226 reg = <0 0x1802e000 0 0x1000>; 2227 mediatek,larb-id = <21>; 2228 mediatek,smi = <&smi_common_vdo>; 2229 clocks = <&vdecsys CLK_VDEC_LARB1>, 2230 <&vdecsys CLK_VDEC_LARB1>; 2231 clock-names = "apb", "smi"; 2232 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2233 }; 2234 2235 vdecsys: clock-controller@1802f000 { 2236 compatible = "mediatek,mt8195-vdecsys"; 2237 reg = <0 0x1802f000 0 0x1000>; 2238 #clock-cells = <1>; 2239 }; 2240 2241 larb22: larb@1803e000 { 2242 compatible = "mediatek,mt8195-smi-larb"; 2243 reg = <0 0x1803e000 0 0x1000>; 2244 mediatek,larb-id = <22>; 2245 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2246 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2247 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2248 clock-names = "apb", "smi"; 2249 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2250 }; 2251 2252 vdecsys_core1: clock-controller@1803f000 { 2253 compatible = "mediatek,mt8195-vdecsys_core1"; 2254 reg = <0 0x1803f000 0 0x1000>; 2255 #clock-cells = <1>; 2256 }; 2257 2258 apusys_pll: clock-controller@190f3000 { 2259 compatible = "mediatek,mt8195-apusys_pll"; 2260 reg = <0 0x190f3000 0 0x1000>; 2261 #clock-cells = <1>; 2262 }; 2263 2264 vencsys: clock-controller@1a000000 { 2265 compatible = "mediatek,mt8195-vencsys"; 2266 reg = <0 0x1a000000 0 0x1000>; 2267 #clock-cells = <1>; 2268 }; 2269 2270 larb19: larb@1a010000 { 2271 compatible = "mediatek,mt8195-smi-larb"; 2272 reg = <0 0x1a010000 0 0x1000>; 2273 mediatek,larb-id = <19>; 2274 mediatek,smi = <&smi_common_vdo>; 2275 clocks = <&vencsys CLK_VENC_VENC>, 2276 <&vencsys CLK_VENC_GALS>; 2277 clock-names = "apb", "smi"; 2278 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2279 }; 2280 2281 venc: video-codec@1a020000 { 2282 compatible = "mediatek,mt8195-vcodec-enc"; 2283 reg = <0 0x1a020000 0 0x10000>; 2284 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2285 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2286 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2287 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2288 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2289 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2290 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2291 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2292 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2293 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2294 mediatek,scp = <&scp>; 2295 clocks = <&vencsys CLK_VENC_VENC>; 2296 clock-names = "venc_sel"; 2297 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2298 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2299 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2300 #address-cells = <2>; 2301 #size-cells = <2>; 2302 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2303 }; 2304 2305 jpgdec-master { 2306 compatible = "mediatek,mt8195-jpgdec"; 2307 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2308 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2309 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2310 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2311 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2312 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2313 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2314 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2315 #address-cells = <2>; 2316 #size-cells = <2>; 2317 ranges; 2318 2319 jpgdec@1a040000 { 2320 compatible = "mediatek,mt8195-jpgdec-hw"; 2321 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2322 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2323 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2324 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2325 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2326 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2327 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2328 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2329 clocks = <&vencsys CLK_VENC_JPGDEC>; 2330 clock-names = "jpgdec"; 2331 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2332 }; 2333 2334 jpgdec@1a050000 { 2335 compatible = "mediatek,mt8195-jpgdec-hw"; 2336 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2337 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2338 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2339 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2340 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2341 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2342 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2343 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 2344 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 2345 clock-names = "jpgdec"; 2346 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2347 }; 2348 2349 jpgdec@1b040000 { 2350 compatible = "mediatek,mt8195-jpgdec-hw"; 2351 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 2352 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 2353 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 2354 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 2355 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 2356 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 2357 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 2358 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 2359 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 2360 clock-names = "jpgdec"; 2361 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2362 }; 2363 }; 2364 2365 vencsys_core1: clock-controller@1b000000 { 2366 compatible = "mediatek,mt8195-vencsys_core1"; 2367 reg = <0 0x1b000000 0 0x1000>; 2368 #clock-cells = <1>; 2369 }; 2370 2371 vdosys0: syscon@1c01a000 { 2372 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 2373 reg = <0 0x1c01a000 0 0x1000>; 2374 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2375 #clock-cells = <1>; 2376 }; 2377 2378 2379 jpgenc-master { 2380 compatible = "mediatek,mt8195-jpgenc"; 2381 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2382 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2383 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2384 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2385 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2386 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2387 #address-cells = <2>; 2388 #size-cells = <2>; 2389 ranges; 2390 2391 jpgenc@1a030000 { 2392 compatible = "mediatek,mt8195-jpgenc-hw"; 2393 reg = <0 0x1a030000 0 0x10000>; 2394 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 2395 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 2396 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 2397 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 2398 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 2399 clocks = <&vencsys CLK_VENC_JPGENC>; 2400 clock-names = "jpgenc"; 2401 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2402 }; 2403 2404 jpgenc@1b030000 { 2405 compatible = "mediatek,mt8195-jpgenc-hw"; 2406 reg = <0 0x1b030000 0 0x10000>; 2407 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2408 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2409 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2410 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2411 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 2412 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 2413 clock-names = "jpgenc"; 2414 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2415 }; 2416 }; 2417 2418 larb20: larb@1b010000 { 2419 compatible = "mediatek,mt8195-smi-larb"; 2420 reg = <0 0x1b010000 0 0x1000>; 2421 mediatek,larb-id = <20>; 2422 mediatek,smi = <&smi_common_vpp>; 2423 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2424 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2425 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2426 clock-names = "apb", "smi", "gals"; 2427 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2428 }; 2429 2430 ovl0: ovl@1c000000 { 2431 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2432 reg = <0 0x1c000000 0 0x1000>; 2433 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2434 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2435 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2436 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2437 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2438 }; 2439 2440 rdma0: rdma@1c002000 { 2441 compatible = "mediatek,mt8195-disp-rdma"; 2442 reg = <0 0x1c002000 0 0x1000>; 2443 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2444 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2445 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2446 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2447 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2448 }; 2449 2450 color0: color@1c003000 { 2451 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2452 reg = <0 0x1c003000 0 0x1000>; 2453 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2454 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2455 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2456 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2457 }; 2458 2459 ccorr0: ccorr@1c004000 { 2460 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2461 reg = <0 0x1c004000 0 0x1000>; 2462 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2463 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2464 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2465 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2466 }; 2467 2468 aal0: aal@1c005000 { 2469 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2470 reg = <0 0x1c005000 0 0x1000>; 2471 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2472 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2473 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2474 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2475 }; 2476 2477 gamma0: gamma@1c006000 { 2478 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2479 reg = <0 0x1c006000 0 0x1000>; 2480 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2481 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2482 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2483 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2484 }; 2485 2486 dither0: dither@1c007000 { 2487 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2488 reg = <0 0x1c007000 0 0x1000>; 2489 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2490 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2491 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2492 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2493 }; 2494 2495 dsc0: dsc@1c009000 { 2496 compatible = "mediatek,mt8195-disp-dsc"; 2497 reg = <0 0x1c009000 0 0x1000>; 2498 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2499 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2500 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2501 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2502 }; 2503 2504 merge0: merge@1c014000 { 2505 compatible = "mediatek,mt8195-disp-merge"; 2506 reg = <0 0x1c014000 0 0x1000>; 2507 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2508 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2509 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2510 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2511 }; 2512 2513 dp_intf0: dp-intf@1c015000 { 2514 compatible = "mediatek,mt8195-dp-intf"; 2515 reg = <0 0x1c015000 0 0x1000>; 2516 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2517 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2518 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2519 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2520 clock-names = "engine", "pixel", "pll"; 2521 status = "disabled"; 2522 }; 2523 2524 mutex: mutex@1c016000 { 2525 compatible = "mediatek,mt8195-disp-mutex"; 2526 reg = <0 0x1c016000 0 0x1000>; 2527 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2528 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2529 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2530 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2531 }; 2532 2533 larb0: larb@1c018000 { 2534 compatible = "mediatek,mt8195-smi-larb"; 2535 reg = <0 0x1c018000 0 0x1000>; 2536 mediatek,larb-id = <0>; 2537 mediatek,smi = <&smi_common_vdo>; 2538 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2539 <&vdosys0 CLK_VDO0_SMI_LARB>, 2540 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2541 clock-names = "apb", "smi", "gals"; 2542 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2543 }; 2544 2545 larb1: larb@1c019000 { 2546 compatible = "mediatek,mt8195-smi-larb"; 2547 reg = <0 0x1c019000 0 0x1000>; 2548 mediatek,larb-id = <1>; 2549 mediatek,smi = <&smi_common_vpp>; 2550 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2551 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2552 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2553 clock-names = "apb", "smi", "gals"; 2554 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2555 }; 2556 2557 vdosys1: syscon@1c100000 { 2558 compatible = "mediatek,mt8195-vdosys1", "syscon"; 2559 reg = <0 0x1c100000 0 0x1000>; 2560 #clock-cells = <1>; 2561 }; 2562 2563 smi_common_vdo: smi@1c01b000 { 2564 compatible = "mediatek,mt8195-smi-common-vdo"; 2565 reg = <0 0x1c01b000 0 0x1000>; 2566 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2567 <&vdosys0 CLK_VDO0_SMI_EMI>, 2568 <&vdosys0 CLK_VDO0_SMI_RSI>, 2569 <&vdosys0 CLK_VDO0_SMI_GALS>; 2570 clock-names = "apb", "smi", "gals0", "gals1"; 2571 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2572 2573 }; 2574 2575 iommu_vdo: iommu@1c01f000 { 2576 compatible = "mediatek,mt8195-iommu-vdo"; 2577 reg = <0 0x1c01f000 0 0x1000>; 2578 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2579 &larb10 &larb11 &larb13 &larb17 2580 &larb19 &larb21 &larb24 &larb25 2581 &larb28>; 2582 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2583 #iommu-cells = <1>; 2584 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2585 clock-names = "bclk"; 2586 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2587 }; 2588 2589 larb2: larb@1c102000 { 2590 compatible = "mediatek,mt8195-smi-larb"; 2591 reg = <0 0x1c102000 0 0x1000>; 2592 mediatek,larb-id = <2>; 2593 mediatek,smi = <&smi_common_vdo>; 2594 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2595 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2596 <&vdosys1 CLK_VDO1_GALS>; 2597 clock-names = "apb", "smi", "gals"; 2598 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2599 }; 2600 2601 larb3: larb@1c103000 { 2602 compatible = "mediatek,mt8195-smi-larb"; 2603 reg = <0 0x1c103000 0 0x1000>; 2604 mediatek,larb-id = <3>; 2605 mediatek,smi = <&smi_common_vpp>; 2606 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2607 <&vdosys1 CLK_VDO1_GALS>, 2608 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2609 clock-names = "apb", "smi", "gals"; 2610 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2611 }; 2612 2613 dp_intf1: dp-intf@1c113000 { 2614 compatible = "mediatek,mt8195-dp-intf"; 2615 reg = <0 0x1c113000 0 0x1000>; 2616 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 2617 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2618 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 2619 <&vdosys1 CLK_VDO1_DPINTF>, 2620 <&apmixedsys CLK_APMIXED_TVDPLL2>; 2621 clock-names = "engine", "pixel", "pll"; 2622 status = "disabled"; 2623 }; 2624 2625 edp_tx: edp-tx@1c500000 { 2626 compatible = "mediatek,mt8195-edp-tx"; 2627 reg = <0 0x1c500000 0 0x8000>; 2628 nvmem-cells = <&dp_calibration>; 2629 nvmem-cell-names = "dp_calibration_data"; 2630 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 2631 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 2632 max-linkrate-mhz = <8100>; 2633 status = "disabled"; 2634 }; 2635 2636 dp_tx: dp-tx@1c600000 { 2637 compatible = "mediatek,mt8195-dp-tx"; 2638 reg = <0 0x1c600000 0 0x8000>; 2639 nvmem-cells = <&dp_calibration>; 2640 nvmem-cell-names = "dp_calibration_data"; 2641 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 2642 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 2643 max-linkrate-mhz = <8100>; 2644 status = "disabled"; 2645 }; 2646 }; 2647}; 2648