1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8192-clk.h> 9#include <dt-bindings/gce/mt8192-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8192-larb-port.h> 13#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mt8192-power.h> 16#include <dt-bindings/reset/mt8192-resets.h> 17 18/ { 19 compatible = "mediatek,mt8192"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl-2l0 = &ovl_2l0; 27 ovl-2l2 = &ovl_2l2; 28 rdma0 = &rdma0; 29 rdma4 = &rdma4; 30 }; 31 32 clk13m: fixed-factor-clock-13m { 33 compatible = "fixed-factor-clock"; 34 #clock-cells = <0>; 35 clocks = <&clk26m>; 36 clock-div = <2>; 37 clock-mult = <1>; 38 clock-output-names = "clk13m"; 39 }; 40 41 clk26m: oscillator0 { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <26000000>; 45 clock-output-names = "clk26m"; 46 }; 47 48 clk32k: oscillator1 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <32768>; 52 clock-output-names = "clk32k"; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x000>; 63 enable-method = "psci"; 64 clock-frequency = <1701000000>; 65 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_0>; 73 capacity-dmips-mhz = <530>; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x100>; 80 enable-method = "psci"; 81 clock-frequency = <1701000000>; 82 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 83 i-cache-size = <32768>; 84 i-cache-line-size = <64>; 85 i-cache-sets = <128>; 86 d-cache-size = <32768>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 next-level-cache = <&l2_0>; 90 capacity-dmips-mhz = <530>; 91 }; 92 93 cpu2: cpu@200 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x200>; 97 enable-method = "psci"; 98 clock-frequency = <1701000000>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 capacity-dmips-mhz = <530>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 clock-frequency = <1701000000>; 116 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 117 i-cache-size = <32768>; 118 i-cache-line-size = <64>; 119 i-cache-sets = <128>; 120 d-cache-size = <32768>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 next-level-cache = <&l2_0>; 124 capacity-dmips-mhz = <530>; 125 }; 126 127 cpu4: cpu@400 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a76"; 130 reg = <0x400>; 131 enable-method = "psci"; 132 clock-frequency = <2171000000>; 133 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 134 i-cache-size = <65536>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; 137 d-cache-size = <65536>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <256>; 140 next-level-cache = <&l2_1>; 141 capacity-dmips-mhz = <1024>; 142 }; 143 144 cpu5: cpu@500 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a76"; 147 reg = <0x500>; 148 enable-method = "psci"; 149 clock-frequency = <2171000000>; 150 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 151 i-cache-size = <65536>; 152 i-cache-line-size = <64>; 153 i-cache-sets = <256>; 154 d-cache-size = <65536>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <256>; 157 next-level-cache = <&l2_1>; 158 capacity-dmips-mhz = <1024>; 159 }; 160 161 cpu6: cpu@600 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a76"; 164 reg = <0x600>; 165 enable-method = "psci"; 166 clock-frequency = <2171000000>; 167 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 168 i-cache-size = <65536>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <256>; 171 d-cache-size = <65536>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <256>; 174 next-level-cache = <&l2_1>; 175 capacity-dmips-mhz = <1024>; 176 }; 177 178 cpu7: cpu@700 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a76"; 181 reg = <0x700>; 182 enable-method = "psci"; 183 clock-frequency = <2171000000>; 184 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 185 i-cache-size = <65536>; 186 i-cache-line-size = <64>; 187 i-cache-sets = <256>; 188 d-cache-size = <65536>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <256>; 191 next-level-cache = <&l2_1>; 192 capacity-dmips-mhz = <1024>; 193 }; 194 195 cpu-map { 196 cluster0 { 197 core0 { 198 cpu = <&cpu0>; 199 }; 200 core1 { 201 cpu = <&cpu1>; 202 }; 203 core2 { 204 cpu = <&cpu2>; 205 }; 206 core3 { 207 cpu = <&cpu3>; 208 }; 209 core4 { 210 cpu = <&cpu4>; 211 }; 212 core5 { 213 cpu = <&cpu5>; 214 }; 215 core6 { 216 cpu = <&cpu6>; 217 }; 218 core7 { 219 cpu = <&cpu7>; 220 }; 221 }; 222 }; 223 224 l2_0: l2-cache0 { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-size = <131072>; 228 cache-line-size = <64>; 229 cache-sets = <512>; 230 next-level-cache = <&l3_0>; 231 }; 232 233 l2_1: l2-cache1 { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-size = <262144>; 237 cache-line-size = <64>; 238 cache-sets = <512>; 239 next-level-cache = <&l3_0>; 240 }; 241 242 l3_0: l3-cache { 243 compatible = "cache"; 244 cache-level = <3>; 245 cache-size = <2097152>; 246 cache-line-size = <64>; 247 cache-sets = <2048>; 248 cache-unified; 249 }; 250 251 idle-states { 252 entry-method = "psci"; 253 cpu_ret_l: cpu-retention-l { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <55>; 258 exit-latency-us = <140>; 259 min-residency-us = <780>; 260 }; 261 cpu_ret_b: cpu-retention-b { 262 compatible = "arm,idle-state"; 263 arm,psci-suspend-param = <0x00010001>; 264 local-timer-stop; 265 entry-latency-us = <35>; 266 exit-latency-us = <145>; 267 min-residency-us = <720>; 268 }; 269 cpu_off_l: cpu-off-l { 270 compatible = "arm,idle-state"; 271 arm,psci-suspend-param = <0x01010002>; 272 local-timer-stop; 273 entry-latency-us = <60>; 274 exit-latency-us = <155>; 275 min-residency-us = <860>; 276 }; 277 cpu_off_b: cpu-off-b { 278 compatible = "arm,idle-state"; 279 arm,psci-suspend-param = <0x01010002>; 280 local-timer-stop; 281 entry-latency-us = <40>; 282 exit-latency-us = <155>; 283 min-residency-us = <780>; 284 }; 285 }; 286 }; 287 288 pmu-a55 { 289 compatible = "arm,cortex-a55-pmu"; 290 interrupt-parent = <&gic>; 291 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 292 }; 293 294 pmu-a76 { 295 compatible = "arm,cortex-a76-pmu"; 296 interrupt-parent = <&gic>; 297 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 298 }; 299 300 psci { 301 compatible = "arm,psci-1.0"; 302 method = "smc"; 303 }; 304 305 timer: timer { 306 compatible = "arm,armv8-timer"; 307 interrupt-parent = <&gic>; 308 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 309 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 310 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 311 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 312 clock-frequency = <13000000>; 313 }; 314 315 gpu_opp_table: opp-table-0 { 316 compatible = "operating-points-v2"; 317 opp-shared; 318 319 opp-358000000 { 320 opp-hz = /bits/ 64 <358000000>; 321 opp-microvolt = <606250>; 322 }; 323 324 opp-399000000 { 325 opp-hz = /bits/ 64 <399000000>; 326 opp-microvolt = <618750>; 327 }; 328 329 opp-440000000 { 330 opp-hz = /bits/ 64 <440000000>; 331 opp-microvolt = <631250>; 332 }; 333 334 opp-482000000 { 335 opp-hz = /bits/ 64 <482000000>; 336 opp-microvolt = <643750>; 337 }; 338 339 opp-523000000 { 340 opp-hz = /bits/ 64 <523000000>; 341 opp-microvolt = <656250>; 342 }; 343 344 opp-564000000 { 345 opp-hz = /bits/ 64 <564000000>; 346 opp-microvolt = <668750>; 347 }; 348 349 opp-605000000 { 350 opp-hz = /bits/ 64 <605000000>; 351 opp-microvolt = <681250>; 352 }; 353 354 opp-647000000 { 355 opp-hz = /bits/ 64 <647000000>; 356 opp-microvolt = <693750>; 357 }; 358 359 opp-688000000 { 360 opp-hz = /bits/ 64 <688000000>; 361 opp-microvolt = <706250>; 362 }; 363 364 opp-724000000 { 365 opp-hz = /bits/ 64 <724000000>; 366 opp-microvolt = <725000>; 367 }; 368 369 opp-748000000 { 370 opp-hz = /bits/ 64 <748000000>; 371 opp-microvolt = <737500>; 372 }; 373 374 opp-772000000 { 375 opp-hz = /bits/ 64 <772000000>; 376 opp-microvolt = <750000>; 377 }; 378 379 opp-795000000 { 380 opp-hz = /bits/ 64 <795000000>; 381 opp-microvolt = <762500>; 382 }; 383 384 opp-819000000 { 385 opp-hz = /bits/ 64 <819000000>; 386 opp-microvolt = <775000>; 387 }; 388 389 opp-843000000 { 390 opp-hz = /bits/ 64 <843000000>; 391 opp-microvolt = <787500>; 392 }; 393 394 opp-866000000 { 395 opp-hz = /bits/ 64 <866000000>; 396 opp-microvolt = <800000>; 397 }; 398 }; 399 400 soc { 401 #address-cells = <2>; 402 #size-cells = <2>; 403 compatible = "simple-bus"; 404 ranges; 405 406 gic: interrupt-controller@c000000 { 407 compatible = "arm,gic-v3"; 408 #interrupt-cells = <4>; 409 #redistributor-regions = <1>; 410 interrupt-parent = <&gic>; 411 interrupt-controller; 412 reg = <0 0x0c000000 0 0x40000>, 413 <0 0x0c040000 0 0x200000>; 414 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 415 416 ppi-partitions { 417 ppi_cluster0: interrupt-partition-0 { 418 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 419 }; 420 ppi_cluster1: interrupt-partition-1 { 421 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 422 }; 423 }; 424 }; 425 426 topckgen: syscon@10000000 { 427 compatible = "mediatek,mt8192-topckgen", "syscon"; 428 reg = <0 0x10000000 0 0x1000>; 429 #clock-cells = <1>; 430 }; 431 432 infracfg: syscon@10001000 { 433 compatible = "mediatek,mt8192-infracfg", "syscon"; 434 reg = <0 0x10001000 0 0x1000>; 435 #clock-cells = <1>; 436 #reset-cells = <1>; 437 }; 438 439 pericfg: syscon@10003000 { 440 compatible = "mediatek,mt8192-pericfg", "syscon"; 441 reg = <0 0x10003000 0 0x1000>; 442 #clock-cells = <1>; 443 }; 444 445 pio: pinctrl@10005000 { 446 compatible = "mediatek,mt8192-pinctrl"; 447 reg = <0 0x10005000 0 0x1000>, 448 <0 0x11c20000 0 0x1000>, 449 <0 0x11d10000 0 0x1000>, 450 <0 0x11d30000 0 0x1000>, 451 <0 0x11d40000 0 0x1000>, 452 <0 0x11e20000 0 0x1000>, 453 <0 0x11e70000 0 0x1000>, 454 <0 0x11ea0000 0 0x1000>, 455 <0 0x11f20000 0 0x1000>, 456 <0 0x11f30000 0 0x1000>, 457 <0 0x1000b000 0 0x1000>; 458 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 459 "iocfg_bl", "iocfg_br", "iocfg_lm", 460 "iocfg_lb", "iocfg_rt", "iocfg_lt", 461 "iocfg_tl", "eint"; 462 gpio-controller; 463 #gpio-cells = <2>; 464 gpio-ranges = <&pio 0 0 220>; 465 interrupt-controller; 466 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 467 #interrupt-cells = <2>; 468 }; 469 470 scpsys: syscon@10006000 { 471 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 472 reg = <0 0x10006000 0 0x1000>; 473 474 /* System Power Manager */ 475 spm: power-controller { 476 compatible = "mediatek,mt8192-power-controller"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 #power-domain-cells = <1>; 480 481 /* power domain of the SoC */ 482 power-domain@MT8192_POWER_DOMAIN_AUDIO { 483 reg = <MT8192_POWER_DOMAIN_AUDIO>; 484 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 485 <&infracfg CLK_INFRA_AUDIO_26M_B>, 486 <&infracfg CLK_INFRA_AUDIO>; 487 clock-names = "audio", "audio1", "audio2"; 488 mediatek,infracfg = <&infracfg>; 489 #power-domain-cells = <0>; 490 }; 491 492 power-domain@MT8192_POWER_DOMAIN_CONN { 493 reg = <MT8192_POWER_DOMAIN_CONN>; 494 clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 495 clock-names = "conn"; 496 mediatek,infracfg = <&infracfg>; 497 #power-domain-cells = <0>; 498 }; 499 500 mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { 501 reg = <MT8192_POWER_DOMAIN_MFG0>; 502 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, 503 <&topckgen CLK_TOP_MFG_REF_SEL>; 504 clock-names = "mfg", "alt"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 #power-domain-cells = <1>; 508 509 mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { 510 reg = <MT8192_POWER_DOMAIN_MFG1>; 511 mediatek,infracfg = <&infracfg>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 #power-domain-cells = <1>; 515 516 power-domain@MT8192_POWER_DOMAIN_MFG2 { 517 reg = <MT8192_POWER_DOMAIN_MFG2>; 518 #power-domain-cells = <0>; 519 }; 520 521 power-domain@MT8192_POWER_DOMAIN_MFG3 { 522 reg = <MT8192_POWER_DOMAIN_MFG3>; 523 #power-domain-cells = <0>; 524 }; 525 526 power-domain@MT8192_POWER_DOMAIN_MFG4 { 527 reg = <MT8192_POWER_DOMAIN_MFG4>; 528 #power-domain-cells = <0>; 529 }; 530 531 power-domain@MT8192_POWER_DOMAIN_MFG5 { 532 reg = <MT8192_POWER_DOMAIN_MFG5>; 533 #power-domain-cells = <0>; 534 }; 535 536 power-domain@MT8192_POWER_DOMAIN_MFG6 { 537 reg = <MT8192_POWER_DOMAIN_MFG6>; 538 #power-domain-cells = <0>; 539 }; 540 }; 541 }; 542 543 power-domain@MT8192_POWER_DOMAIN_DISP { 544 reg = <MT8192_POWER_DOMAIN_DISP>; 545 clocks = <&topckgen CLK_TOP_DISP_SEL>, 546 <&mmsys CLK_MM_SMI_INFRA>, 547 <&mmsys CLK_MM_SMI_COMMON>, 548 <&mmsys CLK_MM_SMI_GALS>, 549 <&mmsys CLK_MM_SMI_IOMMU>; 550 clock-names = "disp", "disp-0", "disp-1", "disp-2", 551 "disp-3"; 552 mediatek,infracfg = <&infracfg>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 #power-domain-cells = <1>; 556 557 power-domain@MT8192_POWER_DOMAIN_IPE { 558 reg = <MT8192_POWER_DOMAIN_IPE>; 559 clocks = <&topckgen CLK_TOP_IPE_SEL>, 560 <&ipesys CLK_IPE_LARB19>, 561 <&ipesys CLK_IPE_LARB20>, 562 <&ipesys CLK_IPE_SMI_SUBCOM>, 563 <&ipesys CLK_IPE_GALS>; 564 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 565 "ipe-3"; 566 mediatek,infracfg = <&infracfg>; 567 #power-domain-cells = <0>; 568 }; 569 570 power-domain@MT8192_POWER_DOMAIN_ISP { 571 reg = <MT8192_POWER_DOMAIN_ISP>; 572 clocks = <&topckgen CLK_TOP_IMG1_SEL>, 573 <&imgsys CLK_IMG_LARB9>, 574 <&imgsys CLK_IMG_GALS>; 575 clock-names = "isp", "isp-0", "isp-1"; 576 mediatek,infracfg = <&infracfg>; 577 #power-domain-cells = <0>; 578 }; 579 580 power-domain@MT8192_POWER_DOMAIN_ISP2 { 581 reg = <MT8192_POWER_DOMAIN_ISP2>; 582 clocks = <&topckgen CLK_TOP_IMG2_SEL>, 583 <&imgsys2 CLK_IMG2_LARB11>, 584 <&imgsys2 CLK_IMG2_GALS>; 585 clock-names = "isp2", "isp2-0", "isp2-1"; 586 mediatek,infracfg = <&infracfg>; 587 #power-domain-cells = <0>; 588 }; 589 590 power-domain@MT8192_POWER_DOMAIN_MDP { 591 reg = <MT8192_POWER_DOMAIN_MDP>; 592 clocks = <&topckgen CLK_TOP_MDP_SEL>, 593 <&mdpsys CLK_MDP_SMI0>; 594 clock-names = "mdp", "mdp-0"; 595 mediatek,infracfg = <&infracfg>; 596 #power-domain-cells = <0>; 597 }; 598 599 power-domain@MT8192_POWER_DOMAIN_VENC { 600 reg = <MT8192_POWER_DOMAIN_VENC>; 601 clocks = <&topckgen CLK_TOP_VENC_SEL>, 602 <&vencsys CLK_VENC_SET1_VENC>; 603 clock-names = "venc", "venc-0"; 604 mediatek,infracfg = <&infracfg>; 605 #power-domain-cells = <0>; 606 }; 607 608 power-domain@MT8192_POWER_DOMAIN_VDEC { 609 reg = <MT8192_POWER_DOMAIN_VDEC>; 610 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 611 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 612 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 613 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 614 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 615 mediatek,infracfg = <&infracfg>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8192_POWER_DOMAIN_VDEC2 { 621 reg = <MT8192_POWER_DOMAIN_VDEC2>; 622 clocks = <&vdecsys CLK_VDEC_VDEC>, 623 <&vdecsys CLK_VDEC_LAT>, 624 <&vdecsys CLK_VDEC_LARB1>; 625 clock-names = "vdec2-0", "vdec2-1", 626 "vdec2-2"; 627 #power-domain-cells = <0>; 628 }; 629 }; 630 631 power-domain@MT8192_POWER_DOMAIN_CAM { 632 reg = <MT8192_POWER_DOMAIN_CAM>; 633 clocks = <&topckgen CLK_TOP_CAM_SEL>, 634 <&camsys CLK_CAM_LARB13>, 635 <&camsys CLK_CAM_LARB14>, 636 <&camsys CLK_CAM_CCU_GALS>, 637 <&camsys CLK_CAM_CAM2MM_GALS>; 638 clock-names = "cam", "cam-0", "cam-1", "cam-2", 639 "cam-3"; 640 mediatek,infracfg = <&infracfg>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 #power-domain-cells = <1>; 644 645 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 646 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 647 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 648 clock-names = "cam_rawa-0"; 649 #power-domain-cells = <0>; 650 }; 651 652 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 653 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 654 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 655 clock-names = "cam_rawb-0"; 656 #power-domain-cells = <0>; 657 }; 658 659 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 660 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 661 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 662 clock-names = "cam_rawc-0"; 663 #power-domain-cells = <0>; 664 }; 665 }; 666 }; 667 }; 668 }; 669 670 watchdog: watchdog@10007000 { 671 compatible = "mediatek,mt8192-wdt"; 672 reg = <0 0x10007000 0 0x100>; 673 #reset-cells = <1>; 674 }; 675 676 apmixedsys: syscon@1000c000 { 677 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 678 reg = <0 0x1000c000 0 0x1000>; 679 #clock-cells = <1>; 680 }; 681 682 systimer: timer@10017000 { 683 compatible = "mediatek,mt8192-timer", 684 "mediatek,mt6765-timer"; 685 reg = <0 0x10017000 0 0x1000>; 686 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 687 clocks = <&clk13m>; 688 }; 689 690 pwrap: pwrap@10026000 { 691 compatible = "mediatek,mt6873-pwrap"; 692 reg = <0 0x10026000 0 0x1000>; 693 reg-names = "pwrap"; 694 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 695 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 696 <&infracfg CLK_INFRA_PMIC_TMR>; 697 clock-names = "spi", "wrap"; 698 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 699 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 700 }; 701 702 spmi: spmi@10027000 { 703 compatible = "mediatek,mt6873-spmi"; 704 reg = <0 0x10027000 0 0x000e00>, 705 <0 0x10029000 0 0x000100>; 706 reg-names = "pmif", "spmimst"; 707 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 708 <&infracfg CLK_INFRA_PMIC_TMR>, 709 <&topckgen CLK_TOP_SPMI_MST_SEL>; 710 clock-names = "pmif_sys_ck", 711 "pmif_tmr_ck", 712 "spmimst_clk_mux"; 713 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 714 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 715 }; 716 717 gce: mailbox@10228000 { 718 compatible = "mediatek,mt8192-gce"; 719 reg = <0 0x10228000 0 0x4000>; 720 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 721 #mbox-cells = <2>; 722 clocks = <&infracfg CLK_INFRA_GCE>; 723 clock-names = "gce"; 724 }; 725 726 scp_adsp: clock-controller@10720000 { 727 compatible = "mediatek,mt8192-scp_adsp"; 728 reg = <0 0x10720000 0 0x1000>; 729 #clock-cells = <1>; 730 /* power domain dependency not upstreamed */ 731 status = "fail"; 732 }; 733 734 uart0: serial@11002000 { 735 compatible = "mediatek,mt8192-uart", 736 "mediatek,mt6577-uart"; 737 reg = <0 0x11002000 0 0x1000>; 738 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 739 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 740 clock-names = "baud", "bus"; 741 status = "disabled"; 742 }; 743 744 uart1: serial@11003000 { 745 compatible = "mediatek,mt8192-uart", 746 "mediatek,mt6577-uart"; 747 reg = <0 0x11003000 0 0x1000>; 748 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 749 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 750 clock-names = "baud", "bus"; 751 status = "disabled"; 752 }; 753 754 imp_iic_wrap_c: clock-controller@11007000 { 755 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 756 reg = <0 0x11007000 0 0x1000>; 757 #clock-cells = <1>; 758 }; 759 760 spi0: spi@1100a000 { 761 compatible = "mediatek,mt8192-spi", 762 "mediatek,mt6765-spi"; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 reg = <0 0x1100a000 0 0x1000>; 766 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 767 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 768 <&topckgen CLK_TOP_SPI_SEL>, 769 <&infracfg CLK_INFRA_SPI0>; 770 clock-names = "parent-clk", "sel-clk", "spi-clk"; 771 status = "disabled"; 772 }; 773 774 pwm0: pwm@1100e000 { 775 compatible = "mediatek,mt8183-disp-pwm"; 776 reg = <0 0x1100e000 0 0x1000>; 777 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 778 #pwm-cells = <2>; 779 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 780 <&infracfg CLK_INFRA_DISP_PWM>; 781 clock-names = "main", "mm"; 782 status = "disabled"; 783 }; 784 785 spi1: spi@11010000 { 786 compatible = "mediatek,mt8192-spi", 787 "mediatek,mt6765-spi"; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 reg = <0 0x11010000 0 0x1000>; 791 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 792 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 793 <&topckgen CLK_TOP_SPI_SEL>, 794 <&infracfg CLK_INFRA_SPI1>; 795 clock-names = "parent-clk", "sel-clk", "spi-clk"; 796 status = "disabled"; 797 }; 798 799 spi2: spi@11012000 { 800 compatible = "mediatek,mt8192-spi", 801 "mediatek,mt6765-spi"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 reg = <0 0x11012000 0 0x1000>; 805 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 806 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 807 <&topckgen CLK_TOP_SPI_SEL>, 808 <&infracfg CLK_INFRA_SPI2>; 809 clock-names = "parent-clk", "sel-clk", "spi-clk"; 810 status = "disabled"; 811 }; 812 813 spi3: spi@11013000 { 814 compatible = "mediatek,mt8192-spi", 815 "mediatek,mt6765-spi"; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 reg = <0 0x11013000 0 0x1000>; 819 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 820 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 821 <&topckgen CLK_TOP_SPI_SEL>, 822 <&infracfg CLK_INFRA_SPI3>; 823 clock-names = "parent-clk", "sel-clk", "spi-clk"; 824 status = "disabled"; 825 }; 826 827 spi4: spi@11018000 { 828 compatible = "mediatek,mt8192-spi", 829 "mediatek,mt6765-spi"; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 reg = <0 0x11018000 0 0x1000>; 833 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 834 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 835 <&topckgen CLK_TOP_SPI_SEL>, 836 <&infracfg CLK_INFRA_SPI4>; 837 clock-names = "parent-clk", "sel-clk", "spi-clk"; 838 status = "disabled"; 839 }; 840 841 spi5: spi@11019000 { 842 compatible = "mediatek,mt8192-spi", 843 "mediatek,mt6765-spi"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 reg = <0 0x11019000 0 0x1000>; 847 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 848 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 849 <&topckgen CLK_TOP_SPI_SEL>, 850 <&infracfg CLK_INFRA_SPI5>; 851 clock-names = "parent-clk", "sel-clk", "spi-clk"; 852 status = "disabled"; 853 }; 854 855 spi6: spi@1101d000 { 856 compatible = "mediatek,mt8192-spi", 857 "mediatek,mt6765-spi"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 reg = <0 0x1101d000 0 0x1000>; 861 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 862 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 863 <&topckgen CLK_TOP_SPI_SEL>, 864 <&infracfg CLK_INFRA_SPI6>; 865 clock-names = "parent-clk", "sel-clk", "spi-clk"; 866 status = "disabled"; 867 }; 868 869 spi7: spi@1101e000 { 870 compatible = "mediatek,mt8192-spi", 871 "mediatek,mt6765-spi"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 reg = <0 0x1101e000 0 0x1000>; 875 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 876 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 877 <&topckgen CLK_TOP_SPI_SEL>, 878 <&infracfg CLK_INFRA_SPI7>; 879 clock-names = "parent-clk", "sel-clk", "spi-clk"; 880 status = "disabled"; 881 }; 882 883 scp: scp@10500000 { 884 compatible = "mediatek,mt8192-scp"; 885 reg = <0 0x10500000 0 0x100000>, 886 <0 0x10720000 0 0xe0000>, 887 <0 0x10700000 0 0x8000>; 888 reg-names = "sram", "cfg", "l1tcm"; 889 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 890 clocks = <&infracfg CLK_INFRA_SCPSYS>; 891 clock-names = "main"; 892 status = "disabled"; 893 }; 894 895 xhci: usb@11200000 { 896 compatible = "mediatek,mt8192-xhci", 897 "mediatek,mtk-xhci"; 898 reg = <0 0x11200000 0 0x1000>, 899 <0 0x11203e00 0 0x0100>; 900 reg-names = "mac", "ippc"; 901 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 902 interrupt-names = "host"; 903 phys = <&u2port0 PHY_TYPE_USB2>, 904 <&u3port0 PHY_TYPE_USB3>; 905 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 906 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 907 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 908 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 909 clocks = <&infracfg CLK_INFRA_SSUSB>, 910 <&apmixedsys CLK_APMIXED_USBPLL>, 911 <&clk26m>, 912 <&clk26m>, 913 <&infracfg CLK_INFRA_SSUSB_XHCI>; 914 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 915 "xhci_ck"; 916 wakeup-source; 917 mediatek,syscon-wakeup = <&pericfg 0x420 102>; 918 status = "disabled"; 919 }; 920 921 audsys: syscon@11210000 { 922 compatible = "mediatek,mt8192-audsys", "syscon"; 923 reg = <0 0x11210000 0 0x2000>; 924 #clock-cells = <1>; 925 926 afe: mt8192-afe-pcm { 927 compatible = "mediatek,mt8192-audio"; 928 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 929 resets = <&watchdog 17>; 930 reset-names = "audiosys"; 931 mediatek,apmixedsys = <&apmixedsys>; 932 mediatek,infracfg = <&infracfg>; 933 mediatek,topckgen = <&topckgen>; 934 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 935 clocks = <&audsys CLK_AUD_AFE>, 936 <&audsys CLK_AUD_DAC>, 937 <&audsys CLK_AUD_DAC_PREDIS>, 938 <&audsys CLK_AUD_ADC>, 939 <&audsys CLK_AUD_ADDA6_ADC>, 940 <&audsys CLK_AUD_22M>, 941 <&audsys CLK_AUD_24M>, 942 <&audsys CLK_AUD_APLL_TUNER>, 943 <&audsys CLK_AUD_APLL2_TUNER>, 944 <&audsys CLK_AUD_TDM>, 945 <&audsys CLK_AUD_TML>, 946 <&audsys CLK_AUD_NLE>, 947 <&audsys CLK_AUD_DAC_HIRES>, 948 <&audsys CLK_AUD_ADC_HIRES>, 949 <&audsys CLK_AUD_ADC_HIRES_TML>, 950 <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 951 <&audsys CLK_AUD_3RD_DAC>, 952 <&audsys CLK_AUD_3RD_DAC_PREDIS>, 953 <&audsys CLK_AUD_3RD_DAC_TML>, 954 <&audsys CLK_AUD_3RD_DAC_HIRES>, 955 <&infracfg CLK_INFRA_AUDIO>, 956 <&infracfg CLK_INFRA_AUDIO_26M_B>, 957 <&topckgen CLK_TOP_AUDIO_SEL>, 958 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 959 <&topckgen CLK_TOP_MAINPLL_D4_D4>, 960 <&topckgen CLK_TOP_AUD_1_SEL>, 961 <&topckgen CLK_TOP_APLL1>, 962 <&topckgen CLK_TOP_AUD_2_SEL>, 963 <&topckgen CLK_TOP_APLL2>, 964 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 965 <&topckgen CLK_TOP_APLL1_D4>, 966 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 967 <&topckgen CLK_TOP_APLL2_D4>, 968 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 969 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 970 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 971 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 972 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 973 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 974 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 975 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 976 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 977 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 978 <&topckgen CLK_TOP_APLL12_DIV0>, 979 <&topckgen CLK_TOP_APLL12_DIV1>, 980 <&topckgen CLK_TOP_APLL12_DIV2>, 981 <&topckgen CLK_TOP_APLL12_DIV3>, 982 <&topckgen CLK_TOP_APLL12_DIV4>, 983 <&topckgen CLK_TOP_APLL12_DIVB>, 984 <&topckgen CLK_TOP_APLL12_DIV5>, 985 <&topckgen CLK_TOP_APLL12_DIV6>, 986 <&topckgen CLK_TOP_APLL12_DIV7>, 987 <&topckgen CLK_TOP_APLL12_DIV8>, 988 <&topckgen CLK_TOP_APLL12_DIV9>, 989 <&topckgen CLK_TOP_AUDIO_H_SEL>, 990 <&clk26m>; 991 clock-names = "aud_afe_clk", 992 "aud_dac_clk", 993 "aud_dac_predis_clk", 994 "aud_adc_clk", 995 "aud_adda6_adc_clk", 996 "aud_apll22m_clk", 997 "aud_apll24m_clk", 998 "aud_apll1_tuner_clk", 999 "aud_apll2_tuner_clk", 1000 "aud_tdm_clk", 1001 "aud_tml_clk", 1002 "aud_nle", 1003 "aud_dac_hires_clk", 1004 "aud_adc_hires_clk", 1005 "aud_adc_hires_tml", 1006 "aud_adda6_adc_hires_clk", 1007 "aud_3rd_dac_clk", 1008 "aud_3rd_dac_predis_clk", 1009 "aud_3rd_dac_tml", 1010 "aud_3rd_dac_hires_clk", 1011 "aud_infra_clk", 1012 "aud_infra_26m_clk", 1013 "top_mux_audio", 1014 "top_mux_audio_int", 1015 "top_mainpll_d4_d4", 1016 "top_mux_aud_1", 1017 "top_apll1_ck", 1018 "top_mux_aud_2", 1019 "top_apll2_ck", 1020 "top_mux_aud_eng1", 1021 "top_apll1_d4", 1022 "top_mux_aud_eng2", 1023 "top_apll2_d4", 1024 "top_i2s0_m_sel", 1025 "top_i2s1_m_sel", 1026 "top_i2s2_m_sel", 1027 "top_i2s3_m_sel", 1028 "top_i2s4_m_sel", 1029 "top_i2s5_m_sel", 1030 "top_i2s6_m_sel", 1031 "top_i2s7_m_sel", 1032 "top_i2s8_m_sel", 1033 "top_i2s9_m_sel", 1034 "top_apll12_div0", 1035 "top_apll12_div1", 1036 "top_apll12_div2", 1037 "top_apll12_div3", 1038 "top_apll12_div4", 1039 "top_apll12_divb", 1040 "top_apll12_div5", 1041 "top_apll12_div6", 1042 "top_apll12_div7", 1043 "top_apll12_div8", 1044 "top_apll12_div9", 1045 "top_mux_audio_h", 1046 "top_clk26m_clk"; 1047 }; 1048 }; 1049 1050 pcie: pcie@11230000 { 1051 compatible = "mediatek,mt8192-pcie"; 1052 device_type = "pci"; 1053 reg = <0 0x11230000 0 0x2000>; 1054 reg-names = "pcie-mac"; 1055 #address-cells = <3>; 1056 #size-cells = <2>; 1057 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 1058 <&infracfg CLK_INFRA_PCIE_TL_26M>, 1059 <&infracfg CLK_INFRA_PCIE_TL_96M>, 1060 <&infracfg CLK_INFRA_PCIE_TL_32K>, 1061 <&infracfg CLK_INFRA_PCIE_PERI_26M>, 1062 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 1063 clock-names = "pl_250m", "tl_26m", "tl_96m", 1064 "tl_32k", "peri_26m", "top_133m"; 1065 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 1066 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 1067 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 1068 bus-range = <0x00 0xff>; 1069 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 1070 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 1071 #interrupt-cells = <1>; 1072 interrupt-map-mask = <0 0 0 7>; 1073 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1074 <0 0 0 2 &pcie_intc0 1>, 1075 <0 0 0 3 &pcie_intc0 2>, 1076 <0 0 0 4 &pcie_intc0 3>; 1077 1078 pcie_intc0: interrupt-controller { 1079 interrupt-controller; 1080 #address-cells = <0>; 1081 #interrupt-cells = <1>; 1082 }; 1083 }; 1084 1085 nor_flash: spi@11234000 { 1086 compatible = "mediatek,mt8192-nor"; 1087 reg = <0 0x11234000 0 0xe0>; 1088 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 1089 clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 1090 <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 1091 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 1092 clock-names = "spi", "sf", "axi"; 1093 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 1094 assigned-clock-parents = <&clk26m>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 efuse: efuse@11c10000 { 1101 compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 1102 reg = <0 0x11c10000 0 0x1000>; 1103 #address-cells = <1>; 1104 #size-cells = <1>; 1105 1106 lvts_e_data1: data1@1c0 { 1107 reg = <0x1c0 0x58>; 1108 }; 1109 1110 svs_calibration: calib@580 { 1111 reg = <0x580 0x68>; 1112 }; 1113 }; 1114 1115 i2c3: i2c@11cb0000 { 1116 compatible = "mediatek,mt8192-i2c"; 1117 reg = <0 0x11cb0000 0 0x1000>, 1118 <0 0x10217300 0 0x80>; 1119 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1120 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 1121 <&infracfg CLK_INFRA_AP_DMA>; 1122 clock-names = "main", "dma"; 1123 clock-div = <1>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 imp_iic_wrap_e: clock-controller@11cb1000 { 1130 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 1131 reg = <0 0x11cb1000 0 0x1000>; 1132 #clock-cells = <1>; 1133 }; 1134 1135 i2c7: i2c@11d00000 { 1136 compatible = "mediatek,mt8192-i2c"; 1137 reg = <0 0x11d00000 0 0x1000>, 1138 <0 0x10217600 0 0x180>; 1139 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1140 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1141 <&infracfg CLK_INFRA_AP_DMA>; 1142 clock-names = "main", "dma"; 1143 clock-div = <1>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 i2c8: i2c@11d01000 { 1150 compatible = "mediatek,mt8192-i2c"; 1151 reg = <0 0x11d01000 0 0x1000>, 1152 <0 0x10217780 0 0x180>; 1153 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1154 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 1155 <&infracfg CLK_INFRA_AP_DMA>; 1156 clock-names = "main", "dma"; 1157 clock-div = <1>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 i2c9: i2c@11d02000 { 1164 compatible = "mediatek,mt8192-i2c"; 1165 reg = <0 0x11d02000 0 0x1000>, 1166 <0 0x10217900 0 0x180>; 1167 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1168 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 1169 <&infracfg CLK_INFRA_AP_DMA>; 1170 clock-names = "main", "dma"; 1171 clock-div = <1>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 imp_iic_wrap_s: clock-controller@11d03000 { 1178 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 1179 reg = <0 0x11d03000 0 0x1000>; 1180 #clock-cells = <1>; 1181 }; 1182 1183 i2c1: i2c@11d20000 { 1184 compatible = "mediatek,mt8192-i2c"; 1185 reg = <0 0x11d20000 0 0x1000>, 1186 <0 0x10217100 0 0x80>; 1187 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1188 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 1189 <&infracfg CLK_INFRA_AP_DMA>; 1190 clock-names = "main", "dma"; 1191 clock-div = <1>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 i2c2: i2c@11d21000 { 1198 compatible = "mediatek,mt8192-i2c"; 1199 reg = <0 0x11d21000 0 0x1000>, 1200 <0 0x10217180 0 0x180>; 1201 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 1202 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 1203 <&infracfg CLK_INFRA_AP_DMA>; 1204 clock-names = "main", "dma"; 1205 clock-div = <1>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c4: i2c@11d22000 { 1212 compatible = "mediatek,mt8192-i2c"; 1213 reg = <0 0x11d22000 0 0x1000>, 1214 <0 0x10217380 0 0x180>; 1215 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1216 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 1217 <&infracfg CLK_INFRA_AP_DMA>; 1218 clock-names = "main", "dma"; 1219 clock-div = <1>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 imp_iic_wrap_ws: clock-controller@11d23000 { 1226 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 1227 reg = <0 0x11d23000 0 0x1000>; 1228 #clock-cells = <1>; 1229 }; 1230 1231 i2c5: i2c@11e00000 { 1232 compatible = "mediatek,mt8192-i2c"; 1233 reg = <0 0x11e00000 0 0x1000>, 1234 <0 0x10217500 0 0x80>; 1235 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1236 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 1237 <&infracfg CLK_INFRA_AP_DMA>; 1238 clock-names = "main", "dma"; 1239 clock-div = <1>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 imp_iic_wrap_w: clock-controller@11e01000 { 1246 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 1247 reg = <0 0x11e01000 0 0x1000>; 1248 #clock-cells = <1>; 1249 }; 1250 1251 u3phy0: t-phy@11e40000 { 1252 compatible = "mediatek,mt8192-tphy", 1253 "mediatek,generic-tphy-v2"; 1254 #address-cells = <1>; 1255 #size-cells = <1>; 1256 ranges = <0x0 0x0 0x11e40000 0x1000>; 1257 1258 u2port0: usb-phy@0 { 1259 reg = <0x0 0x700>; 1260 clocks = <&clk26m>; 1261 clock-names = "ref"; 1262 #phy-cells = <1>; 1263 }; 1264 1265 u3port0: usb-phy@700 { 1266 reg = <0x700 0x900>; 1267 clocks = <&clk26m>; 1268 clock-names = "ref"; 1269 #phy-cells = <1>; 1270 }; 1271 }; 1272 1273 mipi_tx0: dsi-phy@11e50000 { 1274 compatible = "mediatek,mt8183-mipi-tx"; 1275 reg = <0 0x11e50000 0 0x1000>; 1276 clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 1277 #clock-cells = <0>; 1278 #phy-cells = <0>; 1279 clock-output-names = "mipi_tx0_pll"; 1280 status = "disabled"; 1281 }; 1282 1283 i2c0: i2c@11f00000 { 1284 compatible = "mediatek,mt8192-i2c"; 1285 reg = <0 0x11f00000 0 0x1000>, 1286 <0 0x10217080 0 0x80>; 1287 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1288 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 1289 <&infracfg CLK_INFRA_AP_DMA>; 1290 clock-names = "main", "dma"; 1291 clock-div = <1>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 status = "disabled"; 1295 }; 1296 1297 i2c6: i2c@11f01000 { 1298 compatible = "mediatek,mt8192-i2c"; 1299 reg = <0 0x11f01000 0 0x1000>, 1300 <0 0x10217580 0 0x80>; 1301 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1302 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 1303 <&infracfg CLK_INFRA_AP_DMA>; 1304 clock-names = "main", "dma"; 1305 clock-div = <1>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 1311 imp_iic_wrap_n: clock-controller@11f02000 { 1312 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 1313 reg = <0 0x11f02000 0 0x1000>; 1314 #clock-cells = <1>; 1315 }; 1316 1317 msdc_top: clock-controller@11f10000 { 1318 compatible = "mediatek,mt8192-msdc_top"; 1319 reg = <0 0x11f10000 0 0x1000>; 1320 #clock-cells = <1>; 1321 }; 1322 1323 mmc0: mmc@11f60000 { 1324 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1325 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1326 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1327 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1328 <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1329 <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1330 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1331 <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1332 <&msdc_top CLK_MSDC_TOP_AXI>, 1333 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1334 clock-names = "source", "hclk", "source_cg", "sys_cg", 1335 "pclk_cg", "axi_cg", "ahb_cg"; 1336 status = "disabled"; 1337 }; 1338 1339 mmc1: mmc@11f70000 { 1340 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1341 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1342 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1343 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1344 <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1345 <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1346 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1347 <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1348 <&msdc_top CLK_MSDC_TOP_AXI>, 1349 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1350 clock-names = "source", "hclk", "source_cg", "sys_cg", 1351 "pclk_cg", "axi_cg", "ahb_cg"; 1352 status = "disabled"; 1353 }; 1354 1355 gpu: gpu@13000000 { 1356 compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm"; 1357 reg = <0 0x13000000 0 0x4000>; 1358 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, 1359 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, 1360 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1361 interrupt-names = "job", "mmu", "gpu"; 1362 1363 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 1364 1365 power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>, 1366 <&spm MT8192_POWER_DOMAIN_MFG3>, 1367 <&spm MT8192_POWER_DOMAIN_MFG4>, 1368 <&spm MT8192_POWER_DOMAIN_MFG5>, 1369 <&spm MT8192_POWER_DOMAIN_MFG6>; 1370 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1371 1372 operating-points-v2 = <&gpu_opp_table>; 1373 1374 status = "disabled"; 1375 }; 1376 1377 mfgcfg: clock-controller@13fbf000 { 1378 compatible = "mediatek,mt8192-mfgcfg"; 1379 reg = <0 0x13fbf000 0 0x1000>; 1380 #clock-cells = <1>; 1381 }; 1382 1383 mmsys: syscon@14000000 { 1384 compatible = "mediatek,mt8192-mmsys", "syscon"; 1385 reg = <0 0x14000000 0 0x1000>; 1386 #clock-cells = <1>; 1387 #reset-cells = <1>; 1388 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1389 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1390 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1391 }; 1392 1393 mutex: mutex@14001000 { 1394 compatible = "mediatek,mt8192-disp-mutex"; 1395 reg = <0 0x14001000 0 0x1000>; 1396 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1397 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1398 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1399 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1400 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1401 }; 1402 1403 smi_common: smi@14002000 { 1404 compatible = "mediatek,mt8192-smi-common"; 1405 reg = <0 0x14002000 0 0x1000>; 1406 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1407 <&mmsys CLK_MM_SMI_INFRA>, 1408 <&mmsys CLK_MM_SMI_GALS>, 1409 <&mmsys CLK_MM_SMI_GALS>; 1410 clock-names = "apb", "smi", "gals0", "gals1"; 1411 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1412 }; 1413 1414 larb0: larb@14003000 { 1415 compatible = "mediatek,mt8192-smi-larb"; 1416 reg = <0 0x14003000 0 0x1000>; 1417 mediatek,larb-id = <0>; 1418 mediatek,smi = <&smi_common>; 1419 clocks = <&clk26m>, <&clk26m>; 1420 clock-names = "apb", "smi"; 1421 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1422 }; 1423 1424 larb1: larb@14004000 { 1425 compatible = "mediatek,mt8192-smi-larb"; 1426 reg = <0 0x14004000 0 0x1000>; 1427 mediatek,larb-id = <1>; 1428 mediatek,smi = <&smi_common>; 1429 clocks = <&clk26m>, <&clk26m>; 1430 clock-names = "apb", "smi"; 1431 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1432 }; 1433 1434 ovl0: ovl@14005000 { 1435 compatible = "mediatek,mt8192-disp-ovl"; 1436 reg = <0 0x14005000 0 0x1000>; 1437 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1438 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1439 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1440 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1441 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1442 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1443 }; 1444 1445 ovl_2l0: ovl@14006000 { 1446 compatible = "mediatek,mt8192-disp-ovl-2l"; 1447 reg = <0 0x14006000 0 0x1000>; 1448 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1449 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1450 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1451 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1452 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1453 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1454 }; 1455 1456 rdma0: rdma@14007000 { 1457 compatible = "mediatek,mt8192-disp-rdma", 1458 "mediatek,mt8183-disp-rdma"; 1459 reg = <0 0x14007000 0 0x1000>; 1460 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1461 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1462 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1463 mediatek,rdma-fifo-size = <5120>; 1464 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1465 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1466 }; 1467 1468 color0: color@14009000 { 1469 compatible = "mediatek,mt8192-disp-color", 1470 "mediatek,mt8173-disp-color"; 1471 reg = <0 0x14009000 0 0x1000>; 1472 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1473 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1474 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1475 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1476 }; 1477 1478 ccorr0: ccorr@1400a000 { 1479 compatible = "mediatek,mt8192-disp-ccorr"; 1480 reg = <0 0x1400a000 0 0x1000>; 1481 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1482 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1483 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1484 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1485 }; 1486 1487 aal0: aal@1400b000 { 1488 compatible = "mediatek,mt8192-disp-aal", 1489 "mediatek,mt8183-disp-aal"; 1490 reg = <0 0x1400b000 0 0x1000>; 1491 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1492 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1493 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1494 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1495 }; 1496 1497 gamma0: gamma@1400c000 { 1498 compatible = "mediatek,mt8192-disp-gamma", 1499 "mediatek,mt8183-disp-gamma"; 1500 reg = <0 0x1400c000 0 0x1000>; 1501 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1502 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1503 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1504 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1505 }; 1506 1507 postmask0: postmask@1400d000 { 1508 compatible = "mediatek,mt8192-disp-postmask"; 1509 reg = <0 0x1400d000 0 0x1000>; 1510 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1511 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1512 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1513 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1514 }; 1515 1516 dither0: dither@1400e000 { 1517 compatible = "mediatek,mt8192-disp-dither", 1518 "mediatek,mt8183-disp-dither"; 1519 reg = <0 0x1400e000 0 0x1000>; 1520 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1521 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1522 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1523 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1524 }; 1525 1526 dsi0: dsi@14010000 { 1527 compatible = "mediatek,mt8183-dsi"; 1528 reg = <0 0x14010000 0 0x1000>; 1529 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1530 clocks = <&mmsys CLK_MM_DSI0>, 1531 <&mmsys CLK_MM_DSI_DSI0>, 1532 <&mipi_tx0>; 1533 clock-names = "engine", "digital", "hs"; 1534 phys = <&mipi_tx0>; 1535 phy-names = "dphy"; 1536 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1537 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 1538 status = "disabled"; 1539 1540 port { 1541 dsi_out: endpoint { }; 1542 }; 1543 }; 1544 1545 ovl_2l2: ovl@14014000 { 1546 compatible = "mediatek,mt8192-disp-ovl-2l"; 1547 reg = <0 0x14014000 0 0x1000>; 1548 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1549 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1550 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1551 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1552 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1553 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1554 }; 1555 1556 rdma4: rdma@14015000 { 1557 compatible = "mediatek,mt8192-disp-rdma", 1558 "mediatek,mt8183-disp-rdma"; 1559 reg = <0 0x14015000 0 0x1000>; 1560 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1561 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1562 clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1563 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1564 mediatek,rdma-fifo-size = <2048>; 1565 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1566 }; 1567 1568 dpi0: dpi@14016000 { 1569 compatible = "mediatek,mt8192-dpi"; 1570 reg = <0 0x14016000 0 0x1000>; 1571 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1572 clocks = <&mmsys CLK_MM_DPI_DPI0>, 1573 <&mmsys CLK_MM_DISP_DPI0>, 1574 <&apmixedsys CLK_APMIXED_TVDPLL>; 1575 clock-names = "pixel", "engine", "pll"; 1576 status = "disabled"; 1577 }; 1578 1579 iommu0: m4u@1401d000 { 1580 compatible = "mediatek,mt8192-m4u"; 1581 reg = <0 0x1401d000 0 0x1000>; 1582 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 1583 <&larb4>, <&larb5>, <&larb7>, 1584 <&larb9>, <&larb11>, <&larb13>, 1585 <&larb14>, <&larb16>, <&larb17>, 1586 <&larb18>, <&larb19>, <&larb20>; 1587 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1588 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1589 clock-names = "bclk"; 1590 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1591 #iommu-cells = <1>; 1592 }; 1593 1594 imgsys: clock-controller@15020000 { 1595 compatible = "mediatek,mt8192-imgsys"; 1596 reg = <0 0x15020000 0 0x1000>; 1597 #clock-cells = <1>; 1598 }; 1599 1600 larb9: larb@1502e000 { 1601 compatible = "mediatek,mt8192-smi-larb"; 1602 reg = <0 0x1502e000 0 0x1000>; 1603 mediatek,larb-id = <9>; 1604 mediatek,smi = <&smi_common>; 1605 clocks = <&imgsys CLK_IMG_LARB9>, 1606 <&imgsys CLK_IMG_LARB9>; 1607 clock-names = "apb", "smi"; 1608 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 1609 }; 1610 1611 imgsys2: clock-controller@15820000 { 1612 compatible = "mediatek,mt8192-imgsys2"; 1613 reg = <0 0x15820000 0 0x1000>; 1614 #clock-cells = <1>; 1615 }; 1616 1617 larb11: larb@1582e000 { 1618 compatible = "mediatek,mt8192-smi-larb"; 1619 reg = <0 0x1582e000 0 0x1000>; 1620 mediatek,larb-id = <11>; 1621 mediatek,smi = <&smi_common>; 1622 clocks = <&imgsys2 CLK_IMG2_LARB11>, 1623 <&imgsys2 CLK_IMG2_LARB11>; 1624 clock-names = "apb", "smi"; 1625 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 1626 }; 1627 1628 larb5: larb@1600d000 { 1629 compatible = "mediatek,mt8192-smi-larb"; 1630 reg = <0 0x1600d000 0 0x1000>; 1631 mediatek,larb-id = <5>; 1632 mediatek,smi = <&smi_common>; 1633 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1634 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1635 clock-names = "apb", "smi"; 1636 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1637 }; 1638 1639 vdecsys_soc: clock-controller@1600f000 { 1640 compatible = "mediatek,mt8192-vdecsys_soc"; 1641 reg = <0 0x1600f000 0 0x1000>; 1642 #clock-cells = <1>; 1643 }; 1644 1645 larb4: larb@1602e000 { 1646 compatible = "mediatek,mt8192-smi-larb"; 1647 reg = <0 0x1602e000 0 0x1000>; 1648 mediatek,larb-id = <4>; 1649 mediatek,smi = <&smi_common>; 1650 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 1651 <&vdecsys CLK_VDEC_SOC_LARB1>; 1652 clock-names = "apb", "smi"; 1653 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1654 }; 1655 1656 vdecsys: clock-controller@1602f000 { 1657 compatible = "mediatek,mt8192-vdecsys"; 1658 reg = <0 0x1602f000 0 0x1000>; 1659 #clock-cells = <1>; 1660 }; 1661 1662 vencsys: clock-controller@17000000 { 1663 compatible = "mediatek,mt8192-vencsys"; 1664 reg = <0 0x17000000 0 0x1000>; 1665 #clock-cells = <1>; 1666 }; 1667 1668 larb7: larb@17010000 { 1669 compatible = "mediatek,mt8192-smi-larb"; 1670 reg = <0 0x17010000 0 0x1000>; 1671 mediatek,larb-id = <7>; 1672 mediatek,smi = <&smi_common>; 1673 clocks = <&vencsys CLK_VENC_SET0_LARB>, 1674 <&vencsys CLK_VENC_SET1_VENC>; 1675 clock-names = "apb", "smi"; 1676 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1677 }; 1678 1679 vcodec_enc: vcodec@17020000 { 1680 compatible = "mediatek,mt8192-vcodec-enc"; 1681 reg = <0 0x17020000 0 0x2000>; 1682 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1683 <&iommu0 M4U_PORT_L7_VENC_REC>, 1684 <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1685 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1686 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1687 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1688 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1689 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1690 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1691 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1692 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1693 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1694 mediatek,scp = <&scp>; 1695 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1696 clocks = <&vencsys CLK_VENC_SET1_VENC>; 1697 clock-names = "venc-set1"; 1698 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1699 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1700 }; 1701 1702 camsys: clock-controller@1a000000 { 1703 compatible = "mediatek,mt8192-camsys"; 1704 reg = <0 0x1a000000 0 0x1000>; 1705 #clock-cells = <1>; 1706 }; 1707 1708 larb13: larb@1a001000 { 1709 compatible = "mediatek,mt8192-smi-larb"; 1710 reg = <0 0x1a001000 0 0x1000>; 1711 mediatek,larb-id = <13>; 1712 mediatek,smi = <&smi_common>; 1713 clocks = <&camsys CLK_CAM_CAM>, 1714 <&camsys CLK_CAM_LARB13>; 1715 clock-names = "apb", "smi"; 1716 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1717 }; 1718 1719 larb14: larb@1a002000 { 1720 compatible = "mediatek,mt8192-smi-larb"; 1721 reg = <0 0x1a002000 0 0x1000>; 1722 mediatek,larb-id = <14>; 1723 mediatek,smi = <&smi_common>; 1724 clocks = <&camsys CLK_CAM_CAM>, 1725 <&camsys CLK_CAM_LARB14>; 1726 clock-names = "apb", "smi"; 1727 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1728 }; 1729 1730 larb16: larb@1a00f000 { 1731 compatible = "mediatek,mt8192-smi-larb"; 1732 reg = <0 0x1a00f000 0 0x1000>; 1733 mediatek,larb-id = <16>; 1734 mediatek,smi = <&smi_common>; 1735 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 1736 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1737 clock-names = "apb", "smi"; 1738 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 1739 }; 1740 1741 larb17: larb@1a010000 { 1742 compatible = "mediatek,mt8192-smi-larb"; 1743 reg = <0 0x1a010000 0 0x1000>; 1744 mediatek,larb-id = <17>; 1745 mediatek,smi = <&smi_common>; 1746 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 1747 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1748 clock-names = "apb", "smi"; 1749 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 1750 }; 1751 1752 larb18: larb@1a011000 { 1753 compatible = "mediatek,mt8192-smi-larb"; 1754 reg = <0 0x1a011000 0 0x1000>; 1755 mediatek,larb-id = <18>; 1756 mediatek,smi = <&smi_common>; 1757 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 1758 <&camsys_rawc CLK_CAM_RAWC_CAM>; 1759 clock-names = "apb", "smi"; 1760 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 1761 }; 1762 1763 camsys_rawa: clock-controller@1a04f000 { 1764 compatible = "mediatek,mt8192-camsys_rawa"; 1765 reg = <0 0x1a04f000 0 0x1000>; 1766 #clock-cells = <1>; 1767 }; 1768 1769 camsys_rawb: clock-controller@1a06f000 { 1770 compatible = "mediatek,mt8192-camsys_rawb"; 1771 reg = <0 0x1a06f000 0 0x1000>; 1772 #clock-cells = <1>; 1773 }; 1774 1775 camsys_rawc: clock-controller@1a08f000 { 1776 compatible = "mediatek,mt8192-camsys_rawc"; 1777 reg = <0 0x1a08f000 0 0x1000>; 1778 #clock-cells = <1>; 1779 }; 1780 1781 ipesys: clock-controller@1b000000 { 1782 compatible = "mediatek,mt8192-ipesys"; 1783 reg = <0 0x1b000000 0 0x1000>; 1784 #clock-cells = <1>; 1785 }; 1786 1787 larb20: larb@1b00f000 { 1788 compatible = "mediatek,mt8192-smi-larb"; 1789 reg = <0 0x1b00f000 0 0x1000>; 1790 mediatek,larb-id = <20>; 1791 mediatek,smi = <&smi_common>; 1792 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1793 <&ipesys CLK_IPE_LARB20>; 1794 clock-names = "apb", "smi"; 1795 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1796 }; 1797 1798 larb19: larb@1b10f000 { 1799 compatible = "mediatek,mt8192-smi-larb"; 1800 reg = <0 0x1b10f000 0 0x1000>; 1801 mediatek,larb-id = <19>; 1802 mediatek,smi = <&smi_common>; 1803 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1804 <&ipesys CLK_IPE_LARB19>; 1805 clock-names = "apb", "smi"; 1806 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1807 }; 1808 1809 mdpsys: clock-controller@1f000000 { 1810 compatible = "mediatek,mt8192-mdpsys"; 1811 reg = <0 0x1f000000 0 0x1000>; 1812 #clock-cells = <1>; 1813 }; 1814 1815 larb2: larb@1f002000 { 1816 compatible = "mediatek,mt8192-smi-larb"; 1817 reg = <0 0x1f002000 0 0x1000>; 1818 mediatek,larb-id = <2>; 1819 mediatek,smi = <&smi_common>; 1820 clocks = <&mdpsys CLK_MDP_SMI0>, 1821 <&mdpsys CLK_MDP_SMI0>; 1822 clock-names = "apb", "smi"; 1823 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 1824 }; 1825 }; 1826}; 1827