1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8192-clk.h> 9#include <dt-bindings/gce/mt8192-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8192-larb-port.h> 13#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mt8192-power.h> 16#include <dt-bindings/reset/mt8192-resets.h> 17 18/ { 19 compatible = "mediatek,mt8192"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl-2l0 = &ovl_2l0; 27 ovl-2l2 = &ovl_2l2; 28 rdma0 = &rdma0; 29 rdma4 = &rdma4; 30 }; 31 32 clk13m: fixed-factor-clock-13m { 33 compatible = "fixed-factor-clock"; 34 #clock-cells = <0>; 35 clocks = <&clk26m>; 36 clock-div = <2>; 37 clock-mult = <1>; 38 clock-output-names = "clk13m"; 39 }; 40 41 clk26m: oscillator0 { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <26000000>; 45 clock-output-names = "clk26m"; 46 }; 47 48 clk32k: oscillator1 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <32768>; 52 clock-output-names = "clk32k"; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x000>; 63 enable-method = "psci"; 64 clock-frequency = <1701000000>; 65 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_0>; 73 performance-domains = <&performance 0>; 74 capacity-dmips-mhz = <427>; 75 }; 76 77 cpu1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x100>; 81 enable-method = "psci"; 82 clock-frequency = <1701000000>; 83 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 84 i-cache-size = <32768>; 85 i-cache-line-size = <64>; 86 i-cache-sets = <128>; 87 d-cache-size = <32768>; 88 d-cache-line-size = <64>; 89 d-cache-sets = <128>; 90 next-level-cache = <&l2_0>; 91 performance-domains = <&performance 0>; 92 capacity-dmips-mhz = <427>; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a55"; 98 reg = <0x200>; 99 enable-method = "psci"; 100 clock-frequency = <1701000000>; 101 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 102 i-cache-size = <32768>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <128>; 105 d-cache-size = <32768>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <128>; 108 next-level-cache = <&l2_0>; 109 performance-domains = <&performance 0>; 110 capacity-dmips-mhz = <427>; 111 }; 112 113 cpu3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a55"; 116 reg = <0x300>; 117 enable-method = "psci"; 118 clock-frequency = <1701000000>; 119 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_0>; 127 performance-domains = <&performance 0>; 128 capacity-dmips-mhz = <427>; 129 }; 130 131 cpu4: cpu@400 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a76"; 134 reg = <0x400>; 135 enable-method = "psci"; 136 clock-frequency = <2171000000>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 performance-domains = <&performance 1>; 146 capacity-dmips-mhz = <1024>; 147 }; 148 149 cpu5: cpu@500 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a76"; 152 reg = <0x500>; 153 enable-method = "psci"; 154 clock-frequency = <2171000000>; 155 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 156 i-cache-size = <65536>; 157 i-cache-line-size = <64>; 158 i-cache-sets = <256>; 159 d-cache-size = <65536>; 160 d-cache-line-size = <64>; 161 d-cache-sets = <256>; 162 next-level-cache = <&l2_1>; 163 performance-domains = <&performance 1>; 164 capacity-dmips-mhz = <1024>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a76"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 clock-frequency = <2171000000>; 173 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 174 i-cache-size = <65536>; 175 i-cache-line-size = <64>; 176 i-cache-sets = <256>; 177 d-cache-size = <65536>; 178 d-cache-line-size = <64>; 179 d-cache-sets = <256>; 180 next-level-cache = <&l2_1>; 181 performance-domains = <&performance 1>; 182 capacity-dmips-mhz = <1024>; 183 }; 184 185 cpu7: cpu@700 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a76"; 188 reg = <0x700>; 189 enable-method = "psci"; 190 clock-frequency = <2171000000>; 191 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 192 i-cache-size = <65536>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <65536>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&l2_1>; 199 performance-domains = <&performance 1>; 200 capacity-dmips-mhz = <1024>; 201 }; 202 203 cpu-map { 204 cluster0 { 205 core0 { 206 cpu = <&cpu0>; 207 }; 208 core1 { 209 cpu = <&cpu1>; 210 }; 211 core2 { 212 cpu = <&cpu2>; 213 }; 214 core3 { 215 cpu = <&cpu3>; 216 }; 217 core4 { 218 cpu = <&cpu4>; 219 }; 220 core5 { 221 cpu = <&cpu5>; 222 }; 223 core6 { 224 cpu = <&cpu6>; 225 }; 226 core7 { 227 cpu = <&cpu7>; 228 }; 229 }; 230 }; 231 232 l2_0: l2-cache0 { 233 compatible = "cache"; 234 cache-level = <2>; 235 cache-size = <131072>; 236 cache-line-size = <64>; 237 cache-sets = <512>; 238 next-level-cache = <&l3_0>; 239 cache-unified; 240 }; 241 242 l2_1: l2-cache1 { 243 compatible = "cache"; 244 cache-level = <2>; 245 cache-size = <262144>; 246 cache-line-size = <64>; 247 cache-sets = <512>; 248 next-level-cache = <&l3_0>; 249 cache-unified; 250 }; 251 252 l3_0: l3-cache { 253 compatible = "cache"; 254 cache-level = <3>; 255 cache-size = <2097152>; 256 cache-line-size = <64>; 257 cache-sets = <2048>; 258 cache-unified; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 cpu_ret_l: cpu-retention-l { 264 compatible = "arm,idle-state"; 265 arm,psci-suspend-param = <0x00010001>; 266 local-timer-stop; 267 entry-latency-us = <55>; 268 exit-latency-us = <140>; 269 min-residency-us = <780>; 270 }; 271 cpu_ret_b: cpu-retention-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x00010001>; 274 local-timer-stop; 275 entry-latency-us = <35>; 276 exit-latency-us = <145>; 277 min-residency-us = <720>; 278 }; 279 cpu_off_l: cpu-off-l { 280 compatible = "arm,idle-state"; 281 arm,psci-suspend-param = <0x01010002>; 282 local-timer-stop; 283 entry-latency-us = <60>; 284 exit-latency-us = <155>; 285 min-residency-us = <860>; 286 }; 287 cpu_off_b: cpu-off-b { 288 compatible = "arm,idle-state"; 289 arm,psci-suspend-param = <0x01010002>; 290 local-timer-stop; 291 entry-latency-us = <40>; 292 exit-latency-us = <155>; 293 min-residency-us = <780>; 294 }; 295 }; 296 }; 297 298 pmu-a55 { 299 compatible = "arm,cortex-a55-pmu"; 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 302 }; 303 304 pmu-a76 { 305 compatible = "arm,cortex-a76-pmu"; 306 interrupt-parent = <&gic>; 307 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 308 }; 309 310 psci { 311 compatible = "arm,psci-1.0"; 312 method = "smc"; 313 }; 314 315 timer: timer { 316 compatible = "arm,armv8-timer"; 317 interrupt-parent = <&gic>; 318 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 319 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 320 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 321 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 322 clock-frequency = <13000000>; 323 }; 324 325 gpu_opp_table: opp-table-0 { 326 compatible = "operating-points-v2"; 327 opp-shared; 328 329 opp-358000000 { 330 opp-hz = /bits/ 64 <358000000>; 331 opp-microvolt = <606250>; 332 }; 333 334 opp-399000000 { 335 opp-hz = /bits/ 64 <399000000>; 336 opp-microvolt = <618750>; 337 }; 338 339 opp-440000000 { 340 opp-hz = /bits/ 64 <440000000>; 341 opp-microvolt = <631250>; 342 }; 343 344 opp-482000000 { 345 opp-hz = /bits/ 64 <482000000>; 346 opp-microvolt = <643750>; 347 }; 348 349 opp-523000000 { 350 opp-hz = /bits/ 64 <523000000>; 351 opp-microvolt = <656250>; 352 }; 353 354 opp-564000000 { 355 opp-hz = /bits/ 64 <564000000>; 356 opp-microvolt = <668750>; 357 }; 358 359 opp-605000000 { 360 opp-hz = /bits/ 64 <605000000>; 361 opp-microvolt = <681250>; 362 }; 363 364 opp-647000000 { 365 opp-hz = /bits/ 64 <647000000>; 366 opp-microvolt = <693750>; 367 }; 368 369 opp-688000000 { 370 opp-hz = /bits/ 64 <688000000>; 371 opp-microvolt = <706250>; 372 }; 373 374 opp-724000000 { 375 opp-hz = /bits/ 64 <724000000>; 376 opp-microvolt = <725000>; 377 }; 378 379 opp-748000000 { 380 opp-hz = /bits/ 64 <748000000>; 381 opp-microvolt = <737500>; 382 }; 383 384 opp-772000000 { 385 opp-hz = /bits/ 64 <772000000>; 386 opp-microvolt = <750000>; 387 }; 388 389 opp-795000000 { 390 opp-hz = /bits/ 64 <795000000>; 391 opp-microvolt = <762500>; 392 }; 393 394 opp-819000000 { 395 opp-hz = /bits/ 64 <819000000>; 396 opp-microvolt = <775000>; 397 }; 398 399 opp-843000000 { 400 opp-hz = /bits/ 64 <843000000>; 401 opp-microvolt = <787500>; 402 }; 403 404 opp-866000000 { 405 opp-hz = /bits/ 64 <866000000>; 406 opp-microvolt = <800000>; 407 }; 408 }; 409 410 soc { 411 #address-cells = <2>; 412 #size-cells = <2>; 413 compatible = "simple-bus"; 414 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 415 ranges; 416 417 performance: performance-controller@11bc10 { 418 compatible = "mediatek,cpufreq-hw"; 419 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 420 #performance-domain-cells = <1>; 421 }; 422 423 gic: interrupt-controller@c000000 { 424 compatible = "arm,gic-v3"; 425 #interrupt-cells = <4>; 426 #redistributor-regions = <1>; 427 interrupt-parent = <&gic>; 428 interrupt-controller; 429 reg = <0 0x0c000000 0 0x40000>, 430 <0 0x0c040000 0 0x200000>; 431 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 432 433 ppi-partitions { 434 ppi_cluster0: interrupt-partition-0 { 435 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 436 }; 437 ppi_cluster1: interrupt-partition-1 { 438 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 439 }; 440 }; 441 }; 442 443 topckgen: syscon@10000000 { 444 compatible = "mediatek,mt8192-topckgen", "syscon"; 445 reg = <0 0x10000000 0 0x1000>; 446 #clock-cells = <1>; 447 }; 448 449 infracfg: syscon@10001000 { 450 compatible = "mediatek,mt8192-infracfg", "syscon"; 451 reg = <0 0x10001000 0 0x1000>; 452 #clock-cells = <1>; 453 #reset-cells = <1>; 454 }; 455 456 pericfg: syscon@10003000 { 457 compatible = "mediatek,mt8192-pericfg", "syscon"; 458 reg = <0 0x10003000 0 0x1000>; 459 #clock-cells = <1>; 460 }; 461 462 pio: pinctrl@10005000 { 463 compatible = "mediatek,mt8192-pinctrl"; 464 reg = <0 0x10005000 0 0x1000>, 465 <0 0x11c20000 0 0x1000>, 466 <0 0x11d10000 0 0x1000>, 467 <0 0x11d30000 0 0x1000>, 468 <0 0x11d40000 0 0x1000>, 469 <0 0x11e20000 0 0x1000>, 470 <0 0x11e70000 0 0x1000>, 471 <0 0x11ea0000 0 0x1000>, 472 <0 0x11f20000 0 0x1000>, 473 <0 0x11f30000 0 0x1000>, 474 <0 0x1000b000 0 0x1000>; 475 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 476 "iocfg_bl", "iocfg_br", "iocfg_lm", 477 "iocfg_lb", "iocfg_rt", "iocfg_lt", 478 "iocfg_tl", "eint"; 479 gpio-controller; 480 #gpio-cells = <2>; 481 gpio-ranges = <&pio 0 0 220>; 482 interrupt-controller; 483 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 484 #interrupt-cells = <2>; 485 }; 486 487 scpsys: syscon@10006000 { 488 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 489 reg = <0 0x10006000 0 0x1000>; 490 491 /* System Power Manager */ 492 spm: power-controller { 493 compatible = "mediatek,mt8192-power-controller"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 #power-domain-cells = <1>; 497 498 /* power domain of the SoC */ 499 power-domain@MT8192_POWER_DOMAIN_AUDIO { 500 reg = <MT8192_POWER_DOMAIN_AUDIO>; 501 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 502 <&infracfg CLK_INFRA_AUDIO_26M_B>, 503 <&infracfg CLK_INFRA_AUDIO>; 504 clock-names = "audio", "audio1", "audio2"; 505 mediatek,infracfg = <&infracfg>; 506 #power-domain-cells = <0>; 507 }; 508 509 power-domain@MT8192_POWER_DOMAIN_CONN { 510 reg = <MT8192_POWER_DOMAIN_CONN>; 511 clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 512 clock-names = "conn"; 513 mediatek,infracfg = <&infracfg>; 514 #power-domain-cells = <0>; 515 }; 516 517 mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { 518 reg = <MT8192_POWER_DOMAIN_MFG0>; 519 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, 520 <&topckgen CLK_TOP_MFG_REF_SEL>; 521 clock-names = "mfg", "alt"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 #power-domain-cells = <1>; 525 526 mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { 527 reg = <MT8192_POWER_DOMAIN_MFG1>; 528 mediatek,infracfg = <&infracfg>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 #power-domain-cells = <1>; 532 533 power-domain@MT8192_POWER_DOMAIN_MFG2 { 534 reg = <MT8192_POWER_DOMAIN_MFG2>; 535 #power-domain-cells = <0>; 536 }; 537 538 power-domain@MT8192_POWER_DOMAIN_MFG3 { 539 reg = <MT8192_POWER_DOMAIN_MFG3>; 540 #power-domain-cells = <0>; 541 }; 542 543 power-domain@MT8192_POWER_DOMAIN_MFG4 { 544 reg = <MT8192_POWER_DOMAIN_MFG4>; 545 #power-domain-cells = <0>; 546 }; 547 548 power-domain@MT8192_POWER_DOMAIN_MFG5 { 549 reg = <MT8192_POWER_DOMAIN_MFG5>; 550 #power-domain-cells = <0>; 551 }; 552 553 power-domain@MT8192_POWER_DOMAIN_MFG6 { 554 reg = <MT8192_POWER_DOMAIN_MFG6>; 555 #power-domain-cells = <0>; 556 }; 557 }; 558 }; 559 560 power-domain@MT8192_POWER_DOMAIN_DISP { 561 reg = <MT8192_POWER_DOMAIN_DISP>; 562 clocks = <&topckgen CLK_TOP_DISP_SEL>, 563 <&mmsys CLK_MM_SMI_INFRA>, 564 <&mmsys CLK_MM_SMI_COMMON>, 565 <&mmsys CLK_MM_SMI_GALS>, 566 <&mmsys CLK_MM_SMI_IOMMU>; 567 clock-names = "disp", "disp-0", "disp-1", "disp-2", 568 "disp-3"; 569 mediatek,infracfg = <&infracfg>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 #power-domain-cells = <1>; 573 574 power-domain@MT8192_POWER_DOMAIN_IPE { 575 reg = <MT8192_POWER_DOMAIN_IPE>; 576 clocks = <&topckgen CLK_TOP_IPE_SEL>, 577 <&ipesys CLK_IPE_LARB19>, 578 <&ipesys CLK_IPE_LARB20>, 579 <&ipesys CLK_IPE_SMI_SUBCOM>, 580 <&ipesys CLK_IPE_GALS>; 581 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 582 "ipe-3"; 583 mediatek,infracfg = <&infracfg>; 584 #power-domain-cells = <0>; 585 }; 586 587 power-domain@MT8192_POWER_DOMAIN_ISP { 588 reg = <MT8192_POWER_DOMAIN_ISP>; 589 clocks = <&topckgen CLK_TOP_IMG1_SEL>, 590 <&imgsys CLK_IMG_LARB9>, 591 <&imgsys CLK_IMG_GALS>; 592 clock-names = "isp", "isp-0", "isp-1"; 593 mediatek,infracfg = <&infracfg>; 594 #power-domain-cells = <0>; 595 }; 596 597 power-domain@MT8192_POWER_DOMAIN_ISP2 { 598 reg = <MT8192_POWER_DOMAIN_ISP2>; 599 clocks = <&topckgen CLK_TOP_IMG2_SEL>, 600 <&imgsys2 CLK_IMG2_LARB11>, 601 <&imgsys2 CLK_IMG2_GALS>; 602 clock-names = "isp2", "isp2-0", "isp2-1"; 603 mediatek,infracfg = <&infracfg>; 604 #power-domain-cells = <0>; 605 }; 606 607 power-domain@MT8192_POWER_DOMAIN_MDP { 608 reg = <MT8192_POWER_DOMAIN_MDP>; 609 clocks = <&topckgen CLK_TOP_MDP_SEL>, 610 <&mdpsys CLK_MDP_SMI0>; 611 clock-names = "mdp", "mdp-0"; 612 mediatek,infracfg = <&infracfg>; 613 #power-domain-cells = <0>; 614 }; 615 616 power-domain@MT8192_POWER_DOMAIN_VENC { 617 reg = <MT8192_POWER_DOMAIN_VENC>; 618 clocks = <&topckgen CLK_TOP_VENC_SEL>, 619 <&vencsys CLK_VENC_SET1_VENC>; 620 clock-names = "venc", "venc-0"; 621 mediatek,infracfg = <&infracfg>; 622 #power-domain-cells = <0>; 623 }; 624 625 power-domain@MT8192_POWER_DOMAIN_VDEC { 626 reg = <MT8192_POWER_DOMAIN_VDEC>; 627 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 628 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 629 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 630 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 631 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 632 mediatek,infracfg = <&infracfg>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 #power-domain-cells = <1>; 636 637 power-domain@MT8192_POWER_DOMAIN_VDEC2 { 638 reg = <MT8192_POWER_DOMAIN_VDEC2>; 639 clocks = <&vdecsys CLK_VDEC_VDEC>, 640 <&vdecsys CLK_VDEC_LAT>, 641 <&vdecsys CLK_VDEC_LARB1>; 642 clock-names = "vdec2-0", "vdec2-1", 643 "vdec2-2"; 644 #power-domain-cells = <0>; 645 }; 646 }; 647 648 power-domain@MT8192_POWER_DOMAIN_CAM { 649 reg = <MT8192_POWER_DOMAIN_CAM>; 650 clocks = <&topckgen CLK_TOP_CAM_SEL>, 651 <&camsys CLK_CAM_LARB13>, 652 <&camsys CLK_CAM_LARB14>, 653 <&camsys CLK_CAM_CCU_GALS>, 654 <&camsys CLK_CAM_CAM2MM_GALS>; 655 clock-names = "cam", "cam-0", "cam-1", "cam-2", 656 "cam-3"; 657 mediatek,infracfg = <&infracfg>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 #power-domain-cells = <1>; 661 662 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 663 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 664 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 665 clock-names = "cam_rawa-0"; 666 #power-domain-cells = <0>; 667 }; 668 669 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 670 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 671 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 672 clock-names = "cam_rawb-0"; 673 #power-domain-cells = <0>; 674 }; 675 676 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 677 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 678 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 679 clock-names = "cam_rawc-0"; 680 #power-domain-cells = <0>; 681 }; 682 }; 683 }; 684 }; 685 }; 686 687 watchdog: watchdog@10007000 { 688 compatible = "mediatek,mt8192-wdt"; 689 reg = <0 0x10007000 0 0x100>; 690 #reset-cells = <1>; 691 }; 692 693 apmixedsys: syscon@1000c000 { 694 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 695 reg = <0 0x1000c000 0 0x1000>; 696 #clock-cells = <1>; 697 }; 698 699 systimer: timer@10017000 { 700 compatible = "mediatek,mt8192-timer", 701 "mediatek,mt6765-timer"; 702 reg = <0 0x10017000 0 0x1000>; 703 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 704 clocks = <&clk13m>; 705 }; 706 707 pwrap: pwrap@10026000 { 708 compatible = "mediatek,mt6873-pwrap"; 709 reg = <0 0x10026000 0 0x1000>; 710 reg-names = "pwrap"; 711 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 712 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 713 <&infracfg CLK_INFRA_PMIC_TMR>; 714 clock-names = "spi", "wrap"; 715 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 716 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 717 }; 718 719 spmi: spmi@10027000 { 720 compatible = "mediatek,mt6873-spmi"; 721 reg = <0 0x10027000 0 0x000e00>, 722 <0 0x10029000 0 0x000100>; 723 reg-names = "pmif", "spmimst"; 724 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 725 <&infracfg CLK_INFRA_PMIC_TMR>, 726 <&topckgen CLK_TOP_SPMI_MST_SEL>; 727 clock-names = "pmif_sys_ck", 728 "pmif_tmr_ck", 729 "spmimst_clk_mux"; 730 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 731 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 732 }; 733 734 gce: mailbox@10228000 { 735 compatible = "mediatek,mt8192-gce"; 736 reg = <0 0x10228000 0 0x4000>; 737 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 738 #mbox-cells = <2>; 739 clocks = <&infracfg CLK_INFRA_GCE>; 740 clock-names = "gce"; 741 }; 742 743 scp_adsp: clock-controller@10720000 { 744 compatible = "mediatek,mt8192-scp_adsp"; 745 reg = <0 0x10720000 0 0x1000>; 746 #clock-cells = <1>; 747 /* power domain dependency not upstreamed */ 748 status = "fail"; 749 }; 750 751 uart0: serial@11002000 { 752 compatible = "mediatek,mt8192-uart", 753 "mediatek,mt6577-uart"; 754 reg = <0 0x11002000 0 0x1000>; 755 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 756 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 757 clock-names = "baud", "bus"; 758 status = "disabled"; 759 }; 760 761 uart1: serial@11003000 { 762 compatible = "mediatek,mt8192-uart", 763 "mediatek,mt6577-uart"; 764 reg = <0 0x11003000 0 0x1000>; 765 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 766 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 767 clock-names = "baud", "bus"; 768 status = "disabled"; 769 }; 770 771 imp_iic_wrap_c: clock-controller@11007000 { 772 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 773 reg = <0 0x11007000 0 0x1000>; 774 #clock-cells = <1>; 775 }; 776 777 spi0: spi@1100a000 { 778 compatible = "mediatek,mt8192-spi", 779 "mediatek,mt6765-spi"; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 reg = <0 0x1100a000 0 0x1000>; 783 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 784 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 785 <&topckgen CLK_TOP_SPI_SEL>, 786 <&infracfg CLK_INFRA_SPI0>; 787 clock-names = "parent-clk", "sel-clk", "spi-clk"; 788 status = "disabled"; 789 }; 790 791 pwm0: pwm@1100e000 { 792 compatible = "mediatek,mt8183-disp-pwm"; 793 reg = <0 0x1100e000 0 0x1000>; 794 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 795 #pwm-cells = <2>; 796 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 797 <&infracfg CLK_INFRA_DISP_PWM>; 798 clock-names = "main", "mm"; 799 status = "disabled"; 800 }; 801 802 spi1: spi@11010000 { 803 compatible = "mediatek,mt8192-spi", 804 "mediatek,mt6765-spi"; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 reg = <0 0x11010000 0 0x1000>; 808 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 809 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 810 <&topckgen CLK_TOP_SPI_SEL>, 811 <&infracfg CLK_INFRA_SPI1>; 812 clock-names = "parent-clk", "sel-clk", "spi-clk"; 813 status = "disabled"; 814 }; 815 816 spi2: spi@11012000 { 817 compatible = "mediatek,mt8192-spi", 818 "mediatek,mt6765-spi"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 reg = <0 0x11012000 0 0x1000>; 822 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 823 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 824 <&topckgen CLK_TOP_SPI_SEL>, 825 <&infracfg CLK_INFRA_SPI2>; 826 clock-names = "parent-clk", "sel-clk", "spi-clk"; 827 status = "disabled"; 828 }; 829 830 spi3: spi@11013000 { 831 compatible = "mediatek,mt8192-spi", 832 "mediatek,mt6765-spi"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 reg = <0 0x11013000 0 0x1000>; 836 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 837 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 838 <&topckgen CLK_TOP_SPI_SEL>, 839 <&infracfg CLK_INFRA_SPI3>; 840 clock-names = "parent-clk", "sel-clk", "spi-clk"; 841 status = "disabled"; 842 }; 843 844 spi4: spi@11018000 { 845 compatible = "mediatek,mt8192-spi", 846 "mediatek,mt6765-spi"; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 reg = <0 0x11018000 0 0x1000>; 850 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 851 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 852 <&topckgen CLK_TOP_SPI_SEL>, 853 <&infracfg CLK_INFRA_SPI4>; 854 clock-names = "parent-clk", "sel-clk", "spi-clk"; 855 status = "disabled"; 856 }; 857 858 spi5: spi@11019000 { 859 compatible = "mediatek,mt8192-spi", 860 "mediatek,mt6765-spi"; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 reg = <0 0x11019000 0 0x1000>; 864 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 865 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 866 <&topckgen CLK_TOP_SPI_SEL>, 867 <&infracfg CLK_INFRA_SPI5>; 868 clock-names = "parent-clk", "sel-clk", "spi-clk"; 869 status = "disabled"; 870 }; 871 872 spi6: spi@1101d000 { 873 compatible = "mediatek,mt8192-spi", 874 "mediatek,mt6765-spi"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 reg = <0 0x1101d000 0 0x1000>; 878 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 879 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 880 <&topckgen CLK_TOP_SPI_SEL>, 881 <&infracfg CLK_INFRA_SPI6>; 882 clock-names = "parent-clk", "sel-clk", "spi-clk"; 883 status = "disabled"; 884 }; 885 886 spi7: spi@1101e000 { 887 compatible = "mediatek,mt8192-spi", 888 "mediatek,mt6765-spi"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 reg = <0 0x1101e000 0 0x1000>; 892 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 893 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 894 <&topckgen CLK_TOP_SPI_SEL>, 895 <&infracfg CLK_INFRA_SPI7>; 896 clock-names = "parent-clk", "sel-clk", "spi-clk"; 897 status = "disabled"; 898 }; 899 900 scp: scp@10500000 { 901 compatible = "mediatek,mt8192-scp"; 902 reg = <0 0x10500000 0 0x100000>, 903 <0 0x10720000 0 0xe0000>, 904 <0 0x10700000 0 0x8000>; 905 reg-names = "sram", "cfg", "l1tcm"; 906 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 907 clocks = <&infracfg CLK_INFRA_SCPSYS>; 908 clock-names = "main"; 909 status = "disabled"; 910 }; 911 912 xhci: usb@11200000 { 913 compatible = "mediatek,mt8192-xhci", 914 "mediatek,mtk-xhci"; 915 reg = <0 0x11200000 0 0x1000>, 916 <0 0x11203e00 0 0x0100>; 917 reg-names = "mac", "ippc"; 918 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 919 interrupt-names = "host"; 920 phys = <&u2port0 PHY_TYPE_USB2>, 921 <&u3port0 PHY_TYPE_USB3>; 922 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 923 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 924 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 925 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 926 clocks = <&infracfg CLK_INFRA_SSUSB>, 927 <&apmixedsys CLK_APMIXED_USBPLL>, 928 <&clk26m>, 929 <&clk26m>, 930 <&infracfg CLK_INFRA_SSUSB_XHCI>; 931 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 932 "xhci_ck"; 933 wakeup-source; 934 mediatek,syscon-wakeup = <&pericfg 0x420 102>; 935 status = "disabled"; 936 }; 937 938 audsys: syscon@11210000 { 939 compatible = "mediatek,mt8192-audsys", "syscon"; 940 reg = <0 0x11210000 0 0x2000>; 941 #clock-cells = <1>; 942 943 afe: mt8192-afe-pcm { 944 compatible = "mediatek,mt8192-audio"; 945 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 946 resets = <&watchdog 17>; 947 reset-names = "audiosys"; 948 mediatek,apmixedsys = <&apmixedsys>; 949 mediatek,infracfg = <&infracfg>; 950 mediatek,topckgen = <&topckgen>; 951 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 952 clocks = <&audsys CLK_AUD_AFE>, 953 <&audsys CLK_AUD_DAC>, 954 <&audsys CLK_AUD_DAC_PREDIS>, 955 <&audsys CLK_AUD_ADC>, 956 <&audsys CLK_AUD_ADDA6_ADC>, 957 <&audsys CLK_AUD_22M>, 958 <&audsys CLK_AUD_24M>, 959 <&audsys CLK_AUD_APLL_TUNER>, 960 <&audsys CLK_AUD_APLL2_TUNER>, 961 <&audsys CLK_AUD_TDM>, 962 <&audsys CLK_AUD_TML>, 963 <&audsys CLK_AUD_NLE>, 964 <&audsys CLK_AUD_DAC_HIRES>, 965 <&audsys CLK_AUD_ADC_HIRES>, 966 <&audsys CLK_AUD_ADC_HIRES_TML>, 967 <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 968 <&audsys CLK_AUD_3RD_DAC>, 969 <&audsys CLK_AUD_3RD_DAC_PREDIS>, 970 <&audsys CLK_AUD_3RD_DAC_TML>, 971 <&audsys CLK_AUD_3RD_DAC_HIRES>, 972 <&infracfg CLK_INFRA_AUDIO>, 973 <&infracfg CLK_INFRA_AUDIO_26M_B>, 974 <&topckgen CLK_TOP_AUDIO_SEL>, 975 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 976 <&topckgen CLK_TOP_MAINPLL_D4_D4>, 977 <&topckgen CLK_TOP_AUD_1_SEL>, 978 <&topckgen CLK_TOP_APLL1>, 979 <&topckgen CLK_TOP_AUD_2_SEL>, 980 <&topckgen CLK_TOP_APLL2>, 981 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 982 <&topckgen CLK_TOP_APLL1_D4>, 983 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 984 <&topckgen CLK_TOP_APLL2_D4>, 985 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 986 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 987 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 988 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 989 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 990 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 991 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 992 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 993 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 994 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 995 <&topckgen CLK_TOP_APLL12_DIV0>, 996 <&topckgen CLK_TOP_APLL12_DIV1>, 997 <&topckgen CLK_TOP_APLL12_DIV2>, 998 <&topckgen CLK_TOP_APLL12_DIV3>, 999 <&topckgen CLK_TOP_APLL12_DIV4>, 1000 <&topckgen CLK_TOP_APLL12_DIVB>, 1001 <&topckgen CLK_TOP_APLL12_DIV5>, 1002 <&topckgen CLK_TOP_APLL12_DIV6>, 1003 <&topckgen CLK_TOP_APLL12_DIV7>, 1004 <&topckgen CLK_TOP_APLL12_DIV8>, 1005 <&topckgen CLK_TOP_APLL12_DIV9>, 1006 <&topckgen CLK_TOP_AUDIO_H_SEL>, 1007 <&clk26m>; 1008 clock-names = "aud_afe_clk", 1009 "aud_dac_clk", 1010 "aud_dac_predis_clk", 1011 "aud_adc_clk", 1012 "aud_adda6_adc_clk", 1013 "aud_apll22m_clk", 1014 "aud_apll24m_clk", 1015 "aud_apll1_tuner_clk", 1016 "aud_apll2_tuner_clk", 1017 "aud_tdm_clk", 1018 "aud_tml_clk", 1019 "aud_nle", 1020 "aud_dac_hires_clk", 1021 "aud_adc_hires_clk", 1022 "aud_adc_hires_tml", 1023 "aud_adda6_adc_hires_clk", 1024 "aud_3rd_dac_clk", 1025 "aud_3rd_dac_predis_clk", 1026 "aud_3rd_dac_tml", 1027 "aud_3rd_dac_hires_clk", 1028 "aud_infra_clk", 1029 "aud_infra_26m_clk", 1030 "top_mux_audio", 1031 "top_mux_audio_int", 1032 "top_mainpll_d4_d4", 1033 "top_mux_aud_1", 1034 "top_apll1_ck", 1035 "top_mux_aud_2", 1036 "top_apll2_ck", 1037 "top_mux_aud_eng1", 1038 "top_apll1_d4", 1039 "top_mux_aud_eng2", 1040 "top_apll2_d4", 1041 "top_i2s0_m_sel", 1042 "top_i2s1_m_sel", 1043 "top_i2s2_m_sel", 1044 "top_i2s3_m_sel", 1045 "top_i2s4_m_sel", 1046 "top_i2s5_m_sel", 1047 "top_i2s6_m_sel", 1048 "top_i2s7_m_sel", 1049 "top_i2s8_m_sel", 1050 "top_i2s9_m_sel", 1051 "top_apll12_div0", 1052 "top_apll12_div1", 1053 "top_apll12_div2", 1054 "top_apll12_div3", 1055 "top_apll12_div4", 1056 "top_apll12_divb", 1057 "top_apll12_div5", 1058 "top_apll12_div6", 1059 "top_apll12_div7", 1060 "top_apll12_div8", 1061 "top_apll12_div9", 1062 "top_mux_audio_h", 1063 "top_clk26m_clk"; 1064 }; 1065 }; 1066 1067 pcie: pcie@11230000 { 1068 compatible = "mediatek,mt8192-pcie"; 1069 device_type = "pci"; 1070 reg = <0 0x11230000 0 0x2000>; 1071 reg-names = "pcie-mac"; 1072 #address-cells = <3>; 1073 #size-cells = <2>; 1074 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 1075 <&infracfg CLK_INFRA_PCIE_TL_26M>, 1076 <&infracfg CLK_INFRA_PCIE_TL_96M>, 1077 <&infracfg CLK_INFRA_PCIE_TL_32K>, 1078 <&infracfg CLK_INFRA_PCIE_PERI_26M>, 1079 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 1080 clock-names = "pl_250m", "tl_26m", "tl_96m", 1081 "tl_32k", "peri_26m", "top_133m"; 1082 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 1083 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 1084 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 1085 bus-range = <0x00 0xff>; 1086 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 1087 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 1088 #interrupt-cells = <1>; 1089 interrupt-map-mask = <0 0 0 7>; 1090 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1091 <0 0 0 2 &pcie_intc0 1>, 1092 <0 0 0 3 &pcie_intc0 2>, 1093 <0 0 0 4 &pcie_intc0 3>; 1094 1095 pcie_intc0: interrupt-controller { 1096 interrupt-controller; 1097 #address-cells = <0>; 1098 #interrupt-cells = <1>; 1099 }; 1100 }; 1101 1102 nor_flash: spi@11234000 { 1103 compatible = "mediatek,mt8192-nor"; 1104 reg = <0 0x11234000 0 0xe0>; 1105 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 1106 clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 1107 <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 1108 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 1109 clock-names = "spi", "sf", "axi"; 1110 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 1111 assigned-clock-parents = <&clk26m>; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 efuse: efuse@11c10000 { 1118 compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 1119 reg = <0 0x11c10000 0 0x1000>; 1120 #address-cells = <1>; 1121 #size-cells = <1>; 1122 1123 lvts_e_data1: data1@1c0 { 1124 reg = <0x1c0 0x58>; 1125 }; 1126 1127 svs_calibration: calib@580 { 1128 reg = <0x580 0x68>; 1129 }; 1130 }; 1131 1132 i2c3: i2c@11cb0000 { 1133 compatible = "mediatek,mt8192-i2c"; 1134 reg = <0 0x11cb0000 0 0x1000>, 1135 <0 0x10217300 0 0x80>; 1136 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1137 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 1138 <&infracfg CLK_INFRA_AP_DMA>; 1139 clock-names = "main", "dma"; 1140 clock-div = <1>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 imp_iic_wrap_e: clock-controller@11cb1000 { 1147 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 1148 reg = <0 0x11cb1000 0 0x1000>; 1149 #clock-cells = <1>; 1150 }; 1151 1152 i2c7: i2c@11d00000 { 1153 compatible = "mediatek,mt8192-i2c"; 1154 reg = <0 0x11d00000 0 0x1000>, 1155 <0 0x10217600 0 0x180>; 1156 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1157 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1158 <&infracfg CLK_INFRA_AP_DMA>; 1159 clock-names = "main", "dma"; 1160 clock-div = <1>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 status = "disabled"; 1164 }; 1165 1166 i2c8: i2c@11d01000 { 1167 compatible = "mediatek,mt8192-i2c"; 1168 reg = <0 0x11d01000 0 0x1000>, 1169 <0 0x10217780 0 0x180>; 1170 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1171 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 1172 <&infracfg CLK_INFRA_AP_DMA>; 1173 clock-names = "main", "dma"; 1174 clock-div = <1>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 i2c9: i2c@11d02000 { 1181 compatible = "mediatek,mt8192-i2c"; 1182 reg = <0 0x11d02000 0 0x1000>, 1183 <0 0x10217900 0 0x180>; 1184 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1185 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 1186 <&infracfg CLK_INFRA_AP_DMA>; 1187 clock-names = "main", "dma"; 1188 clock-div = <1>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 status = "disabled"; 1192 }; 1193 1194 imp_iic_wrap_s: clock-controller@11d03000 { 1195 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 1196 reg = <0 0x11d03000 0 0x1000>; 1197 #clock-cells = <1>; 1198 }; 1199 1200 i2c1: i2c@11d20000 { 1201 compatible = "mediatek,mt8192-i2c"; 1202 reg = <0 0x11d20000 0 0x1000>, 1203 <0 0x10217100 0 0x80>; 1204 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 1206 <&infracfg CLK_INFRA_AP_DMA>; 1207 clock-names = "main", "dma"; 1208 clock-div = <1>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 i2c2: i2c@11d21000 { 1215 compatible = "mediatek,mt8192-i2c"; 1216 reg = <0 0x11d21000 0 0x1000>, 1217 <0 0x10217180 0 0x180>; 1218 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 1219 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 1220 <&infracfg CLK_INFRA_AP_DMA>; 1221 clock-names = "main", "dma"; 1222 clock-div = <1>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 status = "disabled"; 1226 }; 1227 1228 i2c4: i2c@11d22000 { 1229 compatible = "mediatek,mt8192-i2c"; 1230 reg = <0 0x11d22000 0 0x1000>, 1231 <0 0x10217380 0 0x180>; 1232 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1233 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 1234 <&infracfg CLK_INFRA_AP_DMA>; 1235 clock-names = "main", "dma"; 1236 clock-div = <1>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 imp_iic_wrap_ws: clock-controller@11d23000 { 1243 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 1244 reg = <0 0x11d23000 0 0x1000>; 1245 #clock-cells = <1>; 1246 }; 1247 1248 i2c5: i2c@11e00000 { 1249 compatible = "mediatek,mt8192-i2c"; 1250 reg = <0 0x11e00000 0 0x1000>, 1251 <0 0x10217500 0 0x80>; 1252 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1253 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 1254 <&infracfg CLK_INFRA_AP_DMA>; 1255 clock-names = "main", "dma"; 1256 clock-div = <1>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 imp_iic_wrap_w: clock-controller@11e01000 { 1263 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 1264 reg = <0 0x11e01000 0 0x1000>; 1265 #clock-cells = <1>; 1266 }; 1267 1268 u3phy0: t-phy@11e40000 { 1269 compatible = "mediatek,mt8192-tphy", 1270 "mediatek,generic-tphy-v2"; 1271 #address-cells = <1>; 1272 #size-cells = <1>; 1273 ranges = <0x0 0x0 0x11e40000 0x1000>; 1274 1275 u2port0: usb-phy@0 { 1276 reg = <0x0 0x700>; 1277 clocks = <&clk26m>; 1278 clock-names = "ref"; 1279 #phy-cells = <1>; 1280 }; 1281 1282 u3port0: usb-phy@700 { 1283 reg = <0x700 0x900>; 1284 clocks = <&clk26m>; 1285 clock-names = "ref"; 1286 #phy-cells = <1>; 1287 }; 1288 }; 1289 1290 mipi_tx0: dsi-phy@11e50000 { 1291 compatible = "mediatek,mt8183-mipi-tx"; 1292 reg = <0 0x11e50000 0 0x1000>; 1293 clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 1294 #clock-cells = <0>; 1295 #phy-cells = <0>; 1296 clock-output-names = "mipi_tx0_pll"; 1297 status = "disabled"; 1298 }; 1299 1300 i2c0: i2c@11f00000 { 1301 compatible = "mediatek,mt8192-i2c"; 1302 reg = <0 0x11f00000 0 0x1000>, 1303 <0 0x10217080 0 0x80>; 1304 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1305 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 1306 <&infracfg CLK_INFRA_AP_DMA>; 1307 clock-names = "main", "dma"; 1308 clock-div = <1>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 i2c6: i2c@11f01000 { 1315 compatible = "mediatek,mt8192-i2c"; 1316 reg = <0 0x11f01000 0 0x1000>, 1317 <0 0x10217580 0 0x80>; 1318 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1319 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 1320 <&infracfg CLK_INFRA_AP_DMA>; 1321 clock-names = "main", "dma"; 1322 clock-div = <1>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 imp_iic_wrap_n: clock-controller@11f02000 { 1329 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 1330 reg = <0 0x11f02000 0 0x1000>; 1331 #clock-cells = <1>; 1332 }; 1333 1334 msdc_top: clock-controller@11f10000 { 1335 compatible = "mediatek,mt8192-msdc_top"; 1336 reg = <0 0x11f10000 0 0x1000>; 1337 #clock-cells = <1>; 1338 }; 1339 1340 mmc0: mmc@11f60000 { 1341 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1342 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1343 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1344 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1345 <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1346 <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1347 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1348 <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1349 <&msdc_top CLK_MSDC_TOP_AXI>, 1350 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1351 clock-names = "source", "hclk", "source_cg", "sys_cg", 1352 "pclk_cg", "axi_cg", "ahb_cg"; 1353 status = "disabled"; 1354 }; 1355 1356 mmc1: mmc@11f70000 { 1357 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1358 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1359 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1360 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1361 <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1362 <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1363 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1364 <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1365 <&msdc_top CLK_MSDC_TOP_AXI>, 1366 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1367 clock-names = "source", "hclk", "source_cg", "sys_cg", 1368 "pclk_cg", "axi_cg", "ahb_cg"; 1369 status = "disabled"; 1370 }; 1371 1372 gpu: gpu@13000000 { 1373 compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm"; 1374 reg = <0 0x13000000 0 0x4000>; 1375 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, 1376 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, 1377 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1378 interrupt-names = "job", "mmu", "gpu"; 1379 1380 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 1381 1382 power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>, 1383 <&spm MT8192_POWER_DOMAIN_MFG3>, 1384 <&spm MT8192_POWER_DOMAIN_MFG4>, 1385 <&spm MT8192_POWER_DOMAIN_MFG5>, 1386 <&spm MT8192_POWER_DOMAIN_MFG6>; 1387 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1388 1389 operating-points-v2 = <&gpu_opp_table>; 1390 1391 status = "disabled"; 1392 }; 1393 1394 mfgcfg: clock-controller@13fbf000 { 1395 compatible = "mediatek,mt8192-mfgcfg"; 1396 reg = <0 0x13fbf000 0 0x1000>; 1397 #clock-cells = <1>; 1398 }; 1399 1400 mmsys: syscon@14000000 { 1401 compatible = "mediatek,mt8192-mmsys", "syscon"; 1402 reg = <0 0x14000000 0 0x1000>; 1403 #clock-cells = <1>; 1404 #reset-cells = <1>; 1405 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1406 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1407 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1408 }; 1409 1410 mutex: mutex@14001000 { 1411 compatible = "mediatek,mt8192-disp-mutex"; 1412 reg = <0 0x14001000 0 0x1000>; 1413 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1414 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1415 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1416 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1417 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1418 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1419 }; 1420 1421 smi_common: smi@14002000 { 1422 compatible = "mediatek,mt8192-smi-common"; 1423 reg = <0 0x14002000 0 0x1000>; 1424 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1425 <&mmsys CLK_MM_SMI_INFRA>, 1426 <&mmsys CLK_MM_SMI_GALS>, 1427 <&mmsys CLK_MM_SMI_GALS>; 1428 clock-names = "apb", "smi", "gals0", "gals1"; 1429 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1430 }; 1431 1432 larb0: larb@14003000 { 1433 compatible = "mediatek,mt8192-smi-larb"; 1434 reg = <0 0x14003000 0 0x1000>; 1435 mediatek,larb-id = <0>; 1436 mediatek,smi = <&smi_common>; 1437 clocks = <&clk26m>, <&clk26m>; 1438 clock-names = "apb", "smi"; 1439 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1440 }; 1441 1442 larb1: larb@14004000 { 1443 compatible = "mediatek,mt8192-smi-larb"; 1444 reg = <0 0x14004000 0 0x1000>; 1445 mediatek,larb-id = <1>; 1446 mediatek,smi = <&smi_common>; 1447 clocks = <&clk26m>, <&clk26m>; 1448 clock-names = "apb", "smi"; 1449 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1450 }; 1451 1452 ovl0: ovl@14005000 { 1453 compatible = "mediatek,mt8192-disp-ovl"; 1454 reg = <0 0x14005000 0 0x1000>; 1455 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1456 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1457 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1458 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1459 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1460 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1461 }; 1462 1463 ovl_2l0: ovl@14006000 { 1464 compatible = "mediatek,mt8192-disp-ovl-2l"; 1465 reg = <0 0x14006000 0 0x1000>; 1466 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1467 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1468 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1469 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1470 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1471 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1472 }; 1473 1474 rdma0: rdma@14007000 { 1475 compatible = "mediatek,mt8192-disp-rdma", 1476 "mediatek,mt8183-disp-rdma"; 1477 reg = <0 0x14007000 0 0x1000>; 1478 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1479 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1480 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1481 mediatek,rdma-fifo-size = <5120>; 1482 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1483 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1484 }; 1485 1486 color0: color@14009000 { 1487 compatible = "mediatek,mt8192-disp-color", 1488 "mediatek,mt8173-disp-color"; 1489 reg = <0 0x14009000 0 0x1000>; 1490 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1491 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1492 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1493 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1494 }; 1495 1496 ccorr0: ccorr@1400a000 { 1497 compatible = "mediatek,mt8192-disp-ccorr"; 1498 reg = <0 0x1400a000 0 0x1000>; 1499 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1500 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1501 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1502 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1503 }; 1504 1505 aal0: aal@1400b000 { 1506 compatible = "mediatek,mt8192-disp-aal", 1507 "mediatek,mt8183-disp-aal"; 1508 reg = <0 0x1400b000 0 0x1000>; 1509 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1510 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1511 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1512 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1513 }; 1514 1515 gamma0: gamma@1400c000 { 1516 compatible = "mediatek,mt8192-disp-gamma", 1517 "mediatek,mt8183-disp-gamma"; 1518 reg = <0 0x1400c000 0 0x1000>; 1519 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1520 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1521 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1522 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1523 }; 1524 1525 postmask0: postmask@1400d000 { 1526 compatible = "mediatek,mt8192-disp-postmask"; 1527 reg = <0 0x1400d000 0 0x1000>; 1528 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1529 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1530 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1531 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1532 }; 1533 1534 dither0: dither@1400e000 { 1535 compatible = "mediatek,mt8192-disp-dither", 1536 "mediatek,mt8183-disp-dither"; 1537 reg = <0 0x1400e000 0 0x1000>; 1538 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1539 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1540 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1541 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1542 }; 1543 1544 dsi0: dsi@14010000 { 1545 compatible = "mediatek,mt8183-dsi"; 1546 reg = <0 0x14010000 0 0x1000>; 1547 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1548 clocks = <&mmsys CLK_MM_DSI0>, 1549 <&mmsys CLK_MM_DSI_DSI0>, 1550 <&mipi_tx0>; 1551 clock-names = "engine", "digital", "hs"; 1552 phys = <&mipi_tx0>; 1553 phy-names = "dphy"; 1554 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1555 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 1556 status = "disabled"; 1557 1558 port { 1559 dsi_out: endpoint { }; 1560 }; 1561 }; 1562 1563 ovl_2l2: ovl@14014000 { 1564 compatible = "mediatek,mt8192-disp-ovl-2l"; 1565 reg = <0 0x14014000 0 0x1000>; 1566 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1567 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1568 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1569 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1570 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1571 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1572 }; 1573 1574 rdma4: rdma@14015000 { 1575 compatible = "mediatek,mt8192-disp-rdma", 1576 "mediatek,mt8183-disp-rdma"; 1577 reg = <0 0x14015000 0 0x1000>; 1578 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1579 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1580 clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1581 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1582 mediatek,rdma-fifo-size = <2048>; 1583 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1584 }; 1585 1586 dpi0: dpi@14016000 { 1587 compatible = "mediatek,mt8192-dpi"; 1588 reg = <0 0x14016000 0 0x1000>; 1589 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1590 clocks = <&mmsys CLK_MM_DPI_DPI0>, 1591 <&mmsys CLK_MM_DISP_DPI0>, 1592 <&apmixedsys CLK_APMIXED_TVDPLL>; 1593 clock-names = "pixel", "engine", "pll"; 1594 status = "disabled"; 1595 }; 1596 1597 iommu0: m4u@1401d000 { 1598 compatible = "mediatek,mt8192-m4u"; 1599 reg = <0 0x1401d000 0 0x1000>; 1600 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 1601 <&larb4>, <&larb5>, <&larb7>, 1602 <&larb9>, <&larb11>, <&larb13>, 1603 <&larb14>, <&larb16>, <&larb17>, 1604 <&larb18>, <&larb19>, <&larb20>; 1605 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1606 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1607 clock-names = "bclk"; 1608 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1609 #iommu-cells = <1>; 1610 }; 1611 1612 imgsys: clock-controller@15020000 { 1613 compatible = "mediatek,mt8192-imgsys"; 1614 reg = <0 0x15020000 0 0x1000>; 1615 #clock-cells = <1>; 1616 }; 1617 1618 larb9: larb@1502e000 { 1619 compatible = "mediatek,mt8192-smi-larb"; 1620 reg = <0 0x1502e000 0 0x1000>; 1621 mediatek,larb-id = <9>; 1622 mediatek,smi = <&smi_common>; 1623 clocks = <&imgsys CLK_IMG_LARB9>, 1624 <&imgsys CLK_IMG_LARB9>; 1625 clock-names = "apb", "smi"; 1626 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 1627 }; 1628 1629 imgsys2: clock-controller@15820000 { 1630 compatible = "mediatek,mt8192-imgsys2"; 1631 reg = <0 0x15820000 0 0x1000>; 1632 #clock-cells = <1>; 1633 }; 1634 1635 larb11: larb@1582e000 { 1636 compatible = "mediatek,mt8192-smi-larb"; 1637 reg = <0 0x1582e000 0 0x1000>; 1638 mediatek,larb-id = <11>; 1639 mediatek,smi = <&smi_common>; 1640 clocks = <&imgsys2 CLK_IMG2_LARB11>, 1641 <&imgsys2 CLK_IMG2_LARB11>; 1642 clock-names = "apb", "smi"; 1643 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 1644 }; 1645 1646 vcodec_dec: video-codec@16000000 { 1647 compatible = "mediatek,mt8192-vcodec-dec"; 1648 reg = <0 0x16000000 0 0x1000>; 1649 mediatek,scp = <&scp>; 1650 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; 1651 #address-cells = <2>; 1652 #size-cells = <2>; 1653 ranges = <0 0 0 0x16000000 0 0x26000>; 1654 1655 video-codec@10000 { 1656 compatible = "mediatek,mtk-vcodec-lat"; 1657 reg = <0x0 0x10000 0 0x800>; 1658 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; 1659 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, 1660 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, 1661 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, 1662 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, 1663 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, 1664 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, 1665 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, 1666 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; 1667 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 1668 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 1669 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 1670 <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1671 <&topckgen CLK_TOP_MAINPLL_D4>; 1672 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 1673 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 1674 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 1675 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1676 }; 1677 1678 video-codec@25000 { 1679 compatible = "mediatek,mtk-vcodec-core"; 1680 reg = <0 0x25000 0 0x1000>; 1681 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; 1682 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, 1683 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, 1684 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, 1685 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, 1686 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, 1687 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, 1688 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, 1689 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, 1690 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, 1691 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, 1692 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; 1693 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 1694 <&vdecsys CLK_VDEC_VDEC>, 1695 <&vdecsys CLK_VDEC_LAT>, 1696 <&vdecsys CLK_VDEC_LARB1>, 1697 <&topckgen CLK_TOP_MAINPLL_D4>; 1698 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 1699 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 1700 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 1701 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1702 }; 1703 }; 1704 1705 larb5: larb@1600d000 { 1706 compatible = "mediatek,mt8192-smi-larb"; 1707 reg = <0 0x1600d000 0 0x1000>; 1708 mediatek,larb-id = <5>; 1709 mediatek,smi = <&smi_common>; 1710 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1711 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1712 clock-names = "apb", "smi"; 1713 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1714 }; 1715 1716 vdecsys_soc: clock-controller@1600f000 { 1717 compatible = "mediatek,mt8192-vdecsys_soc"; 1718 reg = <0 0x1600f000 0 0x1000>; 1719 #clock-cells = <1>; 1720 }; 1721 1722 larb4: larb@1602e000 { 1723 compatible = "mediatek,mt8192-smi-larb"; 1724 reg = <0 0x1602e000 0 0x1000>; 1725 mediatek,larb-id = <4>; 1726 mediatek,smi = <&smi_common>; 1727 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 1728 <&vdecsys CLK_VDEC_SOC_LARB1>; 1729 clock-names = "apb", "smi"; 1730 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1731 }; 1732 1733 vdecsys: clock-controller@1602f000 { 1734 compatible = "mediatek,mt8192-vdecsys"; 1735 reg = <0 0x1602f000 0 0x1000>; 1736 #clock-cells = <1>; 1737 }; 1738 1739 vencsys: clock-controller@17000000 { 1740 compatible = "mediatek,mt8192-vencsys"; 1741 reg = <0 0x17000000 0 0x1000>; 1742 #clock-cells = <1>; 1743 }; 1744 1745 larb7: larb@17010000 { 1746 compatible = "mediatek,mt8192-smi-larb"; 1747 reg = <0 0x17010000 0 0x1000>; 1748 mediatek,larb-id = <7>; 1749 mediatek,smi = <&smi_common>; 1750 clocks = <&vencsys CLK_VENC_SET0_LARB>, 1751 <&vencsys CLK_VENC_SET1_VENC>; 1752 clock-names = "apb", "smi"; 1753 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1754 }; 1755 1756 vcodec_enc: vcodec@17020000 { 1757 compatible = "mediatek,mt8192-vcodec-enc"; 1758 reg = <0 0x17020000 0 0x2000>; 1759 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1760 <&iommu0 M4U_PORT_L7_VENC_REC>, 1761 <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1762 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1763 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1764 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1765 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1766 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1767 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1768 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1769 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1770 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1771 mediatek,scp = <&scp>; 1772 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1773 clocks = <&vencsys CLK_VENC_SET1_VENC>; 1774 clock-names = "venc_sel"; 1775 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1776 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1777 }; 1778 1779 camsys: clock-controller@1a000000 { 1780 compatible = "mediatek,mt8192-camsys"; 1781 reg = <0 0x1a000000 0 0x1000>; 1782 #clock-cells = <1>; 1783 }; 1784 1785 larb13: larb@1a001000 { 1786 compatible = "mediatek,mt8192-smi-larb"; 1787 reg = <0 0x1a001000 0 0x1000>; 1788 mediatek,larb-id = <13>; 1789 mediatek,smi = <&smi_common>; 1790 clocks = <&camsys CLK_CAM_CAM>, 1791 <&camsys CLK_CAM_LARB13>; 1792 clock-names = "apb", "smi"; 1793 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1794 }; 1795 1796 larb14: larb@1a002000 { 1797 compatible = "mediatek,mt8192-smi-larb"; 1798 reg = <0 0x1a002000 0 0x1000>; 1799 mediatek,larb-id = <14>; 1800 mediatek,smi = <&smi_common>; 1801 clocks = <&camsys CLK_CAM_CAM>, 1802 <&camsys CLK_CAM_LARB14>; 1803 clock-names = "apb", "smi"; 1804 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1805 }; 1806 1807 larb16: larb@1a00f000 { 1808 compatible = "mediatek,mt8192-smi-larb"; 1809 reg = <0 0x1a00f000 0 0x1000>; 1810 mediatek,larb-id = <16>; 1811 mediatek,smi = <&smi_common>; 1812 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 1813 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1814 clock-names = "apb", "smi"; 1815 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 1816 }; 1817 1818 larb17: larb@1a010000 { 1819 compatible = "mediatek,mt8192-smi-larb"; 1820 reg = <0 0x1a010000 0 0x1000>; 1821 mediatek,larb-id = <17>; 1822 mediatek,smi = <&smi_common>; 1823 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 1824 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1825 clock-names = "apb", "smi"; 1826 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 1827 }; 1828 1829 larb18: larb@1a011000 { 1830 compatible = "mediatek,mt8192-smi-larb"; 1831 reg = <0 0x1a011000 0 0x1000>; 1832 mediatek,larb-id = <18>; 1833 mediatek,smi = <&smi_common>; 1834 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 1835 <&camsys_rawc CLK_CAM_RAWC_CAM>; 1836 clock-names = "apb", "smi"; 1837 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 1838 }; 1839 1840 camsys_rawa: clock-controller@1a04f000 { 1841 compatible = "mediatek,mt8192-camsys_rawa"; 1842 reg = <0 0x1a04f000 0 0x1000>; 1843 #clock-cells = <1>; 1844 }; 1845 1846 camsys_rawb: clock-controller@1a06f000 { 1847 compatible = "mediatek,mt8192-camsys_rawb"; 1848 reg = <0 0x1a06f000 0 0x1000>; 1849 #clock-cells = <1>; 1850 }; 1851 1852 camsys_rawc: clock-controller@1a08f000 { 1853 compatible = "mediatek,mt8192-camsys_rawc"; 1854 reg = <0 0x1a08f000 0 0x1000>; 1855 #clock-cells = <1>; 1856 }; 1857 1858 ipesys: clock-controller@1b000000 { 1859 compatible = "mediatek,mt8192-ipesys"; 1860 reg = <0 0x1b000000 0 0x1000>; 1861 #clock-cells = <1>; 1862 }; 1863 1864 larb20: larb@1b00f000 { 1865 compatible = "mediatek,mt8192-smi-larb"; 1866 reg = <0 0x1b00f000 0 0x1000>; 1867 mediatek,larb-id = <20>; 1868 mediatek,smi = <&smi_common>; 1869 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1870 <&ipesys CLK_IPE_LARB20>; 1871 clock-names = "apb", "smi"; 1872 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1873 }; 1874 1875 larb19: larb@1b10f000 { 1876 compatible = "mediatek,mt8192-smi-larb"; 1877 reg = <0 0x1b10f000 0 0x1000>; 1878 mediatek,larb-id = <19>; 1879 mediatek,smi = <&smi_common>; 1880 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1881 <&ipesys CLK_IPE_LARB19>; 1882 clock-names = "apb", "smi"; 1883 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1884 }; 1885 1886 mdpsys: clock-controller@1f000000 { 1887 compatible = "mediatek,mt8192-mdpsys"; 1888 reg = <0 0x1f000000 0 0x1000>; 1889 #clock-cells = <1>; 1890 }; 1891 1892 larb2: larb@1f002000 { 1893 compatible = "mediatek,mt8192-smi-larb"; 1894 reg = <0 0x1f002000 0 0x1000>; 1895 mediatek,larb-id = <2>; 1896 mediatek,smi = <&smi_common>; 1897 clocks = <&mdpsys CLK_MDP_SMI0>, 1898 <&mdpsys CLK_MDP_SMI0>; 1899 clock-names = "apb", "smi"; 1900 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 1901 }; 1902 }; 1903}; 1904