1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8192-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 12 13/ { 14 compatible = "mediatek,mt8192"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clk26m: oscillator0 { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <26000000>; 23 clock-output-names = "clk26m"; 24 }; 25 26 clk32k: oscillator1 { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 clock-output-names = "clk32k"; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a55"; 40 reg = <0x000>; 41 enable-method = "psci"; 42 clock-frequency = <1701000000>; 43 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 44 next-level-cache = <&l2_0>; 45 capacity-dmips-mhz = <530>; 46 }; 47 48 cpu1: cpu@100 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a55"; 51 reg = <0x100>; 52 enable-method = "psci"; 53 clock-frequency = <1701000000>; 54 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 55 next-level-cache = <&l2_0>; 56 capacity-dmips-mhz = <530>; 57 }; 58 59 cpu2: cpu@200 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x200>; 63 enable-method = "psci"; 64 clock-frequency = <1701000000>; 65 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 66 next-level-cache = <&l2_0>; 67 capacity-dmips-mhz = <530>; 68 }; 69 70 cpu3: cpu@300 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a55"; 73 reg = <0x300>; 74 enable-method = "psci"; 75 clock-frequency = <1701000000>; 76 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 77 next-level-cache = <&l2_0>; 78 capacity-dmips-mhz = <530>; 79 }; 80 81 cpu4: cpu@400 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a76"; 84 reg = <0x400>; 85 enable-method = "psci"; 86 clock-frequency = <2171000000>; 87 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 88 next-level-cache = <&l2_1>; 89 capacity-dmips-mhz = <1024>; 90 }; 91 92 cpu5: cpu@500 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a76"; 95 reg = <0x500>; 96 enable-method = "psci"; 97 clock-frequency = <2171000000>; 98 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 99 next-level-cache = <&l2_1>; 100 capacity-dmips-mhz = <1024>; 101 }; 102 103 cpu6: cpu@600 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a76"; 106 reg = <0x600>; 107 enable-method = "psci"; 108 clock-frequency = <2171000000>; 109 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 110 next-level-cache = <&l2_1>; 111 capacity-dmips-mhz = <1024>; 112 }; 113 114 cpu7: cpu@700 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a76"; 117 reg = <0x700>; 118 enable-method = "psci"; 119 clock-frequency = <2171000000>; 120 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 121 next-level-cache = <&l2_1>; 122 capacity-dmips-mhz = <1024>; 123 }; 124 125 cpu-map { 126 cluster0 { 127 core0 { 128 cpu = <&cpu0>; 129 }; 130 core1 { 131 cpu = <&cpu1>; 132 }; 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 core3 { 137 cpu = <&cpu3>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&cpu4>; 144 }; 145 core1 { 146 cpu = <&cpu5>; 147 }; 148 core2 { 149 cpu = <&cpu6>; 150 }; 151 core3 { 152 cpu = <&cpu7>; 153 }; 154 }; 155 }; 156 157 l2_0: l2-cache0 { 158 compatible = "cache"; 159 next-level-cache = <&l3_0>; 160 }; 161 162 l2_1: l2-cache1 { 163 compatible = "cache"; 164 next-level-cache = <&l3_0>; 165 }; 166 167 l3_0: l3-cache { 168 compatible = "cache"; 169 }; 170 171 idle-states { 172 entry-method = "arm,psci"; 173 cpuoff_l: cpuoff_l { 174 compatible = "arm,idle-state"; 175 arm,psci-suspend-param = <0x00010001>; 176 local-timer-stop; 177 entry-latency-us = <55>; 178 exit-latency-us = <140>; 179 min-residency-us = <780>; 180 }; 181 cpuoff_b: cpuoff_b { 182 compatible = "arm,idle-state"; 183 arm,psci-suspend-param = <0x00010001>; 184 local-timer-stop; 185 entry-latency-us = <35>; 186 exit-latency-us = <145>; 187 min-residency-us = <720>; 188 }; 189 clusteroff_l: clusteroff_l { 190 compatible = "arm,idle-state"; 191 arm,psci-suspend-param = <0x01010002>; 192 local-timer-stop; 193 entry-latency-us = <60>; 194 exit-latency-us = <155>; 195 min-residency-us = <860>; 196 }; 197 clusteroff_b: clusteroff_b { 198 compatible = "arm,idle-state"; 199 arm,psci-suspend-param = <0x01010002>; 200 local-timer-stop; 201 entry-latency-us = <40>; 202 exit-latency-us = <155>; 203 min-residency-us = <780>; 204 }; 205 }; 206 }; 207 208 pmu-a55 { 209 compatible = "arm,cortex-a55-pmu"; 210 interrupt-parent = <&gic>; 211 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 212 }; 213 214 pmu-a76 { 215 compatible = "arm,cortex-a76-pmu"; 216 interrupt-parent = <&gic>; 217 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 218 }; 219 220 psci { 221 compatible = "arm,psci-1.0"; 222 method = "smc"; 223 }; 224 225 timer: timer { 226 compatible = "arm,armv8-timer"; 227 interrupt-parent = <&gic>; 228 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 229 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 230 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 231 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 232 clock-frequency = <13000000>; 233 }; 234 235 soc { 236 #address-cells = <2>; 237 #size-cells = <2>; 238 compatible = "simple-bus"; 239 ranges; 240 241 gic: interrupt-controller@c000000 { 242 compatible = "arm,gic-v3"; 243 #interrupt-cells = <4>; 244 #redistributor-regions = <1>; 245 interrupt-parent = <&gic>; 246 interrupt-controller; 247 reg = <0 0x0c000000 0 0x40000>, 248 <0 0x0c040000 0 0x200000>; 249 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 250 251 ppi-partitions { 252 ppi_cluster0: interrupt-partition-0 { 253 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 254 }; 255 ppi_cluster1: interrupt-partition-1 { 256 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 257 }; 258 }; 259 }; 260 261 topckgen: syscon@10000000 { 262 compatible = "mediatek,mt8192-topckgen", "syscon"; 263 reg = <0 0x10000000 0 0x1000>; 264 #clock-cells = <1>; 265 }; 266 267 infracfg: syscon@10001000 { 268 compatible = "mediatek,mt8192-infracfg", "syscon"; 269 reg = <0 0x10001000 0 0x1000>; 270 #clock-cells = <1>; 271 }; 272 273 pericfg: syscon@10003000 { 274 compatible = "mediatek,mt8192-pericfg", "syscon"; 275 reg = <0 0x10003000 0 0x1000>; 276 #clock-cells = <1>; 277 }; 278 279 pio: pinctrl@10005000 { 280 compatible = "mediatek,mt8192-pinctrl"; 281 reg = <0 0x10005000 0 0x1000>, 282 <0 0x11c20000 0 0x1000>, 283 <0 0x11d10000 0 0x1000>, 284 <0 0x11d30000 0 0x1000>, 285 <0 0x11d40000 0 0x1000>, 286 <0 0x11e20000 0 0x1000>, 287 <0 0x11e70000 0 0x1000>, 288 <0 0x11ea0000 0 0x1000>, 289 <0 0x11f20000 0 0x1000>, 290 <0 0x11f30000 0 0x1000>, 291 <0 0x1000b000 0 0x1000>; 292 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 293 "iocfg_bl", "iocfg_br", "iocfg_lm", 294 "iocfg_lb", "iocfg_rt", "iocfg_lt", 295 "iocfg_tl", "eint"; 296 gpio-controller; 297 #gpio-cells = <2>; 298 gpio-ranges = <&pio 0 0 220>; 299 interrupt-controller; 300 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 301 #interrupt-cells = <2>; 302 }; 303 304 apmixedsys: syscon@1000c000 { 305 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 306 reg = <0 0x1000c000 0 0x1000>; 307 #clock-cells = <1>; 308 }; 309 310 systimer: timer@10017000 { 311 compatible = "mediatek,mt8192-timer", 312 "mediatek,mt6765-timer"; 313 reg = <0 0x10017000 0 0x1000>; 314 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 315 clocks = <&clk26m>; 316 clock-names = "clk13m"; 317 }; 318 319 scp_adsp: clock-controller@10720000 { 320 compatible = "mediatek,mt8192-scp_adsp"; 321 reg = <0 0x10720000 0 0x1000>; 322 #clock-cells = <1>; 323 }; 324 325 uart0: serial@11002000 { 326 compatible = "mediatek,mt8192-uart", 327 "mediatek,mt6577-uart"; 328 reg = <0 0x11002000 0 0x1000>; 329 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 330 clocks = <&clk26m>, <&clk26m>; 331 clock-names = "baud", "bus"; 332 status = "disabled"; 333 }; 334 335 uart1: serial@11003000 { 336 compatible = "mediatek,mt8192-uart", 337 "mediatek,mt6577-uart"; 338 reg = <0 0x11003000 0 0x1000>; 339 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 340 clocks = <&clk26m>, <&clk26m>; 341 clock-names = "baud", "bus"; 342 status = "disabled"; 343 }; 344 345 imp_iic_wrap_c: clock-controller@11007000 { 346 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 347 reg = <0 0x11007000 0 0x1000>; 348 #clock-cells = <1>; 349 }; 350 351 spi0: spi@1100a000 { 352 compatible = "mediatek,mt8192-spi", 353 "mediatek,mt6765-spi"; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 reg = <0 0x1100a000 0 0x1000>; 357 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 358 clocks = <&clk26m>, 359 <&clk26m>, 360 <&clk26m>; 361 clock-names = "parent-clk", "sel-clk", "spi-clk"; 362 status = "disabled"; 363 }; 364 365 spi1: spi@11010000 { 366 compatible = "mediatek,mt8192-spi", 367 "mediatek,mt6765-spi"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <0 0x11010000 0 0x1000>; 371 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 372 clocks = <&clk26m>, 373 <&clk26m>, 374 <&clk26m>; 375 clock-names = "parent-clk", "sel-clk", "spi-clk"; 376 status = "disabled"; 377 }; 378 379 spi2: spi@11012000 { 380 compatible = "mediatek,mt8192-spi", 381 "mediatek,mt6765-spi"; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 reg = <0 0x11012000 0 0x1000>; 385 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 386 clocks = <&clk26m>, 387 <&clk26m>, 388 <&clk26m>; 389 clock-names = "parent-clk", "sel-clk", "spi-clk"; 390 status = "disabled"; 391 }; 392 393 spi3: spi@11013000 { 394 compatible = "mediatek,mt8192-spi", 395 "mediatek,mt6765-spi"; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 reg = <0 0x11013000 0 0x1000>; 399 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 400 clocks = <&clk26m>, 401 <&clk26m>, 402 <&clk26m>; 403 clock-names = "parent-clk", "sel-clk", "spi-clk"; 404 status = "disabled"; 405 }; 406 407 spi4: spi@11018000 { 408 compatible = "mediatek,mt8192-spi", 409 "mediatek,mt6765-spi"; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 reg = <0 0x11018000 0 0x1000>; 413 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 414 clocks = <&clk26m>, 415 <&clk26m>, 416 <&clk26m>; 417 clock-names = "parent-clk", "sel-clk", "spi-clk"; 418 status = "disabled"; 419 }; 420 421 spi5: spi@11019000 { 422 compatible = "mediatek,mt8192-spi", 423 "mediatek,mt6765-spi"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 reg = <0 0x11019000 0 0x1000>; 427 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 428 clocks = <&clk26m>, 429 <&clk26m>, 430 <&clk26m>; 431 clock-names = "parent-clk", "sel-clk", "spi-clk"; 432 status = "disabled"; 433 }; 434 435 spi6: spi@1101d000 { 436 compatible = "mediatek,mt8192-spi", 437 "mediatek,mt6765-spi"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 reg = <0 0x1101d000 0 0x1000>; 441 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 442 clocks = <&clk26m>, 443 <&clk26m>, 444 <&clk26m>; 445 clock-names = "parent-clk", "sel-clk", "spi-clk"; 446 status = "disabled"; 447 }; 448 449 spi7: spi@1101e000 { 450 compatible = "mediatek,mt8192-spi", 451 "mediatek,mt6765-spi"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 reg = <0 0x1101e000 0 0x1000>; 455 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 456 clocks = <&clk26m>, 457 <&clk26m>, 458 <&clk26m>; 459 clock-names = "parent-clk", "sel-clk", "spi-clk"; 460 status = "disabled"; 461 }; 462 463 nor_flash: spi@11234000 { 464 compatible = "mediatek,mt8192-nor"; 465 reg = <0 0x11234000 0 0xe0>; 466 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 467 clocks = <&clk26m>, 468 <&clk26m>, 469 <&clk26m>; 470 clock-names = "spi", "sf", "axi"; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disable"; 474 }; 475 476 audsys: clock-controller@11210000 { 477 compatible = "mediatek,mt8192-audsys", "syscon"; 478 reg = <0 0x11210000 0 0x1000>; 479 #clock-cells = <1>; 480 }; 481 482 i2c3: i2c@11cb0000 { 483 compatible = "mediatek,mt8192-i2c"; 484 reg = <0 0x11cb0000 0 0x1000>, 485 <0 0x10217300 0 0x80>; 486 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 487 clocks = <&clk26m>, <&clk26m>; 488 clock-names = "main", "dma"; 489 clock-div = <1>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 status = "disabled"; 493 }; 494 495 imp_iic_wrap_e: clock-controller@11cb1000 { 496 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 497 reg = <0 0x11cb1000 0 0x1000>; 498 #clock-cells = <1>; 499 }; 500 501 i2c7: i2c@11d00000 { 502 compatible = "mediatek,mt8192-i2c"; 503 reg = <0 0x11d00000 0 0x1000>, 504 <0 0x10217600 0 0x180>; 505 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 506 clocks = <&clk26m>, <&clk26m>; 507 clock-names = "main", "dma"; 508 clock-div = <1>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "disabled"; 512 }; 513 514 i2c8: i2c@11d01000 { 515 compatible = "mediatek,mt8192-i2c"; 516 reg = <0 0x11d01000 0 0x1000>, 517 <0 0x10217780 0 0x180>; 518 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 519 clocks = <&clk26m>, <&clk26m>; 520 clock-names = "main", "dma"; 521 clock-div = <1>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 i2c9: i2c@11d02000 { 528 compatible = "mediatek,mt8192-i2c"; 529 reg = <0 0x11d02000 0 0x1000>, 530 <0 0x10217900 0 0x180>; 531 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 532 clocks = <&clk26m>, <&clk26m>; 533 clock-names = "main", "dma"; 534 clock-div = <1>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 imp_iic_wrap_s: clock-controller@11d03000 { 541 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 542 reg = <0 0x11d03000 0 0x1000>; 543 #clock-cells = <1>; 544 }; 545 546 i2c1: i2c@11d20000 { 547 compatible = "mediatek,mt8192-i2c"; 548 reg = <0 0x11d20000 0 0x1000>, 549 <0 0x10217100 0 0x80>; 550 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 551 clocks = <&clk26m>, <&clk26m>; 552 clock-names = "main", "dma"; 553 clock-div = <1>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 i2c2: i2c@11d21000 { 560 compatible = "mediatek,mt8192-i2c"; 561 reg = <0 0x11d21000 0 0x1000>, 562 <0 0x10217180 0 0x180>; 563 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 564 clocks = <&clk26m>, <&clk26m>; 565 clock-names = "main", "dma"; 566 clock-div = <1>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 i2c4: i2c@11d22000 { 573 compatible = "mediatek,mt8192-i2c"; 574 reg = <0 0x11d22000 0 0x1000>, 575 <0 0x10217380 0 0x180>; 576 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 577 clocks = <&clk26m>, <&clk26m>; 578 clock-names = "main", "dma"; 579 clock-div = <1>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 status = "disabled"; 583 }; 584 585 imp_iic_wrap_ws: clock-controller@11d23000 { 586 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 587 reg = <0 0x11d23000 0 0x1000>; 588 #clock-cells = <1>; 589 }; 590 591 i2c5: i2c@11e00000 { 592 compatible = "mediatek,mt8192-i2c"; 593 reg = <0 0x11e00000 0 0x1000>, 594 <0 0x10217500 0 0x80>; 595 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 596 clocks = <&clk26m>, <&clk26m>; 597 clock-names = "main", "dma"; 598 clock-div = <1>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 imp_iic_wrap_w: clock-controller@11e01000 { 605 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 606 reg = <0 0x11e01000 0 0x1000>; 607 #clock-cells = <1>; 608 }; 609 610 i2c0: i2c@11f00000 { 611 compatible = "mediatek,mt8192-i2c"; 612 reg = <0 0x11f00000 0 0x1000>, 613 <0 0x10217080 0 0x80>; 614 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 615 clocks = <&clk26m>, <&clk26m>; 616 clock-names = "main", "dma"; 617 clock-div = <1>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 i2c6: i2c@11f01000 { 624 compatible = "mediatek,mt8192-i2c"; 625 reg = <0 0x11f01000 0 0x1000>, 626 <0 0x10217580 0 0x80>; 627 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 628 clocks = <&clk26m>, <&clk26m>; 629 clock-names = "main", "dma"; 630 clock-div = <1>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 status = "disabled"; 634 }; 635 636 imp_iic_wrap_n: clock-controller@11f02000 { 637 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 638 reg = <0 0x11f02000 0 0x1000>; 639 #clock-cells = <1>; 640 }; 641 642 msdc_top: clock-controller@11f10000 { 643 compatible = "mediatek,mt8192-msdc_top"; 644 reg = <0 0x11f10000 0 0x1000>; 645 #clock-cells = <1>; 646 }; 647 648 msdc: clock-controller@11f60000 { 649 compatible = "mediatek,mt8192-msdc"; 650 reg = <0 0x11f60000 0 0x1000>; 651 #clock-cells = <1>; 652 }; 653 654 mfgcfg: clock-controller@13fbf000 { 655 compatible = "mediatek,mt8192-mfgcfg"; 656 reg = <0 0x13fbf000 0 0x1000>; 657 #clock-cells = <1>; 658 }; 659 660 mmsys: syscon@14000000 { 661 compatible = "mediatek,mt8192-mmsys", "syscon"; 662 reg = <0 0x14000000 0 0x1000>; 663 #clock-cells = <1>; 664 }; 665 666 imgsys: clock-controller@15020000 { 667 compatible = "mediatek,mt8192-imgsys"; 668 reg = <0 0x15020000 0 0x1000>; 669 #clock-cells = <1>; 670 }; 671 672 imgsys2: clock-controller@15820000 { 673 compatible = "mediatek,mt8192-imgsys2"; 674 reg = <0 0x15820000 0 0x1000>; 675 #clock-cells = <1>; 676 }; 677 678 vdecsys_soc: clock-controller@1600f000 { 679 compatible = "mediatek,mt8192-vdecsys_soc"; 680 reg = <0 0x1600f000 0 0x1000>; 681 #clock-cells = <1>; 682 }; 683 684 vdecsys: clock-controller@1602f000 { 685 compatible = "mediatek,mt8192-vdecsys"; 686 reg = <0 0x1602f000 0 0x1000>; 687 #clock-cells = <1>; 688 }; 689 690 vencsys: clock-controller@17000000 { 691 compatible = "mediatek,mt8192-vencsys"; 692 reg = <0 0x17000000 0 0x1000>; 693 #clock-cells = <1>; 694 }; 695 696 camsys: clock-controller@1a000000 { 697 compatible = "mediatek,mt8192-camsys"; 698 reg = <0 0x1a000000 0 0x1000>; 699 #clock-cells = <1>; 700 }; 701 702 camsys_rawa: clock-controller@1a04f000 { 703 compatible = "mediatek,mt8192-camsys_rawa"; 704 reg = <0 0x1a04f000 0 0x1000>; 705 #clock-cells = <1>; 706 }; 707 708 camsys_rawb: clock-controller@1a06f000 { 709 compatible = "mediatek,mt8192-camsys_rawb"; 710 reg = <0 0x1a06f000 0 0x1000>; 711 #clock-cells = <1>; 712 }; 713 714 camsys_rawc: clock-controller@1a08f000 { 715 compatible = "mediatek,mt8192-camsys_rawc"; 716 reg = <0 0x1a08f000 0 0x1000>; 717 #clock-cells = <1>; 718 }; 719 720 ipesys: clock-controller@1b000000 { 721 compatible = "mediatek,mt8192-ipesys"; 722 reg = <0 0x1b000000 0 0x1000>; 723 #clock-cells = <1>; 724 }; 725 726 mdpsys: clock-controller@1f000000 { 727 compatible = "mediatek,mt8192-mdpsys"; 728 reg = <0 0x1f000000 0 0x1000>; 729 #clock-cells = <1>; 730 }; 731 }; 732}; 733