1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 11 12/ { 13 compatible = "mediatek,mt8192"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clk26m: oscillator0 { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <26000000>; 22 clock-output-names = "clk26m"; 23 }; 24 25 clk32k: oscillator1 { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <32768>; 29 clock-output-names = "clk32k"; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a55"; 39 reg = <0x000>; 40 enable-method = "psci"; 41 clock-frequency = <1701000000>; 42 next-level-cache = <&l2_0>; 43 capacity-dmips-mhz = <530>; 44 }; 45 46 cpu1: cpu@100 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a55"; 49 reg = <0x100>; 50 enable-method = "psci"; 51 clock-frequency = <1701000000>; 52 next-level-cache = <&l2_0>; 53 capacity-dmips-mhz = <530>; 54 }; 55 56 cpu2: cpu@200 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x200>; 60 enable-method = "psci"; 61 clock-frequency = <1701000000>; 62 next-level-cache = <&l2_0>; 63 capacity-dmips-mhz = <530>; 64 }; 65 66 cpu3: cpu@300 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a55"; 69 reg = <0x300>; 70 enable-method = "psci"; 71 clock-frequency = <1701000000>; 72 next-level-cache = <&l2_0>; 73 capacity-dmips-mhz = <530>; 74 }; 75 76 cpu4: cpu@400 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a76"; 79 reg = <0x400>; 80 enable-method = "psci"; 81 clock-frequency = <2171000000>; 82 next-level-cache = <&l2_1>; 83 capacity-dmips-mhz = <1024>; 84 }; 85 86 cpu5: cpu@500 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a76"; 89 reg = <0x500>; 90 enable-method = "psci"; 91 clock-frequency = <2171000000>; 92 next-level-cache = <&l2_1>; 93 capacity-dmips-mhz = <1024>; 94 }; 95 96 cpu6: cpu@600 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a76"; 99 reg = <0x600>; 100 enable-method = "psci"; 101 clock-frequency = <2171000000>; 102 next-level-cache = <&l2_1>; 103 capacity-dmips-mhz = <1024>; 104 }; 105 106 cpu7: cpu@700 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a76"; 109 reg = <0x700>; 110 enable-method = "psci"; 111 clock-frequency = <2171000000>; 112 next-level-cache = <&l2_1>; 113 capacity-dmips-mhz = <1024>; 114 }; 115 116 cpu-map { 117 cluster0 { 118 core0 { 119 cpu = <&cpu0>; 120 }; 121 core1 { 122 cpu = <&cpu1>; 123 }; 124 core2 { 125 cpu = <&cpu2>; 126 }; 127 core3 { 128 cpu = <&cpu3>; 129 }; 130 }; 131 132 cluster1 { 133 core0 { 134 cpu = <&cpu4>; 135 }; 136 core1 { 137 cpu = <&cpu5>; 138 }; 139 core2 { 140 cpu = <&cpu6>; 141 }; 142 core3 { 143 cpu = <&cpu7>; 144 }; 145 }; 146 }; 147 148 l2_0: l2-cache0 { 149 compatible = "cache"; 150 next-level-cache = <&l3_0>; 151 }; 152 153 l2_1: l2-cache1 { 154 compatible = "cache"; 155 next-level-cache = <&l3_0>; 156 }; 157 158 l3_0: l3-cache { 159 compatible = "cache"; 160 }; 161 }; 162 163 pmu-a55 { 164 compatible = "arm,cortex-a55-pmu"; 165 interrupt-parent = <&gic>; 166 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 167 }; 168 169 pmu-a76 { 170 compatible = "arm,cortex-a76-pmu"; 171 interrupt-parent = <&gic>; 172 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 173 }; 174 175 psci { 176 compatible = "arm,psci-1.0"; 177 method = "smc"; 178 }; 179 180 timer: timer { 181 compatible = "arm,armv8-timer"; 182 interrupt-parent = <&gic>; 183 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 184 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 185 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 186 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 187 clock-frequency = <13000000>; 188 }; 189 190 soc { 191 #address-cells = <2>; 192 #size-cells = <2>; 193 compatible = "simple-bus"; 194 ranges; 195 196 gic: interrupt-controller@c000000 { 197 compatible = "arm,gic-v3"; 198 #interrupt-cells = <4>; 199 #redistributor-regions = <1>; 200 interrupt-parent = <&gic>; 201 interrupt-controller; 202 reg = <0 0x0c000000 0 0x40000>, 203 <0 0x0c040000 0 0x200000>; 204 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 205 206 ppi-partitions { 207 ppi_cluster0: interrupt-partition-0 { 208 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 209 }; 210 ppi_cluster1: interrupt-partition-1 { 211 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 212 }; 213 }; 214 }; 215 216 pio: pinctrl@10005000 { 217 compatible = "mediatek,mt8192-pinctrl"; 218 reg = <0 0x10005000 0 0x1000>, 219 <0 0x11c20000 0 0x1000>, 220 <0 0x11d10000 0 0x1000>, 221 <0 0x11d30000 0 0x1000>, 222 <0 0x11d40000 0 0x1000>, 223 <0 0x11e20000 0 0x1000>, 224 <0 0x11e70000 0 0x1000>, 225 <0 0x11ea0000 0 0x1000>, 226 <0 0x11f20000 0 0x1000>, 227 <0 0x11f30000 0 0x1000>, 228 <0 0x1000b000 0 0x1000>; 229 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 230 "iocfg_bl", "iocfg_br", "iocfg_lm", 231 "iocfg_lb", "iocfg_rt", "iocfg_lt", 232 "iocfg_tl", "eint"; 233 gpio-controller; 234 #gpio-cells = <2>; 235 gpio-ranges = <&pio 0 0 220>; 236 interrupt-controller; 237 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 238 #interrupt-cells = <2>; 239 }; 240 241 systimer: timer@10017000 { 242 compatible = "mediatek,mt8192-timer", 243 "mediatek,mt6765-timer"; 244 reg = <0 0x10017000 0 0x1000>; 245 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 246 clocks = <&clk26m>; 247 clock-names = "clk13m"; 248 }; 249 250 uart0: serial@11002000 { 251 compatible = "mediatek,mt8192-uart", 252 "mediatek,mt6577-uart"; 253 reg = <0 0x11002000 0 0x1000>; 254 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 255 clocks = <&clk26m>, <&clk26m>; 256 clock-names = "baud", "bus"; 257 status = "disabled"; 258 }; 259 260 uart1: serial@11003000 { 261 compatible = "mediatek,mt8192-uart", 262 "mediatek,mt6577-uart"; 263 reg = <0 0x11003000 0 0x1000>; 264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 265 clocks = <&clk26m>, <&clk26m>; 266 clock-names = "baud", "bus"; 267 status = "disabled"; 268 }; 269 270 spi0: spi@1100a000 { 271 compatible = "mediatek,mt8192-spi", 272 "mediatek,mt6765-spi"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 reg = <0 0x1100a000 0 0x1000>; 276 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 277 clocks = <&clk26m>, 278 <&clk26m>, 279 <&clk26m>; 280 clock-names = "parent-clk", "sel-clk", "spi-clk"; 281 status = "disabled"; 282 }; 283 284 spi1: spi@11010000 { 285 compatible = "mediatek,mt8192-spi", 286 "mediatek,mt6765-spi"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 reg = <0 0x11010000 0 0x1000>; 290 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 291 clocks = <&clk26m>, 292 <&clk26m>, 293 <&clk26m>; 294 clock-names = "parent-clk", "sel-clk", "spi-clk"; 295 status = "disabled"; 296 }; 297 298 spi2: spi@11012000 { 299 compatible = "mediatek,mt8192-spi", 300 "mediatek,mt6765-spi"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg = <0 0x11012000 0 0x1000>; 304 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 305 clocks = <&clk26m>, 306 <&clk26m>, 307 <&clk26m>; 308 clock-names = "parent-clk", "sel-clk", "spi-clk"; 309 status = "disabled"; 310 }; 311 312 spi3: spi@11013000 { 313 compatible = "mediatek,mt8192-spi", 314 "mediatek,mt6765-spi"; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 reg = <0 0x11013000 0 0x1000>; 318 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 319 clocks = <&clk26m>, 320 <&clk26m>, 321 <&clk26m>; 322 clock-names = "parent-clk", "sel-clk", "spi-clk"; 323 status = "disabled"; 324 }; 325 326 spi4: spi@11018000 { 327 compatible = "mediatek,mt8192-spi", 328 "mediatek,mt6765-spi"; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 reg = <0 0x11018000 0 0x1000>; 332 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 333 clocks = <&clk26m>, 334 <&clk26m>, 335 <&clk26m>; 336 clock-names = "parent-clk", "sel-clk", "spi-clk"; 337 status = "disabled"; 338 }; 339 340 spi5: spi@11019000 { 341 compatible = "mediatek,mt8192-spi", 342 "mediatek,mt6765-spi"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 reg = <0 0x11019000 0 0x1000>; 346 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 347 clocks = <&clk26m>, 348 <&clk26m>, 349 <&clk26m>; 350 clock-names = "parent-clk", "sel-clk", "spi-clk"; 351 status = "disabled"; 352 }; 353 354 spi6: spi@1101d000 { 355 compatible = "mediatek,mt8192-spi", 356 "mediatek,mt6765-spi"; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 reg = <0 0x1101d000 0 0x1000>; 360 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 361 clocks = <&clk26m>, 362 <&clk26m>, 363 <&clk26m>; 364 clock-names = "parent-clk", "sel-clk", "spi-clk"; 365 status = "disabled"; 366 }; 367 368 spi7: spi@1101e000 { 369 compatible = "mediatek,mt8192-spi", 370 "mediatek,mt6765-spi"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 reg = <0 0x1101e000 0 0x1000>; 374 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 375 clocks = <&clk26m>, 376 <&clk26m>, 377 <&clk26m>; 378 clock-names = "parent-clk", "sel-clk", "spi-clk"; 379 status = "disabled"; 380 }; 381 382 i2c3: i2c3@11cb0000 { 383 compatible = "mediatek,mt8192-i2c"; 384 reg = <0 0x11cb0000 0 0x1000>, 385 <0 0x10217300 0 0x80>; 386 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 387 clocks = <&clk26m>, <&clk26m>; 388 clock-names = "main", "dma"; 389 clock-div = <1>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 status = "disabled"; 393 }; 394 395 i2c7: i2c7@11d00000 { 396 compatible = "mediatek,mt8192-i2c"; 397 reg = <0 0x11d00000 0 0x1000>, 398 <0 0x10217600 0 0x180>; 399 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 400 clocks = <&clk26m>, <&clk26m>; 401 clock-names = "main", "dma"; 402 clock-div = <1>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 status = "disabled"; 406 }; 407 408 i2c8: i2c8@11d01000 { 409 compatible = "mediatek,mt8192-i2c"; 410 reg = <0 0x11d01000 0 0x1000>, 411 <0 0x10217780 0 0x180>; 412 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 413 clocks = <&clk26m>, <&clk26m>; 414 clock-names = "main", "dma"; 415 clock-div = <1>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 status = "disabled"; 419 }; 420 421 i2c9: i2c9@11d02000 { 422 compatible = "mediatek,mt8192-i2c"; 423 reg = <0 0x11d02000 0 0x1000>, 424 <0 0x10217900 0 0x180>; 425 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 426 clocks = <&clk26m>, <&clk26m>; 427 clock-names = "main", "dma"; 428 clock-div = <1>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 status = "disabled"; 432 }; 433 434 i2c1: i2c1@11d20000 { 435 compatible = "mediatek,mt8192-i2c"; 436 reg = <0 0x11d20000 0 0x1000>, 437 <0 0x10217100 0 0x80>; 438 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 439 clocks = <&clk26m>, <&clk26m>; 440 clock-names = "main", "dma"; 441 clock-div = <1>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 i2c2: i2c2@11d21000 { 448 compatible = "mediatek,mt8192-i2c"; 449 reg = <0 0x11d21000 0 0x1000>, 450 <0 0x10217180 0 0x180>; 451 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 452 clocks = <&clk26m>, <&clk26m>; 453 clock-names = "main", "dma"; 454 clock-div = <1>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 status = "disabled"; 458 }; 459 460 i2c4: i2c4@11d22000 { 461 compatible = "mediatek,mt8192-i2c"; 462 reg = <0 0x11d22000 0 0x1000>, 463 <0 0x10217380 0 0x180>; 464 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 465 clocks = <&clk26m>, <&clk26m>; 466 clock-names = "main", "dma"; 467 clock-div = <1>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 status = "disabled"; 471 }; 472 473 i2c5: i2c5@11e00000 { 474 compatible = "mediatek,mt8192-i2c"; 475 reg = <0 0x11e00000 0 0x1000>, 476 <0 0x10217500 0 0x80>; 477 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 478 clocks = <&clk26m>, <&clk26m>; 479 clock-names = "main", "dma"; 480 clock-div = <1>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 status = "disabled"; 484 }; 485 486 i2c0: i2c0@11f00000 { 487 compatible = "mediatek,mt8192-i2c"; 488 reg = <0 0x11f00000 0 0x1000>, 489 <0 0x10217080 0 0x80>; 490 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 491 clocks = <&clk26m>, <&clk26m>; 492 clock-names = "main", "dma"; 493 clock-div = <1>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 status = "disabled"; 497 }; 498 499 i2c6: i2c6@11f01000 { 500 compatible = "mediatek,mt8192-i2c"; 501 reg = <0 0x11f01000 0 0x1000>, 502 <0 0x10217580 0 0x80>; 503 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 504 clocks = <&clk26m>, <&clk26m>; 505 clock-names = "main", "dma"; 506 clock-div = <1>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 }; 512}; 513